8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT36HTF1G72FZ – 8GB Features Figure 1: 240-Pin FBDIMM (MO-256 R/C E) • DDR2 functionality and operations supported as defined in the component data sheet • 240-pin, fully buffered dual in-line memory module (FBDIMM) • Fast data transfer rates: PC2-6400, PC2-5300, or PC2-4200 • 8GB (1 Gig x 72) • 3.2 Gb/s, 4 Gb/s, or 4.8 Gb/s link transfer rates • High-speed, 1.5V differential, point-to-point link between the host controller and advanced memory buffer (AMB) • Fault-tolerant; can work around a bad bit lane in each direction • High-density scaling with up to eight FBDIMM devices per channel • SMBus interface to AMB for configuration register access • In-band and out-of-band command access • Deterministic protocol Module height: 30.35mm (1.19in) Options Marking • Package – 240-pin DIMM (halogen-free) • Frequency/CAS latency – 2.5ns @ CL = 5 (DDR2-800) – 3.0ns @ CL = 5 (DDR2-667) Z -80E -667 Features (Continued) • Mixed-signal built-in self-test (MBIST) and interrupt-driven built-in self-test (IBIST) test functions • Transparent mode for DRAM test support • VDD = V DDQ = 1.8V for DRAM • VREF = 0.9V SDRAM command and address termination • VCC = 1.5V for AMB • VDDSPD = 3–3.6V for AMB and EEPROM • Serial presence-detect (SPD) with EEPROM • Gold edge contacts • Dual-rank • Supports 95°C operation with 2X refresh – Enables memory controller to optimize DRAM accesses for maximum performance – Delivers precise control and repeatable memory behavior • Automatic DDR2 SDRAM bus and channel calibration • Transmitter de-emphasis to reduce intersymbol interference (ISI) Table 1: Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = 6 CL = 5 CL = 4 CL = 3 tRCD (ns) tRP (ns) tRC (ns) -80E PC2-6400 800 800 533 400 12.5 12.5 55 -667 PC2-5300 – 667 533 400 15 15 55 -53E PC2-4200 – – 533 400 15 15 55 PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features Table 2: Addressing Parameter 8GB Refresh count 8K Device bank address 8 BA[2:0] Device page size per bank 1KB Device configuration 2Gb (512 Meg x 4) Row address 32K A[14:0] Column address 2K A[11, 9:0] Module rank address 2 S#[1:0] Table 3: Part Numbers and Timing Parameters – 8GB Base device: MT47H512M4,1 2Gb DDR2 SDRAM Module Part Number2 Density Configuration Module Memory Clock/ Clock Cycles Link Transfer Bandwidth Data Rate (CL-tRCD-tRP) Rate MT36HTF1G72FZ-80E__ 8GB 1 Gig x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s MT36HTF1G72FZ-667__ 8GB 1 Gig x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s Notes: 1. The data sheet for the base device can be found on Micron’s Web site. 2. All part numbers end with a four-place code (not shown) that designates component, PCB, and AMB revisions. Consult factory for current revision codes. Example: MT36HTF1G72FZ-667C1D6. PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignments 240-Pin DDR2 FBDIMM Front 240-Pin DDR2 FBDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol PS9#1 121 VDD 151 SN3 181 92 VSS 122 VDD 152 SN3# 93 PS5 123 VDD 153 VSS PN10# 94 PS5# 124 VSS 154 VSS 95 VSS 125 VDD 155 66 PN11 96 PS6 126 VDD 156 PN5 67 PN11# 97 PS6# 127 VDD PN5# 68 VSS 98 VSS 128 VSS 1 VDD 31 PN3 61 PN9# 91 2 VDD 32 PN3# 3 VDD 33 VSS 62 VSS 63 PN10 4 VSS 34 5 VDD 35 PN4 64 PN4# 65 6 VDD 36 VSS 7 VDD 8 VSS 37 38 SS9#1 SN9# 211 182 VSS 212 VSS 183 SN10 213 SS5 SN4 184 SN10# 214 SS5# SN4# 185 VSS 215 VSS VSS 186 SN11 216 SS6 157 SN5 187 SN11# 217 SS6# 158 SN5# 188 VSS 218 VSS 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 10 VCC 40 PN131 70 PS0 100 PS7# 130 VCC 160 SN131 190 SS0 220 SS7# 11 VSS 41 PN13#1 71 PS0# 101 VSS 131 VSS 161 SN13#1 191 SS0# 221 VSS 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 13 VCC 43 VSS 73 PS1 103 PS8# 133 VCC 163 VSS 193 SS1 223 SS8# 14 VSS 44 DNU 74 PS1# 104 VSS 134 VSS 164 DNU 194 SS1# 224 VSS 15 VTT 45 DNU 75 VSS 105 DNU 135 VTT 165 DNU 195 VSS 225 DNU 16 DNU 46 VSS 76 PS2 106 DNU 136 DNU 166 VSS 196 SS2 226 DNU 17 RESET# 47 VSS 77 PS2# 107 VSS 137 M_TEST (DNU) 167 VSS 197 SS2# 227 VSS 18 VSS 48 PN121 78 VSS 108 VDD 138 VSS 168 SN121 198 VSS 228 SCK PN12#1 79 PS3 109 VDD 139 DNU 169 SN12#1 199 SS3 229 SCK# 19 DNU 49 20 DNU 50 VSS 80 PS3# 110 VSS 140 DNU 170 VSS 200 SS3# 230 VSS 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PN0 52 PN6# 82 PS4 112 VDD 142 SN0 172 SN6# 202 SS4 232 VDD 23 PN0# 53 VSS 83 PS4# 113 VDD 143 SN0# 173 VSS 203 SS4# 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7# 85 VSS 115 VDD 145 SN1 175 SN7# 205 VSS 235 VDD 26 PN1# 56 VSS 86 DNU 116 VDD 146 SN1# 176 VSS 206 DNU 236 VDD 27 VSS 57 PN8 87 DNU 117 VTT 147 VSS 177 SN8 207 DNU 237 VTT 28 PN2 58 PN8# 88 VSS 118 SA2 148 SN2 178 SN8# 208 VSS 238 VDDSPD 29 PN2# 59 VSS 89 VSS 119 SDA 149 SN2# 179 VSS 209 VSS 239 SA0 PN9 90 PS91 210 SS91 240 SA1 Note: 1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, and SS9/SS9#. 30 VSS 60 PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 120 SCL 150 3 VSS 180 SN9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Symbol Type Description PS[9:0] Input Primary southbound data, positive lines. PS#[9:0] Input Primary southbound data, negative lines. SCK Input System clock input, positive line. SCK# Input System clock input, negative line. SCL Input Serial presence-detect (SPD) clock input. SS[9:0] Input Secondary southbound data, positive lines. SS#[9:0] Input Secondary southbound data, negative lines. PN[13:0] Output Primary northbound data, positive lines. PN#[13:0] Output Primary northbound data, negative lines. SN[13:0] Output Secondary northbound data, positive lines. SN#[13:0] Output Secondary northbound data, negative lines. VID0 Output Voltage identification, connected to VSS. Indicates 1.5V DRAM present on module. SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB. SPD data input/output. SDA I/O RESET# Supply AMB reset signal. VCC Supply AMB core power and AMB channel interface power (1.5V). VDD Supply DRAM power and AMB DRAM I/O power (1.5V). VTT Supply DRAM clock, command, and address termination power (VDD/2). VDDSPD Supply SPD/AMB SMBus power. VSS Supply Ground. M_TEST – The M_TEST pin provides an external connection for testing the margin of VREF, which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and will be included in this specification at that time. DNU – Do not use. PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM System Block Diagram System Block Diagram Figure 2: System Block Diagram DDR2 connector with unique key 10 Memory controller 14 SMBus Commodity DDR2 SDRAM devices DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component AMB AMB AMB DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component Up to 8 modules • • • DDR2 component AMB CK source SMBus access to buffer registers Common clock source PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Functional Block Diagram Functional Block Diagram Figure 3: Functional Block Diagram VSS RS0# RS1# DQS0 DQS0# DQ0 DQ1 DQ2 DQ3 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 DQS2 DQS2# DQ16 DQ17 DQ18 DQ19 DQS3 DQS3# DQ24 DQ25 DQ26 DQ27 DQS4 DQS4# DQ32 DQ33 DQ34 DQ35 DQS5 DQS5# DQ40 DQ41 DQ42 DQ43 DQS6 DQS6# DQ48 DQ49 DQ50 DQ51 DQS7 DQS7# DQ56 DQ57 DQ58 DQ59 DQS8 DQS8# CB0 CB1 CB2 CB3 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U10 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQS13 DQS13# DQ36 DQ37 DQ38 DQ39 DQS14 DQS14# DQ44 DQ45 DQ46 DQ47 DQS15 DQS15# DQ52 DQ53 DQ54 DQ55 DQS16 DQS16# DQ60 DQ61 DQ62 DQ63 U18 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U23 DQ28 DQ29 DQ30 DQ31 U19 DM CS# DQS DQS# U9 DQS12 DQS12# U30 DM CS# DQS DQS# U8 DQ20 DQ21 DQ22 DQ23 U31 DM CS# DQS DQS# U15 DQS11 DQS11# U24 DM CS# DQS DQS# U14 DQ12 DQ13 DQ14 DQ15 U25 DM CS# DQS DQS# U4 DQS10 DQS10# U36 DM CS# DQS DQS# U3 DQ4 DQ5 DQ6 DQ7 U37 DM CS# DQS DQS# U11 DQS9 DQS9# DQS17 DQS17# CB4 CB5 CB6 CB7 U33 U5 Out to Ctrl PN0-PN13 PN0#-PN13# PS0–PS9 In from Ctrl PS0#–PS9# Data input/output signals to DDR2 channel U1–U4, U6–U37 DQ0–DQ63 DQS0–DQS17 DQS0#–DQS17# CB0–CB7 SCL SDA SA0–SA2 SCK, SCK# RESET# PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN SN0–SN13 In from adjacent FBDIMM SN0#–SN13# SS0-SS9 Out to adjacent FBDIMM SS0#–SS9# A M B A0-A15 RAS#, CAS# WE#, ODT0 CS0#, CS1# CKE0, CKE1 CK0, CK0# CK1, CK1# CK2, CK2# CK3, CK3# DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ WP A0 VSS A1 U26 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U12 U35 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U13 U34 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U6 U21 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U7 U20 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U16 U29 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U17 U28 DM CS# DQS DQS# DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ SDA A2 SA0 SA1 SA2 Command, address, and clock signals to DDR2 channel U1–U4, U6–U37 Command, address, and clock line terminations: RAS#, CAS#, A0–A15, ODT0, WE#, BA0–BA2 VTT CK0, CK0#, CK1, CK1#, CK2, CK2#, CK3, CK3# VTT CS0#, CS1#, CKE0, CKE1 VTT 6 U2 U22 VTT SPD EEPROM U27 DM CS# DQS DQS# U38 SCL U1 VDDSPD U32 Terminators SPD EEPROM/AMB VCC AMB VDD DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM Serial PD/AMB Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM General Description General Description Micron’s FBDIMM devices adhere to the currently proposed industry specifications for FBDIMMs. The following specifications contain detailed information on FBDIMM design, interfaces, and theory of operation and are listed here for the system designers’ convenience. Refer to the JEDEC Web site for available specifications. • • • • • FBDIMM Design Specification – pending JEDEC approval FBDIMM: Architecture and Protocol – JESD206 FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20 Design for Test, Design for Validation (DFx) Specification Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C, page 4.1.2.7-1 This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from the channel behind an AMB on the FBDIMM. Memory device capacity remains high, and total memory capacity scales with DDR2 SDRAM bit density. As shown in the System Block Diagram, the FBDIMM channel provides a communication path from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM devices from the channel enhances the communication path and significantly increases the reliability and availability of the memory subsystem. Advanced Memory Buffer The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB component, located in the center of each FBDIMM, acts as a repeater and buffer for all signals and commands exchanged between the host controller and DDR2 SDRAM devices, including data input and output. The AMB communicates with the host controller and adjacent FBDIMMs on a system board using an industry-standard, high-speed, differential, 1.5V, point-to-point interface. The AMB also enables buffering of memory traffic to support large memory capacities. Refer to the JEDEC JESD82-20 specification for further information. PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Absolute Maximum Ratings Parameter Min Max Units Notes Voltage on any pin relative to VSS Symbol VIN, VOUT –0.3 +1.75 V 1 Voltage on VCC pin relative to VSS VCC –0.3 +1.75 V Voltage on VDD pin relative to VSS VDD –0.5 +2.3 V Voltage on VTT pin relative to VSS VTT –0.5 +2.3 V DDR2 SDRAM device operating case temperature TC 0 +95 °C 0 +110 °C AMB device operating temperature Notes: 2, 3 1. VIN should not be greater than VCC. 2. TC is specified at 95°C only when using 2X refresh timing (tREFI = 7.8µs at or below 85°C; tREFI = 3.9µs above 85°C); refer to the DDR2 SDRAM component data sheet. 3. See applicable DDR2 SDRAM component data sheet for tREFI and extended mode register settings. The tREFI parameter is used to specify the doubled refresh interval necessary to sustain <85°C operation. Table 7: Input DC Voltage and Operating Conditions Symbol Min Nom Max Units AMB supply voltage Parameter VCC 1.46 1.5 1.54 V DDR2 SDRAM supply voltage VDD 1.7 1.8 1.9 V Termination voltage VTT 0.48 × VDD 0.5 × VDD 0.52 × VDD V Notes EEPROM supply voltage VDDSPD 3 3.3 3.6 V 1 SPD input high (logic 1) voltage VIH(DC) 2.1 – VDDSPD V 2 SPD input low (logic 0) voltage VIL(DC) – – 0.8 V 2 RESET input high (logic 1) voltage VIH(DC) 1 – – V 3 RESET input low (logic 0) voltage VIL(DC) – – 0.5 V 2 Leakage current (RESET) lL –90 – +90 µA 3 Leakage current (link) lL –5 – +5 µA 4 Notes: PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 1. 2. 3. 4. Applies to AMB and SPD. Applies to serial memory buffer (SMB) and SPD bus signals. Applies to AMB CMOS signal RESET#. For all other AMB-related DC parameters, please refer to the high-speed differential link interface specification. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Electrical Specifications Table 8: Clock Rates FBDIMM Link Data Rate Reference Clock DRAM Clock DRAM Data Rate 3.2 Gb/s 133 MHz 266 MHz 533 Mb/s 4.0 Gb/s 167 MHz 333 MHz 666 Mb/s 4.8 Gb/s 200 MHz 400 MHz 800 Mb/s Note: PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 1. DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM IDD Specifications and Conditions IDD Specifications and Conditions Table 9: IDD Conditions Symbol Condition IDD_IDLE_0 Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IDLE_1 Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_ACTIVE_1 Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH IDD_ACTIVE_2 Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH; Command and address lines stable IDD_TRAINING Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IBIST IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_EI Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and CKE driven LOW Note: 1. Actual test conditions may vary from published JEDEC test conditions. Table 10: IDD Specifications – 8GB DDR2-800 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC TBD TBD TBD TBD TBD TBD TBD mA IDD TBD TBD TBD TBD TBD TBD TBD mA Total power TBD TBD TBD TBD TBD TBD TBD W Table 11: IDD Specifications – 8GB DDR2-667 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC 2600 3400 3900 3700 4000 4500 2500 mA IDD 1800 1800 3131 1800 1800 1800 632 mA 7.5 8.7 12.0 9.2 9.7 10.5 5.1 W Total power Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Serial Presence-Detect Table 12: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 3 3.6 V Input high voltage: Logic 1; all inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V Input low voltage: Logic 0; all inputs VIL –0.6 VDDSPD × 0.3 V Output low voltage: IOUT = 3mA EEPROM and AMB supply voltage VOL – 0.4 V Input leakage current: VIN = GND to VDD ILI 0.10 3 µA Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA Standby current ISB 1.6 4 µA Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA Table 13: Serial Presence-Detect EEPROM AC Operating Conditions Symbol Min Max Units Notes SCL LOW to SDA data-out valid Parameter/Condition tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH ns 200 – tF – 300 ns Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs tHIGH µs SDA and SCL fall time Clock HIGH period 0.6 – tI – 50 ns tLOW 1.3 – µs tR – 0.3 µs fSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs Stop condition setup time tSU:STO 0.6 – µs tWRC – 10 ms Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency WRITE cycle time Notes: PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions Module Dimensions Figure 4: 240-Pin DDR2 FBDIMM Notes: PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef84e934e8 htf36c1gx72fz.pdf - Rev. A 10/12 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved.