1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT9HTF12872FZ – 1GB Features • Transparent mode for DRAM test support • VDD = V DDQ = 1.8V for DRAM • VREF = 0.9V SDRAM command and address termination • VCC = 1.5V for AMB • VDDSPD = 3–3.6V for AMB and EEPROM • Serial presence-detect (SPD) with EEPROM • Gold edge contacts • Single rank • Supports 95°C operation with 2X refresh • Halogen-free PCB • 240-pin, DDR2 fully-buffered dual in-line memory module (FBDIMM) • Fast data transfer rates: PC2-5300 or PC2-6400 • 1GB (128 Meg x 72) • 4.0 Gb/s and 4.8 Gb/s link transfer rates • High-speed, 1.5V differential, point-to-point link between the host controller and advanced memory buffer (AMB) • Fault-tolerant; can work around a bad bit lane in each direction • High-density scaling with up to eight FBDIMMs per channel • SMBus interface to AMB for configuration register access • In-band and out-of-band command access • Deterministic protocol Figure 1: 240-Pin FBDIMM (MO-256 R/C A) Module height: 30.35mm (1.19in) – Enables memory controller to optimize DRAM accesses for maximum performance – Delivers precise control and repeatable memory behavior • Automatic DDR2 SDRAM bus and channel calibration • Transmitter de-emphasis to reduce ISI • MBIST and IBIST test functions Options Marking • Package – 240-pin DIMM (Halogen-free) • Frequency/CAS latency – 2.5ns @ CL = 5 (DDR2-800) – 3.0ns @ CL = 5 (DDR2-667) Z -80E -667 Table 1: Key Timing Parameters Data Rate (MT/s) tRCD Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) -80E PC2-6400 800 800 533 400 12.5 12.5 55 -667 PC2-5300 – 667 533 400 15 15 55 PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 1 tRP (ns) tRC (ns) Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Features Table 2: Addressing Parameter 1GB Refresh count 8K Device bank address 8 BA[2:0] Device configuration 1Gb (128 Meg x 8) Row address 16K A[13:0] Column address 1K A[9:0] Module rank address 1 S0# Table 3: Part Numbers and Timing Parameters – 1GB Base device: MT47H128M8,1 1Gb DDR2 SDRAM Module Part Number2 Density Configuration MT9HTF12872FZ-80E__ 1GB 128 Meg x 72 MT9HTF12872FZ-667__ 1GB 128 Meg x 72 Notes: 1. Data sheets for the base devices can be found on Micron’s Web page. 2. All part numbers end with a four-place code (not shown) that designates component, PCB, and AMB revisions. Consult factory for current revision codes. Example: MT9HTF12872FZ-80EM1D4. PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN Module Memory Clock/ Clock Cycles Link Transfer Bandwidth Data Rate (CL-tRCD-tRP) Rate 6.4 GB/s 2.5ns/800 MT/s 5-5-5 4.8 GT/s 5.3 GB/s 3.0ns/667 MT/s 5-5-5 4.0 GT/s 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignments 240-Pin FBDIMM Front 240-Pin FBDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VDD 31 PN3 61 PN9# 91 PS9#1 121 VDD 151 SN3 181 SN9# 211 SS9#1 2 VDD 32 PN3# 62 VSS 92 VSS 122 VDD 152 SN3# 182 VSS 212 VSS 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5 4 VSS 34 PN4 64 PN10# 94 PS5# 124 VSS 154 SN4 184 SN10# 214 SS5# 5 VDD 35 PN4# 65 VSS 95 VSS 125 VDD 155 SN4# 185 VSS 215 VSS 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 SS6 7 VDD 37 PN5 67 PN11# 97 PS6# 127 VDD 157 SN5 187 SN11# 217 SS6# 8 VSS 38 PN5# 68 VSS 98 VSS 128 VSS 158 SN5# 188 VSS 218 VSS 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 10 VCC 40 PN131 70 PS0 100 PS7# 130 VCC 160 SN131 190 SS0 220 SS7# 191 SS0# 221 VSS 192 VSS 222 SS8 SS8# 11 VSS 41 PN13#1 71 PS0# 101 VSS 131 VSS 161 SN13#1 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 13 VCC 43 VSS 73 PS1 103 PS8# 133 VCC 163 VSS 193 SS1 223 14 VSS 44 DNU 74 PS1# 104 VSS 134 VSS 164 DNU 194 SS1# 224 VSS 15 VTT 45 DNU 75 VSS 105 DNU 135 VTT 165 DNU 195 VSS 225 DNU 16 DNU 46 VSS 76 PS2 106 DNU 136 DNU 166 VSS 196 SS2 226 DNU 17 RESET# 47 VSS 77 PS2# 107 VSS 137 M_TEST (DNU) 167 VSS 197 SS2# 227 VSS 18 VSS 48 PN121 78 VSS 108 VDD 138 VSS 168 SN121 198 VSS 228 SCK PN12#1 79 PS3 109 VDD 139 DNU 169 SN12#1 199 SS3 229 SCK# 19 DNU 49 20 DNU 50 VSS 80 PS3# 110 VSS 140 DNU 170 VSS 200 SS3# 230 VSS 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PN0 52 PN6# 82 PS4 112 VDD 142 SN0 172 SN6# 202 SS4 232 VDD 23 PN0# 53 VSS 83 PS4# 113 VDD 143 SN0# 173 VSS 203 SS4# 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7# 85 VSS 115 VDD 145 SN1 175 SN7# 205 Vss 235 VDD 26 PN1# 56 VSS 86 DNU 116 VDD 146 SN1# 176 VSS 206 DNU 236 VDD 27 VSS 57 PN8 87 DNU 117 VTT 147 VSS 177 SN8 207 DNU 237 VTT 28 PN2 58 PN8# 88 VSS 118 SA2 148 SN2 178 SN8# 208 VSS 238 VDDSPD 29 PN2# 59 VSS 89 VSS 119 SDA 149 SN2# 179 VSS 209 VSS 239 SA0 30 VSS 60 PN9 90 PS91 120 SCL 150 VSS 180 SN9 210 SS91 240 SA1 Note: PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, SS9/ SS9#. 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Symbol Type Description PS[9:0] Input Primary southbound data, positive lines. PS#[9:0] Input Primary southbound data, negative lines. SCK Input System clock input, positive line. SCK# Input System clock Input, negative line. SCL Input Serial presence-detect (SPD) clock input. SS[9:0] Input Secondary southbound data, positive lines. SS#[9:0] Input Secondary southbound data, negative lines. PN[13:0] Output Primary northbound data, positive lines. PN#[13:0] Output Primary northbound data, negative lines. SN[13:0] Output Secondary northbound data, positive lines. SN#[13:0] Output Secondary northbound data, negative lines. SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB. SDA I/O SPD data input/output. RESET# Supply AMB reset signal. VCC Supply AMB core power and AMB channel interface power (1.5V). VDD Supply DRAM power and AMB DRAM I/O power (1.8V). VDDSPD Supply SPD/AMB SMBUS power (3.3V). VSS Supply Ground. VTT Supply DRAM address/command/clock termination power (VDD/2). M_TEST – The M_Test pin provides an external connection for testing the margin of VREF, which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and will be included in this specification at that time. DNU – Do not use. PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM System Block Diagram System Block Diagram Figure 2: System Block Diagram DDR2 connector with unique key 10 Memory controller 14 SMBus Commodity DDR2 SDRAM devices DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component AMB AMB AMB DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component DDR2 component Up to 8 modules • • • DDR2 component AMB CK source SMBus access to buffer registers Common clock source PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Functional Block Diagram Functional Block Diagram Figure 3: Functional Block Diagram CS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 DQS1 DQS1# DM5 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U11 DQS2 DQS2# DM2 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2 DQS3 DQS3# DM5 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U10 U4 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# U7 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# U5 Out to controller SN[13:0] SN#[13:0] SS[9:0] SS#[9:0] PN[13:0] PN#[13:0] PS[9:0] In from controller PS#[9:0] DQ[63:0] Data input/output signals to DDR2 channel U1–U2, U4–U8, U10–U11 DQS[8:0] DQS#[8:0] CB[7:0] DM[8:0] SCL SDA SA0 A M B A[15:0] RAS#, CAS# WE#, ODT0 CS0# CKE0 In from adjacent FBDIMM SCK, SCK# RESET# SPD EEPROM A2 VSS SA0 SA1 SA2 SDA CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Out to adjacent FBDIMM Command, address, and clock signals to DDR2 channel U1–U2, U4–U8, U10–U11 CK0, CK0# CK1, CK1# VTT VDDSPD SA[2:1] U9 DM/ RDQS CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# U6 DQS8 DQS8# DM8 U3 PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN DQS# DQS7 DQS7# DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A1 DQS DQS6 DQS6# DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 WP A0 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DQS5# DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SCL DM/ RDQS Command, address, and clock line terminations: CK0,CK0#, CK1, CK1#, ODT0, CS0#, RAS#, CKE0, CAS#, A[15:0], WE#, BA[2:0] VTT DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U8 Terminators SPD EEPROM, AMB VCC AMB VDD DDR2 SDRAM VREF VSS 6 DM/ RDQS DDR2 SDRAM DDR2 SDRAM SPD EEPROM, AMB Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM General Description General Description Micron’s FBDIMM devices adhere to the currently proposed industry specifications for FBDIMMs. The following specifications contain detailed information on FBDIMM design, interfaces, and theory of operation and are listed here for the system designers’ convenience. Refer to the JEDEC Web site for available specifications. • • • • • FBDIMM Design Specification – pending JEDEC approval FBDIMM: Architecture and Protocol – JESD206 FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20 Design for Test, Design for Validation (DFx) Specification Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C, page 4.1.2.7-1 This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from the channel behind an AMB on the FBDIMM. Memory device capacity remains high, and total memory capacity scales with DDR2 SDRAM bit density. As shown in the System Block Diagram, the FBDIMM channel provides a communication path from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM devices from the channel enhances the communication path and significantly increases the reliability and availability of the memory subsystem. Advanced Memory Buffer The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB component, located in the center of each FBDIMM, acts as a repeater and buffer for all signals and commands exchanged between the host controller and DDR2 SDRAM devices, including data input and output. The AMB communicates with the host controller and adjacent FBDIMMs on a system board using an industry-standard, high-speed, differential, 1.5V, point-to-point interface. The AMB also enables buffering of memory traffic to support large memory capacities. Refer to the JEDEC JESD82-20 specification for further information. PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Absolute Maximum Ratings Parameter Min Max Units Notes Voltage on any pin relative to VSS Symbol VIN, VOUT –0.3 +1.75 V 1 Voltage on VCC pin relative to VSS VCC –0.3 +1.75 V Voltage on VDD pin relative to VSS VDD –0.5 +2.3 V Voltage on VTT pin relative to VSS VTT –0.5 +2.3 V DDR2 SDRAM device operating case temperature TC 0 +95 °C 0 +110 °C AMB device operating temperature Notes: 2, 3 1. VIN should not be greater than VCC. 2. TC is specified at 95°C only when using 2X refresh timing (tREFI = 7.8µs at or below 85°C; tREFI = 3.9µs above 85°C); refer to the DDR2 SDRAM component data sheet. 3. See applicable DDR2 SDRAM component data sheet for tREFI and extended mode register settings. The tREFI parameter is used to specify the doubled refresh interval necessary to sustain <85°C operation. Table 7: Input DC Voltage and Operating Conditions Symbol Min Nom Max Units AMB supply voltage Parameter VCC 1.46 1.5 1.54 V DDR2 SDRAM supply voltage VDD 1.7 1.8 1.9 V Termination voltage VTT 0.48 × VDD 0.5 × VDD 0.52 × VDD V Notes EEPROM supply voltage VDDSPD 3 3.3 3.6 V 1 SPD input high (logic 1) voltage VIH(DC) 2.1 – VDDSPD V 2 SPD input low (logic 0) voltage VIL(DC) – – 0.8 V 2 RESET input high (logic 1) voltage VIH(DC) 1 – – V 3 RESET input low (logic 0) voltage VIL(DC) – – 0.5 V 2 Leakage current (RESET) lL –90 – +90 µA 3 Leakage current (link) lL –5 – +5 µA 4 Notes: PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 1. 2. 3. 4. Applies to AMB and SPD. Applies to serial memory buffer (SMB) and SPD bus signals. Applies to AMB CMOS signal RESET#. For all other AMB-related DC parameters, please refer to the high-speed differential link interface specification. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM IDD Conditions and Specifications Table 8: Clock Rates FBDIMM Link Data Rate Reference Clock DRAM Clock DRAM Data Rate 3.2 Gb/s 133 MHz 266 MHz 533 Mb/s 4.0 Gb/s 167 MHz 333 MHz 666 Mb/s 4.8 Gb/s 200 MHz 400 MHz 800 Mb/s Note: 1. DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades IDD Conditions and Specifications Table 9: IDD Conditions Symbol Condition IDD_IDLE_0 Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IDLE_1 Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_ACTIVE_1 Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH IDD_ACTIVE_2 Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH; Command and address lines stable IDD_TRAINING Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IBIST IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_EI Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and CKE driven LOW Note: 1. Actual test conditions may vary from published JEDEC test conditions. Table 10: IDD Specifications – 1GB DDR2-667 (Die revision H) IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC Symbol 2600 3400 3900 3700 4000 4500 2500 mA IDD 916 916 1945 916 916 916 263 mA Total power 5.8 7.0 9.8 7.5 8.0 8.8 4.4 W PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Serial Presence-Detect Table 11: IDD Specifications – 1GB DDR2-667 (Die revision M) IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC Symbol 2600 3400 3900 3700 4000 4500 2500 mA IDD 916 916 1945 916 916 916 290 mA Total power 5.8 7.0 9.8 7.5 8.0 8.8 4.5 W Table 12: IDD Specifications – 1GB DDR2-800 (All die revisions) Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC TBD TBD TBD TBD TBD TBD TBD mA IDD TBD TBD TBD TBD TBD TBD TBD mA Total power TBD TBD TBD TBD TBD TBD TBD W Note: 1. Total power is based on maximum voltage levels, ICC at 1.575V and IDD at 1.9V. Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. Table 13: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 3 3.6 V Input high voltage: Logic 1; all inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V Input low voltage: Logic 0; all inputs VIL –0.6 VDDSPD × 0.3 V Output low voltage: IOUT = 3mA VOL – 0.4 V Input leakage current: VIN = GND to VDD ILI 0.10 3 µA Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA Standby current ISB 1.6 4 µA Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA EEPROM and AMB supply voltage Table 14: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns tF – 300 ns Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs tHIGH 0.6 – µs tI – 50 ns SDA and SCL fall time Clock HIGH period Noise suppression time constant at SCL, SDA inputs PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 10 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Serial Presence-Detect Table 14: Serial Presence-Detect EEPROM AC Operating Conditions (Continued) Parameter/Condition Symbol Min Max Units tLOW 1.3 – µs tR – 0.3 µs fSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs Stop condition setup time tSU:STO 0.6 – µs tWRC – 10 ms Clock LOW period SDA and SCL rise time SCL clock frequency WRITE cycle time Notes: PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN Notes 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions Module Dimensions Figure 4: 240-Pin DDR2 FBDIMM Front view 5.1 (0.201) MAX 133.50 (5.256) 133.20 (5.244) 66.68 (2.63) TYP 0.595 (0.0234) R 0.75 (0.03) R 8X 0.5 (0.02) R (4X) 2.0 (0.079) TYP 1.5 (0.059) R (4X) U1 U2 U4 U3 U5 17.3 (0.681) TYP 9.5 (0.374) TYP 2.6 (0.102) D (2X) 5.2 (0.205) TYP 1.25 (0.0492) TYP Pin 1 Detail A 1.0 (0.039) TYP 0.75 (0.03) R Pin 120 123.0 (4.843) TYP 9.9 (0.39) TYP (x4) 1.37 (0.054) 1.17 (0.046) 3.9 (0.153) TYP (x2) 0.8 (0.031) TYP 74.68 (2.94) TYP 5.48 (0.216) TYP 30.5 (1.201) 30.2 (1.189) 45° x 0.18 (0.0071) Back view 1.06 (0.042) 1.19 (0.047) 1.06 (0.042) Detail A 3.1 (0.122) TYP U6 U7 U8 U10 24.95 (0.982) TYP U11 U9 3.05 (0.12) TYP 2.18 (0.086) TYP 120° (2X) Pin 240 5.0 (0.197) TYP 51.0 (2.01) TYP Pin 121 67.0 (2.638) TYP 66.68 (2.63) TYP 7.68 (0.302) MAX* Front view with heat spreader U1 U2 U4 U3 U5 1.37 (0.054) 1.17 (0.046) Back view with heat spreader U6 U7 U8 U10 *Including clip radius 7.92 (0.312) U11 U9 Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83de8266 htf9c128x72fz.pdf - Rev. B 4/14 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.