152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Features Mobile LPDDR (only) 152-Ball Package-on-Package (PoP) TI-OMAP™ MT46HxxxMxxLxCG MT46HxxxMxxLxKZ Features Options • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; 2 data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks (DM) for masking write data—one mask per byte • Programmable burst lengths (BLs): 2, 4, 8, or 161 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Deep power-down (DPD) • STATUS REGISTER READ (SRR) supported2 • Selectable output drive strength (DS) • Clock stop capability • 64ms refresh • VDD/VDDQ – 1.8V/1.8V H • Configuration – 128 Meg x 32 (16 Meg x 16 x 4 banks x 4) 128M32 64M32 – 64 Meg x 32 (8 Meg x 32 x 4 banks x 2) 32M32 – 32 Meg x 32 (8 Meg x 32 x 4 banks) 16M32 – 16 Meg x 32 (4 Meg x 32 x 4 banks) • Device version – Single die, standard addressing LF – 2-die stack, standard addressing L2 – 4-die stack, standard addressing L4 • Plastic “green” package – 152-ball VFBGA (14 x 14 x 1.0mm) CG – 152-ball VFBGA (14 x 14 x 1.2mm) KZ • Timing – cycle time – 5ns @ CL = 3 -5 – 5.4ns @ CL = 3 -54 -6 – 6ns @ CL = 3 • Operating temperature range – Commercial (0°C to +70°C) None – Industrial (–40°C to +85°C) IT Table 1: Marking Notes: 1. BL 16: contact factory for availability. 2. Contact factory for remapped SRR output. Configuration Addressing Architecture 128 Meg x 321 64 Meg x 32 32 Meg x 32 16 Meg x 32 Configuration 16 Meg x 16 x 4 banks x 4 die 8K 8 Meg x 32 x 4 banks x 2 die 8K 8 Meg x 32 x 4 banks 8K 4 Meg x 32 x 4 banks 8K 16K (A[13:0]) 8K (A[12:0]) 8K (A[12:0]) 8K (A[12:0]) 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) 512 (A[8:0]) Refresh count Row addressing Column addressing Notes: 1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bitwide bus. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Part Numbering Information – 152-Ball PoP Part Numbering Information – 152-Ball PoP Micron® 152-ball packaged LPDDR devices are available in several configurations. Figure 1: Marketing Part Number Example MT 46 H 32M32 LF CG Micron Technology -6 IT :A Design Revision :A = First generation Product Family :B = Second generation 46 = LPDDR-SDRAM Operating Temperature Operating Voltage Blank = Commercial (0°C to +70°C) H = 1.8V/1.8V IT = Industrial (–40°C to +85°C) Configuration Cycle Time 128 Meg x 32 64 Meg x 32 -5 = 5ns tCK CL = 3 -54 = 5.4ns tCK CL = 3 32 Meg x 32 -6 = 6ns tCK CL = 3 16 Meg x 32 Package Code Device Version CG = 152-ball (14 x 14 x 1.0mm) VFBGA LF = Single die, standard addressing KZ = 152-ball (14 x 14 x 1.2mm) VFBGA L2 = 2-die stack, standard addressing L4 = Quad die, standard addressing PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Device Marking Table 2: 152-Ball Production Marketing Part Numbers Part Numbers MT46H16M32LFCG-5:B MT46H16M32LFCG-5 IT:B MT46H16M32LFCG-54:B MT46H16M32LFCG-54 IT:B MT46H16M32LFCG-6:B MT46H16M32LFCG-6 IT:B MT46H32M32LFCG-5:A MT46H32M32LFCG-5 IT:A MT46H32M32LFCG-54:A MT46H32M32LFCG-54 IT:A MT46H32M32LFCG-6:A MT46H32M32LFCG-6 IT:A MT46H64M32L2CG-5:A MT46H64M32L2CG-5 IT:A MT46H64M32L2CG-54:A MT46H64M32L2CG-54 IT:A MT46H64M32L2CG-6:A MT46H64M32L2CG-6 IT:A MT46H128M32L4KZ-6 IT ES:A LPDDR Product Physical Part Marking 512Mb DDR, x32, 200 MHz 512Mb DDR, x32, 200 MHz 512Mb DDR, x32, 185 MHz 512Mb DDR, x32, 185 MHz 512Mb DDR, x32, 166 MHz 512Mb DDR, x32, 166 MHz 1Gb DDR, x32, 200 MHz 1Gb DDR, x32, 200 MHz 1Gb DDR, x32, 185 MHz 1Gb DDR, x32, 185 MHz 1Gb DDR, x32, 166 MHz 1Gb DDR, x32, 166 MHz 2 x 1Gb DDR, x32, 200 MHz 2 x 1Gb DDR, x32, 200 MHz 2 x 1Gb DDR, x32, 185 MHz 2 x 1Gb DDR, x32, 185 MHz 2 x 1Gb DDR, x32, 166 MHz 2 x 1Gb DDR, x32, 166 MHz 4 × 1Gb DDR, x32, 166 MHz D9KTK D9KTL D9KTM D9KTN D9KGX D9KGZ D9KTP D9KLD D9KTQ D9KTR D9KHL D9JZJ D9KTS D9KLF D9KTV D9KTW D9KJV D9KFJ Z9KZL Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,” at www.micron.com/csn. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) General Description General Description Micron 152-ball packaged Mobile Low-Power DDR SDRAM (LPDDR) devices contain either 1Gb LPDDR or 512Mb LPDDR die. The 1Gb LPDDR die is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits. The 512Mb LPDDR die is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits. Figure 2: Functional Block Diagram CKE CK# CK WE# CAS# RAS# Command decode CS# Control logic Bank 3 Bank 2 Bank 1 Refresh counter Standard mode register Extended mode register Bank 0 rowaddress latch and decoder Rowaddress MUX Bank 0 memory array Data 32 64 Read latch Sense amplifiers 32 MUX DRVRS 32 4 DQS generator DQ0– DQ31 COL 0 I/O gating DM mask logic 2 Address, BA0, BA1 Address register 2 CK 64 Bank control logic 4 DQS Input registers 64 Column decoder Columnaddress counter/ latch Write FIFO and drivers CK out CK in DQS0, DQS1, DQS2, DQS3 4 Mask 4 4 4 32 32 8 64 RCVRS 32 32 32 Data CK DM0, DM1, DM2, DM3 4 COL 0 1 PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 3: 152-Ball VFBGA Ball Assignments 11 12 13 14 15 16 17 18 19 20 21 DQ19 CK VSS DM2 VDDQ DQ21 DQ20 DM3 DQS3 NC NC A CK# VSSQ DQS2 VDD DQ23 DQ22 DQ28 NC NC B DQS0 DQ24 DQ26 C DQ3 DQ5 DQ25 DQ29 D E DQ0 DQ1 DQ27 DQ31 E F VSSQ VDDQ VSSQ VDDQ F G DQ4 DQ2 A0 DQ30 G H DM0 VSS VSS VDD H J VDD NC A2 A3 J K NC NC A1 A9 K L NC NC VDDQ VSSQ L M NC VSS A7 A6 M N NC NC1 A8 A11 N P NC NC VSS VDD P R NC VSS A5 A12 R T NC NC1 CS1# CS0# T U NC NC CAS# A4 U V NC NC BA1 RAS# V W NC NC VSSQ VDDQ W Y DNU NC NC NC NC VSS NC1 NC NC NC VSS RFU CKE1 VDD CKE0 A10 VSS WE# VSSQ NC DNU Y AA NC NC NC NC NC NC1 VSS NC NC NC VDD TQ VSS VDDQ A13 VSSQ VDD BA0 VDDQ NC NC AA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 8 A NC NC VDDQ DM1 DQ13 DQ15 VSSQ DQ10 B NC NC DQ6 DQ7 VDDQ DQ9 DQ14 DQS1 DQ11 C VSSQ D 9 10 DQ12 DQ16 DQ8 DQ17 DQ18 Top View – Ball Down Notes: LPDDR Supply Ground 1. Although not bonded to the die, these pins may be connected on the package substrate. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Ball Assignments and Descriptions Table 3: Ball Assignments Symbol Type Description A[13:0] Input BA0, BA1 CAS# CK, CK# Input Input CKE0, CKE1 Input CS0#, CS1# Input DM[3:0] RAS# WE# DQ[31:0] Input Input Input Input/ output Input/ output Output Supply Supply Supply – Address inputs: Specify the row or column address. Also used to load the mode registers. The maximum address is determined by density and configuration. Consult the LPDDR product data sheet for the maximum address for a given density and configuration. Unused address pins become RFU.1 Bank address inputs: Specify one of the 4 banks. Column select: Specifies the command to execute. CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#. Clock enable. CKE0 is used for a single LPDDR product. CKE1 is used for dual LPDDR products, and is considered RFU for single products. Chip select: CS0# is used for a single LPDDR product. CS1# is used for dual LPDDR products, and is considered RFU for single products. Data mask: Determines which bytes are written during WRITE operations. Row select: Specifies the command to execute. Write enable: Specifies the command to execute. Data bus: Data inputs/outputs. DQS[3:0] TQ VDD VDDQ VSSQ RFU1 Data strobe: Coordinates read/write transfers of data; one DQS per DQ byte. Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C. VDD: LPDDR power supply. VDDQ: LPDDR I/O power supply. VSSQ: LPDDR I/O ground. Reserved for future use. Notes: Table 4: 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. Non-Device-Specific Ball Assignments Symbol Type VSS Supply DNU NC – – Description VSS: Shared ground. Do not use: Must be grounded or left floating. No connect: Not internally connected. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Electrical Specifications Electrical Specifications Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 5: Absolute Maximum Ratings Note 1 applies to all parameters in this table. Parameters/Conditions VDD, VDDQ Supply voltage relative to VSS Voltage on any pin relative to VSS Symbol Min Max Unit VDD, VDDQ VIN –1.0 –0.5 2.4 V V –55 Storage temperature range Notes: Table 6: 2.4 or (VDDQ + 0.3V), whichever is less +150 °C 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD. Recommended Operating Conditions Parameters Supply voltage I/O supply voltage Operating temperature range PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN Symbol Min Typ Max Unit VDD VDDQ 1.70 1.70 0 -40 1.80 1.80 – – 1.95 1.95 +70 +85 V V °C °C Commercial Industrial 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Device Diagrams Device Diagrams Figure 4: 152-Ball VFBGA Functional Block Diagram (non-Quad Die) CS# VDD VDDQ CK DM CK# CKE RAS# LPDDR DQ CAS# DQS WE# TQ VSS Address, VSSQ BA0, BA1 PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Device Diagrams Figure 5: 152-Ball VFBGA Functional Block Diagram, Quad Die CS0# VDD CK VDDQ CK# DM CKE0 Two x16 LPDDR RAS# in parallel DQ CAS# WE# DQS TQ Address, BA0, BA1 VSS CS1# VDD VSSQ CK VDDQ CK# DM CKE1 Two x16 LPDDR RAS# in parallel DQ CAS# WE# DQS TQ Address, BA0, BA1 PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN VSS VSSQ 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Package Dimensions Package Dimensions Figure 6: 152-Ball VFBGA Package, 1.0mm (Package Code: CG) Seating plane A 0.6 ±0.1 0.1 A 152X Ø0.46 Solder ball material: SAC105. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. Ball A1 ID 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D Ball A1 ID E F G H J K L 13 CTR 14 ±0.1 M N P R T U V W 0.65 TYP Y AA 0.65 TYP 1.0 MAX 13 CTR 0.35 MIN 14 ±0.1 Notes: 1. All dimensions are in millimeters. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Package Dimensions Figure 7: 152-Ball VFBGA Package, 1.2mm (Package Code: KZ) Seating plane A 0.78 ±0.1 0.1 A 152X Ø0.46 Solder ball material: SAC105. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 14 ±0.1 Ball A1 ID Ball A1 ID 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H 14 ±0.1 J K 13 CTR L M N P R T U V W 0.65 TYP Y AA 0.65 TYP 1.2 MAX 0.35 MIN 13 CTR Notes: 1. All dimensions are in millimeters. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) Revision History Revision History Rev. E, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/09 • Table 3, “Ball Assignments,” on page 6: Deleted ball numbers. • Table 4, “Non-Device-Specific Ball Assignments,” on page 6: Deleted ball numbers. • Table 5, “Absolute Maximum Ratings,” on page 7: Added note. • Table 6, “Recommended Operating Conditions,” on page 7: Updated symbol for I/O supply voltage. Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/09 • Added 4Gb option and updated these items to reflect the addition: – “MT46HxxxMxxLxKZ” on page 1 – “Options” on page 1 – Table 1, “Configuration Addressing,” on page 1, including note 1 – Table 2, “152-Ball Production Marketing Part Numbers,” on page 3, part number – Figure 1: “Marketing Part Number Example,” on page 2 – Figure 3: “152-Ball VFBGA Ball Assignments,” on page 5 – Table 4, “Non-Device-Specific Ball Assignments,” on page 6 – Added Figure 5: “152-Ball VFBGA Functional Block Diagram, Quad Die,” on page 9 – Added Figure 7: “152-Ball VFBGA Package, 1.2mm (Package Code: KZ),” on page 11. • Removed references to reduced-page-size devices. • Figure 4: “152-Ball VFBGA Functional Block Diagram (non-Quad Die),” on page 8: Added parenthetic comment to title. • Figure 6: “152-Ball VFBGA Package, 1.0mm (Package Code: CG),” on page 10 and Figure 7: “152-Ball VFBGA Package, 1.2mm (Package Code: KZ),” on page 11: Added package codes to figure titles. Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/08 • Updated template and standards. • Added Table 2, “152-Ball Production Marketing Part Numbers,” on page 3. Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/08 • Added reduced page-size options (LA and LG) to Table 1, “Configuration Addressing,” on page 1; Figure 1: “Marketing Part Number Example,” on page 2; “General Description” on page 4. Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08 • Initial release. PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved.