4Gb: x16 gDDR3L SDRAM Graphics Addendum

4Gb: x16 gDDR3L SDRAM Graphics Addendum
Features
gDDR3L SDRAM Graphics Addendum
MT41K256M16 – 32 Meg x 16 x 8 Banks
Features
Options
Marking
• Configuration
– 256 Meg x 16
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) Rev. E
• Timing – cycle time
– 1.1ns @ CL = 13 (gDDR3-1800)
• Operating temperature
– Commercial (0°C ≤ T C ≤ 95°C)
• Revision
• VDD = V DDQ = +1.35V (1.283–1.45V)
or V DD = V DDQ = +1.5V (1.425–1.575V)
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS READ latency (CL)
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1,
CL - 2
• Programmable CAS WRITE latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms at 85°C to 115°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Note:
256M16
HA
-107G
None
:E
1. For complete device functionality and specifications, refer to the standard 4Gb DDR3
SDRAM data sheet found at www.micron.com. The information in this data
sheet supersedes the standard data sheet.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
tRCD
tRP
-107G
1800
13-13-13
14.3
14.3
14.3
-125G
1600
11-11-11
13.75
13.75
13.75
(ns)
(ns)
CL (ns)
Table 2: Addressing
Parameter
256 Meg x 16
Configuration
32 Meg x 16 x 8 banks
Refresh count
8K
Row addressing
32K (A[14:0])
Bank addressing
8 (BA[2:0])
Column addressing
1K (A[9:0])
PDF: 09005aef84b213dd
ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x16 gDDR3L SDRAM Graphics Addendum
Features
Table 3: Part Number Cross Reference
Micron Part Number
FBGA Code
MT41K256M16HA-107G:E
D9PZD
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
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ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Ball Assignments
Ball Assignments
Figure 1: 96-Ball FBGA – x16 (Top View)
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
NC
NC
A8
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
PDF: 09005aef84b213dd
ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
1. Ball descriptions are listed in the main 4Gb DDR3 data sheet.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS# is selectable between NF or TDQS# via MRS.
3
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© 2010 Micron Technology, Inc. All rights reserved.
4Gb: x16 gDDR3L SDRAM Graphics Addendum
Package Dimensions
Package Dimensions
Figure 2: 96-Ball FBGA – x16 (HA)
0.155
Seating plane
96X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
1.8 CTR
Nonconductive
overmold
9
8
7
3
A
2
0.12
A
Ball A1 Index
(covered by SR)
1
Ball A1 Index
A
B
C
D
E
F
G
H
12 CTR
J
14 ±0.1
K
L
M
N
P
R
0.8 TYP
T
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Note:
PDF: 09005aef84b213dd
ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
1. All dimensions are in millimeters.
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© 2010 Micron Technology, Inc. All rights reserved.
4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Specifications
Electrical Specifications
Input/Output Capacitance
Note 1 applies to the entire table
Capacitance
Parameters
gDDR3L-1600
gDDR3L-1800
Symbol
Min
Max
Min
Max
Unit
CK and CK#
CCK
0.8
1.4
0.8
1.3
pF
ΔC: CK to CK#
CDCK
0
0.15
0
0.15
pF
CIO
1.5
2.2
1.5
2.1
pF
Single-end I/O: DQ, DM
Differential I/O: DQS, DQS#, TDQS, TDQS#
ΔC: DQS to DQS#, TDQS, TDQS#
ΔC: DQ to DQS
Inputs (CTRL, CMD, ADDR)
ΔC: CTRL to CK
Notes
2
CIO
1.5
2.2
1.5
2.1
pF
3
CDDQS
0
0.15
0
0.15
pF
3
CDIO
–0.5
0.3
–0.5
0.3
pF
4
CI
0.75
1.2
0.75
1.2
pF
5
CDI_CTRL
–0.4
0.2
–0.4
0.2
pF
6
CDI_CMD_ADDR
–0.4
0.4
–0.4
0.4
pF
7
ZQ pin capacitance
CZO
–
3.0
–
3.0
pF
Reset pin capacitance
CRE
–
3.0
–
3.0
pF
ΔC: CMD_ADDR to CK
Notes:
PDF: 09005aef84b213dd
ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
1. VDD = +1.35V(1.283–1.45V)V, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) =
0.5 × VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).
5
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© 2010 Micron Technology, Inc. All rights reserved.
4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics – IDD Specifications
Electrical Characteristics – IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise
noted.
Table 4: IDD Maximum Limits - Die Rev. E
Speed Bin
IDD
gDDR3L-1600
gDDR3L-1800
Units
Notes
IDD0
66
73
mA
1, 2
IDD1
87
91
mA
1, 2
IDD2P0 (slow)
18
18
mA
1, 2
IDD2P1 (fast)
32
37
mA
1, 2
IDD2Q
32
35
mA
1, 2
IDD2N
32
35
mA
1, 2
IDD2NT
42
45
mA
1, 2
IDD3P
38
41
mA
1, 2
IDD3N
47
49
mA
1, 2
IDD4R
235
252
mA
1, 2
IDD4W
171
190
mA
1, 2
IDD5B
235
242
mA
1, 2
IDD6
20
20
mA
1, 2, 3,
IDD6ET
25
25
mA
2, 4
IDD7
243
274
mA
1, 2
IDD8
IDD2P + 2mA
IDD2P + 2mA
mA
1, 2
Notes:
1.
2.
3.
4.
5.
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC (MAX) = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
The IDD values must be derated (increased) on IT-option devices when operated outside
of the range 0°C ≤ TC ≤ 85°C:
• When TC < 0°C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7%.
• When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must
be derated by 2%; IDD2Px must be derated by 30%.
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ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Speed Bin Tables
Speed Bin Tables
Table 5: gDDR3L-1600 Speed Bins
gDDR3L-1600 Speed Bin
-125G
CL-tRCD-tRP
11-11-11
Parameter
Symbol
Min
Max
Unit
tRCD
13.75
–
ns
PRECHARGE command period
tRP
13.75
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
48.75
–
ns
tRAS
35
9 x tREF
ns
1
3.0
3.3
ns
2
ns
3
ns
2
ACTIVATE to internal READ or WRITE delay time
ACTIVATE-to-PRECHARGE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8
tCK
(AVG)
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8
tCK
(AVG)
Reserved
ns
3
CWL = 5
tCK
(AVG)
Reserved
ns
3
CWL = 6
tCK
(AVG)
ns
2
CWL = 7, 8
tCK
(AVG)
ns
3
CWL = 5
tCK
(AVG)
ns
3
CWL = 6
tCK
(AVG)
ns
2
CWL = 7, 8
tCK
(AVG)
Reserved
ns
3
CWL = 5, 6
tCK
(AVG)
Reserved
ns
3
CWL = 7
tCK
(AVG)
ns
2
CWL = 8
tCK
(AVG)
Reserved
ns
3
CWL = 5, 6
tCK
(AVG)
Reserved
ns
3
CWL = 7
tCK
(AVG)
ns
2
CWL = 8
tCK
(AVG)
Reserved
ns
3
CWL = 5, 6, 7
tCK
(AVG)
Reserved
ns
3
CWL = 8
tCK
(AVG)
ns
2
Supported CL settings
Supported CWL settings
Notes:
PDF: 09005aef84b213dd
ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
Notes
Reserved
2.5
3.3
1.875
<2.5
Reserved
Reserved
1.875
<2.5
1.5
<1.875
1.5
<1.875
1.25
<1.5
5, 6, 7, 8, 9, 10, 11
CK
5, 6, 7, 8
CK
1. tREFI depends on TOPER.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Speed Bin Tables
Table 6: gDDR3-1800 Speed Bins
gDDR3L-1800 Speed Bin
-107G
CL-tRCD-tRP
13-13-13
Parameter
Symbol
Min
Max
Unit
tRCD
14.3
–
ns
PRECHARGE command period
tRP
14.3
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
48.91
–
ns
tRAS
35
9 x tREFI
ns
1
3.0
3.3
ns
3
ns
3
ns
2
ns
3
ns
3
ACTIVATE to internal READ or WRITE delay time
ACTIVATE-to-PRECHARGE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CL - 12
CL = 13
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8, 9
tCK
(AVG)
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8, 9
tCK
(AVG)
CWL = 5, 7, 8, 9
tCK
(AVG)
CWL = 6
tCK
(AVG)
Reserved
ns
3
CWL = 5, 7, 8, 9
tCK
(AVG)
Reserved
ns
3
CWL = 6
tCK
(AVG)
ns
2
CWL = 5, 6, 8, 9
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
ns
3
CWL = 5, 6, 9
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
ns
2
CWL = 8
tCK
(AVG)
Reserved
ns
3
CWL = 5, 6, 7
tCK
(AVG)
Reserved
ns
3
CWL = 8
tCK
(AVG)
ns
3
CWL = 9
tCK
(AVG)
Reserved
ns
3
CWL = 5, 6, 7, 8
tCK
(AVG)
Reserved
ns
3
CWL = 9
tCK
(AVG)
Reserved
ns
3
CWL = 5, 6, 7, 8
tCK
(AVG)
Reserved
ns
3
CWL = 9
tCK
(AVG)
2
Supported CL settings
Supported CWL settings
Notes:
PDF: 09005aef84b213dd
ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
Notes
Reserved
2.5
3.3
Reserved
2.5
3.3
1.875
<2.5
Reserved
1.875
<2.5
Reserved
1.5
1.5
1.1
<1.875
<1.875
<1.25
ns
5, 6, 7, 8, 9, 10, 11, 13
CK
5, 6, 7, 8, 9
CK
1. tREFI depends on TOPER.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
Parameter
Symbol
gDDR3L-1600
gDDR3L-1800
Min
Max
Min
Max
Unit
Notes
8
7800
8
7800
ns
9, 42
8
3900
8
3900
ns
42
ns
10, 11
Clock Timing
Clock period average:
DLL disable mode
TC = 0°C to 85°C
tCK
(DLL_DIS)
TC = >85°C to 95°C
Clock period average: DLL enable mode
tCK
(AVG)
High pulse width average
tCH
(AVG)
0.47
0.53
0.47
0.53
CK
12
Low pulse width average
tCL
(AVG)
0.47
0.53
0.47
0.53
CK
12
–80
80
–70
70
ps
13
–70
70
–60
60
ps
13
Clock period jitter
DLL locked
tJIT
PER
DLL locking
tJIT
PER,lck
Clock absolute period
tCK
(ABS)
Clock absolute high pulse width
tCH
(ABS)
See corresonding speed bin table for
tCK range allowed
MIN = tCK (AVG) MIN + tJITPER MIN;
MAX = tCK (AVG) MAX + tJITPER MAX
0.43
–
0.43
–
ps
tCK
14
(AVG)
Clock absolute low pulse width
tCL
(ABS)
0.43
–
0.43
–
tCK
15
(AVG)
Cycle-to-cycle jitter
Cumulative error across
DLL locked
tJIT
CC
160
140
ps
16
CC,lck
140
120
ps
16
103
ps
17
122
ps
17
–136
136
ps
17
–147
147
ps
17
–155
155
ps
17
186
–163
163
ps
17
–193
193
–169
169
ps
17
–200
200
–175
175
ps
17
10 cycles
tERR10
PER
–205
205
–180
180
ps
17
11 cycles
tERR11
PER
–210
210
–184
184
ps
17
12 cycles
tERR12
PER
–215
215
–188
188
ps
17
n = 13, 14 . . .49, 50
cycles
tERRnper
tERRn
ps
17
DLL locking
tJIT
2 cycles
tERR2
PER
–118
118
–103
3 cycles
tERR3
PER
–140
140
–122
4 cycles
tERR4
PER
–155
155
5 cycles
tERR5
PER
–168
168
6 cycles
tERR6
PER
–177
177
7 cycles
tERR7
PER
–186
8 cycles
tERR8
PER
9 cycles
tERR9
PER
t
PER MIN = (1 + 0.68in[n]) × JITPER
MIN
tERRn
t
PER MAX = (1 + 0.68in[n]) × JITPER
MAX
DQ Input Timing
Data setup time to DQS,
DQS#
Base (specification)
VREF @ 1 V/ns
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ddr3L_4gb_graphics_addendum.pdf - Rev. C 08/13 EN
tDS
–
–
–
–
ps
18, 19
(AC175)
–
–
–
–
ps
19, 20
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter
Data setup time to DQS,
DQS#
Base (specification)
Data hold time from
DQS, DQS#
Base (specification)
VREF @ 1 V/ns
VREF @ 1 V/ns
Minimum data pulse width
gDDR3L-1600
gDDR3L-1800
Symbol
Min
Max
Min
Max
Unit
Notes
tDS
30
–
10
–
ps
18, 19
(AC150)
180
–
160
–
ps
19, 20
tDH
65
–
45
–
ps
18, 19
(DC100)
165
–
145
–
ps
19, 20
tDIPW
400
–
360
–
ps
41
125
–
100
ps
–
tCK
DQ Output Timing
tDQSQ
DQS, DQS# to DQ skew, per access
tQH
DQ output hold time from DQS, DQS#
–
0.38
–
0.38
21
(AVG)
DQ Low-Z time from CK, CK#
tLZ
(DQ)
–500
250
–450
225
ps
22, 23
DQ High-Z time from CK, CK#
tHZ
(DQ)
–
250
–
225
ps
22, 23
25
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising
tDQSS
–0.25
0.25
–0.27
0.27
CK
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
CK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
CK
DQS, DQS# falling setup to CK, CK# rising
tDSS
0.2
–
0.18
–
CK
25
DQS, DQS# falling hold from CK, CK# rising
tDSH
0.2
–
0.18
–
CK
25
DQS, DQS# differential WRITE preamble
tWPRE
0.9
–
0.9
–
CK
DQS, DQS# differential WRITE postamble
tWPST
0.3
–
0.3
–
CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
tDQSCK
–255
255
–225
225
ps
23
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
tDQSCK
1
10
1
10
ns
26
(DLL_DIS)
DQS, DQS# differential output high time
tQSH
0.40
–
0.40
–
CK
21
DQS, DQS# differential output low time
tQSL
0.40
–
0.40
–
CK
21
DQS, DQS# Low-Z time (RL - 1)
tLZ
(DQS)
–500
250
–450
225
ps
22, 23
DQS, DQS# High-Z time (RL + BL/2)
tHZ
(DQS)
–
250
–
225
ps
22, 23
DQS, DQS# differential READ preamble
tRPRE
0.9
Note 24
0.9
Note 24
CK
23, 24
DQS, DQS# differential READ postamble
tRPST
0.3
Note 27
0.3
Note 27
CK
23, 27
512
–
CK
28
Command and Address Timing
tDLLK
DLL locking time
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
CTRL, CMD, ADDR hold
from CK,CK#
VREF @ 1 V/ns
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
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512
–
tIS
65
–
45
–
ps
29, 30
(AC175)
240
–
220
–
ps
20, 30
tIS
190
–
170
–
ps
29, 30
(AC150)
340
–
320
–
ps
20, 30
tIH
140
–
120
–
ps
29, 30
(DC100)
240
–
220
–
ps
20, 30
10
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3L-1600
gDDR3L-1800
Symbol
Min
Max
Min
Max
Unit
Notes
Minimum CTRL, CMD, ADDR pulse width
tIPW
620
–
560
–
ps
41
ACTIVATE to internal READ or WRITE delay
tRCD
See corresponding speed bin table for
tRCD
ns
31
tRP
See corresponding speed bin table for
tRP
ns
31
tRAS
See corresponding speed bin table for
tRAS
ns
31, 32
tRC
See corresponding speed bin table for
tRC
ns
31
ACTIVATE-to-ACTIVATE
minimum command period
tRRD
MIN = greater of 4CK or 7.5ns
CK
31
Four ACTIVATE
windows
tFAW
ns
31
Parameter
PRECHARGE command period
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
45
–
40
–
tWR
MIN = 15ns; MAX = N/A
ns
31, 32,
33
tWTR
MIN = greater of 4CK or 7.5ns; MAX =
N/A
CK
31, 34
tRTP
MIN = greater of 4CK or 7.5ns; MAX =
N/A
CK
31, 32
CAS#-to-CAS# command delay
tCCD
MIN = 4CK; MAX = N/A
CK
Auto precharge write recovery + precharge time
tDAL
MODE REGISTER SET command cycle time
tMRD
MIN = 4CK; MAX = N/A
CK
MODE REGISTER SET command update delay
tMOD
MIN = greater of 12CK or 15ns; MAX =
N/A
CK
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register exit
tMPRR
MIN = 1CK; MAX = N/A
CK
Write recovery time
Delay from start of internal WRITE transaction
to internal READ command
READ-to-PRECHARGE time
MIN = WR +
tRP/tCK
(AVG); MAX = N/A
CK
Calibration Timing
ZQCL command: Long
calibration time
tZQ
POWER-UP and
RESET operation
Normal operation
INIT
512
OPER
tZQ
tZQCS
ZQCS command: Short calibration time
–
512
CK
256
–
256
CK
64
–
64
CK
Initialization and Reset Timing
tXPR
MIN = greater of 5CK or tRFC + 10ns;
MAX = N/A
CK
tVDDPR
MIN = N/A; MAX = 200
ms
RESET# LOW to power supplies stable
tRPS
MIN = 0; MAX = 200
ms
RESET# LOW to I/O and RTT High-Z
tIOZ
MIN = N/A; MAX = 20
ns
Exit reset from CKE HIGH to a valid command
Begin power supply ramp to power supplies stable
35
Refresh Timing
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter
Symbol
gDDR3L-1600
gDDR3L-1800
Min
Min
Max
Max
Unit
Notes
tRFC
MIN = 260; MAX = 70,200
ns
–
64 (1X)
ms
36
32 (2X)
ms
36
7.8 (64ms/8192)
µs
36
3.9 (32ms/8192)
µs
36
tXS
MIN = greater of 5CK or tRFC + 10ns;
MAX = N/A
CK
Exit self refresh to commands requiring a
locked DLL
tXSDLL
MIN = tDLLK (MIN);
MAX = N/A
CK
Minimum CKE low pulse width for self refresh
entry to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + CK; MAX = N/A
CK
REFRESH-to-ACTIVATE or REFRESH
command period
Maximum refresh
period
Maximum average
periodic refresh
TC ≤ 85°C
TC > 85°C
TC ≤ 85°C
tREFI
TC > 85°C
Self Refresh Timing
Exit self refresh to commands not requiring a
locked DLL
28
(should be
CKSRE??)
Valid clocks after self refresh entry or powerdown entry
tCKSRE
MIN = greater of 5CK or 10ns; MAX =
N/A
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
tCKSRX
MIN = greater of 5CK or 10ns; MAX =
N/A
CK
Power-Down Timing
tCKE
CKE MIN pulse width
(MIN)
Greater of 3CK or
5.625ns
Greater of 3CK or
5ns
CK
tCPDED
MIN = 1;
MAX = N/A
CK
tPD
MIN = tCKE (MIN);
MAX = 60ms
CK
tANPD
WL - 1CK
CK
Power-down entry period: ODT either
synchronous or asynchronous
PDE
Greater of tANPD or tRFC - REFRESH
command to CKE LOW time
CK
Power-down exit period: ODT either
synchronous or asynchronous
PDX
Command pass disable delay
Power-down entry to power-down exit timing
Begin power-down period prior to CKE
registered HIGH
tANPD
+ tXPDLL
CK
Power-Down Entry Minimum Timing
ACTIVATE command to power-down entry
tACTPDEN
MIN = 1
CK
PRECHARGE/PRECHARGE ALL command to
power-down entry
tPRPDEN
MIN = 1
CK
REFRESH command to power-down entry
tREFPDEN
MIN = 1
CK
MRS command to power-down entry
tMRSPDEN
MIN = tMOD (MIN)
CK
tRDPDEN
MIN = RL + 4 + 1
CK
READ/READ with auto precharge command to
power-down entry
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12
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
Table 7: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
gDDR3L-1600
Parameter
Symbol
Max
Min
Unit
MIN = WL + 4 +
(AVG)
CK
tWRPDEN
MIN = WL + 2 + tWR/tCK (AVG)
CK
BL8 (OTF, MRS)
BC4OTF
tWRAPDEN
MIN = WL + 4 + WR + 1
CK
BC4MRS
tWRAPDEN
MIN = WL + 2 + WR + 1
CK
BC4MRS
tWR/tCK
Max
tWRPDEN
WRITE command to pow- BL8 (OTF, MRS)
er-down entry
BC4OTF
WRITE with auto precharge command to
power-down entry
Min
gDDR3L-1800
Notes
Power-Down Exit Timing
DLL on, any valid command, or DLL off to
commands not requiring locked DLL
Precharge power-down with DLL off to
commands requiring a locked DLL
tXP
MIN = greater of 3CK or 6ns;
MAX = N/A
CK
tXPDLL
MIN = greater of 10CK or 24ns;
MAX = N/A
CK
28
CWL + AL - 2CK
CK
38
ODT Timing
RTT synchronous turn-on delay
ODTL on
RTT synchronous turn-off delay
ODTL off
CK
40
RTT turn-on from ODTL on reference
tAON
–250
CWL + AL - 2CK
250
–225
225
ps
23, 38
RTT turn-off from ODTL off reference
tAOF
0.3
0.7
0.3
0.7
CK
39, 40
Asynchronous RTT turn-on delay
(power-down with DLL off)
tAONPD
MIN = 2; MAX = 8.5
ns
38
Asynchronous RTT turn-off delay
(power-down with DLL off)
tAOFPD
MIN = 2; MAX = 8.5
ns
40
ODT HIGH time with WRITE command and BL8
ODTH8
MIN = 6; MAX = N/A
CK
ODT HIGH time without WRITE command or
with WRITE command and BC4
ODTH4
MIN = 4; MAX = N/A
CK
Dynamic ODT Timing
RTT,nom-to-RTT(WR) change skew
ODTLcnw
WL - 2CK
CK
RTT(WR)-to-RTT,nom change skew - BC4
ODTLcnw4
4CK + ODTLoff
CK
RTT(WR)-to-RTT,nom change skew - BL8
ODTLcnw8
6CK + ODTLoff
CK
tADC
RTT dynamic change skew
0.3
0.7
0.3
0.7
CK
39
Write Leveling Timing
tWLMRD
40
–
40
–
CK
tWLDQSEN
25
–
25
–
CK
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
195
–
165
–
ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
195
–
165
–
ps
Write leveling output delay
tWLO
0
9
0
7.5
ns
Write leveling output error
tWLOE
0
2
0
2
ns
First DQS, DQS# rising edge
DQS, DQS# delay
Notes:
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1. Parameters are applicable with 0°C ≤ TC ≤ 95°C and VDD/VDDQ = 1.35V (1.283–1.45V).
13
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
2. All voltages are referenced to VSS.
3. Output timings are only valid for RON34 output buffer selection.
4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points, and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC).
6. All timings that use time-based values (ns, µs, ms) should use tCK (AVG) to determine the
correct number of clocks (this table uses CK or tCK [AVG] interchangeably). In the case of
noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer.
7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
8. This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ/2 for single-ended signals and the crossing point for differential signals.
9. When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
11. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
13. The period jitter (tJITPER) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge.
16. The cycle-to-cycle jitter tJITCC is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error tERRnPER, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
differential DQS, DQS# slew rate.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJITPER (larger of tJITPER (MIN) or tJITPER (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX): tDQSCK
(MIN), tLZ(DQS) MIN, tLZ(DQ) MIN, and tAON (MIN). The following parameters are required to be derated by subtracting tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ
(DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by
subtracting tJITPER (MAX), while tRPRE (MAX) is derated by subtracting tJITPER (MIN).
24. The maximum preamble is bound by tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied because these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
28. Commands requiring a locked DLL are READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met.
29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM
[ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 15ns, the device will
support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR.
34. The start of the write recovery time is defined as follows:
35.
36.
37.
38.
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• For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity.
The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an average refresh rate of 7.8125µs. However, nine REFRESH commands should be asserted at
least once every 70.3µs. When TC is greater than 85°C, the refresh period is 32ms.
Although CKE is allowed to be registered LOW after a REFRESH command when
tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)
is required.
ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on.
15
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
39. Half-clock output parameters must be derated by the actual tERR10PER and tJITDTY when
input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR
t
t
t
10PER (MAX) and JITDTY (MAX). The parameters ADC (MAX) and AOF (MAX) are ret
t
quired to be derated by subtracting both ERR10PER (MAX) and JITDTY (MAX).
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z.
41. Pulse width of an input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by an AUTO PRECHARGE command.
PDF: 09005aef84b213dd
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Command and Address Setup, Hold, and Derating
Command and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated by adding the data
sheet tIS (base) and tIH (base) values to the ΔtIS and ΔtIH derating values, respectively.
Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition, the input signal
has to remain above/below V IH(AC)/VIL(AC) for some time tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH(AC)/VIL(AC).
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tIS) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and
the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal slew
rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between
the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal
from the AC level to the DC level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and
the first crossing of V REF(DC). If the actual signal is always later than the nominal slew
rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to the V REF(DC) level is used for derating value.
Table 8: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
Symbol
gDDR3L-1600
gDDR3L-1800
Unit
Reference
(base) AC175
65
45
ps
VIH(AC)/VIL(AC)
(base) AC150
190
170
ps
VIH(AC)/VIL(AC)
(base) AC135
–
–
ps
VIH(AC)/VIL(AC)
tIS
(base) AC125
–
–
ps
VIH(AC)/VIL(AC)
tIH
(base) DC100
140
120
ps
VIH(DC)/VIL(DC)
tIS
tIS
tIS
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4Gb: x16 gDDR3L SDRAM Graphics Addendum
Data Setup, Hold, and Derating
Data Setup, Hold, and Derating
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values to the ΔtDS and ΔtDH derating values, respectively. Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the input signal has to remain above/below V IH(AC)/VIL(AC) for some time tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC)) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH/VIL(AC).
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC)
and the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for
derating value. If the actual signal is later than the nominal slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min
and the first crossing of V REF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere
between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual
signal from the DC-to-VREF(DC) region is used for derating value.
Table 9: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
Symbol
tDS
tDS
tDS
tDH
gDDR3L-1600
gDDR3L-1800
Unit
Reference
(base) AC175
–
–
ps
VIH(AC)/VIL(AC)
(base) AC150
30
10
ps
VIH(AC)/VIL(AC)
(base) AC135
60
40
ps
VIH(AC)/VIL(AC)
(base) DC100
65
45
ps
VIH(DC)/VIL(DC)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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