CSR µEnergy® CSR1010D QFN Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Bluetooth Smart IC for Lighting Production Information CSR1010A05-DQQM-R Issue 3 General Description Applications CSR1010D QFN is a CSR µEnergy platform device. CSR µEnergy are CSR's single-mode Bluetooth low energy products for the Bluetooth Smart market. CSR1010D QFN increases application code and data space for greater application development flexibility. CSR μEnergy enables ultra low-power connectivity and basic data transfer for applications previously limited by the power consumption, size constraints and complexity of other wireless standards. CSR1010D QFN provides everything required to create a Bluetooth low energy product with RF, baseband, MCU, qualified Bluetooth v4.1 specification stack and customer application running on a single IC. CSR is the industry leader for Bluetooth low energy, also known as Bluetooth Smart. Bluetooth Smart enables connectivity and data transfer to leading smartphone, tablet and personal computing devices including Apple iPhone, iPad, iPod and Mac products and leading Android devices. Building a smart lighting ecosystem using Bluetooth low energy and CSRmesh™ Bluetooth low energy takes less time to make a connection than conventional Bluetooth wireless technology and can consume approximately 1/20th of the power of Bluetooth Basic Rate. CSRmesh places the smartphone at the centre of the Internet of Things allowing an almost unlimited number of Bluetooth Smart enabled devices to be simply networked together and controlled directly from a single smartphone, tablet or PC. CSR1010D QFN supports CSRmesh and standard Bluetooth Smart applications including: ■ CSRmesh: ■ Internet of Things control ■ Smart home: lighting, heating, appliance and security control ■ Bluetooth Smart: ■ HID: keyboards, mice, touchpads, remote controls ■ Sports and fitness sensors: heart rate, runner speed and cadence, cycle speed and cadence ■ Health sensors: blood pressure, thermometer and glucose meters ■ Mobile accessories: watches, proximity tags, alert tags and camera controls ■ Smart home: lighting, heating, appliances and security Bluetooth LE Radio and Modem MCU I/O UART LED PWM PIO 16MHz 32kHz ROM AIO RAM Debug Clock Generation I 2C / SPI ■ Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 1 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet ■ ■ ■ ■ Bluetooth® v4.1 specification compliant Bluetooth Smart 128KB memory: 64KB RAM and 64KB ROM Support for Bluetooth v4.1 specification host stack including ATT, GATT, SMP, L2CAP, GAP RSSI monitoring for proximity applications <900nA current consumption in dormant mode 15,000 hours of continuous lifetime reliability tested Qualified up to 105°C 32kHz and 16MHz crystal or system clock Switch-mode power supply Programmable general purpose PIO controller 10-bit ADC 12 digital PIOs 3 analogue AIOs UART I²C / SPI for EEPROM / flash memory ICs and peripherals Debug SPI 4 PWM modules Wake-up interrupt and watchdog timer QFN 32-lead, 5 x 5 x 0.6mm, 0.5mm pitch Ordering Information Package Device CSR1010D QFN Type Size Shipment Method QFN‑32-lead (Pb free) 5 x 5 x 0.6mm 0.5mm pitch Tape and reel Order Number CSR1010A05-DQQM-R Note: Minimum order quantity is 4kpcs taped and reeled. Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative. CSR1010D QFN Development Kit Ordering Information Order Number CSR1010D QFN Development Kit example design for software development only DK-CSR1010-10136-1A CSRmesh™ Development Kit for lighting applications DK-CSR1010-10184-1A CSR1010D QFN Data Sheet Description Contacts General information Information on this product Customer support for this product Details of compliance and standards Help with this document www.csr.com [email protected] www.csrsupport.com [email protected] [email protected] Chip Marking Figure shows the CSR1010D QFN chip markings. Note: Marking method is laser and all markings are centre-justified. 1010D A05U YWWAA G-TW-0013689.1.2 csr Figure : Chip Marking Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 2 of 50 CS-315158-DSP3 www.csr.com ■ ■ ■ ■ Location dot: Identifying pin 1 1st row: CSR logo or text 2nd and 3rd row: Device type ■ 1010D = 1010 (4-digit part number) + D (defined temperature range) ■ A05U = A05 (die revision) + U (green and Pb-free) 4th row: Trace code ■ YWWAA = Y (assembly year's last digit) + WW (assembly week) + AA (lot number) CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 3 of 50 CS-315158-DSP3 www.csr.com Device Details Synthesiser Fully integrated synthesiser requires no external VCO varactor diode, resonator or loop filter Baseband and Software ■ Hardware MAC for all packet types enables packet handling without the need to involve the MCU Physical Interfaces ■ SPI master interface ■ SPI programming and debug interface ■ I²C ■ 12 digital PIOs ■ 3 analogue AIOs ■ UART Auxiliary Features ■ Battery monitor ■ Power management features include software shutdown and hardware wake-up ■ CSR1010D QFN can run in low power modes from an external 32.768kHz clock signal ■ Integrated switch-mode power supply ■ Linear regulator (internal use only) ■ Power-on-reset cell detects low supply voltage Package ■ 32-lead 5 x 5 x 0.6mm, 0.5mm pitch QFN ■ Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 4 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Bluetooth Radio ■ On-chip balun (50Ω impedance in TX and RX modes) ■ No external trimming is required in production ■ Bluetooth v4.1 specification compliant Bluetooth Transmitter ■ 9dBm RF transmit power with level control from integrated 6-bit DAC over a dynamic range >25dB ■ No external power amplifier or TX/RX switch required Bluetooth Receiver ■ -93dBm sensitivity ■ Integrated channel filters ■ Digital demodulator for improved sensitivity and cochannel rejection ■ Fast AGC for enhanced dynamic range Bluetooth Stack CSR's protocol stack runs on the integrated MCU: ■ Support for Bluetooth v4.1 specification features: ■ Master and slave operation ■ Including encryption ■ Software stack in firmware includes: ■ GAP ■ L2CAP ■ Security manager ■ Attribute protocol ■ Attribute profile ■ Bluetooth low energy profile support Functional Block Diagram RF XTAL_16M XTAL_32K Bluetooth Radio Clock Generation I/O Bluetooth LE Modem and LC Wake-up UART I2C / SPI Serial Flash DMA CSR1010D QFN Data Sheet RAM 64KB I2C / SPI Serial Flash I2C EEPROM SPI Serial Flash PIO and LED PWM RAM Arbiter AES-CCS and AES Encryption PIO AUX / CLK / PSU Control Memory Protection VDD_PADS Control State Machine Code Data MCU Interrupt ROM Debug Debug Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement LDO SMPU VDDREG_IN VDD_BAT G-TW-0005362.9.2 Timer Page 5 of 50 CS-315158-DSP3 www.csr.com Document History Revision Date Change Reason 1 07 JUL 14 Original publication of this document. 2 10 OCT 14 Updated Product Reliability information. 3 06 JAN 15 Updates include: ■ Section 3 Clock Generation ■ Section 4 Operating Modes. ■ Section 5 Microcontroller, Memory and Baseband Logic. ■ Section 6 Serial Interfaces. ■ Section 7 Power Control and Regulation. ■ Section 8 Example Application Schematic. ■ Section 9 Electrical Characteristics. ■ Section 10 Current Consumption. ■ Other minor updates. CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 6 of 50 CS-315158-DSP3 www.csr.com Status Information Device Implementation Important Note: As the feature-set of the CSR1010D QFN is firmware build-specific, see the relevant software release note for the exact implementation of features on the CSR1010D QFN. Life Support Policy and Use in Safety-critical Applications CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. CSR Green Semiconductor Products and RoHS Compliance CSR1010D QFN devices meet the requirements of Directive 2011/65/EU of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). CSR1010D QFN devices are free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products. Trademarks, Patents and Licences Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by CSR plc or its affiliates. Bluetooth ® and the Bluetooth ® logos are trademarks owned by Bluetooth ® SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc and/or its affiliates. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. Refer to www.csrsupport.com for compliance and conformance to standards information. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 7 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format: ■ Advance Information: ■ Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. ■ Engineering Sample: ■ Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. ■ All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. ■ Pre-production Information: ■ Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. ■ All electrical specifications may be changed by CSR without notice. ■ Production Information: ■ Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. ■ Production Data Sheets supersede all previous document versions. Contents 1 2 4 5 6 Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 8 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet 3 Ordering Information ........................................................................................................................................... 2 CSR1010D QFN Development Kit Ordering Information ........................................................................... 2 Contacts ..................................................................................................................................................... 2 Chip Marking .............................................................................................................................................. 2 Device Details ..................................................................................................................................................... 4 Functional Block Diagram .................................................................................................................................. 5 Package Information ......................................................................................................................................... 11 1.1 Pinout Diagram ........................................................................................................................................ 11 1.2 Device Terminal Functions ....................................................................................................................... 12 1.3 Package Dimensions ............................................................................................................................... 15 1.4 PCB Design and Assembly Considerations ............................................................................................. 16 1.5 Typical Solder Reflow Profile ................................................................................................................... 16 Bluetooth Modem .............................................................................................................................................. 17 2.1 RF Ports ................................................................................................................................................... 17 2.2 RF Receiver ............................................................................................................................................. 17 2.2.1 Low Noise Amplifier .................................................................................................................... 17 2.2.2 RSSI Analogue to Digital Converter ........................................................................................... 17 2.3 RF Transmitter ......................................................................................................................................... 17 2.3.1 IQ Modulator ............................................................................................................................... 17 2.3.2 Power Amplifier .......................................................................................................................... 17 2.4 Bluetooth Radio Synthesiser .................................................................................................................... 17 2.5 Baseband ................................................................................................................................................. 17 2.5.1 Physical Layer Hardware Engine ............................................................................................... 17 Clock Generation ............................................................................................................................................... 18 3.1 Clock Architecture .................................................................................................................................... 18 3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT .......................................................................... 18 3.2.1 Crystal Specification ................................................................................................................... 18 3.2.2 Frequency Trim .......................................................................................................................... 19 3.3 Sleep Clock .............................................................................................................................................. 19 3.3.1 Crystal Specification ................................................................................................................... 19 Operating Modes ............................................................................................................................................... 21 4.1 Run Mode ................................................................................................................................................. 21 4.2 Idle Mode ................................................................................................................................................. 21 4.3 Deep Sleep Mode .................................................................................................................................... 21 4.4 Hibernate Mode ........................................................................................................................................ 21 4.5 Dormant Mode ......................................................................................................................................... 21 Microcontroller, Memory and Baseband Logic .................................................................................................. 22 5.1 System RAM ............................................................................................................................................ 22 5.2 Internal ROM ........................................................................................................................................... 22 5.3 Microcontroller .......................................................................................................................................... 22 5.4 Programmable I/O Ports, PIO and AIO .................................................................................................... 22 5.5 LED Flasher / PWM Module ..................................................................................................................... 23 5.6 Temperature Sensor ................................................................................................................................ 24 5.7 Battery Monitor ......................................................................................................................................... 25 Serial Interfaces ................................................................................................................................................ 26 6.1 Application Interface ................................................................................................................................. 26 6.1.1 UART Interface ........................................................................................................................... 26 6.2 I²C Interface ............................................................................................................................................. 26 6.3 SPI Master Interface ................................................................................................................................ 28 6.4 List of Figures Figure 1.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 13.1 Figure 14.1 Figure 14.2 Figure 14.3 Pinout Diagram .................................................................................................................................... 11 Clock Architecture ................................................................................................................................ 18 Crystal Driver Circuit ............................................................................................................................ 18 Sleep Clock Crystal Driver Circuit ........................................................................................................ 19 Baseband Digits Block Diagram .......................................................................................................... 22 Typical PWM Signal on a PIO ............................................................................................................. 24 Example of an I²C Interface EEPROM Connection ............................................................................. 27 I²C Standard Mode 100 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) ............................. 27 I²C Fast Mode 400 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) .................................... 28 SPI Timing Diagram ............................................................................................................................. 29 Memory Boot-up Sequence ................................................................................................................. 30 Voltage Regulator Configuration .......................................................................................................... 32 Software Architecture .......................................................................................................................... 43 Tape Orientation .................................................................................................................................. 44 Tape Dimensions ................................................................................................................................. 45 Reel Dimensions .................................................................................................................................. 46 Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 9 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Programming and Debug Interface .......................................................................................................... 30 6.4.1 Instruction Cycle ......................................................................................................................... 30 6.4.2 Multi-slave Operation .................................................................................................................. 31 7 Power Control and Regulation .......................................................................................................................... 32 7.1 Switch-mode Regulator ............................................................................................................................ 32 7.2 Low-voltage VDD_CORE Linear Regulator ............................................................................................. 32 7.3 Reset ........................................................................................................................................................ 32 7.3.1 Digital Pin States on Reset ......................................................................................................... 32 7.3.2 Power-on Reset .......................................................................................................................... 33 8 Example Application Schematic ........................................................................................................................ 34 9 Electrical Characteristics ................................................................................................................................... 35 9.1 Absolute Maximum Ratings ..................................................................................................................... 35 9.2 Recommended Operating Conditions ...................................................................................................... 35 9.3 Input/Output Terminal Characteristics ...................................................................................................... 36 9.3.1 Switch-mode Regulator .............................................................................................................. 36 9.3.2 Low-voltage Linear Regulator ..................................................................................................... 36 9.3.3 Digital Terminals ......................................................................................................................... 36 9.3.4 AIO ............................................................................................................................................. 37 9.4 Junction Temperature .............................................................................................................................. 39 9.5 ESD Protection ......................................................................................................................................... 39 10 Current Consumption ........................................................................................................................................ 40 11 Product Reliability Tests .................................................................................................................................... 41 11.1 Die Test .................................................................................................................................................... 41 12 CSR Green Semiconductor Products and RoHS Compliance .......................................................................... 42 13 CSR1010D QFN Software Stack ...................................................................................................................... 43 14 Tape and Reel Information ................................................................................................................................ 44 14.1 Tape Orientation ...................................................................................................................................... 44 14.2 Tape Dimensions ..................................................................................................................................... 45 14.3 Reel Information ....................................................................................................................................... 46 14.4 Moisture Sensitivity Level ......................................................................................................................... 46 15 Document References ....................................................................................................................................... 47 Terms and Definitions ................................................................................................................................................ 48 List of Tables Crystal Specification ............................................................................................................................. 19 Sleep Clock Specification ..................................................................................................................... 20 Wake Options for Sleep Modes ............................................................................................................ 23 Alternative PIO Functions ..................................................................................................................... 23 PWM Operating Range ......................................................................................................................... 24 Possible UART Settings ....................................................................................................................... 26 I²C Standard Mode 100 kHz Timing Definition ..................................................................................... 27 I²C Fast Mode 400 kHz Timing Definition ............................................................................................. 28 SPI Master Serial Flash Memory Interface ........................................................................................... 29 Instruction Cycle for a SPI Transaction ................................................................................................ 31 Pin States on Reset .............................................................................................................................. 33 Power-on Reset .................................................................................................................................... 33 Junction Temperature within Recommended Operating Conditions .................................................... 39 ESD Handling Ratings .......................................................................................................................... 39 Current Consumption ............................................................................................................................ 40 Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 10 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Table 3.1 Table 3.2 Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 7.1 Table 7.2 Table 9.1 Table 9.2 Table 10.1 1 1.1 Package Information Pinout Diagram Orientation from Top of Device 32 31 30 29 28 27 26 25 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 G-TW-0005350.6.1 24 CSR1010D QFN Data Sheet 1 Figure 1.1: Pinout Diagram Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 11 of 50 CS-315158-DSP3 www.csr.com 1.2 Device Terminal Functions Radio RF Lead 7 (a) Pad Type Supply Domain Description RF VDD_RADIO(a) Bluetooth transmitter / receiver. The VDD_RADIO domain is generated from VDD_REG_IN, see Figure 7.1. Synthesiser and Oscillator Lead Pad Type Supply Domain Description XTAL_32K_OUT 2 Analogue VDD_BAT Drive for sleep clock crystal. XTAL_32K_IN 3 Analogue VDD_BAT 32.768kHz sleep clock input. XTAL_16M_OUT 9 Analogue VDD_ANA(b) Drive for crystal. XTAL_16M_IN 10 Analogue VDD_ANA Reference clock input. The VDD_ANA domain is generated from VDD_REG_IN, see Figure 7.1. I²C Interface Lead Pad Type Supply Domain Description VDD_PADS I²C data input / output or SPI serial flash data output (SF_DOUT). If connecting to SPI serial flash, connect this pin to SO on the serial flash. See Section 6.3. I2C_SDA 29 Bidirectional, tristate, with weak internal pull-up I2C_SCL 28 Input with weak internal pull-up VDD_PADS I²C clock or SPI serial flash clock output (SF_CLK), see Section 6.3. PIO Port Lead Pad Type Supply Domain Description PIO[11] 25 PIO[10] 24 VDD_PADS Programmable I/O line. PIO[9] 23 Bidirectional with programmable strength internal pullup/down PIO[8] / DEBUG_MISO 22 PIO[7] / DEBUG_MOSI 20 PIO[6] / DEBUG_CS# 19 PIO[5] / DEBUG_CLK 18 Programmable I/O line or debug SPI MISO selected by SPI_PIO#. Bidirectional with programmable strength internal pullup/down Programmable I/O line or debug SPI MOSI selected by SPI_PIO#. VDD_PADS Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Programmable I/O line or debug SPI chip select (CS#) selected by SPI_PIO#. Programmable I/O line or debug SPI CLK selected by SPI_PIO#. Page 12 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet (b) PIO Port Lead PIO[4] / SF_CS# 17 PIO[3] / SF_DIN 16 27 PIO[1] / UART_RX 15 PIO[0] / UART_TX 14 AIO[2] 11 AIO[1] 12 AIO[0] 13 (c) Supply Domain Description Programmable I/O line or SPI serial flash chip select (SF_CS#), see Section 6.3. Bidirectional with programmable strength internal pullup/down VDD_PADS Programmable I/O line or SPI serial flash data (SF_DIN) input. If connecting to SPI serial flash, this pin connects to SI on the serial flash. See Section 6.3. Bidirectional with programmable strength internal pullup/down VDD_PADS Programmable I/O line or I²C power. Programmable I/O line or UART RX. Bidirectional with programmable strength internal pullup/down VDD_PADS Bidirectional analogue VDD_AUX(c) Programmable I/O line or UART TX. Analogue programmable I/O line. The VDD_AUX domain is generated from VDD_REG_IN, see Figure 7.1. Test and Debug Lead SPI_PIO# 26 Wake-up Lead WAKE 4 Pad Type Supply Domain Description Input with strong internal pull-down VDD_PADS Selects SPI debug on PIO[8:5]. Pad Type Supply Domain Description Input has no internal pull-up or pull-down, use external pulldown. VDD_BAT Input to wake CSR1010D QFN from hibernate or dormant. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 13 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet PIO[2] Pad Type Power Supplies and Control Lead Description VDD_BAT 1 Battery input and regulator enable (active high). VDD_BAT_SMPS 32 Input to high-voltage switch-mode regulator. SMPS_LX 31 High-voltage switch-mode regulator output. VDD_CORE 5, 30 VDD_PADS 21 Positive supply for all digital I/O ports PIO[11:0]. VDD_REG_IN 6 Positive supply for Bluetooth radio and digital linear regulator. VDD_XTAL 8 Decouple with 470nF capacitor to ground. VSS Exposed pad Positive supply for digital domain. Ground connections. CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 14 of 50 CS-315158-DSP3 www.csr.com 1.3 Package Dimensions // D A h C c C Seating Plane M 32 1 PIN 1 Corner M A1 A3 A2 A J g CAB S 25 P PIN 1 ID 32 24 Min Typ Max Dimension Min Typ Max A 0.50 0.55 0.60 e - 0.5 - A1 0 0.035 0.05 g - 0.1 - A2 - 0.4 0.425 h - 0.1 - A3 - 0.152 - J 3.1 3.2 3.3 b 0.20 0.25 0.30 K 3.1 3.2 3.3 c - 0.08 - L 0.35 0.40 0.45 D 4.9 5.0 5.1 P 0.3 - - d - 0.10 - R - 0.093 - E 4.9 5.0 5.1 S - 0.3 - 1 Notes 1. Description 32-lead Quad-flat No-lead Package Size 5 x 5 x 0.6mm JEDEC MO-220 Pitch 0.5 Units mm S Coplanarity applies to leads, corner leads and die attach pad. e/2 K g CAB 8 17 9 16 32X L 32X b R R Exposed Die Attach Pad dMCAB Bottom View View M-M Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement G-TW-0005351.4.3 e Page 15 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet E Top View Dimension C B 1.4 PCB Design and Assembly Considerations This section lists recommendations to achieve maximum board-level reliability of the 5 x 5 x 0.6mm QFN 32-lead package: ■ ■ ■ 1.5 NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation. CSR recommends that the PCB land pattern is in accordance with IPC standard IPC-7351. Solder paste must be used during the assembly process. Typical Solder Reflow Profile For information, see Typical Solder Reflow Profile for Lead-free Devices Information Note. CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 16 of 50 CS-315158-DSP3 www.csr.com 2 2.1 Bluetooth Modem RF Ports CSR1010D QFN contains an integrated balun which provides a single-ended RF TX / RX port pin. No matching components are needed as the receive mode impedance is 50Ω and the transmitter has been optimised to deliver power in to a 50Ω load. 2.2 RF Receiver The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and W‑CDMA cellular phone transmitters without being significantly desensitised. An ADC digitises the IF received signal. 2.2.1 Low Noise Amplifier The LNA operates in differential mode and takes its input from the balanced port of the integrated balun. 2.2.2 RSSI Analogue to Digital Converter 2.3 RF Transmitter 2.3.1 IQ Modulator The transmitter features a direct IQ modulator to minimise frequency drift during a transmit packet, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping. 2.3.2 Power Amplifier The internal PA has a maximum 9dBm output power without needing an external RF PA. 2.4 Bluetooth Radio Synthesiser The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v4.1 specification. 2.5 Baseband 2.5.1 Physical Layer Hardware Engine Dedicated logic performs: ■ Cyclic redundancy check ■ Encryption ■ Data whitening ■ Access code correlation The hardware supports all optional and mandatory features of Bluetooth v4.1 specification. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 17 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet The ADC samples the RSSI voltage on a packet-by-packet basis and implements a fast AGC. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference-limited environments. 3 Clock Generation The Bluetooth reference clock for the system is generated from an external 16MHz clock source, see Figure 3.1. All the CSR1010D QFN internal digital clocks are generated using a phase locked loop, which is locked to the frequency of either the external reference clock source or a sleep clock frequency of 32.768kHz, see Figure 3.1. Clock Architecture Bluetooth PLL Fast XTAL Clock for System Core Digits (16MHz) 32kHz Embedded Digits (32kHz) Figure 3.1: Clock Architecture 3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT CSR1010D QFN contains crystal driver circuits. This operates with an external crystal and capacitors to form a Pierce oscillator. Figure 3.2 shows the external crystal is connected to pins XTAL_16M_IN and XTAL_16M_OUT. - CLOAD1 CLOAD2 G-TW-0005348.1.1 XTAL_16M_IN XTAL_16M_OUT CTRIM Figure 3.2: Crystal Driver Circuit Note: CTRIM is the internal trimmable capacitance in Table 3.1. CLOAD1 and CLOAD2 in combination with CTRIM and any parasitic capacitance provide the load capacitance required by the crystal. 3.2.1 Crystal Specification Table 3.1 shows the specification for an external crystal. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 18 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Slow XTAL Clock for Sleep 16MHz Bluetooth LO (~4.8GHz) G-TW-0005266.2.2 3.1 Parameter Min Typ Max Unit Frequency - 16 - MHz Frequency tolerance (without trimming)(a) - - ±25 ppm Frequency trim range(b) - ±50 - ppm Drive level - 0.4 - V Equivalent series resistance - - 60 Ω Load capacitance - 9 - pF 10 - - ppm/pF Pullability Table 3.1: Crystal Specification Use integrated load capacitors to trim initial frequency tolerance in production or to trim frequency over temperature, increasing the allowable frequency tolerance. (b) Frequency trim range is dependent on crystal load capacitor values and crystal pullability. 3.2.2 Frequency Trim CSR1010D QFN contains variable integrated capacitors to allow for fine-tuning of the crystal resonant frequency. This firmware-programmable feature allows accurate trimming of crystals on a per-device basis on the production line. The resulting trim value is stored in non-volatile memory. 3.3 Sleep Clock The sleep clock is an externally provided 32.768kHz clock that is used during deep sleep and in other low-power modes. Figure 3.3 shows the sleep clock crystal driver circuit. CLOAD1 CLOAD2 G-TW-0005349.2.2 XTAL_32K_IN XTAL_32K_OUT - Figure 3.3: Sleep Clock Crystal Driver Circuit Note: CLOAD1 and CLOAD2 in combination with any parasitic capacitance provide the load capacitance required by the crystal. 3.3.1 Crystal Specification Table 3.2 shows the requirements for the sleep clock. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 19 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet (a) Sleep Clock Min Typ Max Units Frequency 30 32.768 35 kHz Frequency tolerance(a) (b) - - 250 ±ppm Frequency trim range - 50 - ±ppm Drive level - 0.4 - V Load capacitance - - 10 pF 40 - 65 kΩ 30:70 50:50 70:30 % Equivalent series resistance Duty cycle Table 3.2: Sleep Clock Specification The frequency of the slow clock is periodically calibrated against the system clock. As a result the rate of change of the frequency is more important than the maximum deviation. To meet the accuracy requirements the frequency should not drift due to temperature or other effects by more than 80ppm in any 5 minute period. (b) CSR1010D QFN can correct for ±1% by using the fast clock to calibrate the slow clock. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 20 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet (a) 4 Operating Modes CSR1010D QFN has 5 operating modes. 3 of these are sleep modes: ■ ■ ■ Running Idle Sleep modes: ■ Deep Sleep ■ Hibernate ■ Dormant For current consumption rates in the operating modes, see Section 10. 4.1 Run Mode In Run mode, all functions are on. RX and/or TX are active. 4.2 Idle Mode There is a <1μs wake-up time. 4.3 Deep Sleep Mode In Deep Sleep mode, the VDD_PADS and VDD_BAT domains are powered, the sleep clock is on but the reference clock is off, the RAM is on, the digital circuits are on and the SMPS is on (low-power mode). There is a configurable wake-up time. CSR1010D QFN is woken from Deep Sleep mode by any PIO configured to wake the IC. 4.4 Hibernate Mode In Hibernate mode, the VDD_PADS and VDD_BAT domains are powered and the sleep clock is on. The reference clock is off. CSR1010D QFN is woken from Hibernate mode by a selected level on the WAKE pin or by the watchdog timer. 4.5 Dormant Mode In Dormant mode, all functions are off. CSR1010D QFN is woken from Dormant mode by a selected level on the WAKE pin. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 21 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet In Idle mode, the VDD_PADS and VDD_BAT domains are powered, the reference clock and the sleep clock are powered, the RAM is powered and the digital circuits are powered. The MCU is idle. 5 Microcontroller, Memory and Baseband Logic ADCs Bluetooth and Auxiliary Analogue Control DACs Bluetooth low energy Modem and LC Wake-ups RAM Interface (Buffers, LUTs, Tables and State) AES-CCS and AES Encryption RAM Arbiter I/O RAM UART I2C / Serial Flash Serial Flash Memory Protection DMA PIO and LED PWM Code AUX / CLK / PSU Control Interrupt MCU Debug Debug PIOs Data I/O Control Logic Timer Figure 5.1: Baseband Digits Block Diagram 5.1 System RAM 64KB of integrated RAM supports the RISC MCU and is shared between the ring buffers used to hold data for each active connection, general-purpose memory required by the Bluetooth stack and the user application. 5.2 Internal ROM CSR1010D QFN has 64KB of internal ROM. This memory is provided for system firmware implementation. If the internal ROM holds valid program code, on boot-up, this is copied into the program RAM. Code then executes from ROM and RAM. 5.3 Microcontroller The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and external interfaces. A 16-bit RISC microcontroller is used for low power consumption and efficient use of memory. 5.4 Programmable I/O Ports, PIO and AIO 12 lines of programmable bidirectional I/O are provided. They are all powered from VDD_PADS. PIO lines are software-configurable as weak pull-up, weak pull-down, strong pull-up or strong pull-down. Note: At reset all PIO lines are inputs with weak pull-downs. Any of the PIO lines can be configured as interrupt request lines or to wake the IC from deep sleep mode. Table 5.1 lists the options for waking the IC from the sleep modes. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 22 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet I2C / Serial Flash G-TW-0005354.3.2 I2C EEPROM Sleep Mode Wake-up Options Dormant Can only be woken by the WAKE pin. Hibernate Can be woken by the WAKE pin or by the watchdog timer. Deep Sleep Can be woken by any PIO configured to wake the IC. Table 5.1: Wake Options for Sleep Modes The CSR1010D QFN supports alternative functions on the PIO lines, for example: ■ SPI interface, see Section 1.2 and Section 6.4 ■ UART, see Section 1.2 and Section 6.1.1 ■ LED flasher / PWM module, see Section 5.5 Table 5.2 shows the alternative functions on the PIO lines. Function PIO SPI Flash UART PIO[8] DEBUG_MISO - - PIO[7] DEBUG_MOSI - - PIO[6] DEBUG_CS# - - PIO[5] DEBUG_CLK - - PIO[4] - SF_CS# - PIO[3] - SF_DIN - PIO[2] - - - PIO[1] - - UART_RX PIO[0] - - UART_TX CSR1010D QFN Data Sheet Debug SPI Table 5.2: Alternative PIO Functions Note: CSR cannot guarantee that the PIO assignments remain as described. Implementation of the PIO lines is firmware build-specific, for more information see the relevant software release note. CSR1010D QFN has 3 general-purpose analogue interface pins, AIO[2:0]. 5.5 LED Flasher / PWM Module CSR1010D QFN contains an LED flasher / PWM module. Note: The LED flasher functions in Deep Sleep and Active modes only. The PWM functions in all modes except Hibernate and Dormant. These functions are controlled by the on-chip firmware. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 23 of 50 CS-315158-DSP3 www.csr.com Figure 5.2 shows a typical PWM signal on a PIO. For more information, see CSR µEnergy Pulse Width Modulation Application Note. PWM output governed by the timings setup for the brightest part of the pulse sequence T off Ton (bright ) (bright ) T off T on (bright ) (bright ) A mp litud e T hold (bright ) – Duration for which the PWM output is held in the brightest part of the pulse sequence Hold Time (Bright ) PWM output while ramping from brightest to dullest Highest Varying Duty Duty Cycle Cycle (Bright to Dull) Ramp T ramp - Duration of the ramping and the number of pulses and their widths during ramping is proportional to the ramping rate Lowest Varying Duty Duty Cycle Cycle ( Dull to Bright ) Time PWM output governed by the timings setup for the dullest part of the pulse sequence Toff (dull ) (d ull ) T on PWM output while ramping from dullest to brightest T off (dull ) (dull ) T hold (dull ) – Duration for which the PWM output is held in the dullest part of the pulse sequence Tramp - Duration of the ramping, the number of pulses and their widths during ramping is proportional to the ramping rate G-TW-0013938.1.3 To n Figure 5.2: Typical PWM Signal on a PIO Figure 5.2 lists PWM the operating range. Parameter Min Max Unit Off Time (Toff) 30.5 7782 µs On Time (Ton) 30.5 7782 µs Hold Time (Thold) 16 4080 ms Duty Cycle = On Time (Ton) + Off Time (Toff) 61 15564 µs Frequency = 1 / Duty Cycle 64.3 16320 Hz Table 5.3: PWM Operating Range 5.6 Temperature Sensor CSR1010D QFN contains a temperature sensor that measures the temperature of the die to an accuracy of ±1 °C. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 24 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Hold Time (Dull) 5.7 Battery Monitor CSR1010D QFN contains an internal battery monitor that reports the battery voltage to the software. CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 25 of 50 CS-315158-DSP3 www.csr.com 6 Serial Interfaces 6.1 Application Interface 6.1.1 UART Interface The CSR1010D QFN UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. 2 signals implement the UART function, UART_TX and UART_RX. When CSR1010D QFN is connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. UART configuration parameters, e.g. baud rate and data format, are set using CSR1010D QFN firmware. When selected in firmware PIO[0] is assigned to a UART_TX output and PIO[1] is assigned to a UART_RX input, see Section 1.2. Note: To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated serial port adapter card. Parameter Baud rate Possible Values Minimum Maximum Parity 2400 baud (≤2%Error) 9600 baud (≤2%Error) 3.69Mbaud (≤0.1%Error) None, Odd or Even Number of stop bits 1 or 2 Bits per byte 8 Table 6.1: Possible UART Settings 6.1.1.1 UART Configuration While in Deep Sleep The maximum baud rate is 2400 baud during deep sleep. 6.2 I²C Interface The I²C interface communicates to EEPROM, external peripherals or sensors. An external EEPROM connection can hold the program code externally to the CSR1010D QFN. Figure 6.1 shows an example of an EEPROM connected to the I²C interface where I2C_SCL, I2C_SDA and PIO[2] are connected to the external EEPROM. The PIO[2] pin supplies the power to the EEPROM supply pin, e.g. VDD. At bootup, if there is no valid ROM image in the CSR1010D QFN ROM area the CSR1010D QFN tries to boot from the I²C interface, see Figure 6.5. This involves reading the code from the external EEPROM and loading it into the internal CSR1010D QFN RAM. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 26 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Table 6.1 shows the possible UART settings for the CSR1010D QFN. G-TW-0005553.1.1 Figure 6.1: Example of an I²C Interface EEPROM Connection Standard Mode 100 kHz Figure 6.2 shows I²C standard mode 100 kHz timing diagram. t SU;DAT tf tr 70 % 70% 30% 30% 30 % tf SCL tr 70 % 70% 30% SDA 30% Time G-TW-0013940.1.2 Amplitude tVD ;DAT Figure 6.2: I²C Standard Mode 100 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) Table 6.2 lists I²C standard mode 100 kHz timing definition. Parameter Symbol Min Max Unit Clock Rate fSCL - 100 kHz SCL: Rise-time (30% to 70%) tr - 50.3 ns SCL: Fall-time (70% to 30%) tf - 0.9 ns SDA: Rise-time (30% to 70%) tr - 55.3 ns SDA: Fall-time (70% to 30%) tf - 0.7 ns Data set-up time tSU;DAT 2511 - ns Data valid time tVD;DAT - 2.5 µs Table 6.2: I²C Standard Mode 100 kHz Timing Definition Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 27 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet 1 / f SCL Fast Mode 400 kHz Figure 6.3 shows I²C fast mode 400 kHz timing diagram. 1 / f SCL t SU;DAT tf tr 70 % 70% 30 % 30% SCL 30% tf tr 70% 70% 30 % SDA 30 % Time G-TW-0013941.1.2 Amplitude tVD ;DAT Table 6.3 lists I²C fast mode 400 kHz timing definition. Parameter Symbol Min Max Unit Clock Rate fSCL - 400 kHz SCL: Rise-time (30% to 70%) tr 41.4 50.6 ns SCL: Fall-time (70% to 30%) tf 0.7 0.9 ns SDA: Rise-time (30% to 70%) tr 46.0 55.9 ns SDA: Fall-time (70% to 30%) tf 0.5 0.7 ns Data set-up time tSU;DAT 573 - ns Data valid time tVD;DAT - 0.56 µs Table 6.3: I²C Fast Mode 400 kHz Timing Definition 6.3 SPI Master Interface The SPI master memory interface in the CSR1010D QFN is overlaid on the I²C interface and uses a further 3 PIOs for the extra pins, see Table 6.4. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 28 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Figure 6.3: I²C Fast Mode 400 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) SPI Flash Interface Pin Flash_VDD PIO[2] SF_DIN PIO[3] SF_CS# PIO[4] SF_CLK I2C_SCL SF_DOUT I2C_SDA Table 6.4: SPI Master Serial Flash Memory Interface Note: If an application using CSR1010D QFN is designed to boot from SPI serial flash, it is possible for the firmware to map the I²C interface to alternative PIOs. Figure 6.4 shows simple SPI timing diagram. SF_DOUT MSB LSB SF_DIN MSB LSB G-TW-0012787.1.1 SF_CLK Figure 6.4: SPI Timing Diagram The boot-up sequence for CSR1010D QFN is controlled by hardware and firmware. Figure 6.5 shows the sequence of loading RAM with content from RAM, EEPROM and SPI serial flash. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 29 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet SF_CS# Device Starts Hardware Copies Content of ROM to RAM Hardware Checks I2C Interface (Default Pins) No Presence of EEPROM Device Presence of SPI Serial Flash Device Yes Copy Content of SPI Serial Flash to RAM Yes Copy Content of EEPROMto RAM Start MCU Executing fromRAM No Figure 6.5: Memory Boot-up Sequence 6.4 Programming and Debug Interface Important Note: The CSR1010D QFN debug SPI interface is available in SPI slave mode to enable an external MCU to program and control the CSR1010D QFN, generally via libraries or tools supplied by CSR. The protocol of this interface is proprietary. The 4 SPI debug lines directly support this function. The SPI programs, configures and debugs the CSR1010D QFN. It is required in production. Ensure the 4 SPI signals are brought out to either test points or a header. Take SPI_PIO#_SEL high to enable the SPI debug feature on PIO[8:5]. CSR1010D QFN uses a 16-bit data and 16-bit address programming and debug interface. Transactions occur when the internal processor is running or is stopped. Data is written or read one word at a time. Alternatively, the auto-increment feature is available for block access. 6.4.1 Instruction Cycle The CSR1010D QFN is the slave and receives commands on DEBUG_MOSI and outputs data on DEBUG_MISO. Table 6.5 shows the instruction cycle for a SPI transaction. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 30 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Hardware Checks SPI Interface (Default Pins) 1 Reset the SPI interface Hold DEBUG_CS# high for 2 DEBUG_CLK cycles 2 Write the command word Take DEBUG_CS# low and clock in the 8-bit command 3 Write the address Clock in the 16-bit address word 4 Write or read data words Clock in or out 16-bit data word(s) 5 Termination Take DEBUG_CS# high Table 6.5: Instruction Cycle for a SPI Transaction With the exception of reset, DEBUG_CS# must be held low during the transaction. Data on DEBUG_MOSI is clocked into the CSR1010D QFN on the rising edge of the clock line DEBUG_CLK. When reading, CSR1010D QFN replies to the master on DEBUG_MISO with the data changing on the falling edge of the DEBUG_CLK. The master provides the clock on DEBUG_CLK. The transaction is terminated by taking DEBUG_CS# high. 6.4.2 Multi-slave Operation Do not connect the CSR1010D QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines. When CSR1010D QFN is deselected (DEBUG_CS# = 1), the DEBUG_MISO line does not float. Instead, CSR1010D QFN outputs 0 if the processor is running or 1 if it is stopped. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 31 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet The auto increment operation on the CSR1010D QFN cuts down on the overhead of sending a command word and the address of a register for each read or write, especially when large amounts of data are to be transferred. The auto increment offers increased data transfer efficiency on the CSR1010D QFN. To invoke auto increment, DEBUG_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word written or read. 7 Power Control and Regulation CSR1010D QFN contains 2 regulators: ■ 1 switch-mode regulator, which generates the main supply rail from the battery ■ 1 low-voltage linear regulator Figure 7.1 shows the configuration for the power control and regulation with the CSR1010D QFN. SMPS_LX VDD_REG_IN Switch VDD _CORE Low-voltage VDD_CORE Linear Regulator Digits 0.65 /1.20 V Figure 7.1: Voltage Regulator Configuration 7.1 Switch-mode Regulator The switch-mode regulator generates the main rail from the battery supply, VDD_BAT_SMPS. The main rail supplies the lower regulated voltage to a further digital linear regulator and also to the analogue sections of the CSR1010D QFN. The switch-mode regulator generates typically 1.35V. 7.2 Low-voltage VDD_CORE Linear Regulator The integrated low-voltage VDD_CORE linear regulator powers the CSR1010D QFN digital circuits. The input voltage range is 0.65V to 1.35V. It can supply programmable voltages of 0.65V to 1.20V to the digital area of the CSR1010D QFN. The maximum output current for this regulator is 30mA. Connect a minimum 470nF low ESR capacitor, e.g. MLC, to the VDD_CORE output pin. Software controls the output voltage. Important Note: This regulator is only for CSR internal use. Section 8 shows CSR's recommended circuit connection. 7.3 Reset CSR1010D QFN is reset by: ■ ■ 7.3.1 Power-on reset Software-configured watchdog timer Digital Pin States on Reset Table 7.1 shows the pin states of CSR1010D QFN on reset. PU and PD default to weak values unless specified otherwise. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 32 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet VDD_RADIO 1.35 V VDD_ANA 1.35 V VDD_AUX 1.35 V Switch-mode Regulator G-TW-0005367.5.2 VDD _BAT _SMPS Pin Name / Group On Reset I2C_SDA Strong PU I2C_SCL Strong PU PIO[11:0] Weak PD AIO[2:0] Weak PU Table 7.1: Pin States on Reset 7.3.2 Power-on Reset Table 7.2 shows how the power-on reset occurs. Typ Reset release on VDD_CORE rising 1.05 Reset assert on VDD_CORE falling 1.00 Reset assert on VDD_CORE falling (Sleep mode) 0.60 Hysteresis 50 Unit V mV Table 7.2: Power-on Reset Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 33 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Power-on Reset 8 Example Application Schematic SW1 PCM12SMTR 2*AA BATTERY HOLDER 1 + MID 2 RF i L3 0R0 C13 NF RF i C14 NF RF RF 7 C15 0p5 CSR1010D QFN C6 100n C12 1u0 AT24C512C 29 I2C_SDA 28 I2C_SCL 27 PIO[2] SPI_PIO# PIO3 VCHG MOSI CLK CS# MISO 18 19 20 22 14 15 26 SB1 SB2 VCHG VCHG R4 47k UART_TX UART_RX 1 2 3 4 5 6 7 8 9 10 11 12 VCHG SPI_MOSI SPI_CLK SPI_CSB SPI_MISO SERSER+ GND CASE CASE CASE CASE RED GREEN BLUE 1 2 1 R3 0R0 GND VDD_BAT CS# CLK MOSI MISO VCHG UART_RX UART_TX GND GND VBAT CS# CLK MOSI MISO PIO_SEL RX TX GND1 3 4 SW2 SW_3 1 2 SW_4 3 4 SW3 3 XTAL_32K_IN XTAL_32K_OUT 10 2 XTAL_16M_IN XTAL_16M_OUT 9 VDD_XTAL VSS 0 8 SW_2 PIO3 U2 STTS751 Addr/Therm 4 SCL 6 SDA PIO3 5 EVENT CON1 8-PIN SMT USB 23 PIO[9] 24 PIO[10] 25 PIO[11] 16 PIO3 PIO[3] / SF_DIN 17 PIO[4] / SF_CS# 11 AIO[2] AIO[2] 12 AIO[1] AIO[1] 13 AIO[0] AIO[0] 3 8 VCC 7 WP 6 SCL 5 SDA VDD 4 WAKE 5 VDD_CORE U3 PIO[5] / DEBUG_CLK PIO[6] / DEBUG_CS# PIO[7] / DEBUG_MOSI PIO[8] / DEBUG_MISO PIO[0] / UART_TX PIO[1] / UART_RX RF U1 1 A0 2 A1 3 A2 4 GND C11 150n GND C10 470n 30 C9 470n VDD_CORE C7 2u2 2 ANT1 L2 4u7 3 1 X1 16MHz 2 X2 C16 470n SW4 VDD_BAT 32.768kHz C18 6p8 C19 22p C20 22p C3 R5 360R R6 180R R7 160R Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement A3 Red C2 A2 Green C1 A1 Blue G-TW-0013708.2.3 C17 15p LD1 RGB LED Page 34 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet VDD_BAT 1 C8 33p VDD_BAT R2 0R0 6 L1 VDD_REG_IN C5 2u2 31 C4 47n SMPS_LX C3 47n 21 C2 22u VDD_PADS C1 22u 32 R1 100k MZ1005Y152C 1 VDD_BAT_SMPS BAT1 2 VDD_BAT 3 9 Electrical Characteristics Note: Electrical characteristics measurements made at 20°C and at 3.3V VBAT. 9.1 Absolute Maximum Ratings Rating Min Max Unit Storage temperature -30 105 °C Battery (VDD_BAT) operation 1.8 3.6 V I/O supply voltage -0.4 3.6 V VSS - 0.4 VDD + 0.4 V Other terminal voltages(a) (a) Recommended Operating Conditions Operating Condition Min Typ Max Unit Operating temperature range(a) -30 - 105 °C Battery (VDD_BAT) operation 1.8 - 3.6 V I/O supply voltage (VDD_PADS) 1.2 - 3.6 V (a) In ambient conditions where Θ-ja = 10, Θ-jb = 1, Θ-jc = 12 (ºC/W). Note: For information on product reliability at recommended operating conditions, see Section 11. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 35 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet 9.2 VDD = Terminal Supply Domain 9.3 Input/Output Terminal Characteristics 9.3.1 Switch-mode Regulator Switch-mode Regulator Min Typ Max Unit Input voltage 1.8 - 3.6 V - 1.35 - V -200 - 200 ppm/°C Output noise, frequency range 100Hz to 100kHz - - 0.4 mV rms Settling time, settling to within 10% of final value - - 30 μs Output current (Imax) - - 50 mA Quiescent current (excluding load, Iload < 1mA) - - 20 µA Output current (Imax) - - 100 µA Quiescent current - - 1 µA Normal Operation Min Typ Max Unit Input voltage 0.65 - 1.35 V Output voltage 0.65 - 1.20 V Output voltage(a) Temperature coefficient Normal Operation (a) During Run mode, see Section 4.1. 9.3.2 Low-voltage Linear Regulator Important Note: This regulator is only for CSR internal use. Section 8 shows CSR's recommended circuit connection. 9.3.3 Digital Terminals Input Voltage Levels Min Typ Max Unit VIL input logic level low -0.4 - 0.3 x VDD_PADS V VIH input logic level high 0.7 x VDD_PADS - VDD_PADS + 0.4 V - - 25 ns Tr/Tf Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 36 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Ultra Low-power Mode Output Voltage Levels Typ Max Unit - - 0.4 V 0.75 x VDD_PADS - - V - - 5 ns Min Typ Max Unit IOL output current low, VOL max - 8 10 mA IOH output current high, VOH min - 8 10 mA With strong pull-up -150 -40 -10 μA I²C with strong pull-up -250 - - μA With strong pull-down 10 40 150 μA With weak pull-up -5.0 -1.0 -0.33 μA With weak pull-down 0.33 1.0 5.0 μA CI input capacitance 1.0 - 5.0 pF Min Typ Max Unit Input voltage 0 - VDD_AUX V Output voltage 0 - VDD_AUX V Output drive strength - 4 - mA VOL output logic level low, lOL = 4.0mA VOH output logic level high, lOH = -4.0mA Tr/Tf Input, Output and Tristate Currents(a) (a) Maximum current draw from VDD_PADS is less than 30mA depending on board design. 9.3.4 AIO Input/Output Voltage Levels 9.3.4.1 Auxiliary ADC Auxiliary ADC Min Typ Max Unit Resolution - - 10 Bits Input voltage range(a) 0 - VDD_AUX V INL -3 - 3 LSB DNL -3 - 3 LSB Accuracy Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 37 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Min Auxiliary ADC Min Typ Max Unit -1 - 1 LSB -0.8 - 0.8 % Input bandwidth - 100 - kHz Conversion time (measured at application) - 46 - µs Sample rate(b) - - 21000 Samples/s ADC block conversion current - 410 - µA Offset Gain error (a) LSB size = VDD_AUX/1023 (b) The auxiliary ADC is accessed through the firmware API. The sample rate given is achieved as part of this function. 9.3.4.2 Auxiliary DAC Min Typ Max Unit - - 10 Bits 1.30 1.35 1.40 V 0 - VDD_AUX V 1.30 1.35 1.40 V 0 1.32 2.64 mV -1.32 0 1.32 mV Integral non-linearity -3 0 3 LSB Settling time - - 250 ns Resolution Supply voltage, VDD_ANA Output voltage range Full-scale output voltage LSB size Offset Important Note: Access to the auxiliary DAC is firmware-dependent, for more information about its availability contact CSR. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 38 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Auxiliary DAC 9.4 Junction Temperature Table 9.1 lists the junction temperature when the device is operating within recommended operating conditions. Parameter Min Typ Max Unit - - 125 °C Junction temperature Table 9.1: Junction Temperature within Recommended Operating Conditions 9.5 ESD Protection Apply ESD static handling precautions during manufacturing. Table 9.2 lists the ESD handling maximum ratings. Class Max Rating Human Body Model Contact Discharge per AEC Q100-002 H1C 2000V (all pins) Charged Device Model Contact Discharge per AEC Q100-011 C4B 750V (all pins) Table 9.2: ESD Handling Ratings Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 39 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Condition 10 Current Consumption Table 10.1 shows CSR1010D QFN total typical current consumption measured at the battery. Mode Description Total Typical Current at 3.0V Dormant All functions are shut down. To wake them up, toggle <900nA the WAKE pin. Hibernate VDD_PADS = OFF, REFCLK = OFF, SLEEPCLK = ON, VDD_BAT = ON Deep sleep VDD_PADS = ON, REFCLK = OFF, SLEEPCLK = ON, VDD_BAT = ON, RAM = ON, digital circuits = ON, <5μA SMPS = ON (low-power mode), 2.2ms wake-up time Idle VDD_PADS = ON, REFCLK = ON, SLEEPCLK = ON, VDD_BAT = ON, RAM = ON, digital circuits = ON, ~1mA MCU = IDLE, <1μs wake-up time RX active - ~20mA @ 3.0V peak current TX active - ~18mA @ 3.0V peak current <1.9µA Note: Current consumption measurements were made: ■ At 20°C and with 3.0V VBAT. ■ For the whole chip: including radio, microcontroller and necessary peripherals. ■ Using SDK 2.4.3. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 40 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Table 10.1: Current Consumption 11 Product Reliability Tests At 85 °C CSR1010D QFN is guaranteed to: ■ 15000 hours with light on, or ■ 10 year lifetime with a 4 hrs in 24 hrs duty cycle 11.1 Die Test Test High Temperature Operating Life Test Conditions Specification 125°C, VDDmax, 2000 hours JEDEC JESD22-A108 CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 41 of 50 CS-315158-DSP3 www.csr.com 12 CSR Green Semiconductor Products and RoHS Compliance CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements: ■ ■ ■ ■ ■ ■ Global Automotive Declarable Substance List (GADSL) CSR has defined the "CSR Green" standard based on current regulatory and customer requirements including free from bromine, chlorine and antimony trioxide. Products and shipment packaging are marked and labelled with applicable environmental marking symbols in accordance with relevant regulatory requirements. This identifies the main environmental compliance regulatory restrictions CSR specify. For more information on the full "CSR Green" standard, contact [email protected]. 1 Including applicable amendments to EU law which are published in the EU Official Journal, or SVHC Candidate List updates published by the European Chemicals Agency (ECHA). Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 42 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet ■ Restriction of Hazardous Substances directive guidelines in the EU RoHS Directive 2011/65/EU1. EU REACH, Regulation (EC) No 1907/20061: ■ List of substances subject to authorisation (Annex XIV) ■ Restrictions on the manufacture, placing on the market and use of certain dangerous substances, preparations and articles (Annex XVII). This Annex now includes requirements that were contained within EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not limited to, the control of use of Perfluorooctane sulfonates (PFOS). ■ When requested by customers, notification of substances identified on the Candidate List as Substances of Very High Concern (SVHC)1. POP regulation (EC) No 850/20041 EU Packaging and Packaging Waste, Directive 94/62/EC1 Montreal Protocol on substances that deplete the ozone layer. Conflict minerals, Section 1502, Dodd-Frank Wall Street Reform and Consumer Protection act, which affects columbite-tantalite (coltan / tantalum), cassiterite (tin), gold, wolframite (tungsten) or their derivatives. CSR is a fabless semiconductor company: all manufacturing is performed by key suppliers. CSR have mandated that the suppliers shall not use materials that are sourced from "conflict zone mines" but understand that this requires accurate data from the EICC programme. CSR shall provide a complete EICC / GeSI template upon request. 13 CSR1010D QFN Software Stack CSR1010D QFN is supplied with Bluetooth v4.1 specification compliant stack firmware. Figure 13.1 shows that the CSR1010D QFN software architecture enables the Bluetooth processing and the application program to run on the internal RISC MCU. Application Peripherals and Power Control Generic Attribute Profile (GATT) Attribute Profile (ATT) Security Manager (SM) L2CAP CSR1010D QFN Data Sheet Link Layer Control Radio Control Physical Layer Figure 13.1: Software Architecture Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 43 of 50 CS-315158-DSP3 www.csr.com 14 Tape and Reel Information For tape and reel packing and labelling see IC Packing and Labelling Specification. 14.1 Tape Orientation Figure 14.1 shows the CSR1010D QFN packing tape orientation. G-TW-0013430.1.2 User Direction of Feed Figure 14.1: Tape Orientation Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 44 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Pin A1 Marker 14.2 Tape Dimensions Figure 14.2: Tape Dimensions A0 5.25 B0 5.25 K0 0.80 Unit mm Notes 1. 2. 3. 4. 10 sprocket hole pitch cumulative tolerance ±0.2. Camber in compliance with EIA 481. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. A0 and B0 are calculated on a plane at a distance "R" above the bottom of the pocket. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 45 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet G-TW-0005504.1.1 Figure 14.2 shows the dimensions of the tape for the CSR1010D QFN. 14.3 Reel Information a(rim height) ATTENTION Electrostatic Sensitive Devices Safe Handling Required 330.0 2.0 102.0 2.0 Detail "A" 20.2 88 REF MIN 13.0 +0.5 -0.2 "A" "b" REF 6 PS PS (MEASURED AT HUB) W1 (MEASURED AT HUB) W2 G-TW-0002797.5.2 Detail "B" Figure 14.3: Reel Dimensions Package Type Nominal Hub Width (Tape Width) a b W1 W2 Max Units 5 x 5 x 0.6mm QFN 12 4.5 98.0 12.4 (2.0/-0.0) 18.4 mm 14.4 Moisture Sensitivity Level CSR1010D QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020. Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 46 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet 6 2.0 0.5 15 Document References Reference, Date Core Specification of the Bluetooth System. Bluetooth Specification Version 4.1, 03 December 2013 CSR1010 Hardware Design Review Template. CS-218270-DD CSR1010 QFN A05 Performance Specification. CS-233372-SP CSR1010 QFN 4.3V Operation Performance Specification. CS-305811-SP Environmental Compliance Statement for CSR Green Semiconductor Products. CB-001036-ST Global Automotive Declarable Substance List (GADSL) GADSL Version 1.0, 2013 IC Packing and Labelling Specification. CS-112584-SP Stress Qualification for Integrated Circuits (base document only with no test methods) AEC-Q100 Charged Device Model (CDM) Electrostatic Discharge Test Human Body Model (HBM) Electrostatic Discharge Test AEC-Q100-011 AEC-Q100-002 Temperature, Bias, and Operating Life JEDEC JESD22-A108 Typical Solder Reflow Profile for Lead-free Devices. CS-116434-AN Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 47 of 50 CS-315158-DSP3 www.csr.com CSR1010D QFN Data Sheet Document Terms and Definitions Definition AC Alternating Current ADC Analogue to Digital Converter AGC Automatic Gain Control AIO Analogue Input/Output ATT ATTribute protocol balun balanced/unbalanced interface or device that changes a balanced output to an unbalanced input or vice versa Bluetooth® Set of technologies providing audio and data transfer over short-range radio connections CSR Cambridge Silicon Radio dBm Decibels relative to 1 mW DC Direct Current DNL Differential Non Linearity (ADC accuracy parameter) e.g. exempli gratia, for example EDR Enhanced Data Rate EEPROM Electrically Erasable Programmable Read Only Memory ESD Electrostatic Discharge ESR Equivalent Series Resistance GAP Generic Access Profile GATT Generic ATTribute protocol GSM Global System for Mobile communications HID Human Interface Device I²C Inter-Integrated Circuit Interface I/O Input/Output IC Integrated Circuit IF Intermediate Frequency INL Integral Non-Linearity (ADC accuracy parameter) IPC See www.ipc.org IQ In-Phase and Quadrature JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association) KB Kilobyte L2CAP Logical Link Control and Adaptation Protocol LC An inductor (L) and capacitor (C) network Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement CSR1010D QFN Data Sheet Term Page 48 of 50 CS-315158-DSP3 www.csr.com Definition LED Light-Emitting Diode LNA Low Noise Amplifier LSB Least Significant Bit (or Byte) MAC Medium Access Control MCU MicroController Unit MISO Master In Slave Out MLC MultiLayer Ceramic MOSI Master Out Slave In NSMD Non-Solder Mask Defined PA Power Amplifier PC Personal Computer PCB Printed Circuit Board PD Pull-Down PIO Parallel Input/Output PIO Programmable Input/Output, also known as general purpose I/O plc public limited company ppm parts per million PU Pull-Up PWM Pulse Width Modulation QFN Quad-Flat No-lead RAM Random Access Memory RF Radio Frequency RISC Reduced Instruction Set Computer RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/ EC) ROM Read Only Memory RSSI Received Signal Strength Indication RX Receive or Receiver SIG (Bluetooth) Special Interest Group SMP Security Manager Protocol SMPS Switch-Mode Power Supply Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement CSR1010D QFN Data Sheet Term Page 49 of 50 CS-315158-DSP3 www.csr.com Term Definition SPI Serial Peripheral Interface TCXO Temperature Compensated crystal Oscillator TX Transmit or Transmitter UART Universal Asynchronous Receiver Transmitter VCO Voltage Controlled Oscillator W-CDMA Wideband Code Division Multiple Access CSR1010D QFN Data Sheet Production Information © Cambridge Silicon Radio Limited 2014-2015 Confidential Information - This Material is Subject to CSR's Non-Disclosure Agreement Page 50 of 50 CS-315158-DSP3 www.csr.com