4 GHz to 18 GHz Divide-by-4 Prescaler ADF5001 FEATURES APPLICATIONS PLL frequency range extender Point-to-point radios VSAT radios Communications test equipment FUNCTIONAL BLOCK DIAGRAM CE ADF5001 BIAS VDDx 100Ω 3pF RFIN 100Ω 1pF RFOUT DIVIDE BY 4 RFOUT 1pF 50Ω 08402-001 Divide-by-4 prescaler High frequency operation: 4 GHz to 18 GHz Integrated RF decoupling capacitors Low power consumption Active mode: 30 mA Power-down mode: 7 mA Low phase noise: −150 dBc/Hz Single dc supply: 3.3 V compatible with ADF4xxx PLLs Temperature range: −40oC to +105oC Small package: 3 mm × 3 mm LFCSP GND Figure 1. GENERAL DESCRIPTION The ADF5001 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input into a PLL IC, such as the ADF4156 or ADF4106. The ADF5001 provides a divide-by-4 function. The ADF5001 operates off a 3.3 V supply and has differential 100 Ω RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. ADF5001 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Evaluation Board PCB ......................................................................7 Functional Block Diagram .............................................................. 1 PCB Material Stack-Up ................................................................7 Revision History ............................................................................... 2 Bill of Materials ..............................................................................7 Specifications..................................................................................... 3 Application Circuit ............................................................................8 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ..........................................................................9 ESD Caution .................................................................................. 4 Ordering Guide .............................................................................9 REVISION HISTORY 6/10—Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Change to Applications Section ...................................................... 1 Changes to Figure 1 .......................................................................... 1 Changes to Specifications Section .................................................. 3 Changes to Thermal Impedance Ratings, Table 2 ........................ 4 Changes to Figure 4 Through Figure 7 .......................................... 6 Changes to Evaluation Board PCB Section ................................... 7 Changes to Figure 8 .......................................................................... 7 Change to Table 4 ............................................................................. 7 Changes to Figure 10 ........................................................................ 8 Changes to Ordering Guide ............................................................ 9 10/09—Revision 0: Initial Version Rev. A | Page 2 of 12 ADF5001 SPECIFICATIONS VDD1 = VDD2 = 3.3 V ± 10%, GND = 0 V; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. The operating temperature range is −40°C to +105°C. Table 1. Parameter RF CHARACTERISTICS Input Frequency RF Input Sensitivity Output Power Output Voltage Swing Phase Noise Reverse Leakage Second Harmonic Content Third Harmonic Content Fourth Harmonic Content Fifth Harmonic Content CE INPUT VIH, Input High Voltage VIL, Input Low Voltage POWER SUPPLIES Voltage Supply IDD (IDD1 + IDD2) Active Power-Down Min Typ Max Unit 18 +10 4 −10 −10 −7 −5 −2 GHz dBm dBm dBm 200 330 mV p-p 400 660 mV p-p 1000 mV p-p −150 −60 −38 −12 −20 −19 dBc/Hz dBm dBc dBc dBc dBc 2.2 3.0 0.3 V V 3.3 3.6 V 30 7 60 25 mA mA Rev. A | Page 3 of 12 Test Conditions/Comments 4 GHz to 18 GHz Single-ended output connected into 50 Ω load Differential outputs connected into 100 Ω differential load Peak-to-peak voltage swing on each singleended output, connected into 50 Ω load Peak-to-peak voltage swing on differential output, connected into 100 Ω differential load Peak-to-peak voltage swing on each singleended output, no load condition Input frequency (fIN) = 12 GHz, offset = 100 kHz RF input power (PIN) = 0 dBm, RFOUT = 4 GHz CE is high CE is low ADF5001 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDDx to GND RFIN Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature LFCSP Thermal Impedance θJA (Ambient) θJC(Case) Peak Temperature Time at Peak Temperature This device is a high performance RF integrated circuit with an ESD rating of 2 kV, human body model (HBM) and is ESD sensitive. Proper precautions should be taken for handling and assembly. Rating −0.3 V to +3.9 V 10 dBm ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C 90°C/W 30°C/W 260°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 4 of 12 ADF5001 PIN 1 INDICATOR GND 1 12 GND 11 RFOUT GND 3 TOP VIEW (Not to Scale) 10 RFOUT 9 GND GND 8 GND 5 GND 4 CE 7 ADF5001 NC 6 RFIN 2 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO GND. 08402-002 14 VDD2 13 GND 15 VDD1 16 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 3, 4, 5, 8, 9, 12, 13, 16 2 6 7 Mnemonic GND Description RF Ground. All ground pins should be tied together. RFIN NC CE 10 RFOUT 11 RFOUT 14 VDD2 15 N/A 1 VDD1 EP Single-Ended 50 Ω Input to the RF Prescaler. This pin is ac-coupled internally via a 3 pF capacitor. No Connect. This pin can be left unconnected. Chip Enable. This pin is active high. When CE is brought low, the part enters into power-down mode. If this functionality is not required, the pin can remain unconnected because it is pulled up internally through a weak pull-up resistor. Divided Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. Complementary Divided Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. Voltage Supply for the Output Stage. Decouple this pin to ground with a 1 nF capacitor and tie it directly to VDD1. Voltage Supply for the Input Stage and Divider Block. Decouple this pin to ground with a 1 nF capacitor. The LFCSP package has an exposed paddle that must be connected to GND. 1 N/A means not applicable. Rev. A | Page 5 of 12 ADF5001 TYPICAL PERFORMANCE CHARACTERISTICS –5 0 –10 –15 –20 POWER (dBm) –30 THIRD HARMONIC –20 FIFTH HARMONIC –25 FOURTH HARMONIC –40 –30 –50 –35 ROOM TEMPERATURE VDD1 = VDD2 = 3.3V 0 5 10 15 FREQUENCY (GHz) 20 –40 2.4 08402-003 –60 25 2.7 3.0 3.3 3.6 VDDx (V) Figure 3. RFIN Sensitivity 08402-006 MINIMUM INPUT POWER (dBm) FIRST HARMONIC –10 Figure 6. RFOUT Harmonic Content 20 0 18 IDD1 –5 IDDx (mA) 14 OUTPUT POWER (dBm) 16 IDD2 12 10 8 6 4 –10 –15 –20 –25 2.7 2.9 3.1 3.3 3.5 3.7 3.9 VDDx (V) –30 08402-004 0 2.5 0 –2 RF OUTPUT POWER (dBm) –4 –6 –8 –10 –12 –14 –16 2.9 3.1 3.3 VDDx (V) 3.5 3.7 3.9 08402-005 –18 2.7 5 10 15 20 INPUT FREQUENCY (GHz) 25 30 Figure 7. RFOUT Power vs. RFIN Frequency, fIN = 10 GHz, VDD = 3.3 V Figure 4. IDD1 and IDD2 vs. VDDx –20 2.5 0 Figure 5. RFOUT Power (Single-Ended) vs. VDDx, fIN = 10 GHz, PIN = 0 dBm Rev. A | Page 6 of 12 08402-007 2 ADF5001 EVALUATION BOARD PCB The evaluation board has four connectors as shown in Figure 8. The RF input connector (J4) is a high frequency precision SMA connector from Emerson. This connector is mechanically compatible with SMA/3.5 mm and 2.92 mm cables. 1.5oz (53µm) FINISHED COPPER ROGERS RO4003C LAMINATE 0.008” Er = 3.38. STARTING COPPER WEIGHT 0.5oz/0.5oz 0.5oz (18µm) FINISHED COPPER FR4 PREPREG 0.0372” 0.062” ± 0.003” COPPER TO COPPER 0.5oz (18µm) FINISHED COPPER 1.5oz (53µm) FINISHED COPPER Figure 8. Evaluation Board Silkscreen—Top View The evaluation board is powered from a single 3.0 V to 3.6 V supply, which should be connected to the J1 SMA connector. The power supply can also be connected using the T3 (VDDx) and T2 (GND) test points. The differential RF outputs are brought out on the J2 and J3 SMA connectors. If only one of the outputs is being used, the unused output should be correctly terminated using a 50 Ω SMA termination. The chip enable (CE) pin can be controlled using the T1 test point. If this function is not required, the test point can remain unconnected. PCB MATERIAL STACK-UP The evaluation board is built using Rogers RO4003C material (0.008 in.). RF track widths are 0.015 in. to achieve a controlled 50 Ω characteristic impedance. The complete PCB stack-up is shown in Figure 9. 08402-009 08753-008 ROGERS RO4003C LAMINATE 0.008” Er = 3.38.STARTING COPPER WEIGHT 0.5oz/0.5oz Figure 9. Evaluation Board PCB Layer Stack-Up BILL OF MATERIALS Table 4. Qty. 1 Reference Designator C1 1 C2 1 J4 3 J1, J2, J3 3 1 T1, T2, T3 U1 Rev. A | Page 7 of 12 Description 0.1 μF, 0603 capacitor 10 pF, 0402 capacitor 3.5 mm RF SMA connector 3.5 mm RF SMA connector Test points ADF5001 RF prescaler Supplier/Part Number Murata GRM188R71H104KA93D Murata GRM1555C1H100JZ01D Emerson 142-0761-801 Johnson Components 142-0701-851 Vero 20-2137 Analog Devices, Inc., ADF5001BCPZ ADF5001 APPLICATION CIRCUIT typically required by microwave VCOs. The positive input pin of the OP184 is biased at half the ADF4156 charge pump supply (VP). This can be easily achieved using a simple resistor divider, ensuring sufficient decoupling close to the +IN A pin of the OP184 thereby allowing the use of a single positive supply for the op amp. Alternatively, to optimize performance by ensuring a clean bias voltage, a low noise regulator like the ADP150 can be used to power the resistor divider network or the +IN A pin directly. The ADF5001 can be connected either single-ended or differentially to any of the Analog Devices PLL family of ICs. It is recommended to use a differential connection for best performance and to achieve maximum power transfer. The application circuit shown in Figure 10 shows the ADF5001 used as the RF prescaler in a microwave 16 GHz PLL loop. The ADF5001 divides down the 16 GHz RF signal to 4 GHz, which is input differentially into the ADF4156 PLL. An active filter topology, using the OP184 op amp, is used to provide the wide tuning ranges 1.8nF 10pF 0.1µF 330Ω VDD1 ADF5001 RFOUT DECOUPLING INTEGRATED ADF4156 PLL RFINA 220Ω CP PRESCALER VP/2 RFINB RFOUT 820pF GND OP184 1µF 1.8nF MICROWAVE VCO 6dB PAD 37Ω 18Ω RFOUT 150Ω 1kΩ OP AMP 150Ω VTUNE 18Ω 08402-010 RFIN VDD2 47nF 16GHz OUT Figure 10. ADF5001 Used as the RF Prescaler in a Microwave 16 GHz PLL Loop Rev. A | Page 8 of 12 ADF5001 OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 1.60 1.50 SQ 1.40 9 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.45 0.40 0.35 4 8 5 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 111808-A PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 11. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-18) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADF5001BCPZ ADF5001BCPZ-RL7 EVAL-ADF5001EB2Z 1 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ), 7” Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 9 of 12 Package Option CP-16-18 CP-16-18 Branding Q1S Q1S ADF5001 NOTES Rev. A | Page 10 of 12 ADF5001 NOTES Rev. A | Page 11 of 12 ADF5001 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08402-0-6/10(A) Rev. A | Page 12 of 12