Wideband Dual-Channel Linear Multiplier/Divider AD539 FEATURES APPLICATIONS Precise high bandwidth AGC and VCA systems Voltage-controlled filters Video signal processing High speed analog division Automatic signal-leveling Square-law gain/loss control FUNCTIONAL BLOCK DIAGRAM AD539 VY1 × 6kΩ W1 CHAN1 OUTPUT 6kΩ Z1 VX 6kΩ VY2 × Z2 CHAN2 OUTPUT 6kΩ W2 09679-001 2-quadrant multiplication/division 2 independent signal channels Signal bandwidth of 60 MHz (IOUT) Linear control channel bandwidth of 5 MHz Low distortion (to 0.01%) Fully calibrated, monolithic circuit Figure 1. GENERAL DESCRIPTION The AD539 is a low distortion analog multiplier having two identical signal channels (Y1 and Y2), with a common X input providing linear control of gain. Excellent ac characteristics up to video frequencies and a −3 dB bandwidth of over 60 MHz are provided. Although intended primarily for applications where speed is important, the circuit exhibits good static accuracy in computational applications. Scaling is accurately determined by a band-gap voltage reference and all critical parameters are laser-trimmed during manufacture. The full bandwidth can be realized over most of the gain range using the AD539 with simple resistive loads of up to 100 Ω. Output voltage is restricted to a few hundred millivolts under these conditions. The two channels provide flexibility. In single-channel applications, they can be used in parallel to double the output current, in series to achieve a square-law gain function with a control range of over 100 dB, or differentially to reduce distortion. Alternatively, they can be used independently, as in audio stereo applications, with low crosstalk between channels. Voltage-controlled filters and oscillators using the state-variable approach are easily designed, taking advantage of the dual channels and common control. The AD539 can also be configured as a divider with signal bandwidths up to 15 MHz. Power consumption is only 135 mW using the recommended ±5 V supplies. The AD539 is available in three versions: the J and K grades are specified for 0 to 70°C operation and S grade is guaranteed over the extended range of −55°C to +125°C. The J and K grades are available in either a hermetic ceramic SBDIP (D-16) or a low cost PDIP (N-16), whereas the S grade is available in ceramic SBDIP (D-16) or LCC (E-20-1). The S grade is available in MIL-STD-883 and Standard Military Drawing (DESC) Number 5962-8980901EA versions. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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AD539 TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function....................................................................... 11 Applications....................................................................................... 1 Dual Signal Channels................................................................. 11 Functional Block Diagram .............................................................. 1 Common Control Channel....................................................... 11 General Description ......................................................................... 1 Flexible Scaling ........................................................................... 11 Revision History ............................................................................... 2 Applications Information .............................................................. 12 Specifications..................................................................................... 3 Basic Multiplier Connections ................................................... 12 Pin Configurations and Function Descriptions ........................... 5 A 50 MHz Voltage-Controlled Amplifier ............................... 15 Typical Performance Characteristics ............................................. 7 Basic Divider Connections ....................................................... 16 Theory of Operation ...................................................................... 10 Outline Dimensions ....................................................................... 17 Circuit Description..................................................................... 10 Ordering Guide .......................................................................... 18 General Recommendations....................................................... 10 REVISION HISTORY 4/11—Rev. A to Rev. B Updated Format..................................................................Universal Changed Pin Configuration to Functional Block Diagram........ 1 Changes to General Description Section ...................................... 1 Added Pin Configurations and Function Descriptions Section................................................................................................ 5 Added Table 2; Renumbered Sequentially .................................... 5 Added Table 3.................................................................................... 6 Added Typical Performance Characteristics Section .................. 7 Added Figure 6 and Figure 9; Renumbered Sequentially ........... 7 Changes to Figure 18...................................................................... 10 Moved Dual Signal Channels Section, Common Control Channel Section, and Flexible Scaling Section........................... 11 Changes to Figure 20...................................................................... 12 Changes to Table 4, Figure 21, and Table 5 ................................. 13 Changes to Figure 22 and Figure 23............................................. 14 Changes to Figure 24...................................................................... 15 Changes to Figure 25...................................................................... 16 Updated Outline Dimensions....................................................... 17 Changes to Ordering Guide .......................................................... 18 12/91—Rev. 0 to Rev. A Rev. B | Page 2 of 20 AD539 SPECIFICATIONS TA = 25°C, VS = ±5 V, unless otherwise specified. VY = VY1 − VY2, VX = VX1 – VX2. All minimum and maximum specifications are guaranteed. Table 1. Parameter SIGNAL CHANNEL DYNAMICS Minimal Configuration Bandwidth, −3 dB Maximum Output Feedthrough f < 1 MHz f = 20 MHz Differential Phase Linearity −1 V < VY dc < +1 V −2 V < VY dc < +2 V Group Delay Standard 2-Channel Multiplier Maximum Output Feedthrough, f < 100 kHz Crosstalk (Channel 1 to Channel 2) RTO Noise, 10 Hz to 1 MHz THD + Noise VX = 1 V VY = 3 V Wideband 2-Channel Multiplier Bandwidth, −3 dB (LH0032) Maximum Output VX = 3 V Feedthrough VX = 0 V Wideband Single-Channel VCA Bandwidth, −3 dB Maximum Output Feedthrough CONTROL CHANNEL DYNAMICS Bandwidth, −3 dB SIGNAL INPUTS, VY1 AND VY2 Nominal Full-Scale Input Operational Range, Degraded Performance Input Resistance Bias Current Offset Voltage TMIN to TMAX Power Supply Sensitivity Test Conditions/Comments See Figure 22 RL = 50 Ω, CC = 0.01 μF 0.1 V < VX < 3 V, VY ac = 1 V rms VX = 0 V, VY ac = 1.5 V rms Min 30 f = 3.58 MHz, VX = 3 V, VY ac = 100 mV f = 3.58 MHz, VX = 3 V, VY ac = 100 mV VX = 3 V, VY ac = 1 V rms, f = 1 MHz See Figure 20 VX = 3 V, VY ac = 1.5 V rms VX = 0 V, VY ac = 1.5 V rms VY1 = 1 V rms, VY2 = 0 V, VX = 3 V, f < 100 kHz VX = 1.5 V, VY = 0 V f = 10 kHz, VY ac = 1 V rms f = 10 kHz, VY ac = 1 V rms See Figure 20 0.1 V < VX < 3 V, VY ac = 1 V rms VY ac = 1.5 V rms, f = 3 MHz VY ac = 1.0 V rms, f = 3 MHz See Figure 24 0.1 V < VX < 3 V, VY ac = 1 V rms 75 Ω load VX = −0.01 V, f = 5 MHz CC = 3000 pF, VX dc = 1.5 V, VX ac = 100 mV rms AD539J Typ Max 60 −10 Min 30 VX = 3 V, VY = 0 V VX = 3 V, VY = 0 V 60 −10 Min 30 AD539S Typ Max Unit 60 −10 MHz dBm −75 −55 −75 −55 −75 −55 dBm dBm ±0.2 ±0.2 ±0.2 Degrees ±0.5 ±0.5 ±0.5 Degrees 4 4 4 ns 4.5 1 −40 4.5 1 −40 4.5 1 −40 V mV rms dB 200 200 200 nV/√Hz 0.02 0.04 0.02 0.04 0.02 0.04 % % 25 25 25 MHz 4.5 14 4.5 14 4.5 14 V rms mV rms 50 50 50 MHz ±1 −54 ±1 −54 ±1 −54 V dB 5 5 5 MHz ±2 V V ±2 −VS ≤ 7 V AD539K Typ Max ±2 ±4.2 1 ±4.21 400 10 5 10 2 Rev. B | Page 3 of 20 301 201 ±4.21 400 10 5 5 2 201 101 400 10 5 15 2 301 201 35 kΩ μA mV mV mV/V AD539 Parameter CONTROL INPUT, VX Nominal Full-Scale Input Operational Range, Degraded Performance Input Resistance 2 Offset Voltage TMIN to TMAX Power Supply Sensitivity Gain Test Conditions/Comments Min AD539J Typ 500 1 3 30 0.2 TMIN to TMAX VX = 0.1 V to 3.0 V, VY = ±2 V 0.3 Output Resistance Scaling Resistors Channel 1 Channel 2 VOLTAGE OUTPUTS, VW1 AND VW23 Multiplier Transfer Function Either Channel Multiplier Scaling Voltage, VU Accuracy TMIN to TMAX Power Supply Sensitivity Total Multiplication Error 4 TMIN to TMAX Control Feedthrough TMIN to TMAX TEMPERATURE RANGE Rated Performance POWER SUPPLIES Operational Range Current Consumption +VS −VS VX = 3 V, VY = ±2 V VX = 3.3 V, VY = ±5 V, VS = ±7.5 V VX = 0 V, VY = 0 V See Figure 20, VX = 0 V, VY = 0 V ±2 Min 3.0 0.41 0.1 3.0 21 0.21 0.15 ±2 1.51 101 AD539S Typ Max ±1 ±2.8 0.2 3 ±2 1.51 101 Unit V V +3.2 500 1 2 30 41 ±1 ±2.8 0.2 3 Z1, W1 to CH1 Z2, W2 to CH2 AD539K Typ Max +3.2 See Figure 20 VX = 0.1 V to 3.0 V, VY = ±2 V Output Offset Current Output Offset Voltage 3 Min 3.0 +3.2 Absolute Gain Error CURRENT OUTPUT2 Full-Scale Output Current Peak Output Current Max 500 1 2 30 41 51 Ω mV mV μV/V 0.2 0.41 dB 0.25 0.51 dB ±1 ±2.8 0.2 3 mA mA 1.51 101 μA mV 1.2 1.2 1.2 kΩ 6 6 6 6 6 6 kΩ kΩ See Figure 20 VX ≤ 3 V, −2 V < VY < +2 V VX = 0 V to 3 V, VY = 0 V VW = −VX × VY/VU 0.981 1.0 1.021 0.5 21 1 0.04 1 2.5 2 25 601 30 VW = −VX × VY/VU 0.991 1.0 1.011 0.5 11 0.5 0.04 0.6 1.5 1 15 301 0 +70 0 +70 ±4.5 ±15 ±4.5 ±15 8.5 18.5 1 10.21 22.21 8.5 18.5 Rev. B | Page 4 of 20 mV −55 +125 °C ±4.5 ±15 V 10.21 22.21 mA mA 60 10.21 22.21 V % % %/V % FSR % mV 1201 15 Tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Resistance value and absolute current outputs subject to 20% tolerance. 3 Specification assumes the external op amp is trimmed for negligible input offset. 4 Includes all errors. 2 VW = −VX × VY/VU 0.981 1.0 1.021 0.5 2 1.0 31 0.04 1 2.5 2 41 15 601 8.5 18.5 AD539 2 1 Z1 W1 20 19 VY1 4 +VS 5 NC 6 –VS 7 AD539 TOP VIEW (Not to Scale) VY2 8 BASE COMMON 16 NC 15 BASE COMMON 14 CHAN2 OUTPUT Z2 NC W2 INPUT COMMON CHAN1 OUTPUT 17 10 11 12 13 OUTPUT COMMON 9 18 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 09679-002 3 NC HF COMP VX PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 2. 20-Lead LLC Pin Configuration (E-20-1) Table 2. 20-Lead LLC Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic NC VX HF COMP VY1 +VS NC –VS VY2 INPUT COMMON OUTPUT COMMON NC W2 Z2 CHAN2 OUTPUT BASE COMMON NC BASE COMMON CHAN1 OUTPUT Z1 W1 Description No Connect. Do not connect to this pin. Control Channel Input. High Frequency Compensation. Channel 1 Input. Positive Supply Rail. No Connect. Do not connect to this pin. Negative Supply Rail. Channel 2 Input. Internal Common Connection for the Input Amplifier Circuitry. Internal Common Connection for the Output Amplifier Circuitry. No Connect. 6 kΩ Feedback Resistor for Channel 2. 6 kΩ Feedback Resistor for Channel 2. Channel 2 Product of VX and VY2. Increases Negative Output Compliance. No Connect. Do not connect to this pin. Increases Negative Output Compliance. Channel 1 Product of VX and VY1. 6 kΩ Feedback Resistor for Channel 1. 6 kΩ Feedback Resistor for Channel 1. Rev. B | Page 5 of 20 AD539 VX 1 16 W1 HF COMP 2 15 Z1 VY1 3 14 CHAN1 OUTPUT –VS 5 AD539 13 BASE COMMON TOP VIEW (Not to Scale) 12 BASE COMMON VY2 6 11 CHAN2 PUTPUT INPUT COMMON 7 10 Z2 OUTPUT COMMON 8 9 W2 09679-003 +VS 4 Figure 3. 16-Lead PDIP and SBDIP Pin Configurations (N-16, D-16) Table 3. 16-Lead PDIP and SBDIP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VX HF COMP VY1 +VS –VS VY2 INPUT COMMON OUTPUT COMMON W2 Z2 CHAN2 OUTPUT BASE COMMON BASE COMMON CHAN1 OUTPUT Z1 W1 Description Control Channel Input. High Frequency Compensation. Channel 1 Input. Positive Supply Rail. Negative Supply Rail. Channel 2 Input. Internal Common Connection for the Input Amplifier Circuitry. Internal Common Connection for The Output Amplifier Circuitry. 6 kΩ Feedback Resistor for Channel 2. 6 kΩ Feedback Resistor for Channel 2. Channel 2 Product of VX and VY2. Increases Negative Output Compliance. Increases Negative Output Compliance. Channel 1 Product of VX and VY1. 6 kΩ Feedback Resistor for Channel 1. 6 kΩ Feedback Resistor for Channel 1. Rev. B | Page 6 of 20 AD539 TYPICAL PERFORMANCE CHARACTERISTICS VY = VY1 − VY2, VX = VX1 – VX2, unless otherwise noted. 3 1V GAIN/LOSS ERRORS (dB) 2 50ns 100 90 AD539J, S SPECS 1 AD539K SPECS 0 –1 10 –2 0% 10 09679-007 0.1 1 CONTROL VOLTAGE (VX) 09679-004 2V –3 0.01 VX = +3V Figure 7. Multiplier Pulse Response Using LH0032 Op Amp, VX = 3 V Figure 4. Maximum AC Gain Error Boundaries 0.20 1V 50ns 100 0.15 90 0.10 VY = 1.5V rms 0.05 10 VY = 0.5V rms 0% 1 2 CONTROL VOLTAGE (V) 3 VX = +0.1V Figure 5. Total Harmonic Distortion vs. Control Voltage Figure 8. Multiplier Pulse Response Using LH0032 Op Amp, VX = 0.1 V 0 10 HIGH FREQUENCY RESPONSE (dB) VX = 3.162V VX = 1.00V 0 VX = 0.316V –10 VX = 0.1V –20 VX = 0.032V –30 VX = 0.01V –40 –50 FEEDTHROUGH VX = –0.01V 1M 10M FREQUENCY (Hz) 100M 09679-006 HIGH FREQUENCY RESPONSE (dB) 20 –60 100k 09679-008 0 09679-005 100mV 0 Figure 6. Multiplier High Frequency Response Using LH0032 Op Amps Rev. B | Page 7 of 20 VX = 3.162V –10 VX = 1.00V –20 VX = 0.316V –30 VX = 0.1V –40 VX = 0.032V –50 VX = 0.01V –60 –70 100k 1M 10M FREQUENCY (Hz) 100M Figure 9. High Frequency Response in Minimal Configuration 09679-009 TOTAL HARMONIC DISTORTION (%) f = 10kHz AD539 2 100µs 20mV 90 0 10 –1 0 5 FREQUENCY (MHz) 10 Figure 10. Phase Linearity Error in Minimal Configuration Figure 13. Control Feedthrough Differential Mode of Figure 22 0.050 5.0 f = 10kHz TOTAL HARMONIC DISTORTION (%) f = 3.579MHz VX = 0.3V 0 VX = 1V VX = 3V –2.5 –5.0 –2 –1 0 1 SIGNAL INPUT BIAS VOLTAGE (V) 2 0.025 VY = 0.5V rms 0 09679-011 Figure 11. Differential Phase Linearity in Minimal Configuration for a Typical Device 1 2 CONTROL VOLTAGE (V) 3 Figure 14. Distortion in Differential Mode Using LH0032 Op Amp 10 20mV 0 VX = +3.162V 100µs 0 100 90 VX = +1.00V RESPONSE (dB) –10 VX = +0.316V –20 VX = +0.1V –30 VX = +0.032V –40 10 VX = +0.01V 0% 09679-012 –50 VX = –0.01V –60 Figure 12. Control Feedthrough One Channel of Figure 22 1 10 FREQUENCY (MHz) 100 09679-015 PHASE LINEARITY (Degrees) VX = 0.1V 2.5 VY = 1.5V rms 09679-014 –2 09679-013 0% 09679-010 PHASE LINEARITY (Degrees) 100 1 Figure 15. AC Response of the VCA at Different Gains, VY = 0.5 V RMS Rev. B | Page 8 of 20 AD539 2V 500µV 20ns 100 90 VOUT 10 VIN 09679-016 0% Figure 16. Transient Response of the Voltage-Controlled Amplifier, VX = +2 V, VY = ±1 V 50 GAIN (dB) 30 VX = +0.01V VX = +0.032V VX = +0.1V 20 10 VX = +0.316V VX = +1V 0 –10 VX = +3.162V –20 10k 100k 1M FREQUENCY (Hz) 10M 09679-017 40 Figure 17. High Frequency Response of Divider in Figure 25 Rev. B | Page 9 of 20 AD539 THEORY OF OPERATION CIRCUIT DESCRIPTION GENERAL RECOMMENDATIONS Figure 18 shows a simplified schematic of the AD539. Q1 to Q6 are large-geometry transistors designed for low distortion and low noise. Emitter-area scaling further reduces distortion: Q1 is three times larger than Q2; Q4 and Q5 are each three times larger than Q3 and Q6 and are twice as large as Q1 and Q2. A stable reference current of IREF = 1.375 mA is produced by a band gap reference circuit and applied to the common emitter node of a controlled cascode formed by Q1 and Q2. When VX = 0 V, all of IREF flows in Q1 due to the action of the high gain control amplifier, which lowers the voltage on the base of Q2. As VX is raised, the fraction of IREF flowing in Q2 is forced to balance the control current, VX/2.5 kΩ. At the full-scale value of VX (3 V) this fraction is 0.873. Because the base of Q1, Q4, and Q5 are at ground potential and the bases of Q2, Q3, and Q6 are commoned, all three controlled cascodes divide the current applied to their emitter nodes in the same proportion. The control loop is stabilized by the external capacitor, CC. The AD539 is a high speed circuit and requires considerable care to achieve its full performance potential. A high quality ground plane should be used with the device either soldered directly into the board or mounted in a low profile socket. In Figure 18, an open triangle denotes a direct, short connection to this ground plane; the BASE COMMON pins (Pin 12 and Pin 13) are especially prone to unwanted signal pickup. Power supply decoupling capacitors of 0.1 μF to 1 μF should be connected from the +VS and −VS pins (Pin 4 and Pin 5) to the ground plane. In applications using external high speed op amps, use separate supply decoupling. It is good practice to insert small (10 Ω) resistors between the primary supply and the decoupling capacitor. The control amplifier compensation capacitor, CC, should likewise have short leads to ground and a minimum value of 3 nF. Unless maximum control bandwidth is essential, it is advisable to use a larger value of 0.01 μF to 0.1 μF to improve the signal channel phase response, high frequency crosstalk, and high frequency distortion. The control bandwidth is inversely proportional to this capacitance, typically 2 MHz for CC = 0.01 μF, VX = 1.7 V. The bandwidth and pulse response of the control channel can be improved by using a feedforward capacitor of 5% to 20% the value of CC between the VX and HF COMP pins (Pin 1 and Pin 2). Optimum transient response results when the rise/fall time of VX are commensurate with the control channel response time. The signal voltages, VY1 and VY2 (generically referred to as VY), are first converted to currents by voltage-to-current converters with a gm of 575 μmhos. Thus, the full-scale input of ±2 V becomes a current of ±1.15 mA, which is superimposed on a bias of 2.75 mA and applied to the common emitter node of controlled cascode Q3/Q4 or Q5/Q6. As previously explained, the proportion of this current steered to the output node is linearly dependent on VX. Therefore, for full-scale VX and VY inputs, a signal of ±1 mA (0.873 × ±1.15 mA) and a bias component of 2.4 mA (0.873 × 2.75 mA) appear at the output. The bias component absorbed by the 1.25 kΩ resistors also connected to VX and the resulting signal current can be applied to an external load resistor (in which case scaling is not accurate) or can be forced into either or both of the 6 kΩ feedback resistors (to the Z and W nodes) by an external op amp. In the latter case, scaling accuracy is guaranteed. 2.5kΩ CONTROL AMPLIFIER 1.2mA FS 1.25kΩ CHAN1 14 OUTPUT ±1mA FS BASE COMMON 13 Q1 Q2 IREF = 1.375mA +VS 4 –VS 5 BAND-GAP REFERENCE GENERATOR HF COMP 2 CC (EXT) 3nF MIN 6kΩ 6kΩ Q3 1.25kΩ 16 W1 W2 9 15 Z1 Q4 Z2 10 12 6kΩ 6kΩ Q5 CHAN2 OUTPUT 8 OUTPUT COMMON 6 VY2 ±2V FS ±1mA FS Q6 VY1 ±2V FS 3 7 INPUT COMMON Figure 18. Simplified Schematic of AD539 Multiplier (16-Lead SBDIP and PDIP Shown) Rev. B | Page 10 of 20 11 09679-018 VX 1 0V TO +3V FS VX should not exceed the specified range of 0 V to 3 V. The ac gain is zero for VX < 0 V but there remains a feedforward path (see Figure 18) causing control feedthrough. Recovery time from negative values of VX can be improved by adding a small signal Schottky diode with its cathode connected to HF COMP (Pin 2) and its anode grounded. This constrains the voltage swing on CC. Above VX = 3.2 V, the ac gain limits at its maximum value, but any overdrive appears as control feedthrough at the output. AD539 TRANSFER FUNCTION In using any analog multiplier or divider, careful attention must be paid to the matter of scaling, particularly in computational applications. To be dimensionally consistent, a scaling voltage must appear in the transfer function, which, for each channel of the AD539 in the standard multiplier configuration (see Figure 20), is VW = −VXVY/VU where the VX and VY inputs, the VW output, and the scaling voltage, VU, are expressed in a consistent unit, usually volts. In this case, VU is fixed by the design to be 1 V and it is often acceptable in the interest of simplification to use the less rigorous expression VW = −VXVY where it is understood that all signals must be expressed in volts, that is, they are rendered dimensionless by division by 1 V. The accuracy specifications for VU allow the use of either of the two feedback resistors supplied with each channel, because these are very closely matched, or they can be used in parallel to halve the gain (double the effective scaling voltage), when VW = −VXVY/2 also be used with no external load (CHAN2 OUTPUT, Pin 11, or CHAN1 OUTPUT, Pin 14, open circuit), when VU’ is precisely 5 V. DUAL SIGNAL CHANNELS The signal voltage inputs, VY1 and VY2, have nominal full-scale (FS) values of ±2 V with a peak range to ±4.2 V (using a negative supply of 7.5 V or greater). For video applications where differential phase is critical, a reduced input range of ±1 V is recommended, resulting in a phase variation of typically ±0.2° at 3.579 MHz for full gain. The input impedance is typically 400 kΩ shunted by 3 pF. Signal channel distortion is typically well under 0.1% at 10 kHz and can be reduced to 0.01% by using the channels differentially. COMMON CONTROL CHANNEL The control channel accepts positive inputs, VX, from 0 V to 3 V FS, ±3.3 V peak. The input resistance is 500 Ω. An external, grounded capacitor determines the small-signal bandwidth and recovery time of the control amplifier; the minimum value of 3 nF allows a bandwidth at midgain of about 5 MHz. Larger compensation capacitors slow the control channel but improve the high frequency performance of the signal channels. FLEXIBLE SCALING Using either one or two external op amps in conjunction with the on-chip 6 kΩ scaling resistors (see Figure 19), the output currents (nominally ±1 mA FS, ±2.25 mA peak) can be converted to voltages with accurate transfer functions of VW = −VXVY/2, VW = −VXVY, or VW = −2VXVY (where the VX and VY inputs and VW output are expressed in volts), with corresponding full-scale outputs of ±3 V, ±6 V, and ±12 V. Alternatively, low impedance grounded loads can be used to achieve the full signal bandwidth of 60 MHz, in which mode the scaling is less accurate. W1 Z1 CHAN1 MULTIPLY When an external load resistor, RL, is used, the scaling is no longer exact because the internal thin film resistors, although trimmed to high ratiometric accuracy, have an absolute tolerance of 20%. However, the nominal transfer function is VY1 – EXTRNAL OP AMPS VY2 – VX VW = −VXVY/VU’ VW1 = –VXVY1 VW2 = –VXVY2 CHAN2 MULTIPLY where the effective scaling voltage, VU’, can be calculated for each channel using the formula Z2 W2 09679-019 The power supplies to the AD539 can be as low as ±4.5 V and as high as ±16.5 V. The maximum allowable range of the signal inputs, VY, is approximately 0.5 V above +VS; the minimum value is 2.5 V above −VS. To accommodate the peak specified inputs of ±4.2 V the supplies should be nominally +5 V and −7.5 V. Although there is no performance advantage in raising supplies above these values, it may often be convenient to use the same supplies as for the op amps. The AD539 can tolerate the excess voltage with only a slight effect on dc accuracy but dissipation at ±16.5 V can be as high as 535 mW, and some form of heat sink is essential in the interests of reliability. Figure 19. Block Diagram Showing Scaling Resistors and External Op Amps VU’ = VU (5RL + 6.25)/RL where RL is expressed in kilohms. For example, when RL = 100 Ω, VU’ = 67.5 V. Table 5 provides more detailed data for the case where both channels are used in parallel. The AD539 can Rev. B | Page 11 of 20 AD539 APPLICATIONS INFORMATION and apply to all configurations using the internal feedback resistors (W1 and W2 or, alternatively, Z1 and Z2). BASIC MULTIPLIER CONNECTIONS Figure 20 shows the connections for the standard dual-channel multiplier, using op amps to provide useful output power and the AD539 feedback resistors to achieve accurate scaling. The transfer function for each channel is Distortion is a function of the signal input level (VY) and the control input (VX). It is also a function of frequency, although in practice, the op amp generates most of the distortion at frequencies above 100 kHz. Figure 5 shows typical results at f = 10 kHz as a function of VX with VY = 0.5 V rms and 1.5 V rms. VW = −VXVY where the inputs and outputs are expressed in volts (see the Transfer Function section). At the nominal full-scale inputs of VX = 3 V and VY = ±2 V, the full-scale outputs are ±6 V. Depending on the choice of op amp, their supply voltages may need to be about 2 V more than the peak output. Thus, supplies of at least ±8 V are required; the AD539 can share these supplies. Higher outputs are possible if VX and VY are driven to their peak values of +3.2 V and ±4.2 V, respectively, when the peak output is ±13.4 V. This requires operating the op amps at supplies of ±15 V. Under these conditions, it is advisable to reduce the supplies to the AD539 to ±7.5 V to limit its power dissipation; however, with some form of heat-sinking, it is permissible to operate the AD539 directly from ±15 V supplies. VY1 VX 2 HF COMP 3 VY1 4 +VS 5 –VS 6 VY2 7 INPUT COMMON 8 OUTPUT COMMON +VS –VS VY2 W1 16 1 CC = 3nF CF –VS Z1 15 NC VW1 = –VXVY1 CHAN1 14 OUTPUT AD539 BASE COMMON 13 +VS 12 CHAN2 11 OUTPUT VW2 = –VXVY2 Z2 10 NC CF W2 9 –VS 09679-020 VX NOTES 1. ALL DECOUPLING CAPACITORS ARE 0.47µF CERAMIC. Figure 20. Standard Dual-Channel Multiplier (16-Lead SBDIP and PDIP Shown) Viewed as a voltage-controlled amplifier, the decibel gain is simply G = 20 log VX where VX is expressed in volts. This results in a gain of 10 dB at VX = 3.162 V, 0 dB at VX = 1 V, −20 dB at VX = 0.1 V, and so on. In many ac applications, the output offset voltage (for VX = 0 V or VY = 0 V) is not a major concern; however, it can be eliminated using the offset nulling method recommended for the particular op amp, with VX = VY = 0 V. At small values of VX, the offset voltage of the control channel degrades the gain/loss accuracy. For example, a ±1 mV offset uncertainty causes the nominal 40 dB attenuation at VX = 0.01 V to range from 39.2 dB to 40.9 dB. Figure 4 shows the maximum gain error boundaries based on the guaranteed control channel offset voltages of ±2 mV for the AD539K and ±4 mV for the AD539J. These curves include all scaling errors In some cases, it may be desirable to alter the scaling. This can be achieved in several ways. One option is to use both the Z and W feedback resistors (see Figure 18) in parallel, in which case VW = −VXVY/2. This may be preferable where the output swing must be held at ±3 V FS (±6.75 peak), for example, to allow the use of reduced supply voltages for the op amps. Alternatively, the gain can be doubled by connecting both channels in parallel and using only a single feedback resistor, in which case VW = −2VXYY and the full-scale output is ±12 V. Another option is to insert a resistor in series with the control channel input, permitting the use of a large (for example, 0 V to 10 V) control voltage. A disadvantage of this scheme is the need to adjust this resistor to accommodate the tolerance of the nominal 500 Ω input resistance at Pin 1, VX. The signal channel inputs can also be resistively attenuated to permit operation at higher values of VY, in which case it may often be possible to partially compensate for the response roll-off of the op amp by adding a capacitor across the upper arm of this attenuator. Signal Channel AC and Transient Response The HF response is dependent almost entirely on the op amp. Note that the noise gain for the op amp in Figure 20 is determined by the value of the feedback resistor (6 kΩ) and the 1.25 kΩ control-bias resistors (see Figure 18). Op amps with provision for external frequency compensation should be compensated for a closed-loop gain of 6. The layout of the circuit components is very important if low feedthrough and flat response at low values of VX is to be maintained (see the General Recommendations section). For wide bandwidth applications requiring an output voltage swing greater than ±1 V, the LH0032 hybrid op amp is recommended. Figure 6 shows the HF response of the circuit of Figure 20 using this amplifier with VY = 1 V rms and other conditions as shown in Table 4. CF was adjusted for 1 dB peaking at VX = 1 V; the −3 dB bandwidth exceeds 25 MHz. The effect of signal feedthrough on the response becomes apparent at VX = 0.01 V. The minimum feedthrough results when VX is taken slightly negative to ensure that the residual control channel offset is exceeded and the dc gain is reliably zero. Measurements show that the feedthrough can be held to −90 dB relative to full output at low frequencies and to −60 dB up to 20 MHz with careful board layout. The corresponding pulse response is shown in Figure 7 for a signal input of VY of ±1 V and two values of VX (3 V and 0.1 V). Rev. B | Page 12 of 20 AD539 Operating Conditions Op Amp Supply Voltages Op Amp Compensation Capacitor Feedback Capacitor, CF −3 dB Bandwidth, VX = 1 V Load Capacitance HF Feedthrough VX = −0.01 V, f = 5 MHz RMS Output Noise VX = 1 V, BW 10 Hz to10 kHz VX = 1 V, BW 10 Hz to 5 MHz 1 AD7111 ±15 V None None 900 kHz <1 nF LH00321 ±10 V 1 pF to 5 pF 1 pF to 4 pF 25 MHz <10 pF BASE COMMON (Pin 12 and Pin 13) provides extra voltage compliance at the output nodes in the negative direction (to −1 V at 25°C); it is not required if the output swing does not exceed −300 mV. Table 5 compares performance for various load resistances, using this configuration. VX +VS N/A −70 dB 50 μV 120 μV 30 μV 500 μV 1 VX 2 HF COMP CC = 3nF VY 3 VY1 4 +VS 5 –VS 0.47µF –VS For a given load resistance, the output power can be quadrupled by using both channels in parallel, as shown in Figure 21. The small signal silicon diode, D, connected between ground and AD539 BASE COMMON 13 VW = D* 12 VXVY VU RL CHAN2 11 OUTPUT VY2 7 INPUT COMMON Z2 10 NC 8 OUTPUT COMMON W2 9 NC * REQUIRED IF LOAD RESISTANCE >300Ω Figure 21. Minimal Single-Channel Multiplier (16-Lead SBDIP and PDIP Shown) Minimal Wideband Configurations The maximum bandwidth can be achieved using the AD539 with simple resistive loads to convert the output currents to voltages. These currents (nominally ±1 mA FS, ±2.25 mA peak, into short-circuit loads) are shunted by their source resistance of 1.25 kΩ (each channel). Calculations of load power and effective scaling-voltage must allow for this shunting effect when using resistive loads. The output power is quite low in this mode, and the device behaves more like a voltage-controlled attenuator than a classical multiplier. The matching of gain and phase between the two channels is excellent. From dc to 10 MHz, the gains are typically within ±0.025 dB (measured using precision 50 Ω load resistors) and the phase difference within ±0.1°. Z1 15 NC CHAN1 14 OUTPUT 6 For the circuit of Figure 20. In all cases, 0.47 μF ceramic supply decoupling capacitors were used at each IC pin, the AD539 supplies were ±5 V, and the control compensation capacitor CC was 3 nF. W1 16 NC Figure 9 shows the high frequency response for Figure 21 with the AD539 in a carefully shielded 50 Ω test environment; the test system response was first characterized and this background removed by digital signal processing to show the inherent circuit response. In many applications phase linearity over frequency is important. Figure 10 shows the deviation from an ideal linear-phase response for a typical AD539 over the frequency range dc to 10 MHz, for VX = 3 V; the peak deviation is slightly more than 1°. Differential phase linearity (the stability of phase over the signal window at a fixed frequency) is shown in Figure 11 for f = 3.579 MHz and various values of VX. The most rapid variation occurs for VY above 1 V; in applications where this characteristic is critical, it is recommended that a ground-referenced, negative-going signal be used. Table 5. Summary of Performance for Minimal Configuration Load Resistance FS Output Voltage DC AC (RMS) FS Output Power in Load Peak Output Voltage DC AC (RMS) Peak Output Power in Load Effective Scaling Voltage, VU’ 1 2 09679-021 Table 4. Summary of Operating Conditions and Performance for the AD539 When Used with Various External Op Amp Output Amplifiers 50 Ω 75 Ω 100 Ω 150 Ω 600 Ω Open Circuit ±92.6 mV 65.5 mV rms 0.086 mW −10.5 dBm ±134 mV 94.7 mV rms 0.12 mW −9.2 dBm ±172 mV 122 mV rms 0.15 mW −8.3 dBm ±242 mV 171 mV rms 0.195 mW −7.1 dBm ±612 mV 433 mV rms 0.312 mW −5.05 dBm ±1 V Note 1 N/A 2 N/A ±210 mV 148 mV rms 0.44 mW −7 dBm 67.5 V ±300 mV 212 mV rms 0.6 mW −4.4 dBm 46.7 V ±388 mV 274 mV rms 0.75 mW −2.5 dBm 36.3 V ±544 mV 385 mV rms 1 mW 0 dBm 25.8 V ±1 mV Note1 ±1 V Note1 10.2 V ±1 V Note1 ±1 V Note1 5V Peak negative voltage swing limited by output compliance. N/A means not applicable. Rev. B | Page 13 of 20 AD539 When only one signal channel must be handled, it is often advantageous to use the channels differentially. By subtracting the Channel 1 and Channel 2 outputs, any residual transient control feedthrough is virtually eliminated. Figure 22 shows a minimal configuration where it is assumed that the host system uses differential signals and a 50 Ω environment throughout. This figure also shows a recommended control feedforward network to improve large-signal response time. The control feedthrough glitch is shown in Figure 12, where the input was applied to Channel 1 and only the output of Channel 1 was displayed on the oscilloscope. The improvement obtained when CH1 and CH2 outputs are viewed differentially is clear in Figure 13. The envelope rise time is of the order of 40 ns. 56Ω CHAN1 INPUT 51Ω 51Ω CHAN2 INPUT VX VY1 100Ω 5nF 1 VX 2 HF COMP 3 VY1 4 +VS 5 –VS 6 VY2 7 INPUT COMMON Z2 10 8 OUTPUT COMMON W2 9 W1 16 0.1µF 0.1µF +5V –5V VX 2 HF COMP 3 VY1 4 +VS 5 –VS +VS VY2 150pF AD539 BASE COMMON CHAN1 OUTPUT 13 CHAN1 14 OUTPUT AD539 BASE COMMON R1 13 VW = VX (VY2 – VY1) 12 CHAN2 11 OUTPUT VY2 7 INPUT COMMON Z2 10 8 OUTPUT COMMON W2 9 R2 Figure 23. Low Distortion Differential Configuration (16-Lead SBDIP and PDIP Shown) 12 CHAN2 11 OUTPUT Z1 15 6 Z1 15 CHAN1 14 OUTPUT W1 16 1 CC = 3nF –VS CHAN2 OUTPUT 09679-022 CONTROL INPUT (VS) caused by a collector modulation effect in the controlled cascode stages (see the Theory of Operation section) by keeping the voltage swing at the outputs to an acceptable level and should have a value in the range of 100 Ω to 1000 Ω. Figure 14 shows the improvement in distortion over the standard configuration (compare with Figure 5). Note that the Z nodes (Pin 10 and Pin 15) are returned to the control input; this prevents the early onset of output transistor saturation. 09679-023 Differential Configurations Figure 22. High Speed Differential Configuration (16-Lead SBDIP and PDIP Shown) Lower distortion results when Channel 1 and Channel 2 are driven by complementary inputs and the outputs are utilized differentially, using a circuit such as the one shown in Figure 23. Resistors R1 and R2 minimize a secondary distortion mechanism Even lower distortion (0.01%, or −80 dB) has been measured using two output op amps in a configuration similar to that shown in Figure 20 connected as virtual ground current summers (to prevent the modulation effect). Note that to generate the difference output it is merely necessary to connect the output of the Channel 1 op amp to the Z node of Channel 2. In this way, the net input to the Channel 2 op amp is the difference signal, and the low distortion resultant appears as its output. Rev. B | Page 14 of 20 AD539 zero (or slightly negative, to override the residual input offset) there is still a small amount of capacitive feedthrough at high frequencies; therefore, extreme care is required in laying out the PC board to minimize this effect. In addition, for small values of VX, the combination of this feedthrough with the multiplier output can cause a dip in the response where they are out of phase. Figure 15 shows the ac response from the noninverting input, with the response from the inverting input, VY2, essentially identical. Test conditions include VY1 = 0.5 V rms for values of VX from 10 mV to 3.16 V; this is with a 75 Ω load on the output. The feedthrough at VX = −10 mV is also shown. A 50 MHZ VOLTAGE-CONTROLLED AMPLIFIER Figure 24 is a circuit for a 50 MHz voltage-controlled amplifier (VCA) suitable for use in high quality video-speed applications. The outputs from the two signal channels of the AD539 are applied to the op amp in a subtracting configuration. This connection has two main advantages: first, it results in better rejection of the control voltage, particularly when overdriven (VX < 0 V or VX > 3.3 V). Secondly, it provides a choice of either noninverting or inverting response, using either input, VY1 or VY2, respectively. In this circuit, the output of the op amp equals V X (VY 1 − VY 2 ) 2V for V X > 0 V With the VCA driving a 75 Ω load and the transient response of the signal channel at VX = 2 V, VY = VOUT = ±1 V is shown in Figure 16. The rise and fall times are approximately 7 ns. Therefore, the gain is unity at VX = 2 V. Because VX can overrange to 3.3 V, the maximum gain in this configuration is about 4.3 dB. A more detailed description of this circuit, including differential gain and phase characteristics, is given in the AN-213 Application Note, Low Cost, Two Chip Voltage-Controlled Amplifier and Video Switch, available from Analog Devices. The −3 dB bandwidth of this circuit is over 50 MHz at a full gain and is not substantially affected at lower gains. When VX is VX D1 75Ω VY2 IN CF 600pF 2 CC 3000pF +9V VY2 IN 1 VX –9V 10Ω 75Ω 1µF 10Ω 1µF 3 W1 16 HF COMP 2.7Ω 180Ω AD539 +VS 5 –VS 6 VY2 7 INPUT COMMON 8 OUTPUT COMMON BASE COMMON +9V 100kΩ CHAN1 14 OUTPUT VY1 4 75Ω Z1 15 (OPTIONAL) OUTPUT OFFSET 50kΩ –9V +9V 1 10 13 9 14 12 CHAN2 11 OUTPUT 0.47µF VOUT 7 180Ω 3 CF 0.25pF TO Z2 10 1.5pF W2 9 NOTES 1. THOMPSON-CSF BAR. 10 OR SIMILAR SCHOTTKY DIODE SHORT DIRECT CONNECTION TO GROUND PLANE. 200Ω GAIN ADJUST (±4% RANGE) 470Ω 2.7Ω 0.47µF –9V Figure 24. A Wide Bandwidth Voltage-Controlled Amplifier (16-Lead SBDIP and PDIP Shown) Rev. B | Page 15 of 20 09679-024 VOUT = AD539 rms) to avoid clipping. Note that offset adjustment is needed for the op amps to maintain accurate dc levels at the output in high gain applications: the noise gain is 6 V/VX, or 600 at VX = 0.01 V. BASIC DIVIDER CONNECTIONS Standard Scaling The AD539 provides excellent operation as a two-quadrant analog divider in wideband, wide gain-range applications, with the advantage of dual-channel operation. Figure 25 shows the simplest connections for division with a transfer function of The gain magnitude response for this configuration using the LH0032 op amps with nominally 12 pF compensation (HF COMP, Pin 2, to VY1, Pin 3) and CF = 7 pF is shown in Figure 17; however, other amplifiers can also be used. Because there is some manufacturing variation in the HF response of the op amps and load conditions also affect the response, these capacitors should be adjustable: 5 pF to 15 pF is recommended for both positions. The bandwidth in this configuration is nominally 17 MHz at VX = 3.162 V, 4.5 MHz at VX = 1 V, 350 kHz at VX = 0.1 V, and 35 kHz at VX = 0.01 V. The general recommendations regarding the use of a good ground plane and power supply decoupling should be carefully observed. Other suitable high speed op amps include: AD844, AD827, and AD811. Consult these data sheets for suitable applications circuits. VY = −VUVW/VX Recalling that the nominal value of VU is 1 V, this can be simplified to VY = −VW/VX where all signals are expressed in volts. The circuit thus exhibits unity gain for VX = 1 V and a gain of 40 dB when VX = 0.01 V. The output swing is limited to ±2 V nominal full scale and ±4.2 V peak (using a −VS supply of at least 7.5 V for the AD539). Because the maximum loss is 10 dB (at VX = 3.162 V), it follows that the maximum input to VW should be ±6.3 V (4.4 V rms) for low distortion applications and no more than ±13.4 V (9.5 V NUMERATOR 1 VW1 VX 2 HF COMP 3 VY1 CC = 3nF 0.47µF 0.47µF NOTES 1. DECOUPLE OP AMP SUPPLIES. +5V –7.5V 2pF TO 15pF W1 16 1 Z1 15 NC 2pF TO 15pF 2 CHAN1 14 OUTPUT AD539 4 +VS 5 –VS 6 VY2 7 INPUT COMMON 8 OUTPUT COMMON 3 VY1 = – VW1 VX 13 BASE COMMON LH0032 12 CHAN2 11 OUTPUT Z2 10 NC 3 2 VW2 VX 2pF TO 15pF W2 9 2pF TO 15pF NUMERATOR 2 VW2 Figure 25. 2-Channel Divider with 1 V Scaling (16-Lead SBDIP and PDIP Shown) Rev. B | Page 16 of 20 VY2 = – 09679-025 DENOMINATOR INPUT, VX AD539 OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 8 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 26. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN PIN 1 0.200 (5.08) MAX 0.080 (2.03) MAX 16 9 1 8 0.840 (21.34) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 0.070 (1.78) SEATING (2.54) 0.030 (0.76) PLANE BSC 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 27. 16-Lead Side-Brazed Ceramic Dual In-Line Package (SBDIP] (D-16) Dimensions shown in inches and (millimeters) Rev. B | Page 17 of 20 073106-B 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) AD539 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.088 (2.24) 0.054 (1.37) 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 19 18 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) BSC 8 14 13 9 45° TYP 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 022106-A 0.100 (2.54) 0.064 (1.63) Figure 28. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 AD539JN AD539JNZ AD539JDZ AD539KN AD539KNZ AD539KDZ AD539SD AD539SD/883B 5962-8980901EA AD539SE/883B 1 2 Notes 2 Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description 16-Lead PDIP 16-Lead PDIP 16-Lead SBDIP 16-Lead PDIP 16-Lead PDIP 16-Lead SBDIP 16-Lead SBDIP 16-Lead SBDIP 16-Lead SBDIP 20-Terminal LCC Z = RoHS Compliant Part. The standard military drawing version of the AD539 (5962-8980901EA) is now available. Rev. B | Page 18 of 20 Package Option N-16 N-16 D-16 N-16 N-16 D-16 D-16 D-16 D-16 E-20-1 AD539 NOTES Rev. B | Page 19 of 20 AD539 NOTES ©1983–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09679-0-4/11(B) Rev. B | Page 20 of 20