50 Hz to 6 GHz, 50 dB TruPwr™ Detector AD8363 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Power amplifier linearization/control loops Multi-Standard, Multi-Carrier Wireless Infrastructure (MCGSM, CDMA, WCDMA, TD-SCDMA, WiMAX, LTE) Transmitter power control Transmitter signal strength indication (TSSI) RF instrumentation VTGT VREF VPOS COMM 12 11 10 9 AD8363 NC 13 8 TEMP 7 VSET INLO 15 6 VOUT TCM1 16 5 CLPF X2 INHI 14 X2 1 2 3 4 TCM2/PWDN CHPF VPOS COMM 07368-001 Accurate rms-to-dc conversion from 50 Hz to 6 GHz Single-ended input dynamic range of >50 dB No balun or external input tuning required Waveform and modulation independent RF power detection Linear-in-decibels output, scaled: 52 mV/dB Log conformance error: <±0.15 dB Temperature stability: <±0.5 dB Voltage supply range: 4.5 V to 5.5 V Operating temperature range: −40°C to +125°C Power-down capability to 1.5 mW Small footprint, 4 mm × 4 mm, LFCSP Figure 1. AD8363 Block Diagram GENERAL DESCRIPTION The AD8363 is a true rms responding power detector that can be directly driven with a single-ended 50 Ω source. This feature makes the AD8363 frequency versatile by eliminating the need for a balun or any other form of external input tuning for operation up to 6 GHz. The AD8363 provides an accurate power measurement, independent of waveform, for a variety of high frequency communication and instrumentation systems. Requiring only a single supply of 5 V and a few capacitors, it is easy to use and provides high measurement accuracy. The AD8363 can operate from arbitrarily low frequencies to 6 GHz and can accept inputs that have rms values from less than −50 dBm to at least 0 dBm, with large crest factors exceeding the requirements for accurate measurement of WiMAX, CDMA, W-CDMA, TD-SCDMA, multicarrier GSM, and LTE signals. Used as a power measurement device, VOUT is connected to VSET. The output is then proportional to the logarithm of the rms value of the input. The reading is presented directly in decibels and is conveniently scaled to 52 mV/dB, or approximately 1 V per decade; however, other slopes are easily arranged. In controller mode, the voltage applied to VSET determines the power level required at the input to null the deviation from the setpoint. The output buffer can provide high load currents. The AD8363 has 1.5 mW power consumption when powered down by a logic high applied to the TCM2/PWDN pin. It powers up within about 30 μs to its nominal operating current of 60 mA at 25°C. The AD8363 is available in a 4 mm × 4 mm 16-lead LFCSP for operation over the −40°C to +125°C temperature range. A fully populated RoHS compliant evaluation board is also available. The AD8363 can determine the true power of a high frequency signal having a complex low frequency modulation envelope, or it can be used as a simple low frequency rms voltmeter. The highpass corner generated by its internal offset-nulling loop can be lowered by a capacitor added on the CHPF pin. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8363 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 VSET Interface ............................................................................ 17 Applications ....................................................................................... 1 Output Interface ......................................................................... 17 Functional Block Diagram .............................................................. 1 VTGT Interface .......................................................................... 18 General Description ......................................................................... 1 Measurement Mode Basic Connections.................................. 18 Revision History ............................................................................... 2 System Calibration and Error Calculation.............................. 19 Specifications..................................................................................... 3 Operation to 125°C .................................................................... 19 Absolute Maximum Ratings............................................................ 7 Output Voltage Scaling .............................................................. 20 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Offset Compensation, Minimum CLPF, and Maximum CHPF Capacitance Values..................................................................... 20 Typical Performance Characteristics ............................................. 9 Choosing a Value for CLPF.......................................................... 21 Theory of Operation ...................................................................... 14 RF Pulse Response and VTGT ................................................. 23 Square Law Detector and Amplitude Target .............................. 14 Controller Mode Basic Connections ....................................... 23 RF Input Interface ...................................................................... 15 Constant Output Power Operation.......................................... 24 Choice of RF Input Pin .............................................................. 15 Description of RF Characterization ......................................... 25 Small Signal Loop Response ..................................................... 15 Evaluation and Characterization Circuit Board Layouts ...... 26 Temperature Sensor Interface ................................................... 16 Assembly Drawings .................................................................... 28 VREF Interface ........................................................................... 16 Outline Dimensions ....................................................................... 29 Temperature Compensation Interface ..................................... 16 Ordering Guide .......................................................................... 29 Power-Down Interface ............................................................... 17 REVISION HISTORY 3/15—Rev. A to Rev. B Changes to Figure 2 and Table 3 ..................................................... 8 Changes to Controller Mode Basic Connections Section ......... 23 Updated Outline Dimensions ....................................................... 29 Changes to the Ordering Guide.................................................... 29 7/11—Rev. 0 to Rev. A Changes to Features Section and Applications Section ............... 1 Added 3-Point Calibration to Table 1 for All MHz...................... 3 Replaced Typical Performance Characteristics Section; Renumbered Sequentially................................................................ 9 Changes to Theory of Operation Section .................................... 14 Changes to Temperature Compensation Interface Section ...... 16 Changes to System Calibration and Error Calculation Section and Changes to Figure 44 and Figure 45 ....................... 19 Deleted Basis for Error Calculations Section.............................. 20 Changes to Figure 46 ...................................................................... 20 Deleted Selecting and Increasing Calibration Points to Improve Accuracy over a Reduced Range Section..................... 22 Deleted Altering the Slope Section .............................................. 23 Added Output Voltage Scaling Section ....................................... 23 5/09—Revision 0: Initial Version Rev. B | Page 2 of 29 Data Sheet AD8363 SPECIFICATIONS VPOS = 5 V, TA = 25°C, ZO = 50 Ω, single-ended input drive, VOUT connected to VSET, VTGT = 1.4 V, CLPF = 3.9 nF, CHPF = 2.7 nF, error referred to best-fit line (linear regression) from −20 dBm to −40 dBm, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Maximum Input Frequency RF INPUT INTERFACE Input Resistance Common-Mode DC Voltage 100 MHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 900 MHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance Conditions Min INHI (Pin 14), INLO (Pin 15), ac-coupled Single-ended drive TCM1 (Pin 16) = 0.47 V, TCM2 (Pin 1) = 1.0 V, INHI input PIN = −10 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm, and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −10 dBm −40°C < TA < +85°C; PIN = −40 dBm 13 dB peak-to-rms ratio (W-CDMA), over 40 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 40 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 40 dB dynamic range 256 QAM, CF = 8 dB, over 40 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.5 V, TCM2 (Pin 1) = 1.2 V, INHI input PIN = −15 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm, and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −15 dBm −40°C < TA < +85°C; PIN = −40 dBm 13 dB peak-to-rms ratio (W-CDMA), over 40 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 40 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 40 dB dynamic range 256 QAM, CF = 8 dB, over 40 dB dynamic range Single-ended drive Rev. B | Page 3 of 29 Typ Max Unit 6 GHz 50 2.6 Ω V 2.47 0.92 V V 64 65 9 −56 dB dB dBm dBm −0.2/+0.3 −0.5/+0.6 51.7 −58 <±0.1 <±0.1 <±0.1 dB dB mV/dB dBm dB dB dB <±0.1 49 − j0.09 dB Ω 2.2 0.91 V V 60 54 −2 −56 dB dB dBm dBm +0.6/−0.4 +0.8/−0.6 51.8 −58 <±0.1 <±0.1 <±0.1 dB dB mV/dB dBm dB dB dB <±0.1 60 − j3.3 dB Ω AD8363 Parameter 1.9 GHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 2.14 GHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response Rise Time Fall Time Input Impedance 2.6 GHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Data Sheet Conditions TCM1 (Pin 16) = 0.52 V, TCM2 (Pin 1) = 0.51 V, INHI input PIN = −15 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm, and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −15 dBm −40°C < TA < +85°C; PIN = −40 dBm 13 dB peak-to-rms ratio (W-CDMA), over 37 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 37 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 37 dB dynamic range 256 QAM, CF = 8 dB, over 37 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.52 V, TCM2 (Pin 1) = 0.6 V, INHI input PIN = −15 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −15 dBm −40°C < TA < +85°C; PIN = −40 dBm 13 dB peak-to-rms ratio (W-CDMA), over 35 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 35 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 35 dB dynamic range 256 QAM, CF = 8 dB, over 35 dB dynamic range Transition from no input to 1 dB settling at RFIN = −10 dBm, CLPF = 390 pF, CHPF = open Transition from −10 dBm to within 1 dB of final value (that is, no input level), CLPF = 390 pF, CHPF = open Single-ended drive TCM1 (Pin 16) = 0.54 V, TCM2 (Pin 1) = 1.1 V, INHI input PIN = −15 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −15 dBm −40°C < TA < +85°C; PIN = −40 dBm Rev. B | Page 4 of 29 Min Typ Max Unit 2.10 0.8 V V 56 48 −6 −53 dB dB dBm dBm +0.3/−0.5 +0.4/−0.4 52 −55 ±0.1 ±0.1 ±0.1 dB dB mV/dB dBm dB dB dB ±0.1 118 − j26 dB Ω 2.0 0.71 V V 55 44 −8 −52 dB dB dBm dBm +0.1/−0.2 +0.3/−0.5 52.2 −54 ±0.1 ±0.1 ±0.1 dB dB mV/dB dBm dB dB dB ±0.1 3 dB µs 15 µs 130 − j49 Ω 1.84 0.50 V V 50 41 −7 −48 dB dB dBm dBm +0.5/−0.2 +0.6/−0.2 dB dB Data Sheet Parameter Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 3.8 GHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 5.8 GHz Output Voltage: High Power In Output Voltage: Low Power In ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance OUTPUT INTERFACE Output Swing, Controller Mode Current Source/Sink Capability Voltage Regulation Rise Time AD8363 Conditions Min 13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic range 256 QAM, CF = 8 dB, over 32 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.56 V, TCM2 (Pin 1) = 1.0 V, INLO input PIN = −20 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −20 dBm −40°C < TA < +85°C; PIN = −40 dBm 13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic range 256 QAM, CF = 8 dB, over 32 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.88 V, TCM2 (Pin 1) = 1.0 V, INLO input PIN = −20 dBm PIN = −40 dBm CW input, TA = 25°C 3-point calibration at 0 dBm, −10 dBm and −40 dBm Best-fit (linear regression) at −20 dBm and −40 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = −20 dBm −40°C < TA < +85°C; PIN = −40 dBm 13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic range 256 QAM, CF = 8 dB, over 32 dB dynamic range Single-ended drive VOUT (Pin 6) Swing range minimum, RL ≥ 500 Ω to ground Swing range maximum, RL ≥ 500 Ω to ground Output held at VPOS/2 ILOAD = 8 mA, source/sink Transition from no input to 1 dB settling at RFIN = −10 dBm, CLPF = 390 pF, CHPF = open Rev. B | Page 5 of 29 Typ 52.9 −49 ±0.1 ±0.1 ±0.1 Max Unit mV/dB dBm dB dB dB ±0.1 95 − j65 dB Ω 1.54 0.54 V V 50 43 −5 −48 dB dB dBm dBm +0.1/−0.7 +0.4/−0.5 50.0 −51 ±0.1 ±0.1 ±0.1 dB dB mV/dB dBm dB dB dB ±0.1 42 − j4.5 dB Ω 1.38 0.36 V V 50 45 −3 −48 dB dB dBm dBm +0.1/−0.6 +0.3/−0.8 51.1 −47 ±0.1 ±0.1 ±0.1 dB dB mV/dB dBm dB dB dB ±0.1 28 + j1.6 dB Ω 0.03 4.8 V V mA % µs 10/10 −0.2/+0.1 3 AD8363 Parameter Fall Time Noise Spectral Density SETPOINT INPUT Voltage Range Input Resistance Logarithmic Scale Factor Logarithmic Intercept TEMPERATURE COMPENSATION Input Voltage Range Input Bias Current, TCM1 Input Resistance, TCM1 Input Current, TCM2 Input Resistance, TCM2 VOLTAGE REFERENCE Output Voltage Temperature Sensitivity Current Source/Sink Capability Voltage Regulation TEMPERATURE REFERENCE Output Voltage Temperature Coefficient Current Source/Sink Capability Voltage Regulation RMS TARGET INTERFACE Input Voltage Range Input Bias Current Input Resistance POWER-DOWN INTERFACE Logic Level to Enable Logic Level to Disable Input Current Enable Time Disable Time POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Power-Down Current Data Sheet Conditions Transition from −10 dBm to within 1 dB of final value (that is, no input level), CLPF = 390 pF, CHPF = open Measured at 100 kHz VSET (Pin 7) Log conformance error ≤ 1 dB, minimum 2.14 GHz Log conformance error ≤ 1 dB, maximum 2.14 GHz Min f = 2.14 GHz, −40°C ≤ TA ≤ +85°C f = 2.14 GHz, −40°C ≤ TA ≤ +85°C, referred to 50 Ω TCM1 (Pin 16), TCM2 (Pin 1) Typ 15 nV/√Hz 2.0 0.7 72 19.2 −54 V V kΩ dB/V dBm 2.5 −140 80 5 2 750 −2 −3 500 2.3 0.04 −0.06 −0.18 4/0.05 3/0.05 −0.6 1.4 5 4/0.05 3/0.05 −0.1 1.4 VTGT = 1.4 V TCM2 (Pin1) VPWDN decreasing VPWDN increasing VTCM2 = 5 V VTCM2 = 4.5 V VTCM2 = 1 V VTCM2 = 0 V TCM2 low to VOUT at 1 dB of final value, CLPF = 470 pF, CHPF = 220 pF, RFIN = 0 dBm TCM2 high to VOUT at 1 dB of final value, CLPF = 470 pF, CHPF = 220 pF, RFIN = 0 dBm VPOS (Pin 3, Pin 10) 4.5 TA = 25°C, RFIN = −55 dBm TA = 85°C VTCM2 > VPOS − 0.3 V Rev. B | Page 6 of 29 Unit µs 45 0 VTCM1 = 0 V VTCM1 = 0.5 V VTCM1 > 0.7 V VTCM2 = 5 V VTCM2 = 4.5 V VTCM2 = 1 V VTCM2 = 0 V 0.7 V ≤ VTCM2 ≤ 4.0 V VREF (Pin 11) RFIN = −55 dBm 25°C ≤ TA ≤ 70°C 70°C ≤ TA ≤ 125°C −40°C ≤ TA ≤ +25°C 25°C ≤ TA ≤ 125°C −40°C ≤ TA < +25°C TA = 25°C, ILOAD = 3 mA TEMP (Pin 8) TA = 25°C, RL ≥ 10 kΩ −40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ 25°C ≤ TA ≤ 125°C −40°C ≤ TA < +25°C TA = 25°C, ILOAD = 3 mA VTGT (Pin 12) Max 2.5 V µA µA kΩ µA µA µA µA kΩ V mV/°C mV/°C mV/°C mA mA % V mV/°C mA mA % 14 100 V µA kΩ 4.2 4.7 2 750 −2 −3 35 V V µA µA µA µA µs 25 µs 5 60 72 300 5.5 V mA mA µA Data Sheet AD8363 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS Input Average RF Power1 Equivalent Voltage, Sine Wave Input Internal Power Dissipation θJC2 θJB2 θJA2 ΨJT2 ΨJB2 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 21 dBm 2.51 V rms 450 mW 10.6°C/W 35.3°C/W 57.2°C/W 1.0°C/W 34°C/W 150°C −40°C to +125°C −65°C to +150°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION This is for long durations. Excursions above this level, with durations much less than 1 second, are possible without damage. 2 No airflow with the exposed pad soldered to a 4-layer JEDEC board. 1 Rev. B | Page 7 of 29 AD8363 Data Sheet 13 NC 14 INHI 16 TCM1 15 INLO PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TCM2/PWDN 1 12 VTGT CHPF 2 AD8363 11 VREF VPOS 3 TOP VIEW 10 VPOS 9 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE SYSTEM COMMON CONNECTION AND IT MUST HAVE BOTH A GOOD THERMAL AND GOOD ELECTRICAL CONNECTION TO GROUND. 07368-002 VSET 7 COMM TEMP 8 CLPF 5 VOUT 6 COMM 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic TCM2/PWDN 2 CHPF 3, 10 VPOS 4, 9 COMM 5 CLPF 6 VOUT 7 VSET 8 11 12 TEMP VREF VTGT 13 NC 14 INHI 15 INLO 16 TCM1 EPAD Description This is a dual function pin used for controlling the amount of nonlinear intercept temperature compensation at voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the shutdown function is not used, this pin can be connected to the VREF pin through a voltage divider. Connect this pin to VPOS via a capacitor to determine the −3 dB point of the input signal highpass filter. Only add a capacitor when operating at frequencies below 10 MHz. Supply for the Device. Connect these pins to a 5 V power supply. Pin 3 and Pin 10 are not internally connected; therefore, both must connect to the source. System Common Connection. Connect these pins via low impedance to system common. Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. Minimum CLPF value is 390 pF. Output Pin in Measurement Mode (Error Amplifier Output). In measurement mode, this pin is connected to VSET. This pin can be used to drive a gain control when the device is used in controller mode. The voltage applied to this pin sets the decibel value of the required RF input voltage that results in zero current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain amplifier (VGA) gain such that a 50 mV change in VSET reduces the gain by approximately 1 dB. Temperature Sensor Output. General-Purpose Reference Voltage Output of 2.3 V. The voltage applied to this pin determines the target power at the input of the RF squaring circuit. The intercept voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest factor capacity; however, this may affect the system loop response. No Connect. This is the RF input pin for frequencies up to and including 2.6 GHz. The RF input signal is normally ac-coupled to this pin through a coupling capacitor. This is the RF input pin for frequencies above 2.6 GHz. The RF input signal is normally ac-coupled to this pin through a coupling capacitor. This pin is used to adjust the intercept temperature compensation. Connect this pin to VREF through a voltage divider or to an external dc source. Exposed Pad. The exposed pad is the system common connection and it must have both a good thermal and good electrical connection to ground. Rev. B | Page 8 of 29 Equivalent Circuit See Figure 39 See Figure 48 Not applicable Not applicable See Figure 41 See Figure 41 See Figure 40 See Figure 35 See Figure 36 See Figure 42 Not applicable See Figure 34 See Figure 34 See Figure 38 Not applicable Data Sheet AD8363 TYPICAL PERFORMANCE CHARACTERISTICS 4 3.5 3 3.5 3 3.0 2 3.0 2 2.5 1 2.5 1 2.0 0 2.0 0 1.5 –1 1.5 –1 1.0 –2 1.0 –2 0.5 –3 0.5 –3 –10 0 –4 10 –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 VOUT (V) Figure 6. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 100 MHz, CW 4 4.0 4 3.5 3 3.5 3 3.0 2 3.0 2 2.5 1 2.5 1 2.0 0 2.0 0 1.5 –1 1.5 –1 1.0 –2 1.0 –2 0.5 –3 0.5 –3 0 –60 –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 VOUT (V) ERROR (dB) 4.0 0 –60 07368-104 VOUT (V) Figure 3. VOUT and Log Conformance vs. Input Power and Temperature at 100 MHz Figure 4. VOUT and Log Conformance Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 900 MHz, CW, Typical Device –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 Figure 7. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 900 MHz, CW 4 4.0 4 3.5 3 3.5 3 3.0 2 3.0 2 2.5 1 2.5 1 2.0 0 2.0 0 1.5 –1 1.5 –1 1.0 –2 1.0 –2 0.5 –3 0.5 –3 0 –60 –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 VOUT (V) ERROR (dB) 4.0 0 –60 07368-105 VOUT (V) 0 –60 Figure 5. VOUT and Log Conformance Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 1.90 GHz, CW, Typical Device ERROR (dB) –30 –20 PIN (dBm) 07368-107 –40 –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 ERROR (dB) –50 07368-108 0 –60 ERROR (dB) 4.0 07368-106 4 ERROR (dB) 4.0 07368-103 VOUT (V) VPOS = 5 V, ZO = 50 Ω, single-ended input drive, VOUT connected to VSET, VTGT = 1.4 V, CLPF = 3.9 nF, CHPF = 2.7 nF, TA = +25°C (black), −40°C (blue), +85°C (red), where appropriate. Error calculated using 3-point calibration at 0 dBm, −10 dBm, and −40 dBm, unless otherwise indicated. Input RF signal is a sine wave (CW), unless otherwise indicated. Figure 8. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 1.90 GHz, CW Rev. B | Page 9 of 29 4 3.5 3 3.5 3 3.0 2 3.0 2 2.5 1 2.5 1 2.0 0 2.0 0 1.5 –1 1.5 –1 1.0 –2 1.0 –2 0.5 –3 0.5 –3 –10 0 –4 10 –50 –40 –20 –30 PIN (dBm) –10 0 –4 10 Figure 12. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 2.14 GHz, CW 3.00 6 2.75 5 2.75 5 2.50 4 2.50 4 2.25 3 2.25 3 2.00 2 2.00 2 1.75 1 1.75 1 1.50 0 1.50 0 1.25 –1 1.25 –1 1.00 –2 1.00 –2 0.75 –3 0.75 –3 0.50 –4 0.50 –4 0.25 –5 0.25 –5 0 –60 –50 –40 –30 –20 PIN (dBm) –10 0 –6 10 VOUT (V) 6 ERROR (dB) 3.00 0 –60 07368-110 Figure 10. VOUT and Log Conformance Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 2.6 GHz, CW, Typical Device –50 –40 –30 –20 PIN (dBm) –10 0 –6 10 Figure 13. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 2.6 GHz, CW 6 3.00 6 2.75 5 2.75 5 2.50 4 2.50 4 2.25 3 2.25 3 2.00 2 2.00 2 1.75 1 1.75 1 1.50 0 1.50 0 1.25 –1 1.25 –1 1.00 –2 1.00 –2 0.75 –3 0.75 –3 0.50 –4 0.50 –4 0.25 –5 0.25 –5 –50 –40 –30 –20 PIN (dBm) –10 0 –6 10 0 –60 07368-111 0 –60 ERROR (dB) 3.00 OUTPUT VOLTAGE (V) VOUT (V) Figure 9. VOUT and Log Conformance Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 2.14 GHz, CW, Typical Device OUTPUT VOLTAGE (V) 0 –60 Figure 11. VOUT and Log Conformance Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 3.8 GHz, CW, Typical Device ERROR (dB) –30 –20 PIN (dBm) 07368-113 –40 –50 –40 –30 –20 PIN (dBm) –10 0 –6 10 ERROR (dB) –50 07368-114 0 –60 07368-112 4.0 VOUT (V) 4 ERROR (dB) 4.0 ERROR (dB) Data Sheet 07368-109 VOUT (V) AD8363 Figure 14. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 3.8 GHz, CW Rev. B | Page 10 of 29 3.00 6 5 2.75 5 2.50 4 2.50 4 2.25 3 2.25 3 2.00 2 2.00 2 1.75 1 1.75 1 1.50 0 1.50 0 1.25 –1 1.25 –1 1.00 –2 1.00 –2 0.75 –3 0.75 –3 0.50 –4 0.50 –4 0.25 –5 0.25 –5 –40 –30 –20 PIN (dBm) –10 0 0 –60 Figure 15. VOUT and Log Conformance Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 5.8 GHz, Typical Device –30 –20 PIN (dBm) –10 0 –6 10 3 ERROR CW ERROR W-CDMA 1 CAR TM1 64 DPCH ERROR W-CDMA 2 CAR TM1 64 DPCH ERROR W-CDMA 3 CAR TM1 64 DPCH ERROR W-CDMA 4 CAR TM1 64 DPCH 2 2 1 0 0 –1 –1 –2 –2 –50 –40 –30 –20 PIN (dBm) –10 0 10 –3 –60 CW W-CDMA 1 CAR TM1 32 DPCH QPSK 256QAM WIMAX 256 SUBCR, 64 QAM, 10MHz BW CDMA2K 9 CH SR1 4 CAR –50 –40 –30 –20 PIN (dBm) –10 0 10 07368-028 ERROR (dB) 1 07368-026 ERROR (dB) –40 Figure 18. Distribution of VOUT and Error with Respect to 25°C Ideal Line over Temperature vs. Input Amplitude at 5.8 GHz, CW 3 –3 –60 –50 07368-118 –50 –6 10 Figure 19. Error from CW Linear Reference vs. Input Amplitude with Modulation, Frequency at 2.6 GHz, CLPF = 0.1 μF, INHI Input Figure 16. Error from CW Linear Reference vs. Input Amplitude with Modulation, Frequency at 2.14 GHz, CLPF = 0.1 μF, INHI Input NOISE SPECTRAL DENSITY (nV/ Hz) 160 100MHz 900MHz 1.9GHz 2.14GHz 5.8GHz 3.8GHz 2.6GHz 140 120 100 80 60 40 20 07368-030 0 100 Figure 17. Single-Ended Input Impedance (S11) vs. Frequency; ZO = 50 Ω, INHI or INLO 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 20. Typical Noise Spectral Density of VOUT; All CLPF Values Rev. B | Page 11 of 29 07368-031 0 –60 OUTPUT VOLTAGE (V) 6 2.75 ERROR (dB) 3.00 ERROR (dB) AD8363 07368-115 OUTPUT VOLTAGE (V) Data Sheet AD8363 Data Sheet 5.0 5.0 –20dBm –30dBm –40dBm 0dBm 4.5 4.0 4.0 3.5 VOUT (V) 2.0 1.5 0.5 0 0 –0.5 –0.5 5 6 7 8 9 10 11 12 13 14 15 16 TIME (µs) –1.0 –2 07368-033 4 Figure 21. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 390 pF, CHPF = Open, Rising Edge 5.0 5.0 4.5 4.5 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TIME (µs) 0dBm –10dBm –20dBm –30dBm –40dBm RF ENVELOPE 3.5 3.0 2.5 2.5 VOUT (V) 3.0 2.0 1.5 2.0 1.5 1.0 1.0 0.5 0.5 0 0 0dBm –10dBm –20dBm –30dBm –40dBm 1 2 TIME (ms) 3 4 5 –1.0 –1 5 3 TCM2 LOW TCM2 HIGH 4 3 4 Figure 25. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 0.1 µF, CHPF = Open, Falling Edge VTCM2 (V) 6 2 1 TIME (ms) Figure 22. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 0.1 µF, CHPF = Open, Rising Edge 6 0 07368-036 0 –0.5 07368-034 –0.5 2.00 4 1.75 3 1.50 2 1.25 1 1.00 0 0.75 –1 0.50 –2 0.25 –3 0dBm 3 ERROR (°C) 0 VTEMP (V) OUTPUT VOLTAGE, VOUT (V) 2 4.0 RF ENVELOPE 3.5 –1.0 –1 0 Figure 24. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 390 pF, CHPF = Open, Falling Edge 4.0 VOUT (V) 1.5 1.0 3 –40dBm 2.0 0.5 2 –30dBm 2.5 1.0 1 –20dBm 3.0 2.5 –1.0 –2 –1 0 –10dBm RF ENVELOPE 3.5 RF ENVELOPE 3.0 VOUT (V) –10dBm 07368-035 0dBm 4.5 2 1 TIME (µs) –4 0 –50–40–30–20–10 0 10 20 30 40 50 60 70 80 90 100 110 120130 TEMPERATURE (°C) 07368-037 –50 –25 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 0 Figure 23. Output Response Using Power-Down Mode for Various RF Input Levels Carrier Frequency at 2.14 GHz, CLPF = 470 pF, CHPF = 220 pF 07368-027 –50dBm Figure 26. VTEMP and Error with Respect to Straight Line vs. Temperature for Eleven Devices Rev. B | Page 12 of 29 Data Sheet AD8363 REPRESENTS APPROXIMATELY 3000 PARTS FROM SIX LOTS 500 600 QUANTITY QUANTITY 800 REPRESENTS APPROXIMATELY 3000 PARTS FROM SIX LOTS 600 400 400 300 200 200 1.36 1.38 1.40 VTEMP (V) 1.42 1.44 0 2.24 07368-077 0 1.34 1.46 Figure 27. Distribution of VTEMP Voltage at 25oC, No RF Input 100 2.26 2.28 2.30 VREF (V) 2.32 2.34 2.36 07368-029 100 Figure 30. Distribution of VREF, 25°C, No RF Input 2.320 VTCM2 INCREASING 2.318 10 2.314 VREF (V) SUPPLY CURRENT (mA) 2.316 VTCM2 DECREASING 1 2.312 2.310 2.308 2.306 2.304 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 VTCM2 (V) 2.300 4.5 07368-051 4.1 Figure 28. Supply Current vs. VTCM2 4.6 4.7 4.8 4.9 5.0 5.1 VPOS (V) 5.2 5.3 5.4 5.5 07368-038 2.302 0.1 4.0 Figure 31. Change in VREF with VPOS for Nine Devices 2.34 2.325 2.33 2.320 2.32 2.315 VREF (V) VREF (V) 2.31 2.30 2.310 2.305 2.29 2.300 2.28 –25 –20 –15 –10 –5 PIN (dBm) 0 5 10 07368-049 2.26 –30 Figure 29. Change in VREF with Input Amplitude for Eleven Devices 2.290 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 32. Change in VREF with Temperature for Eleven Devices Rev. B | Page 13 of 29 07368-048 2.295 2.27 AD8363 Data Sheet THEORY OF OPERATION The computational core of the AD8363 is a high performance AGC loop. As shown in Figure 33, the AGC loop comprises a wide bandwidth variable gain amplifier (VGA), square law detectors, an amplitude target circuit, and an output driver. For a more detailed description of the functional blocks, see the AD8362 data sheet. The output of the VGA, VSIG, is applied to a wideband square law detector. The detector provides the true rms response of the RF input signal, independent of waveform. The detector output, ISQR, is a fluctuating current with positive mean value. The difference between ISQR and an internally generated current, ITGT, is integrated by CF and the external capacitor attached to the CLPF pin at the summing node. CF is an on-chip 25 pF filter capacitor, and CLPF, the external capacitance connected to the CLPF pin, can be used to arbitrarily increase the averaging time while trading off with the response time. When the AGC loop is at equilibrium The nomenclature used in this data sheet to distinguish between a pin name and the signal on that pin is as follows: The pin name is all uppercase (for example, VPOS, COMM, and VOUT). The signal name or a value associated with that pin is the pin mnemonic with a partial subscript (for example, CLPF, CHPF, and VOUT). Mean(ISQR) = ITGT This equilibrium occurs only when Mean(VSIG2) = VTGT2 SQUARE LAW DETECTOR AND AMPLITUDE TARGET The VGA gain has the form GSET = GO exp(−VSET/VGNS) (1) where: GO is the basic fixed gain. VGNS is a scaling voltage that defines the gain slope (the decibel change per voltage). The gain decreases with increasing VSET. The VGA output is VSIG = GSET × RFIN = GO × RFIN exp(VSET/VGNS) (3) (4) where VTGT is the voltage presented at the VTGT pin. This pin can conveniently be connected to the VREF pin through a voltage divider to establish a target rms voltage VATG of ~70 mV rms, when VTGT = 1.4 V. Because the square law detectors are electrically identical and well matched, process and temperature dependent variations are effectively cancelled. (2) where RFIN is the ac voltage applied to the input terminals of the AD8363. INHI VSIG VGA X2 SUMMING NODE ISQR ITGT VATG = VTGT 20 X2 VTGT INLO GSET CLPF VSET CLPF (EXTERNAL) VPOS CF (INTERNAL) VOUT COMM CHPF CHPF (EXTERNAL) TEMPERATURE COMPENSATION AND BIAS TCM1 TCM2/PWDN TEMPERATURE SENSOR TEMP (1.4V) BAND GAP REFERENCE VREF (2.3V) Figure 33. Simplified Architecture Details Rev. B | Page 14 of 29 07368-076 CH (INTERNAL) Data Sheet AD8363 RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG VBIAS VPOS By forcing the previous identity through varying the VGA setpoint, it is apparent that ESD (5) 2.5kΩ INHI 50Ω Substituting the value of VSIG from Equation 2 results in ESD ESD INLO ESD ESD ESD ESD ESD ESD (6) ESD ESD ESD ESD ESD ESD When connected as a measurement device, VSET = VOUT. Solving for VOUT as a function of RFIN VOUT = VSLOPE × log10(RMS(RFIN)/VZ) ESD (7) ESD 07368-039 RMS(G0 × RFIN exp(−VSET/VGNS)) = VATG 2.5kΩ Figure 34. RF Inputs Simplified Schematic where: VSLOPE is 1 V/decade (or 50 mV/dB). VZ is the intercept voltage. Extensive ESD protection is employed on the RF inputs, which limits the maximum possible input amplitude to the AD8363. When RMS(RFIN) = VZ, because log10(1) = 0, this implies that VOUT = 0 V, making the intercept the input that forces VOUT = 0 V. VZ has been fixed to approximately 280 μV (approximately −58 dBm, referred to 50 Ω) with a CW signal at 100 MHz. In reality, the AD8363 does not respond to signals less than ~−56 dBm. This means that the intercept is an extrapolated value outside the operating range of the device. The dynamic range of the AD8363 can be optimized by choosing the correct RF input pin for the intended frequency of operation. Using INHI (Pin 14), users can obtain the best dynamic range at frequencies up to 2.6 GHz. Above 2.6 GHz, it is recommended that INLO (Pin 15) be used. At 2.6 GHz, the performance obtained at the two inputs is approximately equal. If desired, the effective value of VSLOPE can be altered by using a resistor divider between VOUT and VSET. (Refer to the Output Voltage Scaling section for more information.) In most applications, the AGC loop is closed through the setpoint interface and the VSET pin. In measurement mode, VOUT is directly connected to VSET. (See the Measurement Mode Basic Connections section for more information.) In controller mode, a control voltage is applied to VSET and the VOUT pin typically drives the control input of an amplification or attenuation system. In this case, the voltage at the VSET pin forces a signal amplitude at the RF inputs of the AD8363 that balances the system through feedback. (See the Controller Mode Basic Connections section for more information.) RF INPUT INTERFACE Figure 34 shows the connections of the RF inputs within the AD8363. The input impedance is set primarily by an internal 50 Ω resistor connected between INHI and INLO. A dc level of approximately half the supply voltage on each pin is established internally. Either the INHI pin or the INLO pin can be used as the single-ended RF input pin. (See the Choice of RF Input Pin section.) If the dc levels at these pins are disturbed, performance is compromised; therefore, signal coupling capacitors must be connected from the input signal to INHI and INLO. The input signal high-pass corner formed by the coupling capacitors and the internal resistances is fHIGH-PASS = 1/(2 × π × 50 × C) CHOICE OF RF INPUT PIN The AD8363 was designed with a single-ended RF drive in mind. A balun can be used to drive INHI and INLO differentially, but it is not necessary, and it does not result in improved dynamic range. SMALL SIGNAL LOOP RESPONSE The AD8363 uses a VGA in a loop to force a squared RF signal to be equal to a squared dc voltage. This nonlinear loop can be simplified and solved for a small signal loop response. The lowpass corner pole is given by FreqLP ≈ 1.83 × ITGT/(CLPF) where: ITGT is in amperes. CLPF is in farads. FreqLP is in hertz. ITGT is derived from VTGT; however, ITGT is a squared value of VTGT multiplied by a transresistance, namely ITGT = gm × VTGT2 (10) gm is approximately 18.9 μs, so with VTGT equal to the typically recommended 1.4 V, ITGT is approximately 37 μA. The value of this current varies with temperature; therefore, the small signal pole varies with temperature. However, because the RF squaring circuit and dc squaring circuit track with temperature, there is no temperature variation contribution to the absolute value of VOUT. For CW signals, (8) where C is in farads and fHIGH-PASS is in hertz. The input coupling capacitors must be large enough in value to pass the input signal frequency of interest. The other input pin should be RF ac-coupled to common (ground). (9) FreqLP ≈ 67.7 × 10−6/(CLPF) (11) However, signals with large crest factors include low pseudorandom frequency content that either needs to be filtered out or sampled and averaged out. See the Choosing a Value for CLPF section for more information. Rev. B | Page 15 of 29 AD8363 Data Sheet TEMPERATURE SENSOR INTERFACE The AD8363 provides a temperature sensor output with an output voltage scaling factor of approximately 5 mV/°C. The output is capable of sourcing 4 mA and sinking 50 μA maximum at temperatures at or above 25°C. If additional current sink capability is desired, an external resistor can be connected between the TEMP and COMM pins. The typical output voltage at 25°C is approximately 1.4 V. VPOS Compensating the device for the temperature drift using TCM1 and TCM2/PWDN allows for great flexibility and the user may wish to modify these values to optimize for another amplitude point in the dynamic range, for a different temperature range, or for an operating frequency other than those shown in Table 4. To find a new compensation point, VTCM1 and VTCM2 can be swept while monitoring VOUT over the temperature at the frequency and amplitude of interest. The optimal voltages for VTCM1 and VTCM2 to achieve minimum temperature drift at a given power and frequency are the values of VTCM1 and VTCM2 where VOUT has minimum movement. See the AD8364 and ADL5513 data sheets for more information. INTERNAL VPAT TEMP 12kΩ 07368-041 4kΩ COMM The values in Table 4 were chosen to give the best drift performance at the high end of the usable dynamic range over the −40°C to +85°C temperature range. Figure 35. TEMP Interface Simplified Schematic VREF INTERFACE The VREF pin provides an internally generated voltage reference. The VREF voltage is a temperature stable 2.3 V reference that is capable of sourcing 4 mA and sinking 50 μA maximum at temperatures at or above 25°C. An external resistor can be connected between the VREF and COMM pins to provide additional current sink capability. The voltage on this pin can be used to drive the TCM1, TCM2/PWDN, and VTGT pins, if desired. Varying VTCM1 and VTCM2 has only a very slight effect on VOUT at device temperatures near 25°C; however, the compensation circuit has more and more effect, and is more and more necessary for best temperature drift performance, as the temperature departs farther from 25°C. Figure 37 shows the effect on temperature drift performance at 25°C and 85°C as VTCM1 is varied but VTCM2 is held constant at 0.6 V. 3 2 VTCM1 = 0.62V VPOS 1 ERROR (dB) INTERNAL VOLTAGE VREF –1 07368-042 16kΩ COMM 0 VTCM1 = 0.42V 25°C 85°C –2 –3 –60 TEMPERATURE COMPENSATION INTERFACE Proprietary techniques are used to maximize the temperature stability of the AD8363. For optimal performance, the output temperature drift must be compensated for using the TCM1 and TCM2/PWDN pins. The absolute value of compensation varies with frequency and VTGT. Table 4 shows the recommended voltages for the TCM1 and TCM2/PWDN pins to maintain the best temperature drift error over the rated temperature range (−40°C < TA < 85°C) when driven single-ended and using a VTGT = 1.4 V. Table 4. Recommended Voltages for TCM1 and TCM2/PWDN Frequency 100 MHz 900 MHz 1.9 GHz 2.14 GHz 2.6 GHz 3.8 GHz 5.8 GHz TCM1 (V) 0.47 0.5 0.52 0.52 0.54 0.56 0.88 TCM2/PWDN (V) 1.0 1.2 0.51 0.6 1.1 1.0 1.0 –50 –40 –30 –20 RFIN (dBm) –10 0 10 07368-050 Figure 36. VREF Interface Simplified Schematic Figure 37. Error vs. Input Amplitude over Stepped VTCM1 Values, 25oC and 85oC, 2.14 GHz, VTCM2 = 0.6 V TCM1 primarily adjusts the intercept of the AD8363 at temperature. In this way, TCM1 can be thought of as a coarse adjustment to the compensation. Conversely, TCM2 performs a fine adjustment. For this reason, it is advised that when searching for compensation with VTCM1 and VTCM2, that VTCM1 be adjusted first, and when best performance is found, VTCM2 can then be adjusted for optimization. It is evident from Figure 37 that the temperature compensation circuit can be used to adjust for the lowest drift at any input amplitude of choice. Though not shown in Figure 37, a similar analysis can simultaneously be performed at −40°C, or any other temperature within the operating range of the AD8363. Performance varies slightly from device to device; therefore, optimal VTCM1 and VTCM2 values must be arrived at statistically Rev. B | Page 16 of 29 Data Sheet AD8363 over a population of devices to be useful in mass production applications. VSET INTERFACE The VSET interface has a high input impedance of 72 kΩ. The voltage at VSET is converted to an internal current used to set the internal VGA gain. The VGA attenuation control is approximately 19 dB/V. GAIN ADJUST VSET 54kΩ 18kΩ 2.5kΩ Figure 38 shows a simplified schematic representation of TCM1. See the Power-Down Interface section for the TCM2 interface. COMM VPOS 07368-045 The TCM1 and TCM2 pins have high input impedances, approximately 5 kΩ and 500 kΩ, respectively, and can be conveniently driven from an external source or from a fraction of VREF by using a resistor divider. VREF does change slightly with temperature and RF input amplitude (see Figure 32 and Figure 29); however, the amount of change is unlikely to result in a significant effect on the final temperature stability of the RF measurement system. Figure 40. VSET Interface Simplified Schematic ESD ESD TCM1 3kΩ 07368-043 ESD COMM Figure 38. TCM1 Interface Simplified Schematic POWER-DOWN INTERFACE The quiescent and disabled currents for the AD8363 at 25°C are approximately 60 mA and 300 μA, respectively. The dual function pin, TCM2/PWDN, is connected to a temperature compensation circuit as well as a power-down circuit. Typically, when PWDN is greater than VPOS − 0.1 V, the device is fully powered down. Figure 28 shows this characteristic as a function of VPWDN. Note that because of the design of this section of the AD8363, as VTCM2 passes through a narrow range at ~4.5 V (or ~VPOS − 0.5 V), the TCM2/PWDN pin sinks approximately 750 μA. The source used to disable the AD8363 must have a sufficiently high current capability for this reason. Figure 23 shows the typical response times for various RF input levels. The output reaches within 0.1 dB of its steady-state value in approximately 35 μs; however, the reference voltage is available to full accuracy in a much shorter time. This wake-up response varies depending on the input coupling and the capacitances, CHPF and CLPF. The output driver used in the AD8363 is different from the output stage on the AD8362. The AD8363 incorporates rail-torail output drivers with pull-up and pull-down capabilities. The closed-loop −3 dB bandwidth of the VOUT buffer with no load is approximately 58 MHz with a single-pole roll-off of −20 dB/dec. The output noise is approximately 45 nV/√Hz at 100 kHz, which is independent of CLPF due to the architecture of the AD8363. VOUT can source and sink up to 10 mA. There is an internal load between VOUT and COMM of 2.5 kΩ. VPOS ESD TCM2/ PWDN 200Ω 7kΩ 200Ω 200Ω ESD ESD 7kΩ VREF INTERCEPT TEMPERATURE COMPENSATION COMM 07368-044 SHUTDOWN POWER-UP CIRCUIT CIRCUIT Figure 39. PWDN Interface Simplified Schematic Rev. B | Page 17 of 29 VPOS ESD 2pF CLPF VOUT ESD 2kΩ ESD 500Ω COMM Figure 41. VOUT Interface Simplified Schematic 07368-046 3kΩ OUTPUT INTERFACE AD8363 Data Sheet VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS The target voltage can be set with an external source or by connecting the VREF pin (nominally 2.3 V) to the VTGT pin through a resistive voltage divider. With 1.4 V on the VTGT pin, the rms voltage that must be provided by the VGA to balance the AGC feedback loop is 1.4 V × 0.05 = 70 mV rms. Most of the characterization information in this data sheet was collected at VTGT = 1.4 V. Voltages higher and lower than this can be used; however, doing so increases or decreases the gain at the internal squaring cell, which results in a corresponding increase or decrease in intercept. This in turn affects the sensitivity and the usable measurement range. Because the gain of the squaring cell varies with temperature, oscillations or a loss in measurement range can result. For these reasons, do not reduce VTGT below 1.3 V. The AD8363 requires a single supply of nominally 5 V. The supply is connected to the two supply pins, VPOS. Decouple the pins using two capacitors with values equal or similar to those shown in Figure 43. These capacitors must provide a low impedance over the full frequency range of the input, and they should be placed as close as possible to the VPOS pins. Use two different capacitor values in parallel to provide a broadband ac short to ground. Input signals can be applied differentially or single-ended; however, in both cases, the input impedance is 50 Ω. Most performance information in this data sheet was derived with a single-ended drive. The optimal measurement range is achieved using a singleended drive on the INHI pin at frequencies below 2.6 GHz (as shown in Figure 43), and likewise, optimal performance is achieved using the INLO pin above 2.6 GHz (similar to Figure 43; except INLO is ac-coupled to the input and INHI is ac-coupled to ground). VPOS ESD g × X2 VTGT 50kΩ ITGT The AD8363 is placed in measurement mode by connecting VOUT to VSET. This closes the AGC loop within the device with VOUT representing the VGA control voltage, which is required to present the correct rms voltage at the input of the internal square law detector. ESD 50kΩ 10kΩ 07368-047 ESD COMM Figure 42. VTGT Interface Simplified Schematic VPOS2 C7 0.1µF VREF VPOS TEMP NC INHI AD8363 VSET INLO DUT1 VOUT 1 CLPF 2 3 6 VOUT 5 C9 0.1µF 4 C3 OPEN C4 100pF PADDLE AGND C13 0.1µF TCM2/PWDN VPOS1 Figure 43. Measurement Mode Basic Connections Rev. B | Page 18 of 29 7 07368-062 TCM1 8 COMM 16 TEMP 9 VPOS 15 C12 0.1µF TCM1 10 CHPF 14 TCM2/PWDN LOW FREQUENCY INPUT 13 11 COMM VTGT 12 C10 0.1µF C5 100pF R10 845Ω VREF R11 1.4kΩ Data Sheet AD8363 VOUT(IDEAL) = Slope × (PIN − Intercept) (12) where: 4 3.5 3 3.0 2 2.5 1 2.0 0 1.5 –1 1.0 –2 0.5 –3 0 –60 –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 ERROR (dB) 4.0 07368-144 VOUT (V) Slope is the change in output voltage divided by the change in input power (dB). Figure 44. 1.9 GHz Transfer Function and Linearity Error using a Two-Point Calibration (Calibration Points −20 dBm and −40 dBm) Figure 45 shows the output voltage and error at 25°C and over temperature when a three-point calibration is used (calibration points are 0 dBm, −10 dBm and −40 dBm). When choosing calibration points, there is no requirement for, or value in equal spacing between the points. There is also no limit to the number of calibration points used. Intercept is the calculated input power level at which the output voltage would equal 0 V (note that Intercept is an extrapolated theoretical value not a measured value). In general, calibration, which establishes the Slope and Intercept, is performed during equipment manufacture by applying two or more known signal levels to the input of the AD8363 and measuring the corresponding output voltages. The calibration points are generally chosen within the linear-in-dB operating range of the device. 4.0 4 3.5 3 3.0 2 2.5 1 2.0 0 1.5 –1 1.0 –2 0.5 –3 0 –60 –50 –40 –30 –20 PIN (dBm) –10 0 –4 10 ERROR (dB) Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. The equation for the idealized output voltage can be written as The residual nonlinearity of the transfer function that is apparent in the two-point calibration error plot can be reduced by increasing the number of calibration points. Figure 45 shows the post-calibration error plots for three-point calibration. With a multipoint calibration, the transfer function is segmented, with each segment having its own slope and intercept. During calibration, multiple known power levels are applied, and multiple voltages are measured. When the equipment is in operation, the measured voltage from the detector is first used to determine which of the stored slope and intercept calibration coefficients are to be used. Then the unknown power level is calculated by inserting the appropriate slope and intercept into Equation 15. 07368-145 The measured transfer function of the AD8363 at 1.9 GHz is shown in Figure 44, which contains plots of both output voltage vs. input amplitude (power) and calculated error vs. input level. As the input level varies from −55 dBm to +0 dBm, the output voltage varies from ~0 V to ~3.1 V. Figure 44 includes a plot of this error when using a two-point calibration (calibration points are −20 dBm and −40 dBm). The error at the calibration points is equal to 0 by definition. VOUT (V) SYSTEM CALIBRATION AND ERROR CALCULATION Figure 45. 1.9 GHz Transfer Function and Error at +25°C, −40°C, and +85°C Using a Three-Point Calibration (0 dBm, −10 dBm and −40 dBm) Slope = (VOUT1 − VOUT2)/(PIN1 − PIN2) (13) The −40°C and +85°C error plots in Figure 44 and Figure 45 are generated using the 25°C calibration coefficients. This is consistent with equipment calibration in a mass production environment where calibration at just a single temperature is practical. Intercept = PIN1 − (VOUT1/Slope) (14) OPERATION TO 125°C With a two-point calibration, the slope and intercept are calculated as follows: After the slope and intercept are calculated and stored in nonvolatile memory during equipment calibration, an equation can be used to calculate an unknown input power based on the output voltage of the detector. PIN (Unknown) = (VOUT1(MEASURED)/Slope) + Intercept (15) The log conformance error is the difference between this straight line and the actual performance of the detector. Error (dB) = (VOUT(MEASURED) − VOUT(IDEAL))/Slope The AD8363 operates up to 125°C with slightly degraded performance. Figure 46 shows the typical operation (Errors are plotted using two-point calibration) at 125°C as compared to other temperatures using the TCM1 and TCM2 values in Table 4. Temperature compensation can be optimized for operation above 85°C by modifying the voltages on the TCM1 and TCM2 pins from those shown in Table 4. (16) Rev. B | Page 19 of 29 AD8363 Data Sheet 3 6 –40°C +25°C +85°C +125°C 4 1 3 0 2 –1 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.6V 1 0 –60 –50 –40 –30 –20 PIN (dBm) –10 0 ERROR (dB) 2 –2 –3 10 07368-053 OUTPUT VOLTAGE (V) 5 where: VO is the nominal maximum output voltage (see Figure 4 through Figure 18). V'O is the new maximum output voltage (for example, up to 4.8 V). RIN is the VSET input resistance (72 kΩ). Figure 46. VOUT and Log Conformance Error vs. Input Amplitude at 2.14 GHz, −40°C to +125°C OUTPUT VOLTAGE SCALING The output voltage range of the AD8363 (nominally 0 V to 3.5 V) can be easily increased or decreased. There are a number of situations where adjustment of the output scaling makes sense. For example, if the AD8363 is driving an analog-todigital converter (ADC) with a 0 V to 5 V input range, it makes sense to increase the detector’s nominal maximum output voltage of 3.5 V so that it is closer to 5 V. This makes better use of the input range of the ADC and maximizes the resolution of the system in terms of bits/dB. If only a part of the RF input power range of the AD8363 is being used (for example, −10 dBm to −40 dBm), it may make sense to increase the scaling so that this reduced input range fits into the available output swing of the AD8363 (0 V to 4.8 V). The output swing can be reduced by adding a voltage divider on the output pin, as shown in Figure 47 (with VOUT connected directly to VSET and a resistor divider on VOUT). Figure 47 also shows how the output voltage swing can be increased using a technique that is analogous to setting the gain of an op amp in noninverting mode. With the VSET pin being the equivalent of the inverting input of the op amp, a resistor divider is connected between VOUT and VSET. R2 7 VSET 7 VSET When choosing R1 and R2, attention must be paid to the current drive capability of the VOUT pin and the input resistance of the VSET pin. The choice of resistors should not result in excessive current draw out of VOUT. However, making R1 and R2 too large is also problematic. If the value of R2 is compatible with the 72 kΩ input resistance of the VSET input, this input resistance, which varies slightly from device to device, contributes to the resulting slope and output voltage. In general, the value of R2 should be at least ten times smaller than the input resistance of VSET. Values for R1 and R2 should, therefore, be in the 1 kΩ to 5 kΩ range. It is also important to take into account device-to-device and frequency variation in output swing along with the AD8363 output stage’s maximum output voltage of 4.8 V. The VOUT distribution is well characterized at the bands of major frequencies in the Typical Performance Characteristics section (Figure 3 to Figure 18). OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES An offset-compensation loop is used to eliminate small dc offsets within the internal VGA as shown in Figure 48. The high-pass corner frequency of this loop is set to about 1 MHz using an on-chip 25 pF capacitor. Because input signals that are below 1 MHz are interpreted as unwanted offset voltages, this restricts the operating frequency range of the device. To operate the AD8363 at lower frequencies (than 1 MHz), the high-pass corner frequency must be reduced by connecting a capacitor between CHPF and VPOS. Internal offset voltages vary depending on the gain at which the VGA is operating and, therefore, on the input signal amplitude. When a large CHPF value is used, the offset correction process can lag the more rapid changes in the gain of the VGA, which can increase the time required for the loop to fully settle for a given steady input amplitude. This can manifest itself in a jumpy, seemingly oscillatory response of the AD8363. R1 6 VOUT R1 6 VOUT 07368-146 R2 Figure 47. Decreasing and Increasing Slope Equation 17 is the general function that governs this. V ' R1 ( R2 || RIN ) O 1 V O (17) Care should therefore be taken in choosing CHPF and CLPF because there is a potential to create oscillations. In general, make the capacitance on the CLPF pin as large as possible; there is no maximum on the amount of capacitance that can be added to this pin. At high frequencies, there is no need for an external capacitor on the CHPF pin; therefore, the pin can be left open. However, when trying to get a fast response time and/or when working at low frequencies, extra care in choosing the proper capacitance values for CHPF and CLPF is prudent. With the gain control pin (VSET) connected to VOUT, VSET can slew at a rate determined by the on-chip squaring cell and CLPF. When VSET is changing with time, the dc offsets in the VGA also vary with Rev. B | Page 20 of 29 Data Sheet AD8363 time. The speed at which VSET slews can create a time varying offset that falls within the high-pass corner set by CHPF. Therefore, in measurement mode, take care to set CLPF appropriately to reduce the slew. It is also worth noting that most of the typical performance data was derived with CLPF = 3.9 nF and CHPF = 2.7 nF and with a CW waveform. The minimum appropriate CLPF based on slew rate limitations is as follows Note that per Equation 9 (18) where: CLPF is in farads. FREQRFIN is in hertz. This takes into account the on-chip 25 pF capacitor, CF, in parallel with CLPF. However, because there are other internal device time delays that affect loop stability, use a minimum CLPF of 390 pF. Choose CHPF to set a 3 dB corner to the offset compensation system. See Equation 19, where FHPPOLE is in this case 100 MHz, one decade below the desired signal. This results in a negative number and, obviously, a negative value is not practical. Because the high-pass corner frequency is already 1 MHz, this result simply illustrates that the appropriate solution is to use no external CHPF capacitor. FreqLP ≈ 1.83 × ITGT/(CLPF) A CLPF of 470 pF results in a small signal low-pass corner frequency of approximately 144 kHz. This reflects the bandwidth of the measurement system, and how fast the user can expect changes on the output. It does not imply any limitations on the input RF carrier frequency. VPOS 25pF (INTERNAL) 110Ω The minimum appropriate CHPF for a given high-pass pole frequency is CHPF = 29.2 × 10 /FHPPOLE − 25 pF −6 (19) The subtraction of 25 pF is a result of the on-chip 25 pF capacitor in parallel with the external CHPF. Typically, choose CHPF to give a pole (3 dB corner) at least 1 decade below the desired signal frequency. Note that the high pass corner of the offset compensation system is approximately 1 MHz without an external CHPF; therefore, adding an external capacitor lowers the corner frequency. The following example illustrates the proper selection of the input coupling capacitors, minimum CLPF, and maximum CHPF when using the AD8363 in measurement mode for a 1 GHz input signal. 2. 1pF CHPF VGA gm1 RFIN where FHPPOLE is in hertz. 1. 1pF 110Ω Choose the input coupling capacitors that have a 3 dB corner at least one decade below the input signal frequency. From Equation 8, C > 10/(2 × π × RFIN × 50) = 32 pF minimum. According to this calculation, 32 pF is sufficient; however, the input coupling capacitors should be a much larger value, typically 0.1 µF. The offset compensation circuit, which is connected to CHPF, should be the true determinant of the system high-pass corner frequency and not the input coupling capacitors. With 0.1 µF coupling capacitors, signals as low as 32 kHz can couple to the input, which is well below the system high-pass frequency. Choose CLPF to reduce instabilities due to VSET slew rate. See Equation 18, where FRQRFIN = 1 GHz, and this results in CLPF > 20 pF. However, as previously mentioned, values below 390 pF are not recommended. For this reason, a 470 pF capacitor was chosen. In addition, if fast response times are not required, an even larger CLPF value than given here should be chosen. gm2 gm A=1 VX 40dB g × X2 IRF 07368-040 CLPF > 20 × 10 /FREQRFIN −3 3. Figure 48. Offset Compensation Circuit CHOOSING A VALUE FOR CLPF The Small Signal Loop Response section and the Offset Compensation, Minimum CLPF, and Maximum CHPF Capacitance Values section discussed how to choose the minimum value capacitance for CLPF based on a minimum capacitance of 390 pF, slew rate limitation, and frequency of operation. Using the minimum value for CLPF allows the quickest response time for pulsed type waveforms (such as WiMAX) but also allows the most residual ripple on the output caused by the pseudorandom modulation waveform. There is not a maximum for the capacitance that can be applied to the CLPF pin, and in most situations, a large enough capacitor can be added to remove the residual ripple caused by the modulation and yet allow a fast enough response to changes in input power. Figure 49 shows how residual ripple, rise time, and fall time vary with filter capacitance when the AD8363 is driven by a single carrier CDMA2000 9CH SR1 signal at 2.14 GHz. The rise time and fall time is based on a signal that is pulsed between no signal and 10 dBm but is faster if the input power change is less. Rev. B | Page 21 of 29 AD8363 Data Sheet 400 350 2450 RESIDUAL RIPPLE (mV) RISE TIME (µs) FALL TIME (µs) 2100 250 1750 200 1400 150 1050 100 700 50 350 0 0 10 20 30 40 50 60 70 CLPF CAPACITANCE (nF) 80 90 0 100 FALL TIME (µs) 300 T CH1 RISE 81.78µs CH1 FALL 1.337ms 07368-069 RESIDUAL RIPPLE (mV p-p) RISE TIME (µs) Figure 50 shows how the rise time cuts off the preamble. Note that the power in the preamble can be easily measured; however, the CLPF value would have to be reduced slightly, and the noise in the main signal would increase. 2800 1 Table 5 shows the recommended values of CLPF for popular modulation schemes. For nonpulsed waveforms, increase CLPF until the residual output noise falls below 50 mV (±0.5 dB). In each case, the capacitor can be increased to further reduce the noise. A 10% to 90% step response to an input step is also listed. Where the increased response time is unacceptably high, reduce CLPF, which increases the noise on the output. Due to the random nature of the output ripple, if it is sampled by an ADC, averaging in the digital domain further reduces the residual noise. Table 5 gives CLPF values to minimize noise while trying to keep a reasonable response time. For non-pulsed type waveforms, averaging is not required on the output. For pulsed waveforms, the smaller the noise, the less averaging is needed on the output. CH1 500mV M 1.00ms T 10.00% A CH1 600mV 07368-054 Figure 49. Residual Ripple, Rise Time, and Fall Time vs. CLPF Capacitance, Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz with 10 dBm Pulse Figure 50. AD8363 Output Response to a WiMAX 802.16, 64 QAM, 256 Subcarriers, 10 MHz Bandwidth Signal with CLPF = 0.027 µF As shown in Figure 49, the fall time for the AD8363 increases faster than the rise time with an increase in CLPF capacitance. Some pulse-type modulation standards require a fast fall time as well as a fast rise time, and in all cases, less output ripple is desired. Placing an RC filter on the output reduces the ripple, according to the frequency content of the ripple and the poles and zeros of the filter. Using an RC output filter also changes the rise and fall time vs. the output ripple response as compared to increasing the CLPF capacitance. System specifications determine the necessary rise time and fall time. For example, the suggested CLPF value for WiMAX assumes that it is not necessary to measure the power in the preamble. Table 5. Recommended CLPF Values for Various Modulation Schemes Modulation/Standard W-CDMA, 1Carrier, TM1-64 W-CDMA, 1Carrier, TM1-64 (EVDO) W-CDMA 4Carrier, TM1-64 CDMA2000, 1Carrier, 9CH CDMA2000, 3Carrier, 9CH WiMAX 802.16 , 64 QAM, 256 Subcarriers, 10 MHz Bandwidth 6C TD-SCDMA 1C TD-SCDMA Crest Factor (dB) 12 12 11 9.1 11 14 14 11.4 Rev. B | Page 22 of 29 CLPF 0.1 µF 3900 pF 0.1 µF 0.1 µF 0.1 µF 0.027 µF 0.01 µF 0.01 µF Residual Ripple (mV p-p) 15 150 8 10 13 10 69 75 Response Time (Rise/Fall) 10% to 90% 236 μs/2.9 ms 8.5 μs/100 µs 240 μs/2.99 ms 210 μs/3.1 ms 215 μs/3.14 ms 83 µs/1.35 ms 24 μs/207 μs 24 μs /198 μs Data Sheet AD8363 Figure 51 shows the response for a 2.14 GHz pulsed signal, with CLPF = 3900 pF. The residual ripple from a single carrier CDMA2000 9CH SR1 signal is 150 mV p-p. (The ripple is not shown in Figure 51. The ripple was measured separately.) Figure 52 shows the response for a 2.14 GHz pulse signal with a CLPF of 390 pF and an output filter that consists of a series 75 Ω resistor (closest to the output) followed by a 0.15 μF capacitor to ground. The residual ripple for this configuration is also 150 mV p-p. Note that the rise time is faster and the fall time is slower when the larger CLPF is used to obtain a 150 mV p-p ripple. T CH1 RISE 8.480µs CH1 FALL 101.4µs CH1 500mV M 100µs T 10.40% A CH1 07368-070 CH1 AMPL 2.37V 1 720mV Figure 51. Pulse Response with CLPF = 3900 pF Resulting in a 150 mV p-p Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz T 8 7 6 5 TEMP VSET VOUT 75Ω CLPF OSCILLOSCOPE PROBE CH1 RISE 13.66µs CONTROLLER MODE BASIC CONNECTIONS In addition to being a measurement device, the AD8363 can also be configured to control rms signal levels, as shown in Figure 53. The RF input to the device is configured as it was in measurement mode and either input can be used. A directional coupler taps off some of the power being generated by the VGA. If loss in the main signal path is not a concern, and there are no issues with reflected energy from the next stage in the signal chain, a power splitter can be used instead of a directional coupler. Some additional attenuation may be required to set the maximum input signal at the AD8363 to be equal to the recommended maximum input level for optimum linearity and temperature stability at the frequency of operation. The VSET and VOUT pins are no longer shorted together. VOUT now provides a bias or gain control voltage to the VGA. The gain control sense of the VGA must be negative and monotonic, that is, increasing voltage tends to decrease gain. However, the gain control transfer function of the device does not need to be well controlled or particularly linear. If the gain control sense of the VGA is positive, an inverting op amp circuit with a dc offset shift can be used between the AD8363 and the VGA to keep the gain control voltage in the 0.03 V to 4.8 V range. VSET becomes the set-point input to the system. This can be driven by a DAC, as shown in Figure 53, if the output power is expected to vary, or it can simply be driven by a stable reference voltage, if constant output power is required. This DAC should have an output swing that covers the 0.15 V to 3.5 V range. 0.15µF 390pF CH1 FALL 35.32µs VGA OR VVA (OUTPUT POWER DECREASES AS VAPC INCREASES) PIN CH1 AMPL 2.36V 1 POUT VAPC ATTENUATOR M 100µs T 10.60% A CH1 750mV VOUT C10 INHI Figure 52. Pulse Response with CLPF = 390 pF and Series 75 Ω Resistor Followed by a 0.15 μF Capacitor to Ground, Resulting in a 150 mV p-p Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz AD8363 INLO VSET CLPF RF PULSE RESPONSE AND VTGT The response of the AD8363 to pulsed RF waveforms is affected by VTGT. Referring to Figure 21 and Figure 22, there is a period of inactivity between the start of the RF waveform and the time at which VOUT begins to show a reaction. This happens as a result of the implementation of the balancing of the squarer currents within the AD8363. This delay can be reduced by decreasing VTGT; however, as previously noted in the VTGT Interface section, this has implications on the sensitivity, intercept, and dynamic range. While the delay is reduced, reducing VTGT increases the rise and fall time of VOUT. C12 C9 SEE TEXT DAC (0.15V TO 3.5V) 07368-063 CH1 500mV 07368-071 (0.03V TO 4.8V AVAILABLE SWING) Figure 53. Controller Mode Operation for Automatic Power Control When VSET is set to a particular value, the AD8363 compares this value to the equivalent input power present at the RF input. If these two values do not match, VOUT increases or decreases in an effort to balance the system. The dominant pole of the error amplifier/integrator circuit that drives VOUT is set by the capacitance on the CLPF pin; some experimentation may be necessary to choose the right value for this capacitor. Rev. B | Page 23 of 29 AD8363 Data Sheet In general, CLPF should be chosen to provide stable loop operation for the complete output power control range. If the slope (in dB/V) of the gain control transfer function of the VGA is not constant, CLPF must be chosen to guarantee a stable loop when the gain control slope is at its maximum. In addition, CLPF must provide adequate averaging to the internal low range squaring detector so that the rms computation is valid. Larger values of CLPF tend to make the loop less responsive. The low end power is limited by the maximum gain of the VGA (ADL5330) and can be increased by using a VGA with more gain. The temperature performance is directly related to the temperature performance of the AD8363 at 2.14 GHz and −26 dBm, using TCM1 = 0.52 V and TCM2 = 0.6 V. All other temperature variations are removed by the AD8363. PIN C5 100pF T1 The relationship between VSET and the RF input follows the measurement mode behavior of the device. For example, Figure 4 shows the measurement mode transfer function at 900 MHz and that an input power of −10 dBm yields an output voltage of approximately 2.5 V. Therefore, in controller mode, if VSET is 2.5 V, the AD8363 output would go to whatever voltage is necessary to set the AD8363 input power to −10 dBm. C11 100pF ADL5330 INHI OPHI INLO OPLO C6 100pF 10dB COUPLER POUT T2 C12 100pF GAIN AD8062 10kΩ 10kΩ CONSTANT OUTPUT POWER OPERATION In controller mode, the AD8363 can be used to hold the output power of a VGA stable over a broad temperature/input power range. This is useful in topologies where a transmit card is driving an HPA, or when connecting any two power sensitive modules together. 10kΩ 5V C10 0.1µF VOUT 0.52V Figure 54 shows a schematic of a circuit setup that holds the output power to approximately −26 dBm at 2.14 GHz, when the input power is varied over a 40 dB dynamic range. Figure 55 shows the results. A portion of the output power is coupled off using a 10 dB directional coupler, and it is then fed into the AD8363. VSET is fixed at 0.95 V, which forces to AD8363 output voltage to control the ADL5330 so that the input to the AD8363 is approximately −36 dBm. TCM1 INHI AD8363 TCM2 VSET INLO CLPF C12 0.1µF C9 0.1µF 0.95V 07368-072 0.6V Figure 54. Constant Power Circuit –25.0 –25.5 –26.0 –26.5 –27.0 –20°C –40°C +85°C +25°C 0°C –27.5 –28.0 –40 –35 –30 –25 –20 –15 PIN (dBm) –10 –5 Figure 55. Performance of the Circuit Shown in Figure 54 Rev. B | Page 24 of 29 0 07368-055 POUT (dBm) If the AD8363 was in measurement mode and a −36 dBm input power is applied, the output voltage would be 0.95 V. A generalpurpose, rail-to-rail op amp (AD8062) is used to invert the slope of the AD8363 so that the gain of the ADL5330 decreases as the AD8363 control voltage increases. The output power is controlled to a 10 dB higher power level than that seen by the AD8363 due to the coupler. The high-end power is limited by the linearity of the VGA (ADL5330) with high attenuation and can be increased by using a higher linearity VGA. 10kΩ Data Sheet AD8363 A voltmeter measured the subsequent response to the stimulus, and the results were stored in a database for later analysis. In this way, multiple AD8363 devices were characterized over amplitude, frequency, and temperature in a minimum amount of time. DESCRIPTION OF RF CHARACTERIZATION The general hardware configuration used for most of the AD8363 characterization is shown in Figure 56. The AD8363 was driven in a single-ended configuration for all characterization. The RF stimulus amplitude was calibrated up to the connector of the circuit board that carries the AD8363. However, the calibration does not account for the slight losses due to the connector and the traces from the connector to the device under test. For this reason, there is a small absolute amplitude error (<0.5 dB) not accounted for in the characterization data. Characterization of the AD8363 employed a multisite test strategy. Several AD8363 devices mounted on circuit boards constructed with Rogers 3006 material was simultaneously inserted into a remotely-controlled thermal test chamber. A Keithley S46 RF switching network connected an Agilent E8251A signal source to the appropriate device under test. An Agilent 34980A switch matrix provided switching of dc power and metering for the test sites. A PC running Agilent VEE Pro controlled the signal source, switching, and chamber temperature. This implies a slight error in the reported intercept; however, this is generally not important because the slope and the relative accuracy of the AD8363 are not affected. The typical performance data was derived with CLPF = 3.9 nF and CHPF = 2.7 nF with a CW waveform. AGILENT E3631A DC POWER SUPPLIES AGILENT 34980A SWITCH MATRIX/ DC METER AGILENT E8251A MICROWAVE SIGNAL GENERATOR KEITHLEY S46 MICROWAVE SWITCH AD8363 CHARACTERIZATION BOARD – TEST SITE 1 AD8363 CHARACTERIZATION BOARD – TEST SITE 2 AD8363 PERSONAL COMPUTER DC DATA AND CONTROL Figure 56. General RF Characterization Configuration Rev. B | Page 25 of 29 07368-075 RF CHARACTERIZATION BOARD – TEST SITE 3 AD8363 Data Sheet EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS Figure 57 to Figure 61 show the evaluation board for the AD8363. VTGT VREF VPOS C7 0.1µF VPOS R10 845Ω 11 C12 0.1µF 16 TCM1 R17 OPEN DUT1 INLO TCM1 R18 OPEN 1 VREFC VOUT CLPF 2 3 7 6 R13 OPEN R6 0Ω VOUT R15 0Ω R1 0Ω VOUT 5 C9 0.1µF C8 OPEN R5 0Ω 4 PADDLE AGND TCM2/PWDN R12 OPEN VSET AD8363 8 C3 OPEN R9 OPEN R16 0Ω C4 100pF GND GNDI C13 0.1µF VPOSC VREFC VPOS1 Figure 57. Evaluation Board Schematic Rev. B | Page 26 of 29 07368-074 C6 OPEN R2 OPEN TEMP INHI VSET TEMP COMM 15 9 VPOS 14 IN C5 100pF NC CHPF 13 C11 OPEN TCM2/PWDN C10 0.1µF 10 VREF VTGT 12 R14 0Ω VPOS R11 1.4kΩ R8 0Ω COMM R7 0Ω Data Sheet AD8363 Table 6. Evaluation Board Configuration Options Component C6, C10, C11, C12 R7, R8, R10, R11 Function/Notes Input. The AD8363 is single-ended driven. At frequencies ≤2.6 GHz, the best dynamic range is achieved by driving Pin 14 (INHI). When driving INHI, populate C10 and C12 with an appropriate capacitor value for the frequency of operation and leave C6 and C11 open. For frequencies >2.6 GHz, additional dynamic range can be achieved by driving Pin 15 (INLO). When driving INLO, populate C6 and C11 with an appropriate capacitor value for the frequency of operation and leave C10 and C12 open. VTGT. R10 and R11 are set up to provide 1.4 V to VTGT from VREF. If R10 and R11 are removed, an external voltage can be used. Alternatively, R7 and R11 can be used to form a voltage divider for an external reference. C4, C5, C7, C13, R14, R16 Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the AD8363, a 0 Ω series resistor, and a 0.1 µF capacitor placed close to the power supply input pin. The 0 Ω resistor can be replaced with a larger resistor to add more filtering; however, it is at the expense of a voltage drop. R1, R2, R6, R13, R15 Output Interface (Default Configuration) in Measurement Mode. In this mode, a portion of the output voltage is fed back to the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude of the slope at VOUT is increased by reducing the portion of VOUT that is fed back to VSET. If a fast responding output is expected, the 0 Ω resistor (R15) can be removed to reduce parasitics on the output. C8, C9, R5 C3 R9, R12 R17, R18 Paddle Output Interface in Controller Mode. In this mode, R6 must be open and R13 must have a 0 Ω resistor. In controller mode, the AD8363 can control the gain of an external component. A setpoint voltage is applied to the VSET pin, the value of which corresponds to the desired RF input signal level applied to the AD8363. If a fast responding output is expected, the 0 Ω resistor (R15) can be removed to reduce parasitics on the output. Low-Pass Filter Capacitors, CLPF. The low-pass filter capacitors reduce the noise on the output and affect the pulse response time of the AD8363. This capacitor should be as large as possible. The smallest CLPF capacitance should be 390 pF. R5, when set to a value other than 0 Ω, is used in conjunction with C8 and C9 to modify the loop transfer function and change the loop dynamics in controller mode. CHPF Capacitor. The CHPF capacitor introduces a high-pass filter affect into the AD8363 transfer function and can also affect the response time. The CHPF capacitor should be as small as possible and connect to VPOS when used. No capacitor is needed for input frequencies greater than 10 MHz. TCM2/PWDN. The TCM2/PWDN pin controls the amount of nonlinear intercept temperature compensation and/or shuts down the device. The evaluation board is configured to control this from a test loop, but VREF can also be used by the voltage divider created by R9 and R12. TCM1. TCM1 controls the temperature compensation (5 kΩ impedance). The evaluation board is configured to control this from a test loop, but VREF can also be used by the voltage divider created by R17 and R18. Due to the relatively low impedance of the TCM1 pin and the limited current of the VREF pin, care should be taken when choosing the R17 and R18 values. Connect the paddle to both a thermal and electrical ground. Rev. B | Page 27 of 29 Default Value C6 = open, C10 = 0.1 µF, C11 = open C12 = 0.1 µF R7 = 0 Ω, R8 = 0 Ω, R10 = 845 Ω, R11 = 1.4 kΩ C4 = 100 pF, C5 = 100 pF, C7 = 0.1µF, C13 = 0.1µF, R14 = 0 Ω, R16 = 0 Ω R1 = 0 Ω, R2 = open, R6 = 0 Ω, R13 = open, R15 = 0 Ω C8 = open, C9 = 0.1 µF, R5 = 0 Ω C3 = open R9 = open, R12 = open R17 = open, R18 = open AD8363 Data Sheet 07368-060 07368-058 ASSEMBLY DRAWINGS Figure 60. Evaluation Board Assembly, Top Side 07368-059 07368-061 Figure 58. Evaluation Board Layout, Top Side Figure 61. Evaluation Board Assembly, Bottom Side Figure 59. Evaluation Board Layout, Bottom Side Rev. B | Page 28 of 29 Data Sheet AD8363 OUTLINE DIMENSIONS 0.35 0.30 0.25 0.65 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 2.40 2.35 SQ 2.30 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 8 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3. 07-18-2012-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 62. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-20) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8363ACPZ-R2 AD8363ACPZ-R7 AD8363ACPZ-WP AD8363-EVALZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07368-0-3/15(B) Rev. B | Page 29 of 29 Package Option CP-16-20 CP-16-20 CP-16-20 Ordering Quantity 250 1,500 64