OP184/OP284/OP484 (Rev. J)

Precision Rail-to-Rail
Input and Output Operational Amplifiers
OP184/OP284/OP484
FEATURES
PIN CONFIGURATIONS
Single-supply operation
Wide bandwidth: 4 MHz
Low offset voltage: 65 μV
Unity-gain stable
High slew rate: 4.0 V/ μs
Low noise: 3.9 nV/√Hz
DNC
1
–IN A
2
OP184
8
NC
7
V+
6
OUT A
5
DNC
–
+IN A
3
V–
4
TOP VIEW
(Not to Scale)
00293-001
+
NOTES
1. NC = NO CONNECT
2. DNC = DO NOT CONNECT
APPLICATIONS
Figure 1. 8-Lead SOIC (S-Suffix)
GENERAL DESCRIPTION
These amplifiers are superb for single-supply applications requiring
both ac and precision dc performance. The combination of wide
bandwidth, low noise, and precision makes the OP184/OP284/
OP484 useful in a wide variety of applications, including filters
and instrumentation.
Other applications for these amplifiers include portable telecommunications equipment, power supply control and protection,
and use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
1
OP284
8
V+
OUT B
–IN A
2
7
+IN A
3
6
–IN B
V–
4
5
+IN B
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
OUT A
1
14
OUT D
–IN A
2
13
–IN D
+IN A
3
12
+IN D
V+
4
11
V–
+IN B
5
10
+IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
OP484
TOP VIEW
(Not to Scale)
00293-003
The OP184/OP284/OP484 are single, dual, and quad single-supply,
4 MHz bandwidth amplifiers featuring rail-to-rail inputs and
outputs. They are guaranteed to operate from 3 V to 36 V (or
±1.5 V to ±18 V).
OUT A
00293-002
Battery-powered instrumentation
Power supply control and protection
Telecommunications
DAC output amplifier
ADC input buffer
Figure 3. 14-Lead PDIP (P-Suffix)
14-Lead Narrow-Body SOIC (S-Suffix)
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The OP184/OP284/OP484 are specified over the hot extended
industrial temperature range of −40°C to +125°C. The single
OP184 is available in 8-lead SOIC surface mount packages. The
dual OP284 is available in 8-lead PDIP and SOIC surface mount
packages. The quad OP484 is available in 14-lead PDIP and
14-lead, narrow-body SOIC packages.
Table 1. Low Noise Op Amps
Voltage Noise
Single
Dual
Quad
0.9 nV
AD797
1.1 nV
AD8597
AD8599
1.8 nV
ADA4004-1
ADA4004-2
ADA4004-4
2.8 nV
AD8675/ADA4075-2
AD8676
3.2 nV
OP27
OP270
OP470
3.8 nV
AD8671
AD8672
AD8674
3.9 nV
OP184
OP284
OP484
Rev. J
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved.
OP184/OP284/OP484
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Phase Reversal ............................................................... 15
Applications ....................................................................................... 1
General Description ......................................................................... 1
Designing Low Noise Circuits in Single-Supply Applications
....................................................................................................... 15
Pin Configurations ........................................................................... 1
Overdrive Recovery ................................................................... 16
Revision History ............................................................................... 2
Single-Supply, 3 V Instrumentation Amplifier ...................... 16
Specifications..................................................................................... 3
2.5 V Reference from a 3 V Supply .......................................... 17
Electrical Characteristics ............................................................. 3
5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 17
Absolute Maximum Ratings ............................................................ 6
High-Side Current Monitor ...................................................... 18
Thermal Resistance ...................................................................... 6
Capacitive Load Drive Capability ............................................ 18
ESD Caution .................................................................................. 6
Low Dropout Regulator with Current Limiting..................... 19
Typical Performance Characteristics ............................................. 7
3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 20
Applications Information .............................................................. 14
Outline Dimensions ....................................................................... 21
Functional Description .............................................................. 14
Ordering Guide .......................................................................... 23
Input Overvoltage Protection ................................................... 14
REVISION HISTORY
4/11—Rev. I to Rev J
Change to Figure 27 ....................................................................... 10
10/10—Rev. H to Rev I
Change to Output Characteristics, Output Voltage High
Parameter, Table 2............................................................................. 3
Change to Output Characteristics, Output Voltage High
Parameter, Table 3............................................................................. 4
7/10—Rev. G to Rev. H
Added Table 1.................................................................................... 1
2/09—Rev. F to Rev. G
Change to Large Signal Voltage Gain, Table 3 .............................. 5
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
9/08—Rev. E to Rev. F
Changes to General Description .................................................... 1
Changes to Figure 4 .......................................................................... 6
Changes to Low Dropout Regulator with Current Limiting .... 20
7/08—Rev. D to Rev. E
Changes to Figure 1 .......................................................................... 1
Changes to Figure 12 ........................................................................ 8
Changes to Figure 36 and Figure 37............................................. 12
Changes to Designing Low Noise Circuits in Single-Supply
Applications Section ....................................................................... 15
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
4/06—Rev. C to Rev. D
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................5
Deleted Reference to 1993 System Applications Guide .............. 15
3/06—Rev. B to Rev. C
Changes to Figure 1 Caption............................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................5
Changes to Table 4.............................................................................6
Changes to Figure 5 through Figure 9 ............................................7
Changes to Functional Description Section ............................... 14
Deleted SPICE Macro Model ........................................................ 21
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
9/02—Rev. A to Rev. B
Changes to Pin Configurations .......................................................1
Changes to Specifications, Input Bias Current Maximum ..........2
Changes to Ordering Guide .............................................................5
Updated Outline Dimensions ....................................................... 19
6/02—Rev. 0 to Rev. A
10/96—Revision 0: Initial Version
Rev. J | Page 2 of 24
OP184/OP284/OP484
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade 1
Symbol
Conditions
Min
Typ
VOS
−40°C ≤ TA ≤ +125°C
Offset Voltage, OP184/OP284F Grade1
VOS
Offset Voltage, OP484E Grade1
VOS
Offset Voltage, OP484F Grade1
VOS
−40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Input Bias Current
IB
60
–40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
2
–40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Bias Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
VCM = 0 V to 5 V
VCM = 1.0 V to 4.0 V, −40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 1 V ≤ VO ≤ 4 V
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C
0
60
86
50
25
ΔIB/ΔT
Max
Unit
65
165
125
350
75
175
150
450
450
600
50
50
5
μV
μV
μV
μV
μV
μV
μV
μV
nA
nA
nA
nA
V
dB
dB
V/mV
V/mV
pA/°C
240
150
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
PSRR
ISY
VS
VS = 2.0 V to 10 V, −40°C ≤ TA ≤ +125°C
VO = 2.5 V, −40°C ≤ TA ≤ +125°C
SR
tS
GBP
ΦM
RL = 2 kΩ
To 0.01%, 1.0 V step
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
4.80
125
±6.5
76
1.45
36
3
1.65
dB
mA
V
2.4
2.5
3.25
45
V/µs
µs
MHz
Degrees
0.3
3.9
0.4
μV p-p
nV/√Hz
pA/√Hz
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Rev. J | Page 3 of 24
V
mV
mA
OP184/OP284/OP484
VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1
Symbol
Conditions
Min
Typ
VOS
−40°C ≤ TA ≤ +125°C
Offset Voltage, OP184/OP284F Grade1
VOS
Offset Voltage, OP484E Grade1
VOS
Offset Voltage, OP484F Grade1
VOS
Input Bias Current
IB
−40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise Density
1
IOS
60
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
0
60
56
CMRR
VCM = 0 V to 3 V
VCM = 0 V to 3 V, −40°C ≤ TA ≤ +125°C
VOH
VOL
IL = 1.0 mA
IL = 1.0 mA
2.80
PSRR
ISY
VS = ±1.25 V to ±1.75 V
VO = 1.5 V, −40°C ≤ TA ≤ +125°C
76
GBP
en
f = 1 kHz
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Rev. J | Page 4 of 24
Max
Unit
65
165
125
350
100
200
150
450
450
600
50
3
μV
μV
μV
μV
μV
μV
μV
μV
nA
nA
nA
V
dB
dB
125
V
mV
1.35
dB
mA
3
MHz
3.9
nV/√Hz
OP184/OP284/OP484
VS = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1
Symbol
Conditions
Min
Typ
VOS
−40°C ≤ TA ≤ +125°C
Offset Voltage, OP184/OP284F Grade1
VOS
Offset Voltage, OP484E Grade1
VOS
Offset Voltage, OP484F Grade1
VOS
Input Bias Current
IB
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
IOS
Large Signal Voltage Gain
AVO
Offset Voltage Drift E Grade
Bias Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
CMRR
80
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = −14.0 V to +14.0 V, −40°C ≤ TA ≤ +125°C
VCM = −15.0 V to +15.0 V
RL = 2 kΩ, −10 V ≤ VO ≤ 10 V
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C
−15
86
80
150
75
ΔVOS/ΔT
ΔVB/ΔT
IL = 1.0 mA
IL = 1.0 mA
PSRR
ISY
ISY
VS = ±2.0 V to ±18 V, −40°C ≤ TA ≤ +125°C
VO = 0 V, −40°C ≤ TA ≤ +125°C
VS = ±18 V, −40°C ≤ TA ≤ +125°C
90
SR
BWp
tS
GBP
ΦM
RL = 2 kΩ
1% distortion, RL = 2 kΩ, VO = 29 V p-p
To 0.01%, 10 V step
2.4
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
Unit
100
200
175
375
150
300
250
500
450
575
50
+15
μV
μV
μV
μV
μV
μV
μV
μV
nA
nA
nA
V
dB
dB
V/mV
V/mV
μV/°C
pA/°C
90
1000
0.2
150
VOH
VOL
IOUT
Max
2.00
14.8
−14.875
±10
2.0
2.25
dB
mA
mA
4.0
35
4
4.25
50
V/µs
kHz
µs
MHz
Degrees
0.3
3.9
0.4
µV p-p
nV/√Hz
pA/√Hz
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Rev. J | Page 5 of 24
V
V
mA
OP184/OP284/OP484
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration to GND
Storage Temperature Range
P-Suffix, S-Suffix Packages
Operating Temperature Range
OP184/OP284/OP484E/OP484F
Junction Temperature Range
P-Suffix, S-Suffix Packages
Lead Temperature
(Soldering 60 sec)
1
THERMAL RESISTANCE
Rating
±18 V
±18 V
±0.6 V
Indefinite
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device in socket for PDIP. θJA is specified for a
device soldered in the circuit board for SOIC packages.
Table 6. Thermal Resistance
Package Type
8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
14-Lead PDIP (P-Suffix)
14-Lead SOIC (S-Suffix)
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
θJA
103
158
83
92
θJC
43
43
39
27
Unit
°C/W
°C/W
°C/W
°C/W
ESD CAUTION
For input voltages greater than 0.6 V, the input current should be limited to
less than 5 mA to prevent degradation or destruction of the input devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply to both DICE and packaged
parts, unless otherwise noted.
VCC
RB1
R4
R3
QB5
QB6
RB3
RB4
R11
TP
Q8
Q7
QL1
Q3
Q4
–IN
QB10
+IN
QL2
Q5
CC2
Q10
Q9
Q6
QB2
CB1 N+
QB9
Q2
OUT
C O
C FF
R6
Q18
QB3
RB2
M P+
R7
QB4
QB7
QB1
R1
JB2
R2
CC1
R5
QB8
Q13
R8
Q14
Q15
R9
R10
VEE
Figure 4. Simplified Schematic
Rev. J | Page 6 of 24
00293-004
Q1
Q17
Q16
Q12
Q11
JB1
OP184/OP284/OP484
TYPICAL PERFORMANCE CHARACTERISTICS
270
300
VS = 3V
TA = 25°C
VCM = 1.5V
VS = 5V
–40°C ≤ TA ≤ +125°C
250
240
200
180
QUANTITY
150
120
150
100
90
60
00293-005
50
30
0
–100
–75
–50
–25
0
25
50
75
0
100
0
200
180
QUANTITY
QUANTITY
1.50
250
150
120
150
100
90
60
00293-006
50
30
0
–100
–75
–50
–25
0
25
50
75
0
100
0
0.25
0.50
0.75
1.00
1.25
1.50
OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
INPUT OFFSET VOLTAGE (µV)
Figure 6. Input Offset Voltage Distribution
Figure 9. Input Offset Voltage Drift Distribution
–40
VS = ±15V
TA = 25°C
VCM = VS/2
INPUT BIAS CURRENT (nA)
–45
150
125
100
75
50
–50
–55
VS = +5V
–60
–65
–70
VS = ±15V
25
0
–125 –100
–75
00293-007
QUANTITY
1.25
VS = ±15V
–40°C ≤ TA ≤ +125°C
210
175
1.00
300
VS = 5V
TA = 25°C
VCM = 2.5V
240
200
0.75
00293-009
270
0.50
Figure 8. Input Offset Voltage Drift Distribution
Figure 5. Input Offset Voltage Distribution
300
0.25
OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
INPUT OFFSET VOLTAGE (µV)
–75
–50 –25
0
25
50
75
INPUT OFFSET VOLTAGE (µV)
100
–80
–40
125
00293-010
QUANTITY
210
00293-008
300
25
85
TEMPERATURE (°C)
Figure 7. Input Offset Voltage Distribution
Figure 10. Bias Current vs. Temperature
Rev. J | Page 7 of 24
125
OP184/OP284/OP484
500
1.50
VS = ±15V
200
100
0
–100
–200
00293-011
–300
–500
–15
–10
–5
0
5
10
1.25
1.00
0.75
0.50
0.25
00293-014
INPUT BIAS CURRENT (nA)
300
–400
TA = 25°C
SUPPLY CURRENT/PER AMPLIFIER (mA)
400
0
15
0
±2.5
±5.0
COMMON-MODE VOLTAGE (V)
±7.5
±10.0
±12.5
±15.0
±17.5
±20.0
SUPPLY VOLTAGE (V)
Figure 11. Input Bias Current vs. Common-Mode Voltage
Figure 14. Supply Current vs. Supply Voltage
1000
50
VS = ±15V
SHORT-CIRCUIT CURRENT (mA)
SOURCE
100
SINK
30
0.1
1
–ISC
–ISC
20
+ISC
10
0
–50
10
–25
0
LOAD CURRENT (mA)
25
50
125
Figure 15. Short-Circuit Current vs. Temperature
70
1.2
VS = 5V
TA = 25°C
NO LOAD
60
1.1
OPEN-LOOP GAIN (dB)
0.9
0.8
VS = +5V
0.7
VS = +3V
0.6
25
85
40
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
10k
125
100k
1M
10M
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. Open-Loop Gain and Phase vs. Frequency (No Load)
Figure 13. Supply Current vs. Temperature
Rev. J | Page 8 of 24
PHASE SHIFT (Degrees)
50
VS = ±15V
1.0
00293-013
SUPPLY CURRENT/AMPLIFIER (mA)
100
TEMPERATURE (°C)
Figure 12. Output Voltage to Supply Rail vs. Load Current
0.5
–40
75
00293-015
VS = +5V, VCM = +2.5V
00293-016
10
0.01
+ISC
00293-012
OUTPUT VOLTAGE (mV)
VS = ±15V
40
OP184/OP284/OP484
70
60
VS = 3V
TA = 25°C
NO LOAD
60
50
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
10k
100k
1M
30
20
10
0
–10
–20
00293-020
0
CLOSED-LOOP GAIN (dB)
40
PHASE SHIFT (Degrees)
40
00293-017
OPEN-LOOP GAIN (dB)
VS = 5V
RL = 2kΩ
TA = 25°C
50
–30
–40
10
10M
100
1k
FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase vs. Frequency (No Load)
100k
10M
60
VS = ±15V
TA = 25°C
NO LOAD
60
VS = ±15V
RL = 2kΩ
TA = 25°C
50
50
90
10
135
0
180
225
–20
270
–30
10k
100k
1M
30
20
10
0
–10
–20
00293-020
45
20
CLOSED-LOOP GAIN (dB)
30
00293-018
0
PHASE SHIFT (Degrees)
40
40
–10
–30
–40
10
10M
100
1k
FREQUENCY (Hz)
10k
100k
10M
Figure 21. Closed-Loop Gain vs. Frequency (2 kΩ Load)
2500
60
VS = 3V
RL = 2kΩ
TA = 25°C
50
2000
CLOSED-LOOP GAIN (dB)
40
1500
VS = ±15V
–10V < VO < +10V
RL = 2kΩ
1000
VS = +5V
+1V < VO < +10V
RL = 2kΩ
–25
0
25
30
20
10
0
–10
50
75
100
00293-020
–20
00293-019
500
0
–50
1M
FREQUENCY (Hz)
Figure 18. Open-Loop Gain and Phase vs. Frequency (No Load)
OPEN-LOOP GAIN (V/mV)
1M
Figure 20. Closed-Loop Gain vs. Frequency (2 kΩ Load)
70
OPEN-LOOP GAIN (dB)
10k
FREQUENCY (Hz)
–30
–40
10
125
TEMPERATURE (°C)
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 19. Open-Loop Gain vs. Temperature
Figure 22. Closed-Loop Gain vs. Frequency (2 kΩ Load)
Rev. J | Page 9 of 24
10M
OP184/OP284/OP484
300
AV = +10
MAXIMUM OUTPUT SWING (V p-p)
OUTPUT IMPEDANCE (Ω)
240
AV = +100
210
180
150
120
90
AV = +1
30
0
10
100
1k
10k
100k
1M
3
2
1
00293-023
60
4
0
1k
10M
VS = 5V
VIN = 0.5V TO 4.5V
RL = 2kΩ
TA = 25°C
00293-026
270
5
VS = 5V
TA = 25°C
10k
100k
FREQUENCY (Hz)
Figure 23. Output Impedance vs. Frequency
30
25
240
210
20
AV = +10
AV = +100
VOUT (V)
OUTPUT IMPEDANCE (Ω)
VS = ±15V
VIN = ±14V
RL = 2kΩ
TA = 25°C
VS = 15V
TA = 25°C
180
10M
Figure 26. Maximum Output Swing vs. Frequency
300
270
1M
FREQUENCY (Hz)
150
120
15
10
90
60
100
1k
10k
100k
1M
0
1k
10M
10k
FREQUENCY (Hz)
180
VS = 3V
TA = 25°C
AV = +10
160
TA = 25°C
AV = +100
240
140
120
180
100
150
120
60
90
40
60
20
AV = +1
30
100
1k
10k
100k
1M
VS = ±15V
80
VS = +3V
VS = +5V
00293-028
CMRR (dB)
210
00293-025
OUTPUT IMPEDANCE (Ω)
10M
Figure 27. Maximum Output Swing vs. Frequency
300
0
10
1M
FREQUENCY (Hz)
Figure 24. Output Impedance vs. Frequency
270
100k
00293-027
0
10
AV = +1
00293-024
5
30
0
–20
10
10M
FREQUENCY (Hz)
100
1k
10k
100k
FREQUENCY (Hz)
Figure 25. Output Impedance vs. Frequency
Figure 28. CMRR vs. Frequency
Rev. J | Page 10 of 24
1M
10M
OP184/OP284/OP484
30
160
25
NOISE DENSITY (nV/ Hz)
120
PSRR (dB)
100
80
VS = ±15V
60
40
VS = +5V
20
0
20
15
10
100
1k
10k
100k
1M
00293-029
5
VS = +3V
–20
–40
10
±2.5V ≤ VS ≤ ±15V
TA = 25°C
00293-032
140
TA = 25°C
0
1
10M
10
Figure 29. PSRR vs. Frequency
10
OVERSHOOT (%)
60
–OS
40
+OS
30
20
00293-030
10
0
10
100
±2.5V ≤ VS ≤ ±15V
TA = 25°C
8
6
4
2
00293-033
CURRENT NOISE DENSITY (pA/ Hz)
VS = ±2.5V
TA = 25°C, AVCL = 1
70 V = ±50mV
IN
50
1000
Figure 32. Voltage Noise Density vs. Frequency
80
0
1000
1
10
100
1000
FREQUENCY (Hz)
CAPACITIVE LOAD (pF)
Figure 30. Small Signal Overshoot vs. Capacitive Load
Figure 33. Current Noise Density vs. Frequency
7
5
VS = ±15V
RL = 2kΩ
6
VS = 5V
TA = 25°C
4
3
+SLEW RATE
5
STEP SIZE (V)
2
–SLEW RATE
4
3
+SLEW RATE
1
0.1%
0
0.01%
–1
–2
2
–SLEW RATE
0
–50
–25
0
25
50
75
100
00293-034
–3
VS = ±5V
RL = 2kΩ
1
00293-031
SLEW RATE (V/µs)
100
FREQUENCY (Hz)
FREQUENCY (Hz)
–4
–5
0
125
1
2
3
4
SETTLING TIME (µs)
TEMPERATURE (°C)
Figure 31. Slew Rate vs. Temperature
Figure 34. Step Size vs. Settling Time
Rev. J | Page 11 of 24
5
6
OP184/OP284/OP484
160
10
VS = ±15V
TA = 25°C
TA = 25°C
140
CHANNEL SEPARATION (dB)
6
STEP SIZE (V)
4
2
0.1%
0
0.01%
–2
–4
00293-035
–6
–8
–10
0
1
2
3
4
5
120
VS = ±15V
100
80
60
VS = +3V
40
20
0
00293-038
8
–20
–40
100
6
1k
10k
100k
1M
10M
FREQUENCY (Hz)
SETTLING TIME (µs)
Figure 35. Step Size vs. Settling Time
Figure 38. Channel Separation vs. Frequency
0.3
VS = 5V
AV = +1
RL = OPEN
CL = 300pF
TA = 25°C
VS = ±2.5V
AV = 10M
0.2
100
400mV
90
0V
10
NOISE (µV)
0.1
0
–0.1
–4
–3
–2
–1
0
TIME
1
2
3
4
5
1µs
00293-036
100mV
–0.3
–5
00293-039
0%
–0.2
Figure 39. Small Signal Transient Response
Figure 36. 0.1 Hz to 10 Hz Noise
0.3
VS = 5V
AV = +1
RL = 2kΩ
CL = 300pF
TA = 25°C
VS = ±15V
AV = 10M
0.2
100
400mV
90
0V
10
0
–0.1
100mV
–0.3
–5
–4
–3
–2
–1
0
TIME
1
2
3
4
5
1µs
Figure 37. 0.1 Hz to 10 Hz Noise
Figure 40. Small Signal Transient Response
Rev. J | Page 12 of 24
00293-040
0%
–0.2
00293-037
NOISE (µV)
0.1
OP184/OP284/OP484
0.1
VS = ±1.5V
AV = +1
NO LOAD
TA = 25°C
100
90
THD+N (%)
+200mV
VO = ±0.75V
0V
–200mV
AV = +1000
VS = ±2.5V
RL = 2kΩ
0.01
VO = ±2.5V
10
500ns
VO = ±1.5V
0.001
0.0005
20
100
00293-043
100mV
00293-041
0%
1k
10k
FREQUENCY (Hz)
Figure 41. Small Signal Transient Response
VS = ±0.75V
AV = +1
NO LOAD
TA = 25°C
100
+200mV
Figure 43. Total Harmonic Distortion + Noise vs. Frequency
90
0V
10
0%
100mV
1µs
00293-042
–200mV
Figure 42. Small Signal Transient Response
Rev. J | Page 13 of 24
20k
OP184/OP284/OP484
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The OP184/OP284/OP484 are precision single-supply, rail-to-rail
operational amplifiers. Intended for the portable instrumentation
marketplace, the OPx84 family of devices combine the attributes
of precision, wide bandwidth, and low noise to make them a superb
choice in single-supply applications that require both ac and
precision dc performance. Other low supply voltage applications for which the OP284 is well suited are active filters,
audio microphone preamplifiers, power supply control, and
telecommunications. To combine all of these attributes with
rail-to-rail input/output operation, novel circuit design techniques
are used.
To achieve rail-to-rail output, the OP284 output stage design
employs a unique topology for both sourcing and sinking current.
This circuit topology is illustrated in Figure 45. The output stage
is voltage-driven from the second gain stage. The signal path
through the output stage is inverting; that is, for positive input
signals, Q1 provides the base current drive to Q6 so that it conducts
(sinks) current. For negative input signals, the signal path via
Q1→Q2→D1→Q4→Q3 provides the base current drive for Q5 to
conduct (source) current. Both amplifiers provide output current
until they are forced into saturation, which occurs at approximately 20 mV from the negative supply rail and 100 mV from
the positive supply rail.
V+
V+
R4
R2
4kΩ
I1
–
Q1
Q3
+IN x
D1
Q4
I2
INPUT FROM
SECOND GAIN
STAGE
V01
Q2
VOUT
R1
Q6
–IN x
D2
R2
–
I2
D1
R5
I1
R4
3kΩ
V–
Q4
Q2
V02
R3
00293-044
R3
3kΩ
Q5
Q3
Q1
R6
V–
00293-045
R1
4kΩ
Figure 44. OP284 Equivalent Input Circuit
Figure 45. OP284 Equivalent Output Circuit
For example, Figure 44 illustrates a simplified equivalent circuit
for the input stage of the OP184/OP284/OP484. It comprises
an NPN differential pair, Q1→Q2, and a PNP differential pair,
Q3→Q4, operating concurrently. Diode Network D1→Diode
Network D2 serves to clamp the applied differential input
voltage to the OP284, thereby protecting the input transistors
against avalanche damage. Input stage voltage gains are kept low
for input rail-to-rail operation. The two pairs of differential
output voltages are connected to the second stage of the OP284,
which is a compound folded cascade gain stage. It is also in the
second gain stage, where the two pairs of differential output
voltages are combined into a single-ended, output signal voltage
used to drive the output stage. A key issue in the input stage is
the behavior of the input bias currents over the input commonmode voltage range. Input bias currents in the OP284 are the
arithmetic sum of the base currents in Q1→Q3 and in Q2→Q4.
As a result of this design approach, the input bias currents in
the OP284 not only exhibit different amplitudes; they also
exhibit different polarities. This effect is best illustrated by
Figure 10. It is, therefore, of paramount importance that the
effective source impedances connected to the OP284 inputs
be balanced for optimum dc and ac performance.
Thus, the saturation voltage of the output transistors sets the
limit on the OP284 maximum output voltage swing. Output
short-circuit current limiting is determined by the maximum
signal current into the base of Q1 from the second gain stage.
Under output short-circuit conditions, this input current level
is approximately 100 µA. With transistor current gains around 200,
the short-circuit current limits are typically 20 mA. The output
stage also exhibits voltage gain. This is accomplished by the use
of common-emitter amplifiers, and, as a result, the voltage gain
of the output stage (thus, the open-loop gain of the device)
exhibits a dependence to the total load resistance at the output
of the OP284.
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier could be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current. Figure 46 illustrates the
overvoltage I-V characteristic of the OP284. This graph was
generated with the supply pins connected to GND and a curve
tracer’s collector output drive connected to the input.
Rev. J | Page 14 of 24
OP184/OP284/OP484
external clamping diodes, with the anode connected to ground
and the cathode to the inputs, prevent input signal excursions
from exceeding the negative supply of the device (that is, GND),
preventing a condition that causes the output voltage to change
phase. JFET-input amplifiers can also exhibit phase reversal;
and, if so, a series input resistor is usually required to prevent it.
4
INPUT CURRENT (mA)
3
2
1
0
–1
–2
00293-046
–3
–4
–5
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT VOLTAGE (V)
Figure 46. Input Overvoltage I-V Characteristics of the OP284
As shown in Figure 46, internal p-n junctions to the OP284
energize and permit current flow from the inputs to the supplies
when the input is 1.8 V more positive and 0.6 V more negative
than the respective supply rails. As illustrated in the simplified
equivalent circuit shown in Figure 44, the OP284 does not have
any internal current limiting resistors; thus, fault currents can
quickly rise to damaging levels.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. For the OP284, once
the input exceeds the negative supply by 0.6 V, the input current
quickly exceeds 5 mA. If this condition continues to exist, an
external series resistor should be added at the expense of additional thermal noise. Figure 47 illustrates a typical noninverting
configuration for an overvoltage-protected amplifier where the
series resistance, RS, is chosen such that
RS =
The OP284 is free from reasonable input voltage range restrictions,
provided that input voltages no greater than the supply voltages
are applied. Although device output does not change phase, large
currents can flow through the input protection diodes, as shown
in Figure 46. Therefore, the technique recommended in the Input
Overvoltage Protection section should be applied to those applications where the likelihood of input voltages exceeding the
supply voltages is high.
DESIGNING LOW NOISE CIRCUITS IN SINGLESUPPLY APPLICATIONS
In single-supply applications, devices like the OP284 extend the
dynamic range of the application through the use of rail-to-rail
operation. In fact, the OPx84 family is the first of its kind to
combine single-supply, rail-to-rail operation, and low noise in
one device. It is the first device in the industry to exhibit an input
noise voltage spectral density of less than 4 nV/√Hz at 1 kHz.
It was also designed specifically for low-noise, single-supply
applications, and as such, some discussion on circuit noise
concepts in single-supply applications is appropriate.
Referring to the op amp noise model circuit configuration
illustrated in Figure 48, the expression for an amplifier’s total
equivalent input noise voltage for a source resistance level, RS,
is given by
e nT = 2 [(e nR ) 2 + (inOA ×
VIN ( MAX ) − VSUPPLY
5 mA
For example, a 1 kΩ resistor protects the OP284 against input
signals up to 5 V above and below the supplies. For other configurations where both inputs are used, each input should be protected
against abuse with a series resistor. Again, to ensure optimum
dc and ac performance, it is recommended that source impedance
levels be balanced.
R2
OP284
VIN
VOUT
R
enR
NOISELESS
Figure 47. Resistance in Series with Input Limits Overvoltage Currents
to Safe Values
OUTPUT PHASE REVERSAL
R
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. Typically, for
single-supply bipolar op amps, the negative supply determines
the lower limit of their common-mode range. With these devices,
V
Hz
where:
RS = 2R is the effective, or equivalent, circuit source resistance.
(enR)2 is the source resistance thermal noise voltage power (4kTR).
k is the Boltzmann’s constant = 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvins of the circuit = 273.15 +
TA (°C).
(inOA)2 is the op amp equivalent input noise current spectral power
(1 Hz bandwidth).
(enOA)2 is the op amp equivalent input noise voltage spectral power
(1 Hz bandwidth).
00293-047
1/2
R1
R S )2 ] + (e nOA )2 , units in
NOISELESS
enOA
inOA
enR
inOA
IDEAL
NOISELESS
OP AMP
RS = 2R
00293-048
5
Figure 48. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
Rev. J | Page 15 of 24
OP184/OP284/OP484
As a design aid, Figure 49 shows the total equivalent input noise
of the OP284 and the total thermal noise of a resistor for comparison. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the OP284 is dominant.
10
NOISE FIGURE (dB)
8
FREQUENCY = 1kHz
TA = 25°C
OP284 TOTAL
EQUIVALENT NOISE
7
6
5
4
3
00293-050
2
10
1
0
100
RESISTOR THERMAL
NOISE ONLY
10k
100k
TOTAL SOURCE RESISTANCE, RS (Ω)
Figure 49. OP284 Equivalent Thermal Noise vs. Total Source Resistance
Because circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is often expressed in terms of its
noise figure, NF. The noise figure is defined as the ratio of a
circuit’s output signal-to-noise to its input signal-to-noise.
An expression of a circuit NF in dB, and in terms of the
operational amplifier voltage and current noise parameters
defined previously, is given by
  (e )2 + (inOA × RS )2
NF (dB ) = 10 log 1 +  nOA
(enRS )2
 
100k




Therefore, to achieve optimum circuit SNR in single-supply
applications, it is recommended that an operational amplifier
with the lowest equivalent input noise voltage be chosen, along
with source resistance levels that are consistent with maintaining
low total circuit noise.
OVERDRIVE RECOVERY
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear region
from a saturated condition. The recovery time is important in
applications where the amplifier must recover quickly after a
large transient event. The circuit shown in Figure 51 was used
to evaluate the OP284 overload recovery time. The OP284
takes approximately 2 µs to recover from positive saturation
and approximately 1 µs to recover from negative saturation.
R1
10kΩ
where:
NF (dB) is the noise figure of the circuit, expressed in decibels.
(enOA)2 is the OP284 noise voltage spectral power (1 Hz bandwidth).
(inOA)2 is the OP284 noise current spectral power (1 Hz bandwidth).
(enRS)2 is the source resistance thermal noise voltage power =
(4kTRS).
RS is the effective, or equivalent, source resistance presented to
the amplifier.
Calculation of the circuit noise figure is straightforward because
the signal level in the application is not required to determine it.
However, many designers using NF calculations as the basis for
achieving optimum SNR believe that a low noise figure is equal to
low total noise. In fact, the opposite is true, as shown in Figure 50.
The noise figure of the OP284 is expressed as a function of
the source resistance level. Note that the lowest noise figure for
the OP284 occurs at a source resistance level of 10 kΩ.
However, Figure 49 shows that this source resistance level and
the OP284 generate approximately 14 nV/ √Hz of total
equivalent circuit noise. Signal levels in the application
invariably increase to maximize circuit SNR, which is not an
option in low voltage, single-supply applications.
R2
10kΩ
+5V
2
R3
9kΩ
VIN
10V STEP
8
1/2
3
OP284
1
VOUT
4
–5V
00293-051
1k
1k
10k
TOTAL SOURCE RESISTANCE, RS (Ω)
Figure 50. OP284 Noise Figure vs. Source Resistance
00293-049
EQUIVALENT THERMAL NOISE (nV/ Hz)
100
1
100
FREQUENCY = 1kHz
TA = 25°C
9
Figure 51. Output Overload Recovery Test Circuit
SINGLE-SUPPLY, 3 V INSTRUMENTATION
AMPLIFIER
The low noise, wide bandwidth, and rail-to-rail input/output
operation of the OP284 make it ideal for low supply voltage
applications such as in the two op amp instrumentation amplifier
shown in Figure 52. The circuit uses the classic two op amp
instrumentation amplifier topology with four resistors to set the
gain. The transfer equation of the circuit is identical to that of a
noninverting amplifier. Resistor R2 and Resistor R3 should be
closely matched to each other, as well as to Resistors (R1 + P1)
and Resistor R4 to ensure good common-mode rejection
performance.
Rev. J | Page 16 of 24
OP184/OP284/OP484
1
f (3 dB ) =
2π R 4 C 2
RP1
1kΩ
5
3
2
A1
1
R3
1.1kΩ
2
1
2.5VREF
4
R2
100kΩ
P1
5kΩ
RESISTORS = 1%, 100ppm/°C
POTENTIOMETER = 10 TURN, 100ppm/°C
Figure 53. 2.5 V Reference That Operates on a Single 3 V Supply
6
5V
1.23V
8
7
A2
The OP284 is ideal for use with a CMOS DAC to generate a
digitally controlled voltage with a wide output range. Figure 54
shows a DAC8043 used in conjunction with the AD589 to generate a voltage output from 0 V to 1.23 V. The DAC is actually
operating in voltage switching mode, where the reference is
connected to the current output, IOUT, and the output voltage is
taken from the VREF pin. This topology is inherently noninverting,
as opposed to the classic current output mode, which is inverting
and not usable in single-supply applications.
VOUT
AD589
R4
10kΩ
3
IOUT
RRB
C2
Figure 52. Single Supply, 3 V Low Noise Instrumentation Amplifier
The low TCVOS of the OP284 at 1.5 μV/°C helps maintain an
output voltage temperature coefficient that is dominated by
the temperature coefficients of R2 and R3. In this circuit with
100 ppm/°C TCR resistors, the output voltage exhibits a temperature coefficient of 200 ppm/°C. Lower tempco resistors are
recommended for more accurate performance over temperature.
2
1
DAC8043 VREF
5V
GND CLK SR1
7
LD
6
5
DIGITAL
CONTROL
R3
232Ω
1%
00293-052
A1, A2 = 1/2 OP284
R4
GAIN = 1 +
R3
SET R2 = R3
R1 + P1 = R4
8
VDD
4
R1
9.53kΩ
P1
500Ω
0.1µF
1/2
OP284
R3
100kΩ
4
R2
1.1kΩ
C1
AC CMRR
TRIM
5pF TO 40pF
8
3
+
AD589
–
R1
17.8kΩ
3V
+
–
3V
R1
17.4kΩ
R2
32.4Ω
1%
3
8
1/2
2
OP284
1
VOUT =
D
4096 (5V)
4
R4
100kΩ
1%
00293-054
In many single-supply applications, the need for a 2.5 V reference
often arises. Many commercially available monolithic 2.5 V
references require at least a minimum operating supply of 4 V.
The problem is exacerbated when the minimum operating
supply voltage is 3 V. The circuit illustrated in Figure 53 is an
example of a 2.5 V reference that operates from a single 3 V
supply. The circuit takes advantage of the OP284 rail-to-rail
input/output voltage ranges to amplify an AD589 1.235 V
output to 2.5 V.
RP2
1kΩ
3V
5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL
2.5 V REFERENCE FROM A 3 V SUPPLY
VIN
One measure of the performance of a voltage reference is its
capacity to recover from sudden changes in load current. While
sourcing a steady-state load current of 1 mA, this circuit recovers
to 0.01% of the programmed output voltage in 1.5 μs for a total
change in load current of ±1 mA.
00293-053
Resistor networks should be used in this circuit for R2 and R3
because they exhibit the necessary relative tolerance matching for
good performance. Matched networks also exhibit tight relative
resistor temperature coefficients for good circuit temperature
stability. Trimming Potentiometer P1 is used for optimum dc
CMR adjustment, and C1 is used to optimize ac CMR. With the
circuit values as shown, Circuit CMR is better than 80 dB over the
frequency range of 20 Hz to 20 kHz. Circuit referred-to-input
(RTI) noise in the 0.1 Hz to 10 Hz band is an impressively low
0.45 μV p-p. Resistor RP1 and Resistor RP2 serve to protect the
OP284 inputs against input overvoltage abuse. Capacitor C2 can
be included to the limit circuit bandwidth and, therefore, wide
bandwidth noise in sensitive applications. The value of this
capacitor should be adjusted, depending on the required closedloop bandwidth of the circuit. The R4 to C2 time constant creates
a pole at a frequency equal to
Figure 54. 5 V Only, 12-Bit DAC Swings Rail-to-Rail
In this application, the OP284 serves two functions. First, it
buffers the high output impedance of the DAC VREF pin, which
is on the order of 10 kΩ. The op amp provides a low impedance
output to drive any following circuitry.
Second, the op amp amplifies the output signal to provide a railto-rail output swing. In this particular case, the gain is set to 4.1
so that the circuit generates a 5 V output when the DAC output
is at full scale. If other output voltage ranges are needed, such as
0 V ≤ VOUT ≤ 4.095 V, the gain can be easily changed by adjusting
the values of R2 and R3.
Rev. J | Page 17 of 24
OP184/OP284/OP484
HIGH-SIDE CURRENT MONITOR
5V
R
Monitor Output = R2 ×  SENSE  × I L
 R1 
For the element values shown, the transfer characteristic of the
monitor output is 2.5 V/A.
RSENSE
0.1Ω
1/2
VIN
100mV p-p
OP284
VOUT
RS
50Ω
CS
100nF
Figure 56. Snubber Network Compensates for Capacitive Load
The first step is to determine the value of Resistor RS. A good
starting value is 100 Ω (typically, the optimum value is less than
100 Ω). This value is reduced until the small-signal transient
response is optimized. Next, CS is determined; 10 μF is a good
starting point. This value is reduced to the smallest value for
acceptable performance (typically, 1 μF). For the case of a 10 nF
load capacitor on the OP284, the optimal snubber network is
a 20 Ω in series with 1 μF. The benefit is immediately apparent,
as shown in the scope photo in Figure 57. The top trace was taken
with a 1 nF load, and the bottom trace was taken with the 50 Ω,
100 nF snubber network in place. The amount of overshoot and
ringing is dramatically reduced. Table 7 shows a few sample
snubber networks for large load capacitors.
3V
3V
R1
100Ω
3
OP284
2
S
5.49µs
DLY
0.1µF
100
90
8
1/2
1nF LOAD
ONLY
1
4
G
D
SNUBBER
IN
CIRCUIT
Figure 55. High-Side Load Current Monitor
10
0%
50mV 50mV
CAPACITIVE LOAD DRIVE CAPABILITY
The OP284 exhibits excellent capacitive load driving capabilities.
It can drive up to 1 nF, as shown in Figure 30. Even though the
device is stable, a capacitive load does not come without penalty in
bandwidth. The bandwidth is reduced to less than 1 MHz for loads
greater than 2 nF. A snubber network on the output does not
increase the bandwidth, but it does significantly reduce the amount
of overshoot for a given capacitive load.
B
W
2µs
Figure 57. Overshoot and Ringing Are Reduced by Adding a Snubber
Network in Parallel with the 1 nF Load
Table 7. Snubber Networks for Large Capacitive Loads
Load Capacitance (CL)
1 nF
10 nF
100 nF
A snubber consists of a series R-C network (RS, CS), as shown in
Figure 56, connected from the output of the device to ground.
This network operates in parallel with the load capacitor, CL, to
provide the necessary phase lag compensation. The value of the
resistor and capacitor is best determined empirically.
Rev. J | Page 18 of 24
Snubber Network (RS, CS)
50 Ω, 100 nF
20 Ω, 1 µF
5 Ω, 10 µF
00293-057
R2
2.49kΩ
00293-055
M1
SI9433
CL
1nF
IL
3V
MONITOR
OUTPUT
0.1µF
00293-056
In the design of power supply control circuits, a great deal of design
effort is focused on ensuring the long-term reliability of a pass
transistor over a wide range of load current conditions. As a result,
monitoring and limiting device power dissipation is of prime
importance in these designs. The circuit shown in Figure 55 is
an example of a 3 V, single-supply, high-side current monitor that
can be incorporated into the design of a voltage regulator with
fold-back current limiting or a high current power supply with
crowbar protection. This design uses an OP284 rail-to-rail input
voltage range to sense the voltage drop across a 0.1 Ω current shunt.
A P-channel MOSFET, used as the feedback element in the circuit,
converts the differential input voltage of the op amp into a current.
This current is applied to R2 to generate a voltage that is a linear
representation of the load current. The transfer equation for the
current monitor is given by
OP184/OP284/OP484
LOW DROPOUT REGULATOR WITH CURRENT
LIMITING
For this example, because VOUT of 4.5 V with VOUT2 = 2.5 V requires
a U1B gain of 1.8 times, R3 and R2 are chosen for a ratio of 1.2:1 or
10.0 k Ω:8.06 kΩ (using closest 1% values). Note that for the lowest
VOUT dc error, R2||R3 should be maintained equal to R1 (as in
this example), and the R2 to R3 resistors should be stable, close
tolerance metal film types. The table in Figure 58 summarizes
R1 to R3 values for some popular voltages. However, note that,
in general, the output can be anywhere between VOUT2 and the
12 V maximum rating of Q1.
Many circuits require stable, regulated voltages relatively close
in potential to an unregulated input source. This low dropout
type of regulator is readily implemented with a rail-to-rail output
op amp, such as the OP284, because the wide output swing allows
easy drive to a low saturation voltage pass device. Furthermore,
it is particularly useful when the op amp also employs a rail-torail input feature because this factor allows it to perform highside current sensing for positive rail current limiting. Typical
examples are voltages developed from 3 V to 9 V range system
sources or anywhere that low dropout performance is required
for power efficiency. This 4.5 V example works from 5 V nominal
sources with worst-case levels down to 4.6 V or less. Figure 58
shows such a regulator set up, using an OP284 plus a low RDS(ON),
P-channel MOSFET pass device. Part of the low dropout performance of this circuit is provided by Q1, which has a rating of 0.11
Ω with a gate drive voltage of only 2.7 V. This relatively low gate
drive threshold allows operation of the regulator on supplies as
low as 3 V without compromising overall performance.
While the low voltage saturation characteristic of Q1 is a key part
of the low dropout, another component is a low current sense comparison threshold with good dc accuracy. Here, this is provided by
Current Sense Amplifier U1A, which is provided by a 20 mV
reference from the 1.235 V, AD589 Reference Diode D2, and the
R7 to R8 divider. When the product of the output current and the
RS value match this voltage threshold, the current control loop is
activated, and U1A drives the Q1 gate through D1. This causes the
overall circuit operation to enter current mode control with a
current limit, ILIMIT, defined as
 VR ( D2 )  R7 

I LIMIT = 


 RS  R7 + R8 
The main voltage control loop operation of the circuit is
provided by U1B, half of the OP284. This voltage control
amplifier amplifies the 2.5 V reference voltage produced by
Three Terminal U2, a REF192. The regulated output voltage,
VOUT, is then
R2 
VOUT = VOUT 2 1 +

 R3 
C4
0.1µF
RS
0.05Ω
Q1
SI9433DY
+VS
VS > VOUT + 0.1V
R6
4.99kΩ
R7
4.99kΩ
D2
AD589
3
U1A
OP284
8
1
R5
22.1kΩ
D1
1N4148
2
R8
301kΩ
4
R4
2.21kΩ
C1
0.01µF
C5
0.01µF
R9
27.4kΩ
6
7
C2
0.1µF
VC
OPTIONAL
ON/OFF CONTROL INPUT
CMOS HI (OR OPEN) = ON
LO = OFF
2
5
R11
1kΩ
R1
4.53kΩ
U2
REF192
6
VOUT2
2.5V
3
4
R10
1kΩ
C2
1µF
U1B
OP284
VOUT
5.0V
R3
10kΩ 4.5V
3.3V
3.0V
R2
8.06kΩ
OUTPUT TABLE
R1kΩ R2kΩ
4.99
10.0
4.53
8.08
2.43
3.24
1.69
2.00
VIN COMMON
VOUT =
4.5V @ 350mA
(SEE TABLE)
R3kΩ
10.0
10.0
10.0
10.0
C6
10µF
VOUT COMMON
Figure 58. Low Dropout Regulator with Current Limiting\
Rev. J | Page 19 of 24
00293-058
D3
1N4148
OP184/OP284/OP484
Performance of the circuit is excellent. For the 4.5 V output
version, the measured dc output change for a 225 mA load
change was on the order of a few microvolts, while the dropout
voltage at this same current level was about 30 mV. The current
limit, as shown in Figure 58, is 400 mA, allowing the circuit to
be used at levels up to 300 mA or more. While the Q1 device can
actually support currents of several amperes, a practical current
rating takes into account the 2.5 W, 25°C dissipation of the
8-lead SOIC device. Because a short-circuit current of 400 mA
at an input level of 5 V causes a 2 W dissipation in Q1, other input
conditions must be considered carefully in terms of potential
overheating of Q1. Of course, if higher powered devices are used
for Q1, this circuit can support outputs of tens of amperes as
well as the higher VOUT levels already noted.
The circuit shown can either be used as a standard low dropout
regulator, or it can be used with on/off control. By driving Pin 3
of U2 with the optional logic control signal, VC, the output is
switched between on and off. Note that when the output is off
in this circuit, it is still active (that is, not an open circuit). This
is because the off state simply reduces the voltage input to R1,
leaving the U1A/U1B amplifiers and Q1 still active.
When the on/off control is used, Resistor R10 should be used
with U2 to speed on/off switching and to allow the output of the
circuit to settle to a nominal zero voltage. Component D3 and
Component R11 also aid in speeding up the on/off transition by
providing a dynamic discharge path for C2. Off/on transition
time is less than 1 ms, while the on/off transition is longer, but
less than 10 ms.
3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH
FALSE GROUND
To process signals in a single-supply system, it is often best to use
a false ground biasing scheme. A circuit that uses this approach is
shown in Figure 59. In this circuit, a false ground circuit biases
an active notch filter used to reject 50 Hz/60 Hz power line
interference in portable patient monitoring equipment.
Notch filters are commonly used to reject power line frequency
interference that often obscures low frequency physiological
signals, such as heart rates, blood pressure readings, EEGs, and
EKGs. This notch filter effectively squelches 60 Hz pickup at a
Filter Q of 0.75. Substituting 3.16 kΩ resistors for the 2.67 kΩ
resistor in the twin-T section (R1 through R5) configures the
active filter to reject 50 Hz interference.
R2
2.67kΩ
3V
R1
2.67kΩ
4
2
A1
VIN
C1
1µF
3
C2
1µF
5
1
A2
11
R3
2.67kΩ
R6
10kΩ
C3
2µF
(1µF × 2)
R4
2.67kΩ
R5
1.33kΩ
(2.68kΩ ÷ 2)
7
VO
6
R8
1kΩ
R7
1kΩ
R11
10kΩ
Q = 0.75
C5
0.03µF
3V
R9
20kΩ
R12
150Ω
9
A3
8
10
C4
1µF
R10
20kΩ
NOTE: FOR 50Hz APPLICATIONS
CHANGE R1, R2, R3, AND R4 TO 3.1kΩ
AND R5 TO 1.58kΩ (3.16kΩ ÷ 2).
C6
1µF
1.5V
A1, A2, A3 = OP484
00293-059
Obviously, it is desirable to keep this comparison voltage small
because it becomes a significant portion of the overall dropout
voltage. Here, the 20 mV reference is higher than the typical
offset of the OP284 but is still reasonably low as a percentage
of VOUT (<0.5%). In adapting the limiter for other ILIMIT levels,
Sense Resistor RS should be adjusted along with R7 to R8, to
maintain this threshold voltage between 20 mV and 50 mV.
Figure 59. A 3 V Single-Supply, 50Hz to 60 Hz Active Notch Filter
with False Ground
Amplifier A3 is the heart of the false ground bias circuit. It buffers
the voltage developed at R9 and R10 and is the reference for the
active notch filter. Because the OP484 exhibits a rail-to-rail input
common-mode range, R9 and R10 are chosen to split the 3 V
supply symmetrically. An in-the-loop compensation scheme is
used around the OP484 that allows the op amp to drive C6, a
1 μF capacitor, without oscillation. C6 maintains a low impedance
ac ground over the operating frequency range of the filter.
The filter section uses an OP484 in a Twin-T configuration whose
frequency selectivity is very sensitive to the relative matching of
the capacitors and resistors in the twin-T section. Mylar is the
material of choice for the capacitors, and the relative matching
of the capacitors and resistors determines the pass band symmetry
of the filter. Using 1% resistors and 5% capacitors produces satisfactory results.
Rev. J | Page 20 of 24
OP184/OP284/OP484
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
4
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 60. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
P-Suffix
Dimensions shown in inches and (millimeters)
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
8
1
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 61. 14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
P-Suffix
Dimensions shown in inches and (millimeters)
Rev. J | Page 21 of 24
070606-A
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
OP184/OP284/OP484
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 62. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
S-Suffix
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 63. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
S-Suffix
Dimensions shown in millimeters and (inches)
Rev. J | Page 22 of 24
060606-A
4.00 (0.1575)
3.80 (0.1496)
OP184/OP284/OP484
ORDERING GUIDE
Model1
OP184ES
OP184ES-REEL
OP184ES-REEL7
OP184ESZ
OP184ESZ-REEL
OP184ESZ-REEL7
OP184FS
OP184FS-REEL
OP184FS–REEL7
OP184FSZ
OP184FSZ-REEL
OP184FSZ-REEL7
OP284EP
OP284EPZ
OP284ES
OP284ES-REEL
OP284ES-REEL7
OP284ESZ
OP284ESZ-REEL
OP284ESZ-REEL7
OP284FS
OP284FS-REEL
OP284FS-REEL7
OP284FSZ
OP284FSZ-REEL
OP284FSZ-REEL7
OP484ES
OP484ES-REEL
OP484ESZ
OP484ESZ-REEL
OP484FPZ
OP484FS
OP484FS-REEL
OP484FS-REEL7
OP484FSZ
OP484FSZ-REEL
OP484FSZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead PDIP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. J | Page 23 of 24
Package Option
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
P-Suffix (N-8)
P-Suffix (N-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
P-Suffix (N-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
OP184/OP284/OP484
NOTES
©1996–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00293-0-4/11(J)
Rev. J | Page 24 of 24