Single-Supply, Rail-to-Rail, Low Power, FET Input Op Amp AD820 PIN CONFIGURATIONS True single-supply operation Output swings rail-to-rail Input voltage range extends below ground Single-supply capability from 5 V to 30 V Dual-supply capability from ±2.5 V to ±15 V Excellent load drive Capacitive load drive up to 350 pF Minimum output current of 15 mA Excellent ac performance for low power 800 μA maximum quiescent current Unity-gain bandwidth: 1.8 MHz Slew rate of 3 V/μs Excellent dc performance 800 μV maximum input offset voltage 2 μV/°C typical offset voltage drift 25 pA maximum input bias current Low noise: 13 nV/√Hz @ 10 kHz NULL 1 NC 8 AD820 –IN 2 7 +VS +IN 3 6 VOUT 5 NULL –VS 4 TOP VIEW (Not to Scale) 00873-001 FEATURES NC = NO CONNECT Figure 1. 8-Lead PDIP NC 1 NC –IN 2 7 +VS +IN 3 6 VOUT 5 NC –VS 4 TOP VIEW (Not to Scale) NC = NO CONNECT 00873-002 8 AD820 Figure 2. 8-Lead SOIC_N and 8-Lead MSOP APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters 12-bit to 14-bit data acquisition systems Medical instrumentation Low power references and regulators GENERAL DESCRIPTION Offset voltage of 800 μV maximum, offset voltage drift of 2 μV/°C, typical input bias currents below 25 pA, and low input voltage noise provide dc precision with source impedances up to 1 GΩ. 1.8 MHz unity gain bandwidth, −93 dB THD at 10 kHz, and 3 V/μs slew rate are provided for a low supply current of 800 μA. The AD820 drives up to 350 pF of direct capacitive load and provides a minimum output current of 15 mA. This allows the amplifier to handle a wide range of load conditions. This combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. The AD820 is available in two performance grades. The A and B grades are rated over the industrial temperature range of −40°C to +85°C. The AD820 is offered in three 8-lead package options: plastic DIP (PDIP), surface mount (SOIC) and (MSOP). 1V 1V 20µs 100 90 10 0% 1V 00873-004 The AD820 is a precision, low power FET input op amp that can operate from a single supply of 5 V to 36 V, or dual supplies of ±2.5 V to ±18 V. It has true single-supply capability, with an input voltage range extending below the negative rail, allowing the AD820 to accommodate input signals below ground in the single-supply mode. Output voltage swing extends to within 10 mV of each rail, providing the maximum output dynamic range. Figure 3. Gain-of-2 Amplifier; VS = 5 V, 0 V, VIN = 2.5 V Sine Centered at 1.25 V Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved. AD820 TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 16 Applications ....................................................................................... 1 Input Characteristics .................................................................. 16 Pin Configurations ........................................................................... 1 Output Characteristics............................................................... 17 General Description ......................................................................... 1 Single-Supply Half-Wave and Full-Wave Rectifiers .............. 17 Revision History ............................................................................... 2 4.5 V Low Dropout, Low Power Reference............................. 18 Specifications..................................................................................... 3 Low Power, 3-Pole, Sallen Key Low-Pass Filter ...................... 18 Absolute Maximum Ratings ............................................................ 9 Offset Voltage Adjustment ............................................................ 19 Thermal Resistance ...................................................................... 9 Outline Dimensions ....................................................................... 20 ESD Caution .................................................................................. 9 Ordering Guide .......................................................................... 21 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 3/11—Rev. G to Rev. H Changes to Figure 43 ...................................................................... 18 2/10—Rev. F to Rev. G Changes to Features Section............................................................ 1 Changes to Open-Loop Gain Parameter ....................................... 3 Changes to Input Voltage Parameter ............................................. 9 Updated Outline Dimensions ....................................................... 20 11/08—Rev. E to Rev. F Added 8-Lead MSOP ......................................................... Universal Changes to Features Section, Figure 2 Caption, and General Description Section .......................................................................... 1 Changes to Settling Time Parameter, Common-Mode Voltage Range Parameter, and Power Supply Rejection Parameter in Table 1 ................................................................................................ 3 Changes to Settling Time Parameter, Common-Mode Voltage Range Parameter, and Power Supply Rejection Parameter in Table 2 ................................................................................................ 5 Changes to Settling Time Parameter, Common-Mode Voltage Range Parameter, and Power Supply Rejection Parameter in Table 3 ................................................................................................ 7 Changes to Table 4 ............................................................................ 9 Added Thermal Resistance Section ............................................... 9 Added Table 5; Renumbered Sequentially .....................................9 Changes to Figure 26...................................................................... 13 Changes to Figure 27...................................................................... 14 Changed Application Notes Section to Applications Information Section ....................................................................... 16 Changes to Figure 40, Figure 41, and Figure 42 ......................... 17 Changes to Figure 44...................................................................... 18 Moved Offset Voltage Adjustment Section ................................. 19 Updated Outline Dimensions ....................................................... 20 Added Figure 49; Renumbered Sequentially .............................. 21 Changes to Ordering Guide .......................................................... 21 2/07—Rev. D to Rev. E Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 21 Changes to the Ordering Guide ................................................... 22 5/02—Rev. C to Rev. D Change to SOIC Package (R-8) Drawing .................................... 15 Edits to Features.................................................................................1 Edits to Product Description ...........................................................1 Delete Specifications for AD820A-3 V ...........................................5 Edits to Ordering Guide ...................................................................6 Edits to Typical Performance Characteristics ................................8 Rev. H | Page 2 of 24 AD820 SPECIFICATIONS VS = 0 V, 5 V @ TA = 25°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted. Table 1. Parameter DC PERFORMANCE Initial Offset Maximum Offset over Temperature Offset Drift Input Bias Current At TMAX Input Offset Current At TMAX Open-Loop Gain Conditions Min 0.1 0.5 2 2 0.5 2 0.5 VCM = 0 V to 4 V VOUT = 0.2 V to 4 V RL = 100 kΩ 400 400 80 80 15 10 TMIN to TMAX RL = 10 kΩ TMIN to TMAX RL = 1 kΩ TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time To 0.1% To 0.01% INPUT CHARACTERISTICS Common-Mode Voltage Range 1 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode AD820A Typ Max RL = 10 kΩ to 2.5 V VOUT = 0.25 V to 4.75 V VOUT p-p = 4.5 V Min 0.8 1.2 25 5 20 1000 500 400 80 80 15 10 150 30 AD820B Typ Max Unit 0.1 0.5 2 2 0.5 2 0.5 mV mV μV/°C pA nA pA nA 0.4 0.9 10 2.5 10 1000 V/mV V/mV V/mV V/mV V/mV V/mV 150 30 2 25 21 16 13 2 25 21 16 13 μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 18 0.8 18 0.8 fA p-p fA/√Hz −93 −93 dB 1.8 210 3 1.8 210 3 MHz kHz V/μs 1.4 1.8 1.4 1.8 μs μs VOUT = 0.2 V to 4.5 V VCM = 0 V to 2 V −0.2 66 66 +4 80 1013||0.5 1013||2.8 Rev. H | Page 3 of 24 –0.2 72 66 +4 80 V dB dB 1013||0.5 1013||2.8 Ω||pF Ω||pF AD820 Parameter OUTPUT CHARACTERISTICS Output Saturation Voltage2 VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX Operating Output Current TMIN to TMAX Short-Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Power Supply Rejection TMIN to TMAX Conditions Min AD820A Typ Max ISINK = 20 μA 5 ISOURCE = 20 μA 10 ISINK = 2 mA 40 ISOURCE = 2 mA 80 ISINK = 15 mA 300 ISOURCE = 15 mA 800 Min 7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12 5 10 40 80 300 800 70 70 620 80 mV mV mV mV mV mV mV mV mV mV mV mV mA mA mA pF 800 μA dB dB 1 25 350 800 66 66 620 80 Unit 7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12 25 350 TMIN to TMAX V+ = 5 V to 15 V AD820B Typ Max This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. H | Page 4 of 24 AD820 VS = ±5 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted. Table 2. Parameter DC PERFORMANCE Initial Offset Maximum Offset over Temperature Offset Drift Input Bias Current At TMAX Input Offset Current At TMAX Open-Loop Gain Conditions Min TMIN to TMAX RL = 10 kΩ TMIN to TMAX RL = 1 kΩ TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time To 0.1% To 0.01% INPUT CHARACTERISTICS Common-Mode Voltage Range1 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode 0.1 0.5 2 2 0.5 2 0.5 VCM = −5 V to +4 V VOUT = −4 V to +4 V RL = 100 kΩ AD820A Typ 400 400 80 80 20 10 RL = 10 kΩ VOUT = ±4.5 V VOUT p-p = 9 V Max Min 0.8 1.5 0.3 0.5 2 2 0.5 2 0.5 25 5 20 1000 400 400 80 80 20 10 150 30 AD820B Typ Max Unit 0.4 1 mV mV μV/°C pA nA pA nA 10 2.5 10 1000 V/mV V/mV V/mV V/mV V/mV V/mV 150 30 2 25 21 16 13 2 25 21 16 13 μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 18 0.8 18 0.8 fA p-p fA/√Hz −93 −93 dB 1.9 105 3 1.8 105 3 MHz kHz V/μs 1.4 1.8 1.4 1.8 μs μs VOUT = 0 V to ±4.5 V VCM = −5 V to +2 V −5.2 66 66 +4 80 1013||0.5 1013||2.8 Rev. H | Page 5 of 24 −5.2 72 66 80 +4 V dB dB 1013||0.5 1013||2.8 Ω||pF Ω||pF AD820 Parameter OUTPUT CHARACTERISTICS Output Saturation Voltage2 VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX Operating Output Current TMIN to TMAX Short-Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Power Supply Rejection TMIN to TMAX Conditions Min AD820A Typ ISINK = 20 μA 5 ISOURCE = 20 μA 10 ISINK = 2 mA 40 ISOURCE = 2 mA 80 ISINK = 15 mA 300 ISOURCE = 15 mA 800 Max Min 7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12 5 10 40 80 300 800 70 70 Max Unit 7 10 14 20 55 80 110 160 500 1000 1500 1900 mV mV mV mV mV mV mV mV mV mV mV mV mA mA mA pF 800 μA dB dB 15 12 30 350 TMIN to TMAX V+ = 5 V to 15 V AD820B Typ 650 80 1 30 350 800 70 70 620 80 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. H | Page 6 of 24 AD820 VS = ±15 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted. Table 3. Parameter DC PERFORMANCE Initial Offset Maximum Offset over Temperature Offset Drift Input Bias Current At TMAX Input Offset Current At TMAX Open-Loop Gain Conditions VOUT = −10 V to +10 V RL = 100 kΩ RL = 10 kΩ TMIN to TMAX RL = 1 kΩ AD820A Typ 0.4 0.5 2 2 40 0.5 2 0.5 VCM = 0 V VCM = −10 V VCM = 0 V TMIN to TMAX TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity Gain Frequency Full Power Response Slew Rate Settling Time To 0.1% To 0.01% INPUT CHARACTERISTICS Common-Mode Voltage Range1 TMIN to TMAX CMRR TMIN to TMAX Input Impedance Differential Common Mode Min 500 500 100 100 30 20 RL = 10 kΩ VOUT = ±10 V VOUT p-p = 20 V Max Min 2 3 0.3 0.5 2 2 40 0.5 2 0.5 25 5 20 2000 500 500 100 100 30 20 500 45 AD820B Typ Max Unit 1.0 2 mV mV μV/°C pA pA nA pA nA 10 2.5 10 2000 V/mV V/mV V/mV V/mV V/mV V/mV 500 45 2 25 21 16 13 2 25 21 16 13 μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 18 0.8 18 0.8 fA p-p fA/√Hz −85 −85 dB 1.9 45 3 1.9 45 3 MHz kHz V/μs 4.1 4.5 4.1 4.5 μs μs VOUT = 0 V to ±10 V VCM = –15 V to +12 V −15.2 70 70 +14 80 1013||0.5 1013||2.8 Rev. H | Page 7 of 24 −15.2 74 74 90 +14 V dB dB 1013||0.5 1013||2.8 Ω||pF Ω||pF AD820 Parameter OUTPUT CHARACTERISTICS Output Saturation Voltage2 VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX Operating Output Current TMIN to TMAX Short-Circuit Current Capacitive Load Drive POWER SUPPLY Quiescent Current Power Supply Rejection TMIN to TMAX Conditions Min AD820A Typ ISINK = 20 μA 5 ISOURCE = 20 μA 10 ISINK = 2 mA 40 ISOURCE = 2 mA 80 ISINK = 15 mA 300 ISOURCE = 15 mA 800 Max Min 7 10 14 20 55 80 110 160 500 1000 1500 1900 20 15 5 10 40 80 300 800 70 70 Max Unit 7 10 14 20 55 80 110 160 500 1000 1500 1900 mV mV mV mV mV mV mV mV mV mV mV mV mA mA mA pF 900 μA dB dB 20 15 45 350 TMIN to TMAX V+ = 5 V to 15 V AD820B Typ 700 80 1 45 350 900 70 70 700 80 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. H | Page 8 of 24 AD820 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Internal Power Dissipation 8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Input Voltage1 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range 8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Operating Temperature Range AD820A/AD820B Lead Temperature(Soldering, 60 sec) 1 See Input Characteristics section. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating ±18 V Table 5. Thermal Resistance 1.6 W 1.0 W 0.8 W ((V+) + 0.2 V) to (V−) − 20 V Indefinite ±30 V Package Type 8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) −65°C to +125°C −65°C to +150°C −65°C to +150°C −40°C to +85°C 260°C θJA 90 160 190 Unit °C/W °C/W °C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. H | Page 9 of 24 AD820 TYPICAL PERFORMANCE CHARACTERISTICS 50 5 VS = 0V, 5V INPUT BIAS CURRENT (pA) NUMBER OF UNITS 40 30 20 0 VS = 0V, +5V AND ±5V VS = ±5V –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 –5 –5 0.5 00873-008 0 –0.5 00873-005 10 –4 –3 OFFSET VOLTAGE (mV) –2 –1 0 1 2 3 4 5 COMMON-MODE VOLTAGE (V) Figure 4. Typical Distribution of Offset Voltage (248 Units) Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = +5 V, 0 V and VS = ±5 V 48 1k VS = ±5V VS = ±15V INPUT BIAS CURRENT (pA) 40 % IN BIN 32 24 16 100 10 1 –8 –6 –4 –2 0 2 4 6 8 0.1 –16 10 00873-009 0 –10 00873-006 8 –12 OFFSET VOLTAGE DRIFT (µV/ºC) –8 –4 0 4 8 12 16 COMMON-MODE VOLTAGE (V) Figure 5. Typical Distribution of Offset Voltage Drift (120 Units) Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = ±15 V 100k 50 45 INPUT BIAS CURRENT (pA) 10k 35 30 25 20 15 1k 100 10 5 0 0 1 2 3 4 5 6 7 8 9 0.1 20 10 00873-010 1 10 00873-007 NUMBER OF UNITS 40 40 60 80 100 120 140 TEMPERATURE (ºC) INPUT BIAS CURRENT (pA) Figure 6. Typical Distribution of Input Bias Current (213 Units) Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V Rev. H | Page 10 of 24 AD820 VS = ±15V 1M VS = 0V, +5V 100k 10k 100 1k POSITIVE RAIL RL = 20kΩ POSITIVE RAIL –20 RL = 100kΩ 0 NEGATIVE RAIL 60 120 240 300 Figure 13. Input Error Voltage vs. Output Voltage Within 300 mV of Either Supply Rail for Various Resistive Loads; VS = ±5 V 1k VS = ±15V RL = 100kΩ 1M VS = 0V, +5V VS = ±15V RL = 10kΩ VS = 0V, +5V 100k VS = ±15V VS = 0V, +5V –40 –20 0 20 40 60 80 100 120 00873-012 RL = 600Ω 100 10 00873-015 INPUT VOLTAGE NOISE (nV/√Hz) 10M 1 1 140 10 100 1k 10k FREQUENCY (Hz) TEMPERATURE (ºC) Figure 11. Open-Loop Gain vs. Temperature Figure 14. Input Voltage Noise vs. Frequency 300 –40 RL = 10kΩ ACL = –1 –50 200 –60 100 RL = 10kΩ RL = 100kΩ THD (dB) 0 –70 –80 VS = ±15V; VOUT = 20V p-p –100 –90 VS = ±5V; VOUT = 9V p-p RL = 600Ω –300 –16 –12 –8 –4 0 4 8 12 VS = 0V, +5V; VOUT = 4.5V p-p –100 00873-013 –200 –110 100 16 OUTPUT VOLTAGE (V) 1k 00873-016 INPUT ERROR VOLTAGE (µV) 180 OUTPUT VOLTAGE FROM RAILS (mV) Figure 10. Open-Loop Gain vs. Load Resistance OPEN-LOOP GAIN (V/V) NEGATIVE RAIL –40 LOAD RESISTANCE (Ω) 10k –60 NEGATIVE RAIL POSITIVE RAIL 0 100k 10k RL = 2kΩ 20 00873-014 INPUT ERROR VOLTAGE (µV) 40 00873-011 OPEN-LOOP GAIN (V/V) 10M 10k FREQUENCY (Hz) Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads Rev. H | Page 11 of 24 Figure 15. Total Harmonic Distortion vs. Frequency 100k AD820 100 100 80 80 100 60 GAIN 40 40 20 20 0 0 RL = 2kΩ CL = 100pF 70 60 100 1k 10k 100k 1M –20 10M FREQUENCY (Hz) VS = ±15V 40 30 20 0 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 16. Open-Loop Gain and Phase Margin vs. Frequency Figure 19. Common-Mode Rejection vs. Frequency 5 COMMON-MODE ERROR VOLTAGE (mV) ACL = +1 VS = ±15V 100 10 1 0.01 100 00873-018 0.1 1k 10k 100k 1M 4 NEGATIVE RAIL 3 2 +25ºC +125ºC 1 –55ºC FREQUENCY (Hz) +125ºC –55ºC 0 –1 10M POSITIVE RAIL 00873-021 1k 0 1 3 2 COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V) Figure 17. Output Impedance vs. Frequency Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (VS − VCM) 16 1k OUTPUT SATURATION VOLTAGE (mV) 12 1% 8 4 0.1% 0 ERROR 0.01% –4 –8 1% 00873-019 –12 –16 0 1 2 3 4 100 VS – VOH 1 0.001 5 SETTLING TIME (µs) VOL – VS 10 00873-022 OUTPUT IMPEDANCE (Ω) VS = 0V, +5V 50 10 00873-017 –20 10 80 00873-020 PHASE MARGIN (DEGREES) 60 OUTPUT SWING FROM 0 TO ±V OPEN-LOOP GAIN (dB) PHASE COMMON-MODE REJECTION (dB) 90 0.01 0.1 1 10 LOAD CURRENT (mA) Figure 18. Output Swing and Error vs. Settling Time Figure 21. Output Saturation Voltage vs. Load Current Rev. H | Page 12 of 24 100 AD820 1k 120 ISINK = 10mA 100 ISOURCE = 1mA ISINK = 1mA ISOURCE = 10µA 10 ISINK = 10µA 1 –60 –40 –20 0 20 40 60 80 100 90 80 70 +PSRR 60 –PSRR 50 40 30 20 10 0 10 140 120 100 00873-026 POWER SUPPLY REJECTION (dB) 110 00873-023 OUTPUT SATURATION VOLTAGE (mV) ISOURCE = 10mA 100 TEMPERATURE (ºC) 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 22. Output Saturation Voltage vs. Temperature Figure 25. Power Supply Rejection vs. Frequency 80 30 25 –OUT VS = ±15V 40 VS = 0V, +5V + – 30 20 VS = 0V, +5V 10 5 –40 –20 0 20 40 60 80 100 120 0 10k 140 TEMPERATURE (ºC) T = +125ºC 700 T = +25ºC 600 T = –55ºC 500 400 300 200 00873-025 100 0 8 12 16 20 24 100k 1M Figure 26. Large Signal Frequency Response 800 4 VS = 0V, +5V FREQUENCY (Hz) Figure 23. Short-Circuit Current Limit vs. Temperature 0 VS = ±15V 15 + 10 0 –60 QUIESCENT CURRENT (µA) 20 00873-027 50 OUTPUT VOLTAGE (V) VS = ±15V 60 00873-024 SHORT-CIRCUIT CURRENT LIMIT (mA) RL = 2kΩ 70 28 32 36 TOTAL SUPPLY VOLTAGE (V) Figure 24. Quiescent Current vs. Supply Voltage over Different Temperatures Rev. H | Page 13 of 24 10M AD820 5µs 5V +VS 100 90 0.01µF 3 + VIN – 7 + AD820 2 6 0.01µF – RL 100pF 00873-028 4 + VOUT – 10 0% 00873-031 –VS Figure 27. Unity-Gain Follower, Used for Figure 28 Through Figure 32 5V Figure 30. Large Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ 10µs 10mV 100 100 90 90 00873-032 10 0% 00873-029 10 0% 500ns Figure 28. 20 V, 25 kHz Sine Input; Unity-Gain Follower; RL = 600 Ω, VS = ±15 V 1V Figure 31. Small Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ 2µs 1V 100 100 90 90 Figure 29. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step 00873-033 10 GND 0% 00873-030 10 GND 0% 2µs Figure 32. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step Rev. H | Page 14 of 24 AD820 10kΩ +VS 20kΩ 0.01µF 2 + RL 100pF 3 00873-034 4 VOUT – – AD820 6 100pF RL + 4 Figure 35. Gain-of-2 Inverter, Used for Figure 36 and Figure 37 Figure 33. Unity-Gain Follower, Used for Figure 34 10mV 7 00873-035 AD820 6 – 2 7 + 3 VOUT – +VS 0.01µF VIN + VIN 1V 2µs 100 100 90 90 10 GND 0% 00873-037 00873-036 10 GND 0% 2µS Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step Centered 40 mV Above Ground Figure 36. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step, Centered −1.25 V Below Ground 10mV 2µs 100 90 10 00873-038 GND 0% Figure 37. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step, Centered 20 mV Below Ground Rev. H | Page 15 of 24 AD820 APPLICATIONS INFORMATION INPUT CHARACTERISTICS 1V In the AD820, N-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input commonmode voltage extends from 0.2 V below –VS to 1 V less than +VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figure 29 and Figure 32) and increased common-mode voltage error, as illustrated in Figure 20. 90 10 GND 0% 1V (a) 1V 90 10 GND 0% 1V (b) 5V AD820 + VOUT – Figure 38. (a) Response with RP = 0 Ω; VIN from 0 V to +VS (b) VIN = 0 V to +VS + 200 mV, VOUT = 0 V to +VS, RP = 49.9 kΩ INPUT VOLTAGE NOISE (µV rms) 100k 10k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. 1kHz 1k RESISTOR JOHNSON NOISE 100 10 10Hz 1 AMPLIFIER-GENERATED NOISE 0.1 10k 100k 1M 10M 100M 1G SOURCE IMPEDANCE (Ω) Figure 39. Total Noise vs. Source Impedance Rev. H | Page 16 of 24 00873-039 + VIN – RP – The AD820 is designed for 13 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure 14). This noise performance, along with the AD820 low input current and current noise, means that the AD820 contributes negligible noise for applications with source resistances greater than 10 kΩ and signal bandwidths greater than 1 kHz. This is illustrated in Figure 39. 10µs 100 +VS A current-limiting resistor should be used in series with the input of the AD820 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV, or if an input voltage is applied to the AD820 when ±VS = 0 V. The amplifier can be damaged if left in that condition for more than 10 seconds. A 1 kΩ resistor allows the amplifier to withstand up to 10 V of continuous overvoltage, and increases the input voltage noise by a negligible amount. Input voltages less than −VS are a completely different story. The amplifier can safely withstand input voltages 20 V below the negative supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. 1V 00873-040 Because the input stage uses N-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +VS − 0.4 V, the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7. 100 + The AD820 does not exhibit phase reversal for input voltages up to and including +VS. Figure 38a shows the response of an AD820 voltage follower to a 0 V to 5 V (+VS) square wave input. The input and output are superimposed. The output polarity tracks the input polarity up to +VS with no phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output waveform. For input voltages greater than +VS, a resistor in series with the AD820 positive input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 38b. 2µs 10G AD820 5 OUTPUT CHARACTERISTICS PI ) PF 4 NOISE GAIN (1+ The AD820 unique bipolar rail-to-rail output stage swings within 5 mV of the negative supply and 10 mV of the positive supply with no external resistive load. The approximate output saturation resistance of the AD820 is 40 Ω sourcing and 20 Ω sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 mA, the saturation voltage to the positive supply rail is 200 mV; when sinking 5 mA, the saturation voltage to the negative rail is 100 mV. 3 2 The open-loop gain characteristic of the amplifier changes as a function of resistive load, as shown in Figure 10 through Figure 13. For load resistances over 20 kΩ, the AD820 input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply. 1 300 1k 30k 10k + If the AD820 output is driven hard against the output saturation voltage, it recovers within 2 μs of the input returning to the linear operating region of the amplifier. – 00873-042 RF R1 Figure 41. Noise Gain vs. Capacitive Load Tolerance Figure 42 shows a possible configuration for extending capacitance load drive capability for a unity-gain follower. With these component values, the circuit drives 5000 pF with a 10% overshoot. +VS 0.01µF + VIN – 3 2 + 7 AD820 – 100Ω 0.01µF 4 –VS 2µs 6 20pF 20kΩ 100 + VOUT – 00873-043 Direct capacitive load interacts with the effective output impedance of the amplifier to form an additional pole in the amplifier feedback loop, which can cause excessive peaking on the pulse response or loss of stability. The worst case occurs when the amplifier is used as a unity-gain follower. Figure 40 shows AD820 pulse response as a unity-gain follower driving 350 pF. This amount of overshoot indicates approximately 20 degrees of phase margin—the system is stable, but is nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, are much less sensitive to capacitance load effects. Figure 41 is a plot of noise gain vs. the capacitive load that results in a 20 degree phase margin for the AD820. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. 20mV 3k CAPACITIVE LOAD FOR 20º PHASE MARGIN (pF) Figure 42. Extending Unity-Gain Follower Capacitive Load Capability Beyond 350 pF 90 SINGLE-SUPPLY HALF-WAVE AND FULL-WAVE RECTIFIERS 10 00873-041 0% Figure 40. Small Signal Response of AD820 as Unity-Gain Follower Driving 350 pF Capacitive Load An AD820 configured as a unity-gain follower and operated with a single supply can be used as a simple half-wave rectifier. The AD820 inputs maintain picoamp level input currents even when driven well below the negative supply. The rectifier puts that behavior to good use, maintaining an input impedance of over 1011 Ω for input voltages from 1 V from the positive supply to 20 V below the negative supply. The full- and half-wave rectifier shown in Figure 43 operates as follows: when VIN is above ground, R1 is bootstrapped through the unity-gain follower, A1, and the loop of Amplifier A2. This forces the inputs of A2 to be equal; thus, no current flows through R1 or R2, and the circuit output tracks the input. When VIN is below ground, the output of A1 is forced to ground. The Rev. H | Page 17 of 24 AD820 noninverting input of Amplifier A2 sees the ground level output of A1; therefore, A2 operates as a unity-gain inverter. The output at Node C is then a full-wave rectified version of the input. Node B is a buffered half-wave rectified version of the input. Input voltages up to ±18 V can be rectified, depending on the voltage supply used. R1 100kΩ R2 100kΩ 0.01µF 0.01µF A VIN – 7 7 – A2 3 6 A1 + 4 – 2 2 + 3 + 4 LOW POWER, 3-POLE, SALLEN KEY LOW-PASS FILTER +VS +VS AD820 6 AD820 With a 1 mA load, this reference maintains the 4.5 V output with a supply voltage down to 4.7 V. The amplitude of the recovery transient for a 1 mA to 10 mA step change in load current is under 20 mV, and settles out in a few microseconds. Output voltage noise is less than 10 μV rms in a 25 kHz noise bandwidth. + C FULL-WAVE RECTIFIED OUPUT – + B HALF-WAVE RECTIFIED OUPUT – A 100 90 The high input impedance of the AD820 makes it a good selection for active filters. High value resistors can be used to construct low frequency filters with capacitors much less than 1 μF. The AD820 picoamp level input currents contribute minimal dc errors. Figure 45 shows an example of a 10 Hz three-pole Sallen Key filter. The high value used for R1 minimizes interaction with signal source resistance. Pole placement in this version of the filter minimizes the Q associated with the two-pole section of the filter. This eliminates any peaking of the noise contribution of Resistor R1, Resistor R2, and Resistor R3, thus minimizing the inherent output voltage noise of the filter. C2 0.022µF +VS B + C R1 243kΩ VIN – 10 R2 243kΩ 0.01µF R3 243kΩ 3 C3 0.022µF 2 C1 0.022µF 0% 7 + 6 AD820 + VOUT – 0.01µF – 00873-045 4 –VS Figure 43. Single-Supply Half- and Full-Wave Rectifier 4.5 V LOW DROPOUT, LOW POWER REFERENCE 0 U2 AD820 4.5V OUTPUT 6 5V U1 AD680 4 4 – + 6 2.5V ± 10mV R1 100kΩ 3 R2 90kΩ (20kΩ) –40 –50 –60 –70 –80 –100 0.1 2 C2 0.1µF FILM 1 10 100 FREQUENCY (Hz) C3 10µF/25V Figure 45. 10 Hz Sallen Key Low-Pass Filter R3 100kΩ (25kΩ) REF COMMON 00873-046 2 C1 0.1µF –30 –90 7 3 –20 00873-047 2.5V OUTPUT –10 FILTER GAIN RESPONSE (dB) The rail-to-rail performance of the AD820 can be used to provide low dropout performance for low power reference circuits powered with a single low voltage supply. Figure 44 shows a 4.5 V reference using the AD820 and the AD680, a low power 2.5 V band gap reference. R2 and R3 set up the required gain of 1.8 to develop the 4.5 V output. R1 and C2 form a lowpass RC filter to reduce the noise contribution of the AD680. Figure 44. Single Supply 4.5 V Low Dropout Reference Rev. H | Page 18 of 24 1k AD820 OFFSET VOLTAGE ADJUSTMENT +VS 3 + 7 AD820 2 – 6 1 5 20kΩ 4 –VS Figure 46. Offset Null Rev. H | Page 19 of 24 00873-044 The offset voltage of the AD820 is low, so external offset voltage nulling is not usually required. Figure 46 shows the recommended technique for the AD820 packaged in plastic DIP. Adjusting offset voltage in this manner changes the offset voltage temperature drift by 4 μV/°C for every millivolt of induced offset. The null pins are not functional for the AD820 in the 8-lead SOIC and MSOP packages. AD820 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 47. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 48. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. H | Page 20 of 24 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD820 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 49. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD820AN AD820ANZ AD820AR AD820AR-REEL AD820AR-REEL7 AD820ARZ AD820ARZ-REEL AD820ARZ-REEL7 AD820ARMZ AD820ARMZ-RL AD820ARMZ-R7 AD820BR AD820BR-REEL AD820BRZ AD820BRZ-REEL AD820BRZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 Z = RoHS Compliant Part. Rev. H | Page 21 of 24 Branding A2L A2L A2L AD820 NOTES Rev. H | Page 22 of 24 AD820 NOTES Rev. H | Page 23 of 24 AD820 NOTES ©1996–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00873-0-3/11(H) Rev. H | Page 24 of 24