Preliminary Technical Data ADP1829, APD210X and ADP171X Reference Design FCDC 00059 FEATURES Seven Output Voltages: 3.6 V, 3.3 V,3.3l V 2.5 V, 1.8 V, 1.25 V, 0.9 V Output Current: 0.002 A to 3.0 A Input voltage: 10.8-13.2 V Ripple 2% ppk of Output Voltage Transient step ±5%, 50% max load ADP1829, APD210X AND ADP171X REFERENCE DESIGN DESCRIPTION This ADP1829, APD210X and ADP171X Reference Design uses 10.8 V to 13.2 V for the input voltage. The output voltages and currents are as follows: • VOUT1 = 3.6 V with a maximum output current of 3.0 A for intermediate rail, • VOUT2 = 3.3 V with a maximum output current of 0.6 A for DCD, • VOUT3 = 3.3 V with a maximum output current of 0.02 A for DCD, • VOUT4 = 2.5 V with a maximum output current of 0.4 A for DCD, • VOUT5 = 1.8 V with a maximum output current of 0.9 A for DCD, • VOUT6 = 1.25 V with a maximum output current of 0.002 A for DCD, • VOUT7 = 0.9 V with a maximum output current of +/-0.5 A for FPGA, Design criteria are for coincidental tracking of VOUT4 and VOUT5 with VOUT2. VOUT7 is a DDR termination and is designed for ratiometric tracking with VOUT5. All outputs discharge to 0.1 V in under 100 ms through external pull down resistors switched on when the rails are disabled. The ripple and transient assumptions are 2% peak to peak voltage ripple (for the switchers) and 5% deviation due to 50% instantaneous load step respectively. The nominal switching frequency is fixed at 300 kHz for VOUT1 and VOUT7. VOUT2 and VOUT5 switch at a fixed nominal frequency of 1.2 MHz. All other outputs are filtered, or linear regulated out of the switching rails. Rev. 0 Reference designs are as supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Reference designs are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Preliminary Technical Data FCDC 00059 TABLE OF CONTENTS Features....................................................................................................................................................................................................... 1 ADP1829, APD210X and ADP171X Reference Design Description ................................................................................................ 1 Revision History........................................................................................................................................................................................ 2 General Description ................................................................................................................................................................................. 3 ADP1823................................................................................................................................................................................................ 3 ADP2105, ADP2106, ADP2107.......................................................................................................................................................... 3 ADP171X ............................................................................................................................................................................................... 3 ADP1581................................................................................................................................................................................................ 3 Block Diagram........................................................................................................................................................................................... 4 Schematic ................................................................................................................................................................................................... 5 Bill of Materials ......................................................................................................................................................................................... 8 TABLE OF FIGURES Figure 1. Block Diagram of the System........................................................................................................................................................4 Figure 2. Schematic: VOUT1 and VOUT7 ..........................................................................................................................................................5 Figure 3. Schematic: VOUT2 ,VOUT3 ,VOUT4 ,VOUT5 and VOUT6 .....................................................................................................................6 Figure 4. Schematic: Power Down Circuitry...............................................................................................................................................7 Figure 5. 12 V Efficiency (linear regulators enabled at no load)............................................................................................................11 Figure 6. Switching regulator turn on at no load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD .......12 Figure 7. Switching regulator turn on at full load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD......12 Figure 8. Switching regulator turn off at no load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD.......13 Figure 9. Switching regulator turn off at full load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD .....13 Figure 10. 2V5_DCD Linear/filtered regulator turn on at no load: Ch1 = 1V25_DCD_L, Ch2 = 3V3_DCD_L, Ch3 = 3V3_DCD, Ch4 = 14 Figure 11. 2V5_DCD Linear/filtered regulator turn off at no load: Ch1 = 1V25_DCD_L, Ch2 = 3V3_DCD_L, Ch3 = 3V3_DCD, Ch4 = 14 Figure 12. 0V9_FPGA Switching regulator ripple and noise at no load: Ch1 = Vo3V6, Ch2 = 3V3_DCD, Ch3 = 1V8_DCD, Ch4 = 15 Figure 13. 0V9_FPGA Switching regulator ripple and noise at full load: Ch1 = Vo3V6, Ch2 = 3V3_DCD, Ch3 = 1V8_DCD, Ch4 = 15 Figure 14. Linear/filtered regulator ripple and noise at no load: Ch1 = 3V3_DCD, Ch2 = 3V3_DCD_L, Ch3 = 2V5_DCD, Ch4 = 1V25_DCD_L ..........................................................................................................................................................................................16 Figure 15. Linear/filtered regulator ripple and noise at full load: Ch1 = 3V3_DCD, Ch2 = 3V3_DCD_L, Ch3 = 2V5_DCD, Ch4 = 1V25_DCD_L ..........................................................................................................................................................................................16 REVISION HISTORY 9/19/2007—Revision 0: Initial Version Rev. 0 | Page 2 of 17 Preliminary Technical Data FCDC 00059 GENERAL DESCRIPTION ADP1823 The ADP1829 is a versatile, dual output, interleaved, synchronous PWM buck controller that generates two independent outputs from an input voltage of 2.9 V to 20 V. Each channel can be configured to provide output voltage from 0.6V to 85% of the input voltage. The two channels operate 180° out of phase, which reduces the current stress on the input capacitor and allows the use of a smaller and lower cost input capacitor. The ADP1829 operates at a pin-selectable fixed switching frequency of either 300 kHz or 600 kHz. For some noise sensitive applications, it can also be synchronized to an external clock to achieve switching frequency between 300 kHz and 1 MHz. The switching frequency chosen is 300 kHz to get good efficiency over a wide range of input and output conditions. The ADP1829 includes an adjustable soft start to limit input inrush current, voltage tracking for sequencing or DDR termination, independent power-good output, and a power enable pin. It also provides current-limit and short-circuit protection by sensing the voltage on the synchronous MOSFET. ADP2105, ADP2106, ADP2107 The ADP2105,6,7 are a versatile, single output, synchronous PWM buck controller with integrated synchronous FETs that generates a single output from an input voltage of 2.7 V to 5.5 V. The controller can be configured to provide output voltage from 0.8 V to the input voltage with an output current up to 2 A. The ADP2105,6,7 operate at a fixed switching frequency of 1.2 MHz to reduce component size. The ADP2105,6,7 include an adjustable soft start to limit input inrush current. Inherent to their current mode design they provide current-limit and short-circuit protection by sensing the voltage dropped across the internal MOSFET. ADP171X The ADP171X is a family of low drop out CMOS linear regulators that provides versatile and inexpensive step-down voltage regulation. The input voltage range is 2.5 V to 5.5 V and the output current capability is up to 500 mA. The various versions provide features such as Enable, Soft Start, Low Noise Bypass and Tracking. They are available is space saving TSOT-5 and MSOP-8 packages and operate over the –40°C to +125°C temperature range. ADP1581 The ADR15811 is a low cost, 2-terminal (shunt), precision band gap reference. It provides an accurate 1.250 V output for input currents between 60 μA and 10 mA. The ADR1581 is available in two grades, A and B, both of which are provided in the SOT-23 package. Both grades are specified over the industrial temperature range of −40°C to +85°C. Rev. 0 | Page 3 of 17 Preliminary Technical Data FCDC 00059 BLOCK DIAGRAM Figure 1. Block Diagram of the System Rev. 0 | Page 4 of 17 Preliminary Technical Data FCDC 00059 SCHEMATIC Figure 2. Schematic: VOUT1 and VOUT7 Rev. 0 | Page 5 of 17 Preliminary Technical Data Figure 3. FCDC 00059 Schematic: VOUT2 ,VOUT3 ,VOUT4 ,VOUT5 and VOUT6 Rev. 0 | Page 6 of 17 Preliminary Technical Data FCDC 00059 Pull Down Circuitry Ensures all rails <0.1V in under 100ms from ON deassertion Rp1 Vo3V6 Rp2 0V9_FPGA Qp1 Qp2 12Vin 3V3_DCD Rp16 Roff Rp17 1V8_DCD Qp16 Rp19 POK3V6 Qoff Qp19 Figure 4. Schematic: Power Down Circuitry Rev. 0 | Page 7 of 17 Qp17 2V5_DCD Preliminary Technical Data FCDC 00059 BILL OF MATERIALS Table 1. Vout1, and Vout7 Bill of Materials (Vo3V6 and 0V9_FPGA) Description Designator Quantity Manufacturer MFR# Original Designator Capacitor Ceramic X7R 3.3n 0603 50V C6 1 Vishay Generic Cc12 Capacitor Ceramic COG 22p 0603 50V C5, C19 2 Vishay Generic Cc10, Cc20 Capacitor Ceramic X7R 2.2n 0603 50V C7 1 Vishay Generic Capacitor Ceramic X7R 1u 0603 16V C2, C15, C1 3 Murata GRM188R71C105KA12D Cc11 Cbias1, Cpv1, Cvcc1 Capacitor Ceramic X7R 47n 0603 16V C3 1 Vishay Generic Css1 Capacitor Ceramic X7R 4.7n 0603 50V C26 1 Vishay Generic Css2 Capacitor Ceramic X5R 22u 1210 16V C9, C20 2 grm32er61c226k Cin11, Cin21 Capacitor Al Poly 105C 120u 8mm x 7.6mm 16V -- 1 Murata Nippon Chemicon APXE160ARA121MH70G Cin12 Capacitor Ceramic X7R 100n 0603 16V C10, C22 2 Vishay Generic Cb1, Cb2 Capacitor Ceramic COG 33p 0603 50V C14, C18 2 Vishay Generic Clim1, Clim2 Capacitor Ceramic X7R 1.5n 0603 50V C17 1 Vishay Generic Cc21 Capacitor Ceramic COG 820p 0603 50V C16 1 Vishay Generic Cc22 Capacitor Ceramic X5R 22u 1206 6.3V C11, C23 2 grm31cr60j226k Co11, Co21 Capacitor Al Poly 105C 470u 8mm x 7.7mm 6.3V C12 1 Murata Nippon Chemicon APXE6R3ARA471MH80G Co12 Diode Schottky 200mA SOD-323 30V D1 1 Diodes inc BAT54AW Db1, Db2 Inductor Ferrite 15uH 7.6mm x 7.6mm L1 1 Cooper DR74-150-R L1 Inductor Ferrite 10uH 8mm x 8mm L2 1 Coilcraft MSS7341-103MLD L2 Single N-Channel MOSFET PG-TSDSON-8 30V Q1, Q2 2 Infineon BSZ130N03LS QH1, QL1 Single N-Channel MOSFET SOT23-6 20V Q3, Q4 2 Vishay Si3460DV QH2, QL2 1A Thick Film 0 Ohm jumper 0603 R14, R15, R30 3 Vishay Generic -- 5% Thick Film 10 Ohms 0603 R7, R1 2 Vishay Generic Rpv1, Rin1 1% Thick Film 3.92k 0603 R2 1 Vishay Generic Rf12 1% Thick Film 10.0k 0603 R13, R29, R22 3 Vishay Generic Rpg1, Rpg2, Rc21 0.1% Thin Film 4.99k 0603 R18 1 Vishay Generic Rf23 1% Thick Film 20.0k 0603 R10 1 Vishay Generic Rf11 0.1% Thin Film 20.0k 0603 R26x 1 Vishay Generic Rt21 0.1% Thin Film 24.9k 0603 R24 1 Vishay Generic Rf22 0.1% Thin Film 15.0k 0603 R21 1 Vishay Generic Rf21 0.1% Thin Film 7.68k 0603 R27 1 Vishay Generic Rt22 1% Thick Film 60.4 Ohms 0603 R22 1 Vishay Generic Rc22 1% Thick Film 1.18k 0603 R19 1 Vishay Generic Rlim1 1% Thick Film 1.05k 0603 R23 1 Vishay Generic Rlim2 1% Thick Film 2.87k 0603 R11 1 Vishay Generic Rc12 1% Thick Film 49.9k 0603 R12 1 Vishay Generic Rc11 2 chan 300k to 600k PWM LFCSP-32 U1 1 Analog Devices ADP1829ACPZ U1 Rev. 0 | Page 8 of 17 Preliminary Technical Data FCDC 00059 Table 2. Vout2, Vout3, Vout4, Vout5 and Vout6 Bill of Materials (3V3_DCD, 3V3_DCD_L, 2V5_DCD, 1V8_DCD and 1V25_DCD_L) Description Designator Quantity Manufacturer MFR# Capacitor Ceramic X7R 1u 0603 16V Cin161, Co162 2 Murata GRM188R71C105KA12D Capacitor Ceramic X5R 2.2u 0805 16V Cin171, Cin172, Cin191, Co191 4 Murata GRM21BR61C225KA88L Capacitor Ceramic X7R 1n 0603 50V Css16, Co201 2 Vishay Generic Capacitor Ceramic COG 100p 0603 50V 2 Vishay Generic Capacitor Ceramic X7R 100n 0603 16V Cc171, Css17 Cvcc16, Cvcc17, Co181 3 Vishay Generic Capacitor Ceramic COG 47p 0603 50V Cc161 1 Vishay Generic Capacitor Ceramic X5R 22u 1206 6.3V Co161 1 Murata grm31cr60j226k Capacitor Ceramic X5R 10u 1206 10V Co171 1 grm31mr61a106k Capacitor Al Poly 105C 150u 5mm x 5.8mm 4V Co182 1 Murata Nippon Chemicon Inductor Ferrite 4.7uH 1210 1A L16 1 Taiyo Yuden CB C3225T4R7MR Inductor Ferrite 2.2uH 1210 1.1A L17 1 Taiyo Yuden CB C3225T2R2MR Inductor Ferrite 100uH 1210 0.27A L18 1 Taiyo Yuden CB C3225T101MR 5% Thick Film 10 Ohms 0603 Rin16, Rin17, Rin18 3 Vishay Generic 1% Thick Film 402 Ohms 0603 Rin20 1 Vishay Generic 1A Thick Film 0 Ohm jumper 0603 Rf171 1 Vishay Generic 1% Thick Film 249k 0603 Rf161 1 Vishay Generic 1% Thick Film 80.6k 0603 Rf162 1 Vishay Generic 1% Thick Film 100k 0603 Rt171 1 Vishay Generic 1% Thick Film 80.6k 0603 Rt172 1 Vishay Generic 1% Thick Film 200k 0603 Rc161 1 Vishay Generic 1% Thick Film 76.8k 0603 Rc171 1 Vishay Generic Diode Dual Schottky 200mA SOT-323 30V D18 1 Diodes inc BAT54SW Integrated 1.2MHz PWM LFCSP-16 U16 1 Analog Devices ADP2105ACPZ-3.3-R7 Integrated 1.2MHz PWM LFCSP-16 U17 1 Analog Devices ADP2105ACPZ-1.8-R7 500mA 2.5V Linear Reg MSOP-8 w/track U19 1 Analog Devices ADP1716ARMZ-2.5-R7 10mA 1.25V Shunt Ref SOT23 U20 1 Analog Devices ADR1581ARTZ Rev. 0 | Page 9 of 17 APXE4R0ARA151ME61G Preliminary Technical Data FCDC 00059 Table 3. Power Down Bill of Materials Description Designator Quantit y Manufacturer MFR# Single N-Channel MOSFET SOT23 60V Qoff, Qp1, Qp2, Qp16, Qp17, Qp19 6 Diodes inc 2N7002-F 1% Thick Film 10.0k 0603 Roff 1 Vishay Generic 1% Thick Film 28.7 Ohms 1206 Rp1 1 Vishay Generic 1% Thick Film 1.43k 0603 Rp2 1 Vishay Generic 1% Thick Film 9.76k 0603 Rp19 1 Vishay Generic 1% Thick Film 154 Ohms 0603 Rp16 1 Vishay Generic 1% Thick Film 2.37k 0603 Rp17 1 Vishay Generic Rev. 0 | Page 10 of 17 Preliminary Technical Data FCDC 00059 Switching Regulators Efficiency 85% 80% 75% Efficiency 70% 65% Switching Regulators 60% 55% 50% 45% 0% 20% 40% 60% 80% 100% % of full load of switching regulators Figure 5. 12 V Efficiency (linear regulators enabled at no load) Rev. 0 | Page 11 of 17 120% Preliminary Technical Data FCDC 00059 Figure 6. Switching regulator turn on at no load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD Figure 7. Switching regulator turn on at full load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD Rev. 0 | Page 12 of 17 Preliminary Technical Data FCDC 00059 Figure 8. Switching regulator turn off at no load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD Figure 9. Switching regulator turn off at full load: Ch1 = 0V9_FPGA, Ch2 = Vo3V6, Ch3 = 3V3_DCD, Ch4 = 1V8_DCD Rev. 0 | Page 13 of 17 Preliminary Technical Data FCDC 00059 Figure 10. Linear/filtered regulator turn on at no load: Ch1 = 1V25_DCD_L, Ch2 = 3V3_DCD_L, Ch3 = 3V3_DCD, Ch4 = 2V5_DCD Figure 11. Linear/filtered regulator turn off at no load: Ch1 = 1V25_DCD_L, Ch2 = 3V3_DCD_L, Ch3 = 3V3_DCD, Ch4 = 2V5_DCD Rev. 0 | Page 14 of 17 Preliminary Technical Data FCDC 00059 Figure 12. Switching regulator ripple and noise at no load: Ch1 = Vo3V6, Ch2 = 3V3_DCD, Ch3 = 1V8_DCD, Ch4 = 0V9_FPGA Figure 13. Switching regulator ripple and noise at full load: Ch1 = Vo3V6, Ch2 = 3V3_DCD, Ch3 = 1V8_DCD, Ch4 = 0V9_FPGA Rev. 0 | Page 15 of 17 Preliminary Technical Data FCDC 00059 Figure 14. Linear/filtered regulator ripple and noise at no load: Ch1 = 3V3_DCD, Ch2 = 3V3_DCD_L, Ch3 = 2V5_DCD, Ch4 = 1V25_DCD_L Figure 15. Linear/filtered regulator ripple and noise at full load: Ch1 = 3V3_DCD, Ch2 = 3V3_DCD_L, Ch3 = 2V5_DCD, Ch4 = 1V25_DCD_L Rev. 0 | Page 16 of 17 Preliminary Technical Data FCDC 00059 NOTES Efficiency measurements include loss due to linear and shunt regulators being active at no load. Lower than average efficiency is to be expected due to the two stage conversion (creation of intermediate 3.6 V bus). Additionally, the 3.6 V converter is sized to provide over double the required current for this demo board, therefore its no load loss will be high. Ripple voltage measurements especially on the low noise linear outputs show high frequency spikes that are likely probe noise pickup from attempting to probe the non-ideal two layer copper board. Noise levels are expected to be much lower on a multilayer FR4 board with proper decoupling techniques. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB Rev. 0 | Page 17 of 17