DEM-DAI1808 User's Guide August 2006 DAP SLEU078 DEM-DAI1808 User's Guide Literature Number: SLEU078 August 2006 Contents 1 Description ................................................................................................................ 5 1.1 Block Diagram ....................................................................................................... 6 1.2 Basic Connection and Operation ................................................................................. 7 1.3 ................................................................. 7 1.2.2 Configuration Controls .................................................................................... 7 Typical Performance and Measurement Example ............................................................ 12 1.2.1 2 Basic Connections and Configurations Schematics and Printed Circuit Boards ....................................................................... 15 2.1 DEM-DAI1808 Schematics ....................................................................................... 16 2.2 DEM-DAI1808 Bill of Materials (BOM) 2.3 ......................................................................... DEM-DAI1808 Printed Circuit Boards .......................................................................... SLEU078 – August 2006 Submit Documentation Feedback Contents 19 22 3 List of Figures 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 DEM-DAI1808 Block Diagram ............................................................................................. 6 External Interfaces ......................................................................................................... 11 DEM-DAI1808 Digital Section (Digital Audio Interface) ............................................................... 16 DEM-DAI1808 Regulator and Connector ............................................................................... 17 DEM-DAI1808 ADC Section .............................................................................................. 17 DEM-DAI1808 Analog Section ........................................................................................... 18 DEM-DAI1808 Silkscreen ................................................................................................. 22 DEM-DAI1808 — Top View ............................................................................................... 23 DEM-DAI1808 — Bottom View ........................................................................................... 24 List of Tables 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 4 System Clock Source Selection ........................................................................................... 7 Master/Slave Interface Mode Selection ................................................................................... 7 Interface Format Selection.................................................................................................. 8 System Clock Rate Selection .............................................................................................. 8 Sampling Frequency and System Clock Frequency Selection ........................................................ 9 Analog Input Level/Path Selection ......................................................................................... 9 S/PDIF Transmitter Format (Channel Status) Setting for DIT4096 .................................................. 10 Mode and Format Control for PCM1808 ................................................................................ 11 List of Figures SLEU078 – August 2006 Submit Documentation Feedback Chapter 1 SLEU078 – August 2006 Description The DEM-DAI1808 is an evaluation board for the PCM1808, a 96-kHz, 24-bit PCM audio analog-to-digital converter (ADC), with digital audio transmitter, optical and coaxial interface, onboard multiple clock generator, –6-dB amplifier with LPF, and switches or jumpers for mode or clock control. Related documentation includes the DIT4096 96-kHz Digital Audio Transmitter data sheet (literature number SBOS225) and the PLL1707, PLL1708 3.3-V Dual PLL Multiclock Generator data sheet (literature number SLES065) The DEM-DAI1808 operates under 5-V and ±15-V analog power supplies, with 1-Vrms or 2-Vrms unbalanced analog signal input. Topic 1.1 1.2 1.3 .................................................................................................. Page Block Diagram ............................................................................ 6 Basic Connection and Operation .................................................. 7 Typical Performance and Measurement Example .......................... 12 SLEU078 – August 2006 Submit Documentation Feedback Description 5 www.ti.com Block Diagram 1.1 Block Diagram 3.3 V 5V ±15 V Mode Control Switches SPDIF Optical 3.3 V DIT Setting Sel Reg. 5V Coaxial Ext Clock Digital Interface Transmitter DIT4096 15 V L-ch Sel I/F Buffer DUT PCM1807 DAI Bridge PLL and DIT Setting -6dB LPF R-ch Sel Sel External PCM Interface Clock Generator PLL1707 -15 V Cont. Bridge Reset Digital -6dB LPF Analog Figure 1-1. DEM-DAI1808 Block Diagram 6 Description SLEU078 – August 2006 Submit Documentation Feedback www.ti.com Basic Connection and Operation 1.2 Basic Connection and Operation 1.2.1 Basic Connections and Configurations • • • • • • • Connect the 5-V and ±15-V power supplies to VCC, ±AVCC, and GND on CN051–CN055. The ±15-V power supplies only are required for 2-Vrms input. Connect the SPDIF output to CN003 (coaxial) or U001 (optical). Select the system clock source from 256/512 fs or 384 fs generated by on-board clock generator (PLL1707), or external clock input connector (CN001) using JP001, and ensure the presence of system clock on it. Set the interface mode (master or slave) using SW002 M/S for board and SW004 MD1/0 for PCM1808. Set the interface format (LJ-24 or I2S-24) using SW002 FMT0 for board and SW004 FMT for PCM1808. Select the combination of sampling frequency (16 kHz to 96 kHz) and system clock rate (256 fs, 384 fs, 512 fs), using SW002 CLK1/0, SR, FS2/1 for board and SW004 for PCM1808. Set the channel status for DIT4096 if required. (It is not required for PCM1808 evaluation.) 1.2.2 Configuration Controls 1.2.2.1 System Clock Source Selection The system clock (master clock) source for the evaluation module (EVM) including the PCM1808, which is associated with sampling frequency, can be selectable by the JP001 setting as follows. Table 1-1. System Clock Source Selection JP001 1.2.2.2 DESCRIPTION 256 Internal, 256/512 times of sampling frequency (default) 384 Internal, 384 times of sampling frequency EXT External, TTL interface level, up to 25 MHz Master/Slave (M/S) Interface Mode Selection The audio interface mode of the PCM1808 and EVM can be selectable as follows. In slave mode, audio interface clock, BCK, and LRCK are generated in the DIT4096 and supplied to the PCM1808 through a buffer. In master mode, they are generated in the PCM1808 and supplied to the DIT4096. Mode control to the PCM1808 can be performed by the SW004 setting. Table 1-2. Master/Slave Interface Mode Selection SW002, M/S (1) DESCRIPTION MD1 MD0 ON (Low) ON (Low) ON (Low) ON (Low) OFF (High) ON (Low) OFF (High) ON (Low) Master mode, 384 fs ON (Low) OFF (High) OFF (High) Master mode, 256 fs OFF (High) (1) SW004, MD1/0 (1) Slave mode Master mode, 512 fs (default) Other inconsistent combinations between SW002 M/S and SW004 MD1/0 selection are not available. SLEU078 – August 2006 Submit Documentation Feedback Description 7 www.ti.com Basic Connection and Operation 1.2.2.3 Interface Format Selection The audio interface format of the PCM1808 and EVM can be changed as follows. Table 1-3. Interface Format Selection SW002, (1) 1.2.2.4 FMT0 (1) SW004, FMT (1) DESCRIPTION OFF (High) ON (Low) I2S 24 bits (default) ON (Low) OFF (High) Left-justified 24 bits Other inconsistent combinations between SW002 FMT0 and SW004 FMT selection are not available. Sampling Frequency and System Clock Frequency Selection The sampling frequency and the system clock frequency for the PCM1808 and EVM can be selectable as shown in Table 1-4 and Table 1-5 by setting JP001, SW002, and SW004. Sampling frequencies of 16 kHz to 96 kHz and system clock rates of 256 fs, 384 fs, and 512 fs are available for the EVM. The settings of JP001, CLK1/0 of SW002, and MD1/0 of SW004 (see Table 1-4) determine the system clock rate. The settings of SR and FS2/1 of SW002 (see Table 1-5) determine the sampling clock and system clock frequencies. The possible combinations of sampling clock and system clock frequencies appear in the right-most column of Table 1-5. Table 1-4. System Clock Rate Selection JP001 (1) 8 SW004 (3) SYSTEM CLOCK RATE CLK1 CLK0 MD1 MD0 ON/Low ON/Low – – 256 ON/Low OFF/High OFF/High OFF/High 256 fs 384 OFF/High ON/Low OFF/High ON/Low 384 fs 256 OFF/High OFF/High ON/Low OFF/High – (1) (2) (3) SW002 (2) Reserved 512 fs (default) Other inconsistent combinations between SW002 CLK1/0 and SW004 MD1/0 selection are not available. Select the DIT4096 master clock rate. Select the PCM1808 system clock rate if master-mode operation of the PCM1808 is required. If slave-mode operation of the PCM1808 is required, the combination of MD1 = ON/Low and MD0 = ON/Low is available for all three rates: 256 fs, 384 fs, and 512 fs. Description SLEU078 – August 2006 Submit Documentation Feedback www.ti.com Basic Connection and Operation Table 1-5. Sampling Frequency and System Clock Frequency Selection SW002 (1) FS2 FS1 FREQUENCIES SAMPLING CLOCK (kHz)/SYSTEM CLOCK (MHz) OFF/Low ON/High OFF/Low 32/8.192 OFF/Low OFF/Low ON/High 44.1/11.2896 OFF/Low OFF/Low OFF/Low 48/12.288 ON/High ON/High OFF/Low 64/16.384 ON/High OFF/Low ON/High 88.2/22.5792 ON/High OFF/Low OFF/Low 96/24.576 OFF/Low ON/High OFF/Low 32/12.288 OFF/Low OFF/Low ON/High 44.1/16.9344 OFF/Low OFF/Low OFF/Low 48/18.432 ON/High ON/High OFF/Low 64/24.576 ON/High OFF/Low ON/High 88.2/33.8688 (2) ON/High OFF/Low OFF/Low 96/36.864 (2) OFF/Low ON/High OFF/Low 16/8.192 (3) OFF/Low OFF/Low ON/High 22.05/11.2896 OFF/Low OFF/Low OFF/Low 24/12.288 ON/High ON/High OFF/Low 32/16.384 ON/High OFF/Low ON/High 44.1/22.5792 ON/High OFF/Low OFF/Low 48/24.576 (default) SR 256-fs Operation 384-fs Operation 512-fs Operation (1) (2) (3) 1.2.2.5 Select the clock output frequency of the PLL1707 SCKOx; the combination of FS2 = ON/High and FS1 = ON/High is reserved. Not applicable through the SPDIF interface due to a limitation of the DIT4096. Frequencies are applicable for PCM direct interface between the PCM1808 and externals. May not be applicable through the SPDIF interface due to interface receiver limitations of digital-domain measurement equipment, like Audio Precision. This frequency is applicable for PCM direct interface between the PCM1808 and externals. Analog Input Level/Path Selection The DEM-DAI1808 supports 1-Vrms and 2-Vrms input for full scale of analog input signal by the JP101, JP102 setting. For 2-Vrms input selection, an onboard 100-kHz LPF and –6-dB attenuator is applied on the input signal. The default setting is 2-Vrms input. Table 1-6. Analog Input Level/Path Selection JP101, JP102 1.2.2.6 DESCRIPTION 1 Vrms 1-Vrms full-scale analog input is fed to ADC directly. 2 Vrms 2-Vrms full-scale analog input is fed to ADC through 100 kHz LPF and –6-dB attenuator (default). Reset Control The DEM-DAI1808 supports Reset Control for DIT4096 by SW003. SLEU078 – August 2006 Submit Documentation Feedback Description 9 www.ti.com Basic Connection and Operation 1.2.2.7 S/PDIF Transmitter Format (Channel Status) Setting for DIT4096 The extended configurations of the digital audio interface transmitter, DIT4096, and the channel status of SPDIF can be set using the DIP switches, SW001. The individual switch settings and their functions are described in Table 1-7. For general evaluation or test of function and performance of the PCM1808, the change from default setting of this SW001 is not needed. This is provided for evaluation of the DIT4096 function, mainly related to channel status information. Table 1-7. S/PDIF Transmitter Format (Channel Status) Setting for DIT4096 SW001 CSS ON/OFF Off (High) On (Low) COPY/C, L, /AUDIO, and /EMPH inputs are used to set associated channel status data bits (default). Off (High) Copy and generation status information with L input for CSS = Low, channel status data bit = 1 for CSS = High On (Low) Copy and generation status information with L input for CSS = Low, channel status data bit = 0 for CSS = High (default) Off (High) User data input = 1 On (Low) User data input = 0 (default) Off (High) Validity data input = 1 On (Low) Validity data input = 0 (default) Off (High) Copy and generation status with COPY/C for CSS = Low COPY/C (1) U V L (1) /AUDIO /EMPH BLSM BLS (1) 10 DESCRIPTION Channel status data bits are set in serial fashion at the COPY/C input with clock input at the SYNC input. On (Low) Copy and generation status with COPY/C for CSS = Low (default) Off (High) Audio data valid control input, not linear PCM On (Low) Audio data valid control input, linear PCM (default) Off (High) Pre-emphasis status input, not applied pre-emphasis (default) On (Low) Pre-emphasis status input, applied pre-emphasis Off (High) BLS mode control input, BLS is an output (default) On (Low) BLS mode control input, BLS is an input Off (High) Block start input for BLSM = Low, output for BLSM = High (default) On (Low) Not block start Copy and generation status information for CSS = Low COPY/C L On (Low) On (Low) Consumer mode, PRO = 0, COPY = 0, L = 0 (default) On (Low) Off (High) Consumer mode, PRO = 0, COPY = 0, L = 1 Off (High) On (Low) Consumer mode, PRO = 0, COPY = 1, L = 0 Off (High) Off (High) Professional mode, PRO = 1, No copy protection Description COPY AND GENERATION STATUS SLEU078 – August 2006 Submit Documentation Feedback www.ti.com Basic Connection and Operation 1.2.2.8 Audio Interface Mode and Format Control for PCM1808 The audio interface mode and format control for the PCM1808 can be performed by the SW004 setting. The summary of the PCM1808 pin configuration is given in Table 1-8. Table 1-8. Mode and Format Control for PCM1808 MD1 (#11) MD0 (#10) DESCRIPTION Low Low Slave mode Low High Master mode 512 fs (default) High Low Master mode 384 fs High High Master mode 256 fs FMT (#12) 1.2.2.9 DESCRIPTION Low I2S 24 bits (default) High Left-justified 24 bits DAI Bridge and Control Bridge Selection The DEM-DAI1808 supports flexible PCM audio interface through a DAI bridge, so that the PCM1808 can interface with external devices or equipment in place of an internal buffer and the DIT4096. Interfacing with externals can be done by changing JP052 and JP053 connections for SCLK, BCK, LRCK, DATA, and GND as shown in Figure 1-2. The DEM-DAI1808 also supports flexible mode and format control to the PCM1808 by redirection of the control port through the header setting of the control bridge, JP054. The default setting is interfaced with internal DIT4096 and DIP switch, SW004. DIT DIT EXT GND GND SCLK SCLK BCK BCK LRCK LRCK DATA DATA Default Interface With DIT4096 EXT External Interface With External Device/Equipment Figure 1-2. External Interfaces SLEU078 – August 2006 Submit Documentation Feedback Description 11 www.ti.com Typical Performance and Measurement Example 1.3 Typical Performance and Measurement Example Typical performance of the DEM-DAI1808 for default condition is as follows, and FFT results for full-scale input and –60-dB input are shown. THD+N @ 48 kHz/512 fs: –93.5 dB D. Range @ 48 kHz/512 fs: 99.3 dB SNR @ 48 kHz/512 fs: 99.3 dB PCM1808, Master, 48 kHz/512 fs, –0.5 dB +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz 12 Description SLEU078 – August 2006 Submit Documentation Feedback www.ti.com Typical Performance and Measurement Example PCM1808, Master, 48 kHz/512 fs, –60 dB +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz SLEU078 – August 2006 Submit Documentation Feedback Description 13 www.ti.com Typical Performance and Measurement Example 14 Description SLEU078 – August 2006 Submit Documentation Feedback Chapter 2 SLEU078 – August 2006 Schematics and Printed Circuit Boards This chapter presents the DEM-DAI1808 schematics, Bill of Materials (BOM), and printed circuit boards. Topic 2.1 2.2 2.3 .................................................................................................. Page DEM-DAI1808 Schematics .......................................................... 16 DEM-DAI1808 Bill of Materials (BOM) .......................................... 19 DEM-DAI1808 Printed Circuit Boards ........................................... 22 SLEU078 – August 2006 Submit Documentation Feedback Schematics and Printed Circuit Boards 15 www.ti.com DEM-DAI1808 Schematics 2.1 DEM-DAI1808 Schematics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 32 33 34 35 36 (CN004) 57LE-40360-7700 (D3) 30 31 BLS BLSM 2 3 1 29 L AUDIO EMPH U 7 10 9 VCC 28 4 27 CSS COPY/C 26 V 25 5 24 6 23 [MD] [MC] 22 8 21 [RST] 20 [MS] 19 SW001 DSS110 VDD RA001 47k x9 L001 47µH C003 10µF/16V 16 15 RST DGND 17 TX- 18 19 VDD TX+ MDAT MONO 20 21 22 23 EMPH SDATA M/S 14 13 SYNC 12 SCLK FMT1 11 9 10 FMT0 DGND MCLK 7 6 CLK0 CLK1 5 4 VIO 2 25 26 27 28 29 11 3 SCKO3 4 DGND1 SCKO0 18 C010 7 0.1µ 8 31 32 33 34 MCKO2 15 SR MCKO1 14 VCC VDD2 35 CSEL XT1 XT2 13 18 4 17 5 16 6 15 7 14 8 13 9 C017 12 0.1µ 11 10 GND 19 3 12 RST MS MC MD 11 GND U004 PLL1707 74LV244A X001 27MHz C014 RA003 15p 47k x4 (C011) 100uF/16V (CN002) FFC-48BMEP1 GND (12) 36 (13) 14 37 38 15 16 39 40 17 41 18 42 19 43 20 44 21 45 22 46 23 47 24 1 U005 C015 15p OUT 2 (C012) 0.1uF 2 11 16 DGND2 FS2 (FIL001) 10 17 FS1 9 AGND 10 C018 0.1µ RST 9 DATA 20 Vcc 2 3 [DATA] 8 DGND3 1 D003 IS133 FMT [LRCK] 7 30 12 GND 4 [BCK] 6 20 SCKO1 19 6 [SCLK] 5 VDD3 VDD1 GND 1 4 13 10 SCKO2 5 3 IN 3 14 8 MD1 R003 75 2 15 7 9 1 1 C016 0.1µ JP001 FFC6BMEP1 1 16 6 D002 IS133 C008 0.1µF R004 75 CN005 GND 17 5 LRCK BCK SCLK C009 10uF/16V 256 384 EXT CN001 BNC-LR-PC4 18 4 SW002 DSS108 R001 47k SW003 FP1F-2M 19 3 MD0 R002 470 20 Vcc 2 D001 1SS133 RESET 4 U003 74LV244A CLK0 2 4 5 3 CLK1 FMT0 SR M/S 8 TR001 DA-02 6 3 2 1 C006 10µF/16V RA002 47k x4 FS1 5 4 7 6 U006 74LVC1G04 DIT4096 C005 0.1µF FS2 C002 0.1uF CN003 RCA pj C001 10uF /16V R005 360 2 C013 0.1uF R006 91 1 L 5 2 4 CSS 2 1 1 3 COPY/C U002 3 8 U001 TOTX179P AUDIO BLSM BLS 24 25 27 26 V U MODE 28 C004 0.1µF SW004 DSS104 48 Figure 2-1. DEM-DAI1808 Digital Section (Digital Audio Interface) 16 Schematics and Printed Circuit Boards SLEU078 – August 2006 Submit Documentation Feedback www.ti.com DEM-DAI1808 Schematics CN056 B2P-VH VDD 2 CN053 CN052 CN051 banana jack banana jack banana jack (blue) (gray) (orange) CN055 CN054 banana jack banana jack (black) (red) AVCC + 1 VCC U051 REG1117-3.3 JP051 2 OUT IN 3 GND 1 C056 10uF /16V C053 100uF /16V C051 0.1uF C054 100uF /16V AVCC - C052 100uF /16V C055 0.1uF AGND DGND AGND Figure 2-2. DEM-DAI1808 Regulator and Connector U052 VCC VDD AGND 10µ/16V 0.1µ C066 C065 C062 C061 10µ/16V 0.1µ C064 C063 10µ/16V 0.1µ VINL VREF VINR 14 2 AGND VINL 13 3 VCC FMT 12 VDD MD1 5 DGND MD0 6 SCKI DOUT 9 LRCK BCK 4 7 JP052 JP053 FFC-12BMEP1x2 DIT EXT PCM1808 1 VINR 11 10 8 GND CN057 DATA LRCK BCK SCLK GND R051-R054 100x4 JP054 FFC-10BMEP1 RST R055-R057 100x3 FMT/MS MD1/MC MD0/MD GND Figure 2-3. DEM-DAI1808 ADC Section SLEU078 – August 2006 Submit Documentation Feedback Schematics and Printed Circuit Boards 17 www.ti.com DEM-DAI1808 Schematics R105 C107 100pF R109 C109 10uF /16V 4.7k 330pF AVCC+ 2 JP101 FFC-4BMEP1 8 2Vrms 1Vrms U101 OPA2134PA 2/2 5 R107 4.7k C111 10uF/16V 3 4 U101 OPA2134PA 1/2 C113 10uF/16V AGND 100pF R110 C110 10uF /16V VINR 1.2k 330pF AVCC+ 2 JP102 FFC-4BMEP1 8 2Vrms 1Vrms 5 R102 2.4k R104 3.3k 1 6 7 R108 4.7k U102 OPA2134PA 2/2 C112 10uF/16V C114 10uF/16V AGND C103 1800pF R111 47k CN103 GND C106 4.7k C101 CN101 10uF RCA pj /16V AVCC- R106 C108 R101 2.4k R103 3.3k 1 6 7 VINL C105 1.2k 3 4 U102 OPA2134PA 1/2 AVCC- C102 CN102 10uF RCA pj /16V C104 1800pF R112 47k CN104 GND Figure 2-4. DEM-DAI1808 Analog Section 18 Schematics and Printed Circuit Boards SLEU078 – August 2006 Submit Documentation Feedback www.ti.com DEM-DAI1808 Bill of Materials (BOM) 2.2 DEM-DAI1808 Bill of Materials (BOM) REF. NO. PART NAME SPEC-1 SPEC-2 PART NO. SUPPLIER REMARKS Parts List 1/4 (Digital Portion) C001 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C002 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C003 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C004 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C005 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C006 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C007 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C008 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C009 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C010 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C011 Electrolytic Capacitor 100 uF/16 V ROA-16V101M ELNA Unmounted C012 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata Unmounted C013 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C014 Ceramic Capacitor 15 pF/50 V PRE131CH150J50 Murata C015 Ceramic Capacitor 15 pF/50 V PRE131CH150J50 Murata C016 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C017 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C018 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata R001 Metal Film Resistor 1/8 W, 47 k J R002 Metal Film Resistor 1/8 W, 470 J R003 Metal Film Resistor 1/8 W, 75 J R004 Metal Film Resistor 1/8 W, 75 J R005 Metal Film Resistor 1/8 W, 360 J R006 Metal Film Resistor 1/8 W, 91 J RA001 Resistor Array 47k × 9 J RA002 Resistor Array 47k × 4 J RA003 Resistor Array 47k × 4 J L001 Micro Inductor 47 uH J EL0606SKI-470J TDK FIL001 Filter D001 Diode 1S133 ROHM D002 Diode 1S133 ROHM D003 Diode 1S133 ROHM U001 Optical Transmitter TOTX-179P Toshiba U002 SPDIF Transmitter DIT4096PW TI U003 Buffer SN74LV244A TI U004 Buffer SN74LV244A TI U005 PLL Clock Generator PLL1707DB TI U006 One Gate Device SN74LVC1G04DBV TI TR001 Pulse Transformer DA-02 JPC X001 Crystal Resonator HC-49/U-S, 27 MHz Kinseki SW001 DIP Switch DSS110 Fujisoku DIT SW002 DIP Switch DSS108 Fujisoku DIT & PLL SLEU078 – August 2006 Submit Documentation Feedback Unmounted Inverter 27 MHz ±50 ppm Schematics and Printed Circuit Boards 19 www.ti.com DEM-DAI1808 Bill of Materials (BOM) REF. NO. PART NAME SPEC-1 SPEC-2 PART NO. SUPPLIER REMARKS SW003 Push Switch FP1F-2M Fujisoku Reset DIT SW004 DIP Switch DSS104 Fujisoku Mode DUT JP001 6-Pin Connector FFC-6BMEP1 Honda 256/384/Ext CN001 BNC Connector BNC-LR-PC4 CN002 48-Pin Connector FFC-48BMEP1 Honda CN003 RCA Connector LPR6520-0804 SMK CN004 Connector 57LE-40360-7700 DDK Unmounted CN005 Test Terminal LC-2-G Mac8 GND ×1 DIC-130 Honda JP001 Short Plug Yellow Right Angle Unmounted Parts List 2/4 (Power Portion) C051 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C052 Electrolytic Capacitor 100 uF/16 V ROA-16V101M ELNA C053 Electrolytic Capacitor 100 uF/16 V ROA-16V101M ELNA C054 Electrolytic Capacitor 100 uF/16 V ROA-16V101M ELNA C055 Ceramic Capacitor 0.1 uF/25 V PRE132F104Z50 Murata C056 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA U051 3.3-V Regulator REG1117-3.3 TI JP051 2-Pin Connector FFC-2AMEP1 Honda CN051 Banana Jack Orange CN052 Banana Jack Gray CN053 Banana Jack Blue CN054 Banana Jack Red CN055 Banana Jack Black CN056 VH Connector B2P-VH Nihon-AccyakuTanshi DIC-130 Honda JP051 GRM39F104Z25PT Murata Chip type R3A-16V100M ELNA GRM39F104Z25PT Murata R3A-16V100M ELNA GRM39F104Z25PT Murata R3A-16V100M ELNA Short Plug ×1 Parts List 3/4 (DUT Portion) 20 C061 Ceramic Capacitor 0.1 uF/25 V C062 Electrolytic Capacitor 10 uF/16 V C063 Ceramic Capacitor 0.1 uF/25 V C064 Electrolytic Capacitor 10 uF/16 V C065 Ceramic Capacitor 0.1 uF/25 V C066 Electrolytic Capacitor 10 uF/16 V R051 Metal Film Resistor 1/8 W, 100 J Chip type R052 Metal Film Resistor 1/8 W, 100 J Chip type R053 Metal Film Resistor 1/8 W, 100 J Chip type R054 Metal Film Resistor 1/8 W, 100 J Chip type R055 Metal Film Resistor 1/8 W, 100 J Chip type R056 Metal Film Resistor 1/8 W, 100 J Chip type R057 Metal Film Resistor 1/8 W, 100 J Chip type U052 A/D Converter (DUT) PCM1808DB TI JP052 12-Pin Connector FFC-12BMEP1 Honda JP053 12-Pin Connector FFC-12BMEP1 Honda JP054 10-Pin Connector FFC-10BMEP1 Honda Schematics and Printed Circuit Boards 1608 type 1608 type 1608 type Chip type Chip type SLEU078 – August 2006 Submit Documentation Feedback www.ti.com DEM-DAI1808 Bill of Materials (BOM) REF. NO. CN057 PART NAME SPEC-1 SPEC-2 Test Terminal Short Plug PART NO. SUPPLIER REMARKS LC-2-G Mac8 GND ×10 DIC-130 Honda JP052, 3, 4 Parts List 4/4 (Analog Portion) C101 Electrolytic Capacitor 10 uF/16 V ROA-16V100M ELNA C102 Electrolytic Capacitor 10 uF/16 V ROA-16V100M ELNA C103 Film Capacitor 1800 pF J APSF0100J182 Nissei C104 Film Capacitor 1800 pF J APSF0100J182 Nissei C105 Film Capacitor 330 pF J APSF0100J331 Nissei C106 Film Capacitor 330 pF J APSF0100J331 Nissei C107 Film Capacitor 100 pF J APSF0100J101 Nissei C108 Film Capacitor 100 pF J APSF0100J101 Nissei C109 Electrolytic Capacitor 10 uF/16 V ROA-16V100M ELNA C110 Electrolytic Capacitor 10 uF/16 V ROA-16V100M ELNA C111 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C112 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C113 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA C114 Electrolytic Capacitor 10 uF/16 V R3A-16V100M ELNA R101 Metal Film Resistor 1/8 W, 2.4 k F R102 Metal Film Resistor 1/8 W, 2.4 k F R103 Metal Film Resistor 1/8 W, 3.3 k F R104 Metal Film Resistor 1/8 W, 3.3 k F R105 Metal Film Resistor 1/8 W, 1.2 k F R106 Metal Film Resistor 1/8 W, 1.2 k F R107 Metal Film Resistor 1/8 W, 4.7 k F R108 Metal Film Resistor 1/8 W, 4.7 k F R109 Metal Film Resistor 1/8 W, 4.7 k F R110 Metal Film Resistor 1/8 W, 4.7 k F R111 Metal Film Resistor 1/8 W, 47 k F R112 Metal Film Resistor 1/8 W, 47 k F U101 Dual Op Amp DIP OPA2134PA TI U102 Dual Op Amp DIP OPA2134PA TI JP101 4-Pin Connector FFC-4BMEP1 Honda JP102 4-Pin Connector FFC-4BMEP1 Honda CN101 RCA Connector White LPR6520-0803 SMK CN102 RCA Connector Red LPR6520-0802 SMK CN103 Test Terminal LC-2-G Mac8 GND CN104 Test Terminal LC-2-G Mac8 GND IC Socket DIP 8 pin IC Socket DIP 8 pin Short Plug ×2 SLEU078 – August 2006 Submit Documentation Feedback U101 U102 DIC-130 Honda JP101, 102 Schematics and Printed Circuit Boards 21 www.ti.com DEM-DAI1808 Printed Circuit Boards 2.3 DEM-DAI1808 Printed Circuit Boards Figure 2-5. DEM-DAI1808 Silkscreen 22 Schematics and Printed Circuit Boards SLEU078 – August 2006 Submit Documentation Feedback www.ti.com DEM-DAI1808 Printed Circuit Boards Figure 2-6. DEM-DAI1808 — Top View SLEU078 – August 2006 Submit Documentation Feedback Schematics and Printed Circuit Boards 23 www.ti.com DEM-DAI1808 Printed Circuit Boards Figure 2-7. DEM-DAI1808 — Bottom View 24 Schematics and Printed Circuit Boards SLEU078 – August 2006 Submit Documentation Feedback www.ti.com DEM-DAI1808 Printed Circuit Boards EVM TERMS AND CONDITIONS Texas Instruments (TI) provides the enclosed Evaluation Module and related material (EVM) to you, the user, (you or user) SUBJECT TO the terms and conditions set forth below. By accepting and using the EVM, you are indicating that you have read, understand and agree to be bound by these terms and conditions. IF YOU DO NOT AGREE TO BE BOUND BY THESE TERMS AND CONDITIONS, YOU MUST RETURN THE EVM AND NOT USE IT. This EVM is provided to you by TI and is intended for your INTERNAL ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided “AS IS” and “WITH ALL FAULTS.” It is not considered by TI to be fit for commercial use. As such, the EVM may be incomplete in terms of required design−, marketing−, and/or manufacturing−related protective considerations, including product safety measures typically found in the end product. As a prototype, the EVM does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive. Should this EVM not meet the specifications indicated in the EVM User’s Guide, it may be returned within 30 days from the date of delivery for a full refund of any amount paid by user for the EVM, which user agrees shall be user’s sole and exclusive remedy. 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User assumes all responsibility and liability for proper and safe handling and use of the EVM and the evaluation of the EVM. TI shall have no liability for any costs, losses or damages resulting from the use or handling of the EVM. User acknowledges that the EVM may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the EVM it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE USER’S INDEMNITY OBLIGATIONS SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES WHETHER TI IS NOTIFIED OF THE POSSIBILITY OR NOT. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. User agrees to read the EVM User’s Guide and, specifically, the EVM warnings and Restrictions notice in the EVM User’s Guide prior to handling the EVM and the product. This notice contains important safety information about temperatures and voltages. It is user’s responsibility to ensure that persons handling the EVM and the product have electronics training and observe good laboratory practice standards. By providing user with this EVM, product and services, TI is NOT granting user any license in any patent or other intellectual property right. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated SLEU078 – August 2006 Submit Documentation Feedback Schematics and Printed Circuit Boards 25 www.ti.com DEM-DAI1808 Printed Circuit Boards EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range and the output voltage range that is less than 120% of the corresponding nominal voltage ranges described in the EVM user’s guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 50°C. The EVM is designed to operate properly with certain components above 50°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated 26 Schematics and Printed Circuit Boards SLEU078 – August 2006 Submit Documentation Feedback www.ti.com DEM-DAI1808 Printed Circuit Boards IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated SLEU078 – August 2006 Submit Documentation Feedback Schematics and Printed Circuit Boards 27