TIDA-00604 Test Report
Powering the Altera® Cyclone® III with TPS65023 Power
Management IC
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Design Resources
TIDA-00604
Design Folder
TPS65023
Product Folder
TPS65023EVM-205
Tools Folder
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Report Contents
Figure 1 - Top Side
Block Diagram: TPS65023/Cyclone® III
Efficiency Curves
Load Regulation Curves
Output Ripple Voltage
Load Transients
Design Considerations
Feature Applications
Motor Control
Test and Measurement
Wireless
Motion Control
Communication
Description
Figure 2 - Bottom Side
The TIDA-00604 design is a compact, integrated power solution for Altera® Cyclone® III SoC (out of
the Cyclone® series family of products). This design showcases TPS65023 as an all-in-one IC used to
supply the rails needed for powering the Cyclone® III SoC. The TPS65023 offers simple, flexibile
output voltages and sequencing. The voltages on the DC/DC Converters can be set through software
or via an external resistor divider. This power management IC has a input range from 2.5 – 6V and can
be run from a single 5V supply or from a single cell Li-Ion battery. This design has been tested and
verified for industrial applications (-40°C to 105°C).
TIDA-00604 - Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
Copyright © 2015, Texas Instruments Incorporated
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TPS65023/Cyclone® III Block Diagram (Return to Top)
Power Supply Block Diagram
Figure 3 – Cyclone III Block Diagram
TIDA-00604 - Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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Typical Voltage and Current Requirements in End Applications
Depending on application and design on FPGA, current consumption can vary. The table below
highlights the typical max currents each power output of the TPS65023 converters to the rails of
the Cyclone III. The VCCIO Rails on the Cyclone III range from 1.2 – 3.3V. The TPS65023 has 2
Linear Regulators (LDOs) that can supply the full range of Cyclone III’s VCCIO.
Cyclone III Supply Rails
VCCINT
VCC_PLL
VCCA
VCCIO_1.8
VCCIO_3.3
Voltage
1.2V
1.2V
2.5V
1.8V
3.3V
Supply Current (A)
1.7
1.2
1.0
0.2
0.2
Note: The current consumption numbers above are only estimates and the actual current
consumption may vary depending on the application.
Efficiency Curves (Return to Top)
DCDC1 (Vout=1.2V) – VCCINT
DCDC1 Efficiency vs Load Current @ Ta=25°C
100%
90%
80%
Efficinecy
70%
60%
50%
40%
30%
20%
10%
0%
0.00
0.00
0.01
0.10
1.00
10.00
Iout (A)
Vout = 1.2V
Vin = 3.3V (PWM Mode)
Vin = 5.0V (PWM Mode)
Vin = 3.3V (PFM/PWM)
Vin = 5.0V (PFM/PWM)
Figure 4 - DCDC1 Efficiency @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC2 (Vout=1.2V) – VCCPLL
Efficinecy
DCDC2 Efficiency vs Load Current @ Ta=25°C
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.0
0.0
0.0
0.1
1.0
10.0
Iout (A)
Vout = 1.2V
Vin = 3.3V (PWM Mode)
Vin = 5.0V (PWM Mode)
Vin = 3.3V (PFM/PWM)
Vin = 5.0V (PFM/PWM)
Figure 5 - DCDC2 Efficiency @ 25C
DCDC3 (Vout=2.5V) – VCCA
Efficinecy
DCDC3 Efficiency vs Load Current @ Ta=25°C
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.0
0.0
0.0
0.1
1.0
10.0
Iout (A)
Vout = 2.5V
Vin = 3.3V (PWM Mode)
Vin = 5.0V (PWM Mode)
Vin = 3.3V (PFM/PWM)
Vin = 5.0V (PFM/PWM)
Figure 6 - DCDC3 Efficiency @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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Load Regulation (Return to Top)
DCDC1 (Vout=1.2V) – VCCINT
DCDC1 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.0
0.0
0.1
1.0
10.0
1.0
10.0
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 7 – DCDC1 Load Regulation @ 25C
DCDC2 (Vout=1.2V) – VCCD_PLL
DCDC2 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.0
0.0
0.1
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 8 – DCDC2 Load Regulation @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC3 (Vout=2.5V) – VCCA
DCDC3 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.0
0.0
0.1
1.0
10.0
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 9 – DCDC3 Load Regulation @ 25C
Output Ripple Voltage (Return to Top)
DCDC1 (Vout = 1.2V) – VCCPINT (Light Load, PFM Mode)
Figure 10 – DCDC1 Voltage Ripple, Light Load @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC1 (Vout = 1.2V) – VCCPINT (Max Typical Load)
Figure 11 – DCDC1 Voltage Ripple, Max Load @ 25C
DCDC2 (Vout = 1.2V) – VCCD_PLL (Light Load, PFM Mode)
Figure 12 – DCDC2 Voltage Ripple, Light Load @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC2 (Vout = 1.2V) – VCCD_PLL (Max Typical Load)
Figure 13 – DCDC2 Voltage Ripple, Max Load @ 25C
DCDC3 (Vout = 2.5V) – VCCA (Light Load, PFM Mode)
Figure 14 – DCDC3 Voltage Ripple, Light Load @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC3 (Vout = 2.5V) – VCCA (Max Typical Load)
Figure 15 – DCDC3 Voltage Ripple, Max Load @ 25C
Load Transients (Return to Top)
Load transients for each of the DC-DC converters were completed by applying a load step of
0mA to around 50% of the max load for the converter under test. Rise time and fall time were
both set at 15µS. The regulators surpass specifications set for the Altera Cyclone Family.
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC1 (Vout = 1.2V) – VCCINT Load Step (0mA to 700mA, Rise Time: 15µS; Fall Time:15µS)
Figure 16 – DCDC1 Load Transient Response @ 25C
DCDC2 (Vout = 1.2V) – VCCD_PLL Load Step (0mA to 500mA, Rise Time: 15µS; Fall
Time:15µS)
Figure 17 – DCDC2 Load Transient Response @ 25C
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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DCDC3 (Vout = 2.5V) – VCCO_DDR, VCCO_1.5V Load Step (0mA to 500mA, Rise Time: 15µS;
Fall Time:15µS)
Figure 18 – DCDC3 Load Transient Response @ 25C
Design Considerations (Return to Top)
Altera® Cyclone® III Recommended Power Considerations
For reference, the power requirements from the Altera Cyclone III datasheet are shown below:
Power Supply
VCCINT
VCCIO
VCCA
VCCD_PLL
VREF (See Below)
Description
Core voltage power supply
I/O power supply to the input and output buffers in Bank 1 to Bank 6
Analog power supply for PLL
Digital power supply for PLL
Input reference voltage for voltage-references I/O standards
VCCIO and VREF Design Considerations
The VCCIO pin connections depend on the design’s I/O standards, and support 1.2, 1.5, 1.8, 2.5,
3.0 and 3.3 V. Each bank can support a different voltage level. The VREF pin serves as an input
reference voltage for the voltage reference I/O standards and is used mainly for a voltage bias
and does not source or sink much current. The voltage can be created with a regulator or a
resistor divider network. If voltage reference I/O standards are not used in the bank, the VREF
pins are available as user I/O pins
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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Cyclone III Noise Reduction
To reduce system noise, it is important to ensure that the power supply is clean. Place a ferrite
bead and bulk parallel capacitors where the power supply enters the board’s power plane to filter
out the noise to the power plane. Generally, the tantalum capacitors are used for circuits which
demand high stability in the capacitance values.
The ferrite bead should be connected in series between the power supply and the power plane,
while the capacitors are connected between the power plane and ground, in parallel with each
other. Decoupling depends on the design decoupling requirements of the specific board.
TPS65023 Power Sequencing
Though the Altera Cyclone III does not require a specific power sequencing to ensure proper
power up and power down, the TPS65023 offers flexible, customer driven power sequencing.
This is achieved by providing separate enable pins for each switch-mode converter and a
common enable signal for the LDOs. The table below shows the Pins used in the TPS65023 to
create a customized, customer driven power sequence.
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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Figure 10 – TPS65023 Example Startup Sequence
Inductor Selection for Buck Converters:
Each of the converters in the TPS65023 typically use a 2.2 μH output inductor. Larger or smaller
inductor values are used to optimize the performance of the device for specific operation
conditions. The selected inductor has to be rated for its dc resistance and saturation current. The
dc resistance of the inductance influences directly the efficiency of the converter. Therefore, an
inductor with lowest dc resistance should be selected for highest efficiency. For a fast transient
response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended. The
equation below calculates the maximum inductor current under static load conditions. The
saturation current of the inductor should be rated higher than the maximum inductor current as
calculated with the equation below. This is needed because during heavy load transient the
inductor current rises above the value calculated.
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Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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The following inductors have been used with the TPS6023:
Device
VALUE
2.2 µH, 2.5 A, 100
mΩ
2.2 µH, 1.7 A, 59
mΩ
2.2 µH, 1.6 A, 90
mΩ
1.5 µH, 1.75 A, 68
mΩ
All Converters
For DCDC2 or
DCDC3
For DCDC1
2.2 µH, 2.2 A, 80
mΩ
All Converters
TYPE
MANUFACTURER
LPS4012-222LMB
Coilcraft
VLCF4020T-2R2N1R7
TDK
LQH32PN2R2NN0
Murata
LQH32PN1R5NN0
Murata
PST25201B-2R2MS
Cyntec
Output Capacitor Selection
TPS65023, TPS65023B allow the use of small ceramic capacitors with a typical value of 10 μF
for each converter without having large output voltage under and overshoots during heavy load
transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and
are recommended.
At light load currents, the converters operate in PSM and the output voltage ripple is dependent
on the output capacitor value. The output voltage ripple is set by the internal comparator delay
and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output
voltage.
CAPACITOR VALUE
22µF
CASE SIZE
1206
COMPONENT SUPPLIER
TDK C3216X5R0J226M
Taiyo Yuden
JMK316BJ226ML
COMMENTS
Ceramic
22µF
1206
22µF
0805
TDK C2012X5R0J226MT
Ceramic
22µF
0805
Taiyo Yuden
JMK212BJ226MG
Ceramic
10µF
0805
Taiyo Yuden
JMK212BJ106M
Ceramic
10µF
0805
TDK C2012X5R0J106M
Ceramic
Ceramic
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input
capacitor is required for best input voltage filtering and minimizing the interference with other
circuits caused by high input voltage spikes. Each dc-dc converter requires a 10-μF ceramic
input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for
better input voltage filtering. The VCC pin is separated from the input for the dc-dc converters. A
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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filter resistor of up to 10R and a 1-μF capacitor is used for decoupling the VCC pin from
switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can
flow via this resistor into the VCC pin when all converters are running in PWM mode.
Low Ripple Mode
Low ripple mode can be enabled over I2C for all the DCDC converters if operated in PFM mode.
For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the
converter, the lower the output ripple voltage. For an output current above 10 mA, there is only
minor difference in output voltage ripple between PFM mode and low ripple PFM mode. As this
feature also increases switching frequency, it is used to keep the switching frequency above the
audible range in PFM mode down to a low output current.
Power Supply Recommendations
The device is designed to operate with an input voltage supply range between 2.5V and 6.0V.
This input supply can be from a single cell Li-Ion battery or other externally regulated supply.
The low power section of the control circuit for the step-down converters DCDC1, DCDC2 and
DCDC3 is supplied by the Vcc pin while the circuitry with high power such as the power stage is
powered from the VINDCDC1, VINDCDC2 and VINDCDC3 pins. For proper operation of the
step-down converters, VINDCDC1, VINDCDC2,VNDCDC3 and Vcc need to be tied to the same
voltage rail. Step-down converters that are planned to be not used, still need to be powered from
their input pin on the same rails than the other step-down converters and Vcc.
LDO1 and LDO2 share a supply voltage pin which can be powered from the Vcc rails or from a
voltage lower than Vcc e.g. the output of one of the step-down converters as long as it is
operated within the input voltage range of the LDOs. If both LDOs are not used, the VINLDO pin
can be tied to GND.
Layout Guidelines
Provide a low impedance ground path
o Use wide and short traces for the main current paths.
The input capacitors should be placed as close as possible to the IC pins as well as the
inductor and output capacitor
Connect the PGND pins of the device to the PowerPAD™ land of the PCB
Connect the analog ground connections (AGND) to the PGND at the PowerPAD™
Keep the common path to the AGND pins, which returns the small signal components,
and the high current of the output capacitors as short as possible to avoid ground noise.
The VDCDCx line should be connected right to the output capacitor and routed away
from noisy components and traces
TIDA-00604 – Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
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QFN Package Information
TIDA-00604 - Test Report
Powering the Altera® Cyclone® III with TPS65023 Power Management IC
Copyright © 2015, Texas Instruments Incorporated
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