Triple Inverter Gate, SN74LVC3GU04 (Rev. D)

SN74LVC3GU04
www.ti.com
SCES539D – JANUARY 2004 – REVISED DECEMBER 2013
Triple Inverter Gate
Check for Samples: SN74LVC3GU04
FEATURES
DESCRIPTION
•
This triple inverter is designed for 1.65-V to 5.5-V VCC
operation.
1
2
•
•
•
•
•
•
•
•
•
•
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Available in the Texas Instruments NanoFree™
Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 3.9 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Support Live Insertion, Partial Power Down
Mode and Back Drive Protection
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
The SN74LVC3GU04 contains three inverters with
unbuffered outputs and performs the Boolean
function Y = A.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
DCU PACKAGE
(TOP VIEW)
1A
1
8
VCC
3Y
2
7
1Y
2A
3
6
3A
GND
4
5
2Y
1A
3Y
2A
GND
1
8
2
7
3
6
4
5
YZP PACKAGE
(BOTTOM VIEW)
VCC
1Y
3A
2Y
GND
2A
3Y
1A
4 5
3 6
2 7
1 8
2Y
3A
1Y
VCC
See mechanical drawings for dimensions.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
SN74LVC3GU04
SCES539D – JANUARY 2004 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
Logic Diagram (Positive Logic)
1A
2A
3A
1
7
3
5
6
2
1Y
2Y
3Y
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
(2)
MIN
MAX
–0.5
6.5
UNIT
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through VCC or GND
θJA
Tstg
(1)
(2)
(3)
(4)
2
Package thermal impedance (4)
DCT package
220
DCU package
227
YZP package
102
Storage temperature range
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Product Folder Links: SN74LVC3GU04
SN74LVC3GU04
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SCES539D – JANUARY 2004 – REVISED DECEMBER 2013
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
IO = –100 μA
VIL
Low-level input voltage
IO = 100 μA
VI
Input voltage
VO
Output voltage
MIN
MAX
1.65
5.5
V
0.25 × VCC
V
0
5.5
V
0
VCC
V
–4
VCC = 2.3 V
High-level output current
–8
–16
VCC = 3 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
Low-level output current
8
16
VCC = 3 V
(1)
mA
24
VCC = 4.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
0.75 × VCC
VCC = 1.65 V
IOH
UNIT
32
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETE
R
TEST CONDITIONS
VCC
1.65 V to
5.5 V
IOH = –100 mA
VOH
VIL = 0 V
MIN
VCC – 0.1
VCC – 0.1
1.65 V
1.2
1.2
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3.8
3.8
3V
TYP (1)
MAX
4.5 V
IOL = 100 mA
1.65 V to
5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.75
0.55
0.75
3V
IOL = 24 mA
IOL = 32 mA
4.5 V
UNIT
V
IOH = –32 mA
IOL = 16 mA
V
VI = 5.5 V or GND
0 to 5.5 V
±5
±5
μA
ICC
VI = 5.5 V or GND, IO = 0
1.65 V to
5.5 V
10
10
μA
Ci
VI = VCC or GND
II
(1)
–40°C to 125°C
MAX
IOH = –8 mA
IOH = –24 mA
VIH = VCC
TYP (1)
IOH = –4 mA
IOH = –16 mA
VOL
–40°C to 85°C
MIN
3.3 V
7
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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3
SN74LVC3GU04
SCES539D – JANUARY 2004 – REVISED DECEMBER 2013
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC3GU04
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
0.2
9.2
0.2
4
0.6
3.9
0.5
3.2
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC3GU04
–40°C to 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
0.2
10.5
0.2
4.5
0.6
4.7
1.1
4
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
8
8
11
23
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UNIT
pF
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC3GU04
SN74LVC3GU04
www.ti.com
SCES539D – JANUARY 2004 – REVISED DECEMBER 2013
Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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Product Folder Links: SN74LVC3GU04
5
SN74LVC3GU04
SCES539D – JANUARY 2004 – REVISED DECEMBER 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (Feburary 2007) to Revision D
Page
•
Updated document to new TI data sheet format. ................................................................................................................. 1
•
Removed Ordering Information table. ................................................................................................................................... 2
•
Added ESD warning. ............................................................................................................................................................ 2
•
Updated operating temperature range. ................................................................................................................................. 3
6
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Copyright © 2004–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
TBD
Call TI
Call TI
-40 to 125
Device Marking
(4/5)
74LVC3GU04DCURE4
ACTIVE
VSSOP
DCU
8
SN74LVC3GU04DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CU4
Z
SN74LVC3GU04DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(CU4Q ~ CU4R)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC3GU04DCUR
VSSOP
DCU
8
3000
178.0
9.5
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC3GU04DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC3GU04DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC3GU04DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
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