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24-V DC,10-A eFuse and Protection Circuit for
Programmable Logic Controllers (PLC)
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VIN Shunt
Protection
– Configurable Undervoltage Lockout (UVLO) and
Overvoltage Lockout (OVLO)
– Overcurrent Protection (OCP)
– Reverse Current protection
– Reverse Polarity Protection
– Miswire Protection
– Surge Protection (IEC61000-4-5)
Low Power Operation
– 0.5-mA Quiescent Current
– 99% Efficiency in Normal Operation
Programmable Logic Controller
– Power Supply
– CPU
– I/O Module
Distributed Control System (DCS)
Motor Control
Sensor Concentrators
VOUT
Q1
Q2
LM5069
OVLO, UVLO, OCP
LM5050
Miswire
ReverseCurrent
Protection
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
All trademarks are the property of their respective owners.
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24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
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Copyright © 2014, Texas Instruments Incorporated
1
System Description
1
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System Description
+24-V DC(field)
Power
protection
Surge, miswire, overcurrent and reverse
current protection
Signal
Power
Protected internal 24V
Interface
Power
Level
Shifter
Coms
ISO
De-serializer
IF
Status
LED
> 500V Isolation
And
PCB boundary
Highside
Driver
Overcurrent
and Short
Protection
O1
Diagnostic/
Wire break
1st channel
Output
LED
nth channel
PLC side
On
Field side
Figure 1. Use of This Design (Orange Block) in System Context (High Side Driver with 24-V Field Supply)
PLC or Distributed Control System (DCS) I/O modules connected to a field power supply capable of
delivering stable 24-V DC at high power benefit from protection on the 24-V, field-input connectors. The
reason that the PLC or DCS modules may benefit from protection is due to power-supply faults or
miswiring. Power-supply faults or miswiring might damage the modules or cause the modules to not
operate correctly. OVLO and UVLO protect integrated circuits (ICs) on the I/O module from voltages
outside of the operating range which might permanently damage the modules, make the modules
nonfunctional, or cause the modules to operate in an undesired region. An example of an undesired
region is the linear region of MOSFETs, with large resulting power dissipation.
A field power supply is often connected to multiple I/O modules. A field power supply is capable of
delivering more current than a single I/O module can handle. OCP limits the current from the power supply
to the module so that the maximum current does not rise above what the board is designed for. OCP also
acts as a short circuit protection (SCP) as the maximum current is limited to 10 A.
The design also acts as a smart diode with protection against reverse current. A reverse current could
damage the field power supply and cause other ICs on the module to run hot or cause permanent
damage. A Schottky diode is often used to provide protection against reverse current with the
disadvantage that the forward-voltage drop causes a permanent power loss. At high currents, a
permanent power loss becomes significant in normal operation mode. At 10 A, the forward loss with a
Schottky diode is approximately 7 W. At 10 A, the forward loss with the smart diode function in this design
is approximately 1 W.
If the field power supply is connected with reverse polarity (which is not unlikely as field power supplies
are usually connected with screw terminals), ICs connected after connecting the power supply will not
operate as desired and potentially receive permanent damage. The reverse polarity protection in this
design will prevent the reverse power from getting into the module. If the field power supply is connected
to an input or output of the module, the miswire protection breaks the path that might cause the current to
flow from an input or output to the field supply input.
NOTE: Status LEDs on the board indicate input and output voltage.
2
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
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Design Features
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2
Design Features
2.1
Specifications
Table 1. Specifications (1)
SYMBOL
VIN
Input voltage
IQ
Quiescent current
VOVLO_DIS
SPECIFICATION
CONDITIONS
MIN.
TYP.
UNIT
MAX.
Normal operation
-33
24
33
V
Normal operation
5
7.6
10
mA
OVLO output disabled
VIN increasing
-
32.5
33.0
VOVLO_EN
OVLO output re-enabled
VIN decreasing
29.9
30.5
tOVLO
OVLO delay
VIN increasing
UUVLO_EN
UVLO output enabled
VIN increasing
UUVLO_DIS
UVLO output disabled
VIN decreasing
IOCP
OCP
VIN = 12 V to 30 V
tOCP
OCP delay
IIN > IOCP
tSCP
SCP delay
IIN > 2 × IOCP
IREV_POL
Reverse polarity protection current
VIN = -30 V or -10 V
IMIS
Miswire and reverse-current
protection current
VIN = 10 V, 12 V, or 30 V
tREV
Miswire and reverse-current
protection delay
(1)
(2)
3
PARAMETER
(2)
V
-
V
50
µs
12.64
V
V
-
12.4
11.29
11.4
-
-
10.3
11
A
50
µsSpe
2.0
0.5
µs
0.1
1
µA
2.2
3
mA
40
100
ns
Ambient temperature TA = 25°C
Without indicator LEDs, the quiescent current is reduced by 2 x I_LED = 2 x 2.2 mA (Vin = 24 V) = 4.4 mA.
Block Diagram
VIN Shunt
VOUT
Q1
Q2
LM5069
OVLO, UVLO, OCP
LM5050
Miswire
ReverseCurrent
Protection
Figure 2. Simplified Block Diagram with the High Power Path between V IN and VOUT
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3
Component Description
4
Component Description
4.1
MOSFET Controllers
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This design is using two MOSFET controllers to regulate the circuit’s high power path. The LM5069-2 (U1)
is a high voltage controller with OVLO, UVLO, and current sense capability over an external shunt resistor.
OVLO and UVLO are set with external resistor dividers. The OCP is set with a shunt resistor in the high
power path. The LM5069-2 is controlling MOSFET Q1.
The LM5050-1 (U2) is also a MOSFET controller, that with an external MOSFET (Q2), becomes and ideal
diode. The ideal diode is used to protect the high power path from reverse current due to miswiring or
reverse polarity.
4.2
MOSFET
Two CSD18532Q5B (Q1 and Q2), 60-V, 2.5-mΩ RDS(on) MOSFETs are used in the high power path,
connected back-to-back, to control the current. The low RDS(on) helps reduce the power loss and heat
dissipation.
5
Circuit Design and Component Selection
Figure 3. Circuit Schematics
5.1
UVLO and OVLO
From VIN(MIN) to VUVLO_EN, the design blocks VIN from reaching the output terminals (J3 and J4). From
VUVLO_EN to VOVLO_DIS, the design passes VIN to the output. From VOVLO_DIS to VIN(MAX), the design blocks VIN
from reaching the output. For VIN < VIN(MIN) or VIN > VIN(MAX), the behavior is set by the TVS diodes (D1 and
D4), which block surge voltages above the reverse standoff voltage VR = 33 V.
Therefore, VIN(MAX) = 33 V.
UVLO and OVLO is performed by a function in U1. The resistor divider R1 and R2 is setting the threshold
level for OVLO. The resistor divider R3 and R4 is setting the threshold for UVLO. Keeping both dividers
separate enables different hysteresis settings for UVLO and OVLO. The resistor values are calculated with
Equation 1 through Equation 4.
4
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
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Circuit Design and Component Selection
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Once U1 detects a VIN undervoltage or overvoltage condition, the output is turned off. Shifting load current
on the output can lead to input-voltage variations in the supply voltage and trigger repeated lockout
conditions. The hysteresis should be selected so that an input-voltage change due to output-current
changes does not trigger a lockout. In this design, the overvoltage hysteresis, VOV(HYS) (VOVLO_DIS - VOVLO_EN)
has been set to 2 V and the undervoltage hysteresis, VUV(HYS) (VUVLO_EN - VUVLO_DIS) has been set to 1 V.
UVLO and OVLO resistor divider equations are shown in Equation 1 through Equation 4:
R1
R2
R3
R3
VOV HYS
21$
2.5 V u R 1
VOVLO_DIS 2.5 V
VUV HYS
(1)
(2)
21 $
VUV HYS
(3)
21 $
(4)
If an overvoltage lockout condition is detected by U1, the gate of Q1 will be discharged with 2 mA. Using
Q1’s gate capacitance of 5.6 nF as the the turn off time, tOVLO = 50 µs.
5.2
Overcurrent Protection (eFuse)
OCP is set by R6 and R7. If the voltage drop across the parallel resistors exceeds 55 mV, which equals
11 A in the high power path, U1 pulls the gate voltage of Q1 low. The tOCP is measured to 50 µs. If the
voltage drop exceeds 110 mV, which equals 22 A (2 × IOCP, short circuit condition) in the high power path,
tSCP is 0.5 µs to prevent damage of Q1. C2 = 0.47 uF gives a 340-ms insertion time. Ambient conditions
(for example, temperature and air flow) can vary depending on implementation. Therefore, a thermal
analysis is needed to select C2 and R5. R5 = 57.6 kΩ with R6||R7 = 5 mΩ, which corresponds to 100-W
power dissipation in Q1. See LM5069 Positive High Voltage Hot Swap / Inrush Current Controller with
Power Limiting, Data Sheet LM5069-2 for selection information on selection of C2 and R5.
R6||R7 sets the over current protection, IOCP(MAX) = 11 A. R6||R7 are non-Kelvin type resistors without
separate voltage sense pins which cause additional resistance in the layout so that IOCP(TYP) = 10.3 A.
5.3
Reverse Polarity Protection
If the input (J1 and J2) is connected to a power supply with reverse polarity, so that VIN becomes negative,
the design will block this voltage from reaching the output. The input current under this condition is
specified by IREV_POL. A negative VIN will connect D2 with the GND pins of U1 and U2 to VIN. As the VDD pins
of U1 and U2 are connected to the same potential, both devices remain unpowered and Q1 and Q2
remain in high-impedance state. At negative VIN , the body diode of Q1 conducts the input voltage to the
drain of Q2. The high impedance in Q2 is blocking the voltage from the output of the design.
5.4
Miswire and Reverse Current Protection
Miswire and reverse-current protection are implemented using U2 to measure the source-drain voltage
drop of Q2. If the voltage drop is negative, the gate of Q2 is pulled low, preventing a reverse-current flow
to the input. This function also prevents the charge from an external output capacitor to flow back into the
power supply, eliminating adverse effects from an input-voltage drop. A short turnoff time is desired to
reduce the capacitor discharge from this reverse current. In this design the turnoff time tREV(MAX) = 100 ns.
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5
Circuit Design and Component Selection
5.5
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Surge Protection
Surge protection is implemented using multiple stages. The first level of protection is given by the TVS
diode, D1. When tested at 0.5 kV over 2 Ω, the surge pulse reaches 250 A. In this case, the voltage
across D1 will rise above 55 V, and an additional protection stage is activated. The high voltage across D1
is causing a current higher than 22 A through D4, which triggers the short-circuit protection described in
Section 5.2. As tSCP = 0.5 µs, Q1 will turn to a high-impedance state before the 8/20 us current pulse
generates a voltage exceeding 45 V across D4. The designer may add a capacitor to the output of the
design covering the power interrupt caused by the surge pulse.
6
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
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Test Setup
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6
Test Setup
6.1
UVLO and OVLO
Power Supply: Hewlett Packard E3631A triple-output DC power supply 0 V to 6V, 5 A and, 0 - ±25 V, 1A
Multimeter: Wavetek 23XT
J1 (red) of the DUT is connected to the positive terminal of the power supply and J2 (black) to the
negative terminal. The negative supply is set to 10 V and the positive supply can be adjusted from 0 V to
25 V. For safety reasons, the current limit is set to 50 mA.
The overvoltage lockout thresholds (VOVLO_DIS and VOVLO_EN) are tested by increasing the positive supply
from 20 V until D8 turns off and then decreasing the positive supply until D8 turns on.
The undervoltage lockout thresholds (VUVLO_DIS and VUVLO_EN) are tested by increasing the positive supply
from 0 V until D8 turns on and then decreasing the positive supply until D8 turns off.
DC
J1
red
0 to 25 V
J3
red
+
+
Input
V
Output
DUT
±
DC
V
±
J2
black
10 V
J4
black
UVLO, OVLO
Figure 4. Measurement setup for over and under voltage lockout
6.2
Overcurrent Protection (eFuse)
Power Supply: Agilent 6574A 0 – 60V, 0-A to 35-A DC power supply
Electronic Load: Agilent 6060B 3-V to 60-V, 0-A to 60-A system DC electronic load
Multimeter: METRAHIT pro professional TRMS
J1 (red) of the DUT is connected to the positive terminal of the power supply and J2 (black) to negative
terminal. In the first test VIN = 12 V, and in the second test, VIN = 30 V with the electronic load connected
to J3 (red) and J4 (black). Under both test conditions, the load of the DUT is sequentially set to 2 A, 6 A, 8
A, and 10 A. The board temperature is monitored at each test point. At 10 A, the load current is slowly
increased until the DUT turns off the output voltage.
WARNING
The operator has to take the usual precautions when handling high
currents.
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Test Setup
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J1
red
J3
red
A
+
DC
Input
V
0 to 33 V
Output
DUT
t
Electronic
Load
J4
black
J2
black
Over current
Figure 5. Measurement Setup for Circuit Breaker Function
6.3
Reverse Polarity Protection
Power Supply: Hewlett Packard E3631A triple-output DC power supply 0 V to 6V, 5 A and 0 - ±25 V, 1A
Multimeter: Wavetek 23XT
The DUT is connected to the ±25 V output of the power supply. J1 (red) is connected to the negative
terminal of the power supply and J2 (black) is connected to the positive terminal. The negative supply is
set to 10 V. The positive supply is set to 0 V, resulting in VIN = -10 V. This process is repeated for VIN = -30
V, with the positive supply set to 20 V. For safety reasons, the current limit is set to 50 mA.
DC
J1
red
0 to 25 V
J3
red
±
±
Input
V
Output
DUT
+
DC
10 V
V
+
J2
black
J4
black
Reverse polarity
Figure 6. Measurement Setup for Reverse Polarity Current Measurement
6.4
Miswire and Reverse Current Protection
Power Supply: Hewlett Packard E3631A triple-output DC power supply 0 V to 6V, 5 A and, 0 - ±25 V, 1A
Multimeter: Wavetek 23XT
The DUT is connected to the ±25 V output of the power supply. J3 (red) is connected to the positive
terminal of the power supply and J4 (black) is connected to the negative terminal. The negative supply is
set to 10 V. The positive supply is set to 0 V, resulting in VIN = 10 V. This process is repeated for VIN = 30
V, with the positive supply set to 20 V. For safety reasons, the current limit is set to 50 mA.
IMIS is measured with the multimeter (ampere meter) connected to J1 (red) and J2 (black).
8
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
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Test Setup
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J1
red
J3
red
0 to 25 V
+
A
DC
+
Input
V
Output
DUT
±
±
J2
black
J4
black
10 V
DC
Miswire
Figure 7. Measurement Setup for Miswire Protection Current Measurement
6.5
Surge Protection
EFT/Surge/ESD Generator: AMETEK, EM TEST UCS500N
Oscilloscope: Tektronix TPS2014B
The design is tested according to IEC61000-4-5 (1.2/50 µs, 2.0 Ω, 18 uF) ±0.5 kV surge specification.
Compliance is confirmed in two separate tests.
6.5.1
Test 1: Power Supply Surge Test
VIN = 28 V. The surge pulse is injected using a surge generator with coupling network as described in
Figure 8. Test 1 is performed with 4 different loads: open circuit, IL = 280 mA, 10A, and short circuit,
connected to J3 (red) and J4 (black). The correct function of the design is first verified using a multimeter
with a peak detector. A battery-powered oscilloscope is then connected in parallel with the load to record
UL. The surge pulse is applied 5 times at 0.5 kV and 5 times at -0.5 kV.
DC
28 V
Surge
Generator
and
coupling
J1
red
J3
red
DUT
Input
J2
black
Output
Load
J4
black
Oscilloscope
Transient recorder
Surge protection
Figure 8. Measurement Setup for Surge Test
6.5.2
Test 2: Reverse Power Surge Test
The power supply is connected to J3 and J4 with a voltage set to 28 V. An oscilloscope is connected
between J1 and J2 to record transients. The surge pulse is injected using a surge generator with coupling
network to J3, as described in Figure 9.
To verify proper operation of the surge protection, Test 1 is repeated after Test 2 with the same DUT, to
ensure Test 2 caused no derating.
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Test Setup
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J1
red
DUT
Input
Oscilloscope
Transient recorder
J3
red
J2
black
Output
Surge
Generator
and
coupling
28 V
DC
J4
black
Reverse surge protection
Figure 9. Measurement Setup for Reverse Power Surge Test
10
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
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Test Results
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7
Test Results
7.1
Measurement Results
Table 2 shows the test results for normal operation and during surge conditions.
Table 2. Test Results Compared to Design Specification
SYMBOL
(1)
PARAMETER
CONDITIONS
SPECIFICATION
MIN.
TYP.
MEAS.
MAX.
UNIT
VIN
Input voltage
Normal operation
-33
24
33
IQ
Quiescent current (1)
Normal operation
5
7.6
10
7.6
mA
V
V
VOVLO_DIS
OVLO output disabled
VIN increasing
-
32.5
33.0
32.5
VOVLO_EN
OVLO output re-enabled
VIN decreasing
29.9
30.5
-
30.5
V
tOVLO
OVLO delay
VIN increasing
50
TBM
µs
UUVLO_EN
UVLO output enabled
VIN increasing
-
12.4
12.64
12.45
V
UUVLO_DIS
UVLO output disabled
VIN decreasing
11.29
11.4
-
11.49
V
IOCP
OCP
VIN = 12 V or 30 V
-
10.3
11
10.3
A
tOCP
OCP delay
I > IOCP
50
TBM
µs
tSCP
SCP delay
I > 2 × IOCP
0.5
TBM
µs
IREV_POL
Reverse polarity protection current
VIN = -30 V or -10 V
0.1
1
0.1
µA
IMIS
Miswire and reverse-current
protection current
VIN = 10 V, 12 V, or 30 V
2.2
3
2.2
mA
tREV
Miswire and reverse-current
protection delay
40
100
TBM
ns
VSURGE_pp
Peak output voltage during surge
VIN = 30 V+ 500 V surge
2.0
0.0
45
V
Without indicator LEDs, the quiescent current is reduced by 2 x I_LED = 2 x 2.2 mA (Vin = 24 V) = 4.4 mA.
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Test Results
7.2
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Surge Protection
Figure 10 through Figure 15 show the output voltage of the protection device at different load conditions
during a surge pulse of 500 V. The device is effectively blocking all dangerous input voltages towards the
load. The maximum output voltage exists during lightly loaded conditions. In that case, the output voltage
reaches its maximum at 45 V before it shuts down for 250 ms. Also, a negative output voltage could be
observed, which is low energy and results from capacitive coupling through MOSFETs Q1 and Q2.
Figure 10. Output Voltage of the Protection Device during Surge at No Load
Figure 11. Zoom into the Waveform in Figure 10 at the Surge Location
Figure 12. Output Voltage of the Protection Device during Surge at 100-Ω Load
Figure 13. Zoom into Figure 12
12
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
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Test Results
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Figure 14. Output Voltage of the Protection Device during Surge at 15-Ω Load
Figure 15. Zoom into Figure 14
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13
Design Files
8
Design Files
8.1
Schematics
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To download the Schematics, see the design files at TIDA-00233.
Figure 16. Schematics — Protection
14
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic Controllers
(PLC)
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Design Files
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8.2
Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-00233.
Table 3. BOM
DESIGNATOR
DESCRIPTION
MANUFACTURER
PARTNUMBER
QTY
SUPPLIER 1
SUPPLIER P/N 1
SUPPLIER 2
SUPPLIER P/N 2
C1
CAP, CERM,
1000pF, 100V, +/5%, X7R, 0603
AVX
06031C102JAT2A
1
Digi-Key
478-3698-1-ND
Mouser
581-06031C102J
C2
CAP, CERM,
0.47uF, 50V, 10%,
X5R, 0603
Taiyo Yuden
UMK107ABJ474KA 1
-T
Digi-Key
587-3171-6-ND
C3, C5, C6
CAP, CERM,
0.1uF, 100V, +/10%, X7R, 0603
MuRata
GRM188R72A104
KA35D
3
Digi-Key
490-3285-1-ND
Mouser
81GRM188R72A104
KA35
C4
CAP, CERM,
4.7uF, 100V, +/10%, X7S, 1210
TDK
C3225X7S2A475K
200AB
1
Digi-Key
445-6042-1-ND
Mouser
810C3225X7S2A475K
D1, D4
Diode, TVS, Bi,
33V, 1500W, SMC
Littlefuse
SMCJ33CA
2
Digi-Key
SMCJ33CALFCTND
Mouser
576-SMCJ33CA
D2, D3, D5, D9
Diode, Switching,
100V, 0.15A, 0603
Diode
Bourns
CD0603-S01575
2
Digi-Key
CD0603S01575CT-ND
Mouser
652-CD0603S01575
D6
LED, Red, SMD
Lite-On
LTST-C190CKT
1
Digi-Key
160-1181-1-ND
Mouser
859-LTSTC190CKT
D7
LED, Blue, SMD
OSRAM
LB Q39G-L2N2-35- 1
1
Digi-Key
475-2816-1-ND
Mouser
720LBQ39GL2N2351
D8
LED, Green, SMD
Lite-On
LTST-C190KGKT
1
Digi-Key
160-1435-1-ND
Mouser
859-LTSTC190KGKT
H2, H5, H8, H11
Standoff, Hex, 0.5
in.L #4-40 Nylon
Keystone
1902C
4
Digi-Key
1902CK-ND
H3, H6, H9, H12
Machine Screw,
Round, #4-40 x
1/4, Nylon, Philips
panhead
B and F Fastener
Supply
NY PMS 440 0025
PH
4
Digi-Key
H542-ND
J1, J3
Standard Banana
Jack, insulated,
10A, red
DEM
Manufacturing
571-0500
2
Newark
30M0087
Mouser
164-6219
J2, J4
Standard Banana
Jack, insulated,
10A, black
DEM
Manufacturing
571-0100
2
Newark
45M6896
Mouser
164-6218
LBL1
Thermal Transfer
Brady
Printable Labels,
0.650 in. W x 0.200
in. H
THT-14-423-10
1
Newark
97C5133
Farnell
2065596
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24-V DC,10-A eFuse and Protection Circuit for Programmable Logic Controllers
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Copyright © 2014, Texas Instruments Incorporated
15
Design Files
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Table 3. BOM (continued)
DESIGNATOR
DESCRIPTION
MANUFACTURER
PARTNUMBER
QTY
SUPPLIER 1
SUPPLIER P/N 1
SUPPLIER 2
SUPPLIER P/N 2
Q1, Q2
MOSFET, N-CH,
60V, 172A, SON
5x6mm
Texas Instruments
CSD18532Q5B
2
Digi-Key
296-35628-1-ND
Mouser
595CSD18532Q5B
R1
RES, 95.3k ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW060395K3F
KEA
1
Digi-Key
541-95.3KHCT-ND
Mouser
71-CRCW060395.3K-E3
R2
RES, 8.06k ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW06038K06F
KEA
1
Digi-Key
541-8.06KHCT-ND
Mouser
71-CRCW06038.06K-E3
R3
RES, 47.5k ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW060347K5F
KEA
1
Digi-Key
541-47.5KHCT-ND
Mouser
71-CRCW060347.5K-E3
R4
RES, 14.0k ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW060314K0F
KEA
1
Digi-Key
541-14.0KHCT-ND
Mouser
71-CRCW060314K-E3
R5
RES, 56.0k ohm,
0.1%, 0.1W, 0603
Vishay-Dale
CRCW060357K6F
KEA
1
Digi-Key
541-57.6KHCT-ND
Mouser
71-CRCW060357.6K-E3
R6, R7
RES, 0.01 ohm,
1%, 1W, 1206
Vishay-Dale
WSLP1206R0100F 2
EA
Digi-Key
WSLP-.01CT-ND
Mouser
71WSLP1206R0100F
EA
R8, R10, R11
RES, 10.0k ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW060310K0F
KEA
3
Digi-Key
541-10.0KHCT-ND
Mouser
71-CRCW060310K-E3
R9
RES, 100 ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW0603100RF
KEA
1
Digi-Key
541-100HCT-ND
Mouser
71-CRCW0603100-E3
TP1
Test Point,
Miniature, Black,
TH
Keystone
5001
1
Digi-Key
5001K-ND
TP2, TP3
Test Point,
Miniature, Red, TH
Keystone
5000
2
Digi-Key
5000K-ND
U1
Positive High
Texas Instruments
Voltage Hot Swap /
Inrush Current
Controller
LM5069MM2/NOPB
1
Digi-Key
LM5069MM2/NOPBTR-ND
U2
LM5050-1 High
Side OR-ing FET
Controller
LM5050MK1/NOPB
1
Digi-Key
LM5050MK1/NOPBTR-ND
16
Texas Instruments
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic Controllers
(PLC)
Copyright © 2014, Texas Instruments Incorporated
TIDU415 – August 2014
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Design Files
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8.3
Layout Guidelines
To withstand the IEC61000-4-5 (1.2/50 µs) ±0.5 kV surge specification, the PCB layout needs special
attention. The surge current is passed over the pads of D1 and D4. The trace width has to be at least 8
mm for longer traces in free air to support IOCP(MAX) = 11 A. As the 24-V pin of D1 has a short trace, D1
provides additional cooling area and the trace width is reduced to 6 mm. The other high power traces are
laid out as copper areas.
Q1 and Q2 are cooled using PCB copper area. The PCB copper area size needs to be large enough to
dissipate the heat over the design's operating temperature range. Q1 has a copper area of 1.2 cm2
available on the top layer and 1.1 cm2 on the bottom layer. Q2 has a copper area of 0.5 cm2 available on
the top layer and 1.8 cm2 on the bottom layer.
R6||R7 are preferably resistors of Kelvin type, where the high power path uses separate connection pads
in addition to the pads for the SENSE and VIN pins of the U1. See Figure 17. To optimize the design for
footprint, resistors of non-Kelvin type are used, which adds the R6||R7 pads’ resistance so that IOCP(TYP) =
10.3 A.
Figure 17. U1 SENSE and VIN Pin Pad Connection using Resistors of Kelvin Type
Figure 18. All Layers
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24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
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Design Files
8.4
www.ti.com
Layer Plots
To download the layer plots, see the design files at TIDA-00233.
18
Figure 19. Top Silkscreen
Figure 20. Top Solder Mask
Figure 21. Top Layer
Figure 22. Bottom Layer
Figure 23. Bottom Solder Mask
Figure 24. Bottom Silkscreen
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
TIDU415 – August 2014
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Design Files
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Figure 25. Drill Drawing
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Figure 26. Board Dimensions
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
19
Design Files
8.5
www.ti.com
Altium Project
To download the Altium project files, see the design files at TIDA-00233.
Figure 27. All Layers
8.6
Gerber Files
To download the Gerber files, see the design files at TIDA-00233
8.7
Assembly Drawings
Figure 28. Top Assembly Drawing
8.8
Figure 29. Bottom Assembly Drawing
Software Files
To download the software files, see the design files at TIDA-00233
9
References
1. LM5050-1/LM5050-1-Q1 High Side OR-ing FET Controller, Data Sheet LM5050-1
2. LM5069 Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting, Data Sheet
LM5069-2
20
24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
TIDU415 – August 2014
Submit Documentation Feedback
About the Author
www.ti.com
10
About the Author
INGOLF FRANK is a systems engineer in the Texas Instruments Industrial Automation Team, focusing on
programmable logic controller I/O modules. Ingolf works across multiple product families and technologies
to leverage the best solutions possible for system level application design. Ingolf earned his Electrical
Engineering degree (Dipl. Ing. (FH)) in the field of information technology at the University of Applied
Sciences Bielefeld, Germany in 1991.
HENRIK MANNESSON is a System Engineer at Texas Instruments Germany, in the Factory Automation
and Control System Team. Henrik earned his Master of Science in Electrical Engineering (MSEE) from
Lunds University of Technology (LTH), Lund, Sweden.
TIDU415 – August 2014
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24-V DC,10-A eFuse and Protection Circuit for Programmable Logic
Controllers (PLC)
Copyright © 2014, Texas Instruments Incorporated
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