SN65LVEL11 www.ti.com............................................................................................................................................................................................ SLLS927 – DECEMBER 2008 3.3 V ECL 1:2 Fanout Buffer FEATURES 1 • • • • • • • • • 1:2 ECL Fanout Buffer Operating Range – PECL VCC = 3.0 V to 3.8 V With VEE = 0 V – NECL: VCC = 0 V with VEE = –3.0 to –3.8V 5 ps Skew Between Outputs Support for Clock Frequencies > 2.0 GHz 265 ps Typical Propagation Delay Deterministic Output Value for Open Input Conditions or When Inputs = VEE Built-in Temperature Compensation Drop in Compatible to MC10LVEL11, MC100LVEL11 Built-In Input Pull Down Resistors DESCRIPTION The SN65LVEL11 is a fully differential 1:2 ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in open condition. The SN65LVEL11 is functionally equivalent to SN65EL11 with improved performance. The SN65LVEL11 is housed in an industry standard SOIC-8 package and is also available in the TSSOP-8 package option. PINOUT ASSIGNMENT Q0 1 8 VCC Q0 2 7 D Q1 3 6 D Q1 4 5 VEE APPLICATIONS • • Data and Clock Transmission Over Backplane Signaling Level Conversion Table 1. Pin Description PIN FUNCTION D, D PECL/ECL data inputs Q0, Q0, Q1, Q1 PECL/ECL outputs VCC Positive supply VEE Negative supply ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE LEAD FINISH SN65LVEL11D SN65LVEL11DGK SN65LVEL11 SOIC NiPdAu SN65LVEL11 SOIC-TSSOP NiPdAu Leaded device options not initially available. Contact TI sales representative for further details. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN65LVEL11 SLLS927 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) PARAMETER CONDITION VALUE UNIT Absolute PECL mode supply voltage, VCC VEE = 0 V 6 V Absolute NECL mode power supply, VEE VCC = 0 V –6 V PECL mode input voltage VEE = 0 V; VI ≤ VCC 6 V NECL mode input voltage VCC = 0 V; VI ≥ VEE –6 V Continuous 50 Surge 100 Output current mA Operating temperature range –40 to 85 °C Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POWER DISSIPATION RATINGS PACKAGE CIRCUIT BOARD MODEL POWER RATING TA < 25°C (mW) THERMAL RESISTANCE, JUNCTION TO AMBIENT NO AIRFLOW DERATING FACTOR TA > 25°C (mW/°C) POWER RATING TA = 85°C (mW) SOIC SOIC-TSSOP Low-K 719 139 7 288 High-K 840 119 8 336 Low-K 469 213 5 188 High-K 527 189 5 211 THERMAL CHARACTERISTICS PARAMETER θJB Junction-to Board Thermal Resistance θJC Junction-to Case Thermal Resistance PACKAGE VALUE UNIT °C/W SOIC 79 SOIC-TSSOP 120 SOIC 98 SOIC-TSSOP 74 °C/W KEY ATTRIBUTES CHARACTERISTICS Internal input pull down resistor VALUE 75 kΩ Moisture sensitivity level Level 1 Flammability rating (Oxygen Index: 28 to 34) UL 94 V-0 at 0.125 in ESD-HBM 4 kV ESD-machine model 200 V ESD-charge device model 2 kV Meets or exceeds JEDEC Spec EIA/JESD78 latchup test 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVEL11 SN65LVEL11 www.ti.com............................................................................................................................................................................................ SLLS927 – DECEMBER 2008 LVPECL DC CHARACTERISTICS (1) (VCC = 3.3 V, VEE = 0.0 V (2) –40°C CHARACTERISTICS ICC Power Supply Current VOH Output HIGH Voltage MIN TYP 25°C MAX 20 (3) (3) MIN TYP 85°C MAX MIN TYP MAX 21 UNIT 25 20 25 25 mA 2215 2420 2215 2286 2420 2215 2420 mV VOL Output LOW Voltage 1470 1680 1470 1584 1680 1470 1680 mV VIH Input High Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV VIHCMR Input HIGH voltage common mode range (Differential) (4) IIH Input HIGH Current IIL Input LOW current (1) (2) (3) (4) V Vpp < 500 mV 1.2 3.1 1.1 3.1 1.1 3.1 Vpp > 500 mV 1.4 3.1 1.3 3.1 1.3 3.1 150 150 150 D 0.5 0.5 0.5 D –600 –600 –600 µA µA Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V Outputs are terminated through a 50 Ω resistor to VCC – 2.0 V. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min and 1 V. LVPNECL DC CHARACTERISTICS (1) (VEE = –3.3 V; VCC = 0.0 V;) –40°C CHARACTERISTICS IEE Power supply current VOH Output HIGH voltage VOL MIN TYP 25°C MAX MIN TYP MIN TYP UNIT 20 25 25 mA –1085 –1013 –880 –1085 –880 mV Output LOW voltage (3) –1830 –1620 –1830 –1722 –1620 –1830 –1620 mV VIH Input high voltage (Single-Ended) –1165 –880 –1165 –880 –1165 –880 mV VIL Input LOW voltage (Single-Ended) –1810 –1475 –1810 –1475 –1810 –1475 mV VIHCMR Input HIGH voltage common mode range (Differential) (4) Input HIGH current IIL Input LOW current (1) (2) (3) (4) 21 MAX –880 (3) 25 85°C MAX –1085 IIH 20 (2) V Vpp < 500 mV –2.1 –0.2 –2.2 –0.2 –2.2 –0.2 Vpp > 500 mV –1.9 –0.2 –2.0 –0.2 –2.0 –0.2 150 150 150 D 0.5 0.5 0.5 D –600 –600 –600 µA µA Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. Outputs are terminated through a 50 Ω resistor to VCC – 2.0 V. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min and 1 V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVEL11 3 SN65LVEL11 SLLS927 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com AC CHARACTERISTICS (1) (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = –3.3 V) (2) –40°C CHARACTERISTIC MIN fMAX Max switching frequency (3) See Figure 6 tPLH/tPHL Propagation delay to output Within device skew tSKEW 25°C TYP MAX MIN TYP 2.9 235 (4) Device to device skew (5) 85°C MAX MIN 350 235 2.7 350 TYP MAX 2.4 235 UNIT GHz 350 ps 10 18 10 18 10 18 ps 10 25 10 25 10 25 ps 5 15 5 15 5 15 ps Duty cycle skew (6) tJITTER Random clock jitter (RMS) VPP Input swing (7) 200 1000 200 1000 200 1000 mV tr/tf Output rise/fall times Q (20%–80%) 150 300 150 300 150 300 ps (1) (2) (3) (4) (5) (6) (7) 0.2 0.2 0.2 ps Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. VEE can vary ±0.3 V Maximum switching frequency measured at output amplitude of 300 mVpp. Within-device skew is defined as identical transitions on similar paths through a device. Device-Device Skew is defined as identical transitions at identical Vcc levels. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. VPP(min) is the minimum input swing for which AC parameters are assured. Typical Termination for Output Driver ZO = 50 W P P Driver Receiver N N ZO = 50 W 50 W 50 W VTT VTT = VCC - 2 V Figure 1. Termination for Output Driver D D Q Q tPHL tPLH Figure 2. Propagation Delay 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVEL11 SN65LVEL11 www.ti.com............................................................................................................................................................................................ SLLS927 – DECEMBER 2008 D VPP(min) VPP(max) D Figure 3. Input Voltage Swing 80% 20% tf tr Figure 4. Output Rise and Fall Times D D Q0 Q0 tPHL0 tPLH0 Q1 Q1 tPHL1 tPLH1 Device Skew = Higher [(tPLH1 - tPLH0), (tPHL1 - tPHL0)] Figure 5. Device Skew Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVEL11 5 SN65LVEL11 SLLS927 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com 1000 VCC = 3.3 V, VEE = 0 V 900 Output Amplitude - mV 800 700 600 TA = -40°C 500 400 TA = 25°C 300 200 TA = 85°C 100 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 f - Frequency - MHz Figure 6. Output Amplitude vs Frequency 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVEL11 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN65LVEL11D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVEL11 SN65LVEL11DGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SINI SN65LVEL11DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-1-260C-UNLIM -40 to 85 SINI SN65LVEL11DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVEL11 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVEL11DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVEL11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVEL11DGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN65LVEL11DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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