TS3A26746E - Texas Instruments

TS3A26746E
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SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
2 X 2 Crosspoint Switch for Audio Applications
Check for Samples: TS3A26746E
FEATURES
1
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•
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Ultra Low RON for GND Switch (80-mΩ typical)
RON for MIC Switch <10-Ω
3.0V to 3.6V V+ Operation
Control Input is 1.8-V Logic Compatible
6-bump, 0.5mm pitch CSP Package (1.45mm ×
0.95mm × 0.5mm)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-B, Class
II)
– 500-V Charged-Device Model (C101)
ESD Performance (SLEEVE, RING2)
– ±8-kV Contact Discharge (IEC 61000-4-2)
APPLICATIONS
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Cellular phones
PDAs
Portable Instrumentation
Digital Still Cameras
Portable Navigation Devices
PINOUT
1
2
A
B
C
DESCRIPTION
The TS3A26746E is a 2 × 2 cross-point switch that is
used to interchange the Ground and MIC connections
on a headphone connector. The Ground switch has
an ultra low RON of <0.1Ω to minimize voltage drop
across it, preventing undesired increases in
headphone ground reference voltage. The switch
state is controlled via the SEL input. When
SEL=High, GND is connected to RING2 and MIC is
connected to SLEEVE. When SEL=Low, GND is
connected to SLEEVE and MIC is connected to
RING2. An internal 100k pull-up resistor on the SEL
input sets the default state of the switch.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TS3A26746E
SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION BLOCK DIAGRAM
MIC BIAS
ACCESSORY
DATA
V+
SLEEVE
MIC
100 kW
RING2
SEL = H
RING1
RIGHT
TIP
LEFT
Figure 1. Standard Headphone Configuration (SEL=H)
MIC BIAS
ACCESSORY
DATA
V+
SLEEVE
MIC
100 kW
RING2
SEL=L
RING1
RIGHT
TIP
LEFT
Figure 2. Alternate Headphone Configuration (SEL=L)
2
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SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
PINOUT
2
1
A
B
C
TERMINAL ASSIGNMENTS
1
2
A
SEL
V+
B
MIC
SLEEVE
C
GND
RING2
PIN FUNCTIONS
BALL #
PIN
DESCRIPTION
NAME
TYPE
A1
SEL
Input
Control Input
A2
V+
Power
Supply Voltage
B1
MIC
I/O
MIC
B2
SLEEV
E
I/O
Sleeve Connection on Headphone Jack
C1
GND
Ground
Ground
C2
RING2
I/O
2nd Ring Connection on Headphone Jack
Table 1. FUNCTION TABLE
SEL
MIC to SLEEVE,
GND to RING2
MIC to RING2,
GND to SLEEVE
L
OFF
ON
H
ON
OFF
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TS3A26746E
SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
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ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX
UNIT
V+
Supply voltage range
(3)
–0.3
4.0
V
VMIC
VSLEEVE
VRING2
Analog voltage range (3)
–0.3
4.0
V
IK
Analog port diode
current
VI
Digital input voltage range
–0.3
IIK
Digital input clamp
current (3)
–50
I+
Continuous current through V+
IGND
Continuous current through GND
θJA
Package thermal
impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
VMIC, VSLEEVE, VRING2 < 0 V
–50
VI < 0 V
mA
4.0
V
mA
100
mA
102
°C/W
150
°C
–100
YZP package
–65
mA
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
The package thermal impedance is calculated in accordance with JESD 51-7.
ELECTRICAL CHARACTERISTICS FOR 3.3 V SUPPLY (1)
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP
MAX UNIT
MIC SWITCH
VMIC, VSLEEVE,
VRING2
Analog signal
range
ron
ON-state
resistance
0 ≤ VSLEEVE or VRING2 ≤ V+, IMIC = –32
mA
Switch
ON
ron(flat)
ON-state
resistance
flatness
0 ≤ VSLEEVE or VRING2 ≤ V+, IMIC = –32
mA
Switch
ON
ISLEEVE(OFF),
IRING2(OFF)
SLEEVE, RING2
OFF leakage
current
VSLEEVE or VRING2 = 1 V, VMIC = 3 V, or
VSLEEVE or VRING2 = 3 V, VMIC = 1 V
Switch
OFF
IMIC(OFF)
MIC OFF leakage VSLEEVE or VRING2 = 3 V, VMIC = 1 V, or
current
VSLEEVE or VRING2 = 1 V, VMIC = 3 V
Switch
OFF
ISLEEVE(ON),
IRING2(ON)
SLEEVE, RING2
ON leakage
current
VSLEEVE or VRING2 = 1 V, VMIC = Open, or
VSLEEVE or VRING2 = 3 V, VMIC = Open
Switch
ON
IMIC(ON)
MIC ON leakage
current
VSLEEVE or VRING2 = Open V, VMIC = 1 V,
or VSLEEVE or VRING2 = Open, VMIC = 3 V
Switch
ON
25°C
ON-state
resistance
ISLEEVE or IRING2 = +32 mA, VGND = 0 V,
IGND = –32 mA
Switch
ON
25°C
VSLEEVE or VRING2 = 3V and VGND = 0 V
Switch
OFF
25°C
VSLEEVE or VRING2 = 0 to 3.6 V and VGND
=0V
Switch
OFF
0
25°C
V+
3V
5
Full
25°C
3V
1
Full
25°C
Full
–0.5
3.6 V
3.6 V
25°C
Full
Full
0.05
–2
0.1
–2
3.6 V
1
2
–2
3.6 V
0.5
–2
0.5
–2
μA
μA
2
2
–2
Ω
0.5
2
–1
Ω
2.3
2.5
25°C
Full
8
10
V
2
2
μA
μA
GND SWITCH
ron
ISLEEVE(OFF),
IRING2(OFF)
ISLEEVE(PWROFF
),
IRING2(PWROFF))
(1)
4
SLEEVE, RING2
OFF leakage
current
Full
Full
3.6 V
25°C
Full
0.08
3V
0.11
–0.5
0.05
–1
–1
0V
0.09
–10
0.5
1
0.5
Ω
μA
1
10
μA
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
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SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
ELECTRICAL CHARACTERISTICS FOR 3.3 V SUPPLY(1) (continued)
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
V+
MIN
TYP
MAX UNIT
DIGITAL CONTROL INPUTS (SEL)
VIH
Input logic high
Full
3.6 V
1.2
3.6
V
VIL
Input logic low
Full
3.6 V
0
0.4
V
IIH
Input logic high
leakage current
VI = V+
25°C
3.6 V
–1
IIL
Input logic low
leakage current
VI = 0 V
tON
Turn-on time
VMIC = V+, RL = 50 Ω
CL = 35
pF
tOFF
Turn-off time
VMIC = V+, RL = 50 Ω
CL = 35
pF
tBBM
Break-beforemake time
VMIC = V+
CMIC
MIC capacitance
Full
25°C
0.05
–2
3.6 V
Full
–38
1
2
–36
–45
–34
–30
μA
μA
DYNAMIC
CSLEEVE
SLEEVE / RING2
capacitance
CI
Digital input
capacitance
THD
Total harmonic
distortion
25°C
3.3 V
Full
3 V to
3.6 V
25°C
3.3 V
Full
3 V to
3.6 V
150
200
250
5
10
15
330
ns
25°C
3.3 V
Full
3 V to
3.6 V
SEL=High
25°C
3.3 V
100
140
pF
SEL=Low
25°C
3.3 V
100
140
pF
SEL=High
25°C
3.3 V
100
140
pF
SEL=Low
25°C
3.3 V
100
140
pF
VI = V+ or 0 V
25°C
3.3 V
4.0
RL = 1k Ω, V = 30 mVPP
f = 20
Hz
to 20
kHz
3.3 V
0.01%
25°C
70
ns
ns
330
pF
SUPPLY
V+
Power Supply
Voltage
3.0
25°C
VI = V+
I+
3.6 V
3.3
3.6
0.01
1
Full
Positive supply
current
25°C
VI = 0 V
Full
5
40
41
50
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V
μA
μA
5
TS3A26746E
SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
www.ti.com
OPERATIONAL CHARACTERISTICS
6
5
SLEEVE-MIC
Ron - Ω
4
3
RING2-MIC
2
1
0
0
0.5
1.0
Figure 3. RON
1.5
2.0
2.5
Vin - V
vs VIN (MIC Switch)
3.0
PARAMETER MEASRUMENT INFORMATION
Figure 4. Turn-On (tON) and Turn-Off Time (tOFF)
6
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SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
PARAMETER MEASRUMENT INFORMATION (continued)
Figure 5. Break-Before-Make Time (tBBM)
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TS3A26746E
SCDS313C – FEBRUARY 2011 – REVISED MAY 2013
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REVISION HISTORY
Changes from Revision B (November 2011) to Revision C
•
8
Page
Replaced 1 page preview with full document. ...................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TS3A26746EYZPR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YZP
6
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
SNAGCU
Level-1-260C-UNLIM
(4/5)
-40 to 85
7N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TS3A26746EYZPR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YZP
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.02
B0
(mm)
K0
(mm)
P1
(mm)
1.52
0.63
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS3A26746EYZPR
DSBGA
YZP
6
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZP0006
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
BALL TYP
0.05 C
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
D: Max = 1.338 mm, Min =1.277 mm
E: Max = 0.838 mm, Min =0.777 mm
A
6X
0.015
0.25
0.21
C A
B
1
2
SYMM
4219524/A 06/2014
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
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EXAMPLE BOARD LAYOUT
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.225)
1
2
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
( 0.225)
METAL
0.05 MAX
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
2
1
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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