Joshua Carnes TI Designs High Speed TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link TI Designs High Speed Equalization Optimization TI Designs High Speed designs are analog solutions created by TI’s analog experts. Reference Designs offer the theory, part selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of useful circuits. Employing equalization techniques is an effective way of compensating for channel loss in JESD204B highspeed serial interfaces for data converters. This reference design discusses the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to prepare the 7.4 Gbps serial data for transmission. Configuration allows a user to optimize the de-emphasis setting (DEM) and output voltage swing setting (VOD) of the output driver to inversely match the characteristics of the channel. Experiments demonstrate the reception of a clean data eye over 20” of FR-4 material at the full data rate. Design Resources Design Files ADC16DX370 ADC16DX370EVM LM97937 LM97937EVM TSW14J56EVM Design Folder ADC16DX370 product page ADC16DX370EVM tools page LM97937 product page LM97937EVM tools page TSW14J56EVM tools page • • ASK Our Analog Experts WebBench™ Calculator Tools • • Achieve a high performance JESD204B serial link using low-cost PCB materials Understand the limitations of lossy channels and equalization techniques to overcome the limitations Use a formula-based approach to optimizing the equalization features of the ADC16DX370 This reference design is tested and includes an EVM, configuration software and user's guide Serial Lanes LMK04828 JESD204B Clock Generator Altera Arria V FPGA SYSREF 2 SYSREF 1 CLKIN+/- SYSREF+/- ADC16DX370 Device Clock 1 CHANNEL SB0+/- Device Clock 2 SA0+/- Reference An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. WebBench is a trademark of Texas Instruments. TIDU551 – October 2014 Submit Documentation Feedback TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated 1 Introduction 1 www.ti.com Introduction The advancements of digital serializer and de-serializer (SERDES) technologies, the availability of gigabit SERDES transceivers in affordable FPGAs, and the progression of the JESD204 standard have made it possible for data converter designs to adopt serialized interfaces, and the proliferation of these interfaces is now a reality. SERDES speeds of up to 12.5 Gbps are accommodated today by the standard on printed-circuit-board (PCB) channels up to 8 inches long but the challenges of transmitting a digital signal across a lossy channel remain. Applications are constantly expanding the boundaries to faster speeds and longer channels. Data transfer rates at 3.125 Gbps and below with channel lengths shorter than 4” can be successful using cheap PCB materials, like FR-4, but pushing beyond these requirements often requires the use of low-loss dielectrics which significantly increase the cost of the design. Providing low-cost solutions to channel limitations is essential to the success of these data link designs. Employing equalization techniques is an effective way of compensating for channel loss. This document discusses the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes deemphasis equalization to prepare the 7.4 Gbps serial data for transmission (Texas Instruments, 2014). Configuration allows a user to optimize the equalization and gain of the output driver to inversely match the characteristics of the channel. Experiments demonstrate the reception of a clean data eye over 20” of FR-4 material at the full data rate. 2 Correcting Channel Loss There are a number of non-ideal qualities of a differential PCB transmission line that make it more difficult to recover the logical state of the signal at the receiver. These non-idealities can generally be grouped into channel irregularities and losses. Channel irregularities, such as dielectric and traces variation, are minute errors in the fabrication of the channel which lead to impedance discontinuities and small signal reflections across the entire length of the channel and are common in PCB manufacturing. Channel irregularities may also include impedance discontinuities caused by stubs and vias. Channel losses include radiative loss, coupling loss, conductor loss and dielectric loss and are generally related to the PCB materials used (conductor, dielectric) and how well the electro-magnetic wave is controlled (radiative, coupling). Assuming a design that extensively uses reference planes to minimize coupling and radiation, the losses are dominated by conductor losses (skin effect) and dielectric losses. At frequencies above approximately 1 GHz, the dielectric loss dominates, a result of permanent electric dipoles in the dielectric re-aligning themselves to the transient electric field as the signal passes by which appears as a small AC leakage current through the substrate. (Bogatin, 2004) This dielectric loss increases with frequency and is described by the dissipation factor of the material, also called the loss tangent. The dissipation factors of a few dielectric materials are shown in Table 1, demonstrating that the improvement in the dissipation factor of premium over low cost dielectrics is nearly an order of magnitude. The JESD204B standard (JEDEC, 2012) suggests loosely that 8" channels are supported but more rigorously specifies a compliant channel in terms of its insertion loss across frequency, shown in the loss mask of Figure 1. Example loss profiles are added to indicate a compliant and a non-compliant channel. The example 8" FR-4 channel conducting a 6.375 Gbps signal is marginally within the boundary of the standard whereas the longer 20" channel is not. Table 1. Dissipation Factor of Various Available Dielectric PCB Materials 2 Dielectric Material Dielectric Constant (Dk) Dissipation Factor (Df), tan(δ) Common FR-4 ≈4.5 ≈0.02 Isola 370HR (FR-4) 3.9 0.025 at 10 GHz Nelco N4000-13 3.7 0.008 at 10 GHz Panasonic Megtron 6 3.5 0.004 at 10 GHz Rogers 4350B 3.5 0.0037 at 10 GHz TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated TIDU551 – October 2014 Submit Documentation Feedback De-Emphasis (DEM) and Voltage Swing (VOD) Control www.ti.com 0 Compliant Insertion Loss SDD21 (dB) 2 Example Compliant Channel Loss (~8" FR-4 Channel @ 6.375 Gb/s) 4 6 8 Example Non-Compliant Channel Loss (~20" FR-4 Channel @ 6.375 Gb/s) Non-Compliant Insertion Loss 10 ¼ Baud ½ Baud ¾ Baud Rate Rate Rate Frequency (GHz) Figure 1. JESD204B Standard Channel Loss Profile for Compliant Channels The quality of the signal at the output of the channel is effectively observed on an eye diagram where the eye opening indicates the horizontal (time) and vertical (voltage) window with which a clock and data recovery (CDR) receiver can recover the signal. In the presence of significant channel loss, the amplitude shrinks, the edge rates become slower and inter-symbol interference becomes so bad that the eye closes and the signal cannot be recovered as shown in the progression of Figure 2 (a)–(c). Figure 2. Effects of Channel Loss on Signal for (a) Little Loss, (b) Moderate Loss, and (c) Significant Loss The purpose of linear equalization is to apply a high-pass frequency shaping response at either the transmitter or receiver to counteract the frequency-dependent dielectric loss and conductor loss through the channel which typically has a low-pass profile. Linear equalization is not effective at correcting the loss due to channel irregularities because these losses result in discontinuities in the phase response (and group delay) of the channel. The high-pass equalization response can be created by either amplifying higher frequencies (pre-emphasis) or attenuating lower frequencies (de-emphasis). To obtain the desired equalization, the slope of the high-pass response must be adjusted to inversely match the loss profile, and the broad band gain must be adjusted to ensure that the vertical eye opening meets the requirements of the eye mask standard or capabilities of the receiving device. 3 De-Emphasis (DEM) and Voltage Swing (VOD) Control The ADC16DX370 uses a linear, continuous-time equalization technique in the output drivers that performs de-emphasis of the signal. The de-emphasis function is configured to different high-pass slopes by changing the DEM setting. The voltage swing configuration varies the broadband gain of the output drivers and is adjusted using the VOD setting. TIDU551 – October 2014 Submit Documentation Feedback TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated 3 Optimization Design Procedure www.ti.com The effects of de-emphasis in the frequency domain can also be intuitively understood in the time domain. Figure 3 shows a waveform at the driver output with and without de-emphasis, demonstrating how the initial edge transient (influenced most by higher frequencies) remains unaffected but the waveform settles to a lower value as a result of attenuation at the lower frequencies. The amount of de-emphasis is given by comparing the settled waveforms with and without de-emphasis and calculating the amount of attenuation, expressed units of decibels, [dB]. In the case of Figure 3, the de-emphasis is 6 dB. At the output of the channel, the overshoot seen in the signal with optimal de-emphasis will be attenuated by the channel loss, resulting in a near-perfect eye with the swing reduced by the de-emphasis value, in this case by 6 dB. (1) When the DEM setting is optimized, the horizontal opening of the eye is greatly recovered but the voltage swing may be unacceptably attenuated. To recover the vertical opening of the eye, the VOD setting can be adjusted, which controls the driver’s output voltage swing and is equivalent to modifying the broadband gain. (2) Figure 3. Eye Diagram of 5-Gbps Signal with (Blue) and Without (Orange) De-Emphasis 4 Optimization Design Procedure Use the following design procedure to optimize the DEM and VOD settings: 1. Characterize the Channel Use test hardware to characterize the channel with a network analyzer or simulate a channel model with an EM simulator to obtain the loss profile of the channel, similar to what is shown in Figure 5. The loss profile is the SDD21 (differential S-parameter), in units of [dB], on a plot versus frequency on a linear scale. 2. Fit the Loss Profile to Empirical De-Emphasis Data and Configure DEM Setting • Create a linear curve fit to the loss profile between the frequencies 0.2 × BR and 0.6 × BR where BR is the baud rate of the data. Note the slope of the line in units of [dB/GHz], referred to here as the loss gradient of the channel. (3) • Calculate the DEM parameter value using Equation 1, based on empirical characterization of the de-emphasis circuit. LG is the loss gradient calculated in the previous step. DEM = 2.1 × LG + 1.23 • (1) (2) (3) 4 (1) Round the DEM value to the nearest integer. Configure the DEM setting to this integer value. spacer spacer spacer spacer This is in contrast with pre-emphasis which amplifies signals at high frequencies, creates an amplification of the edge transient and therefore does not experience an over-all reduction in voltage swing at the channel output. This is equivalent to applying de-emphasis and increasing the voltage swing (broadband gain) at the same time. Modifying the output swing is a tradeoff between bit error rate and power. Increasing the swing improves the eye opening (equivalently the SNR) at the cost of increased power. The loss gradient term here is not to be confused with the loss tangent (also called dissipation factor), a unit-less quantity. TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated TIDU551 – October 2014 Submit Documentation Feedback Measured Results www.ti.com 3. Adjust the Output Swing • Consult Table 2 to determine the VOD setting. From the column of the chosen DEM setting, select the desired differential voltage swing [mVpp-diff] at the output of the channel under perfect deemphasis equalization. Configure the VOD setting appropriately. Table 2. Channel output swing [mVpp-diff] in the case of perfect equalization for All VOD and DEM Settings DEM Setting VOD Setting 5 0 1 2 3 4 5 6 7 0 570 550 500 450 410 370 330 260 1 670 630 550 490 450 390 350 270 2 760 700 590 520 470 420 370 280 3 860 760 640 550 500 440 380 290 4 950 820 670 580 520 450 390 310 5 1050 870 700 600 540 470 400 310 6 1140 920 730 620 560 480 420 320 7 1240 970 760 640 570 490 430 330 Measured Results Differential 100-Ω microstrip traces of 5-mil width and lengths of 5”, 10”, 15”, and 20” were built over FR-4 dielectric as shown in Figure 4. The traces were characterized with a network analyzer and their loss profiles were plotted versus frequency on a linear scale as shown in Figure 5. The optimization procedure was followed and the optimal DEM and VOD settings were derived as shown in Table 3. The differential voltage swing at the output of the channel, as required by the JESD204B standard and LV-OIF-11G-SR electrical variant, must be between 110 and 1050 mVpp-diff (JEDEC, 2012) as shown in Figure 6(b), so an intermediate target swing value of 450 mVpp-diff was chosen when selecting the VOD setting. Figure 4. Channel Characterization Boards for Microstrip Traces over FR-4 Dielectric TIDU551 – October 2014 Submit Documentation Feedback TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated 5 Measured Results www.ti.com Differential Voltage (V) Differential Voltage (V) Figure 5. Loss Profile of 100-Ω, 5 mil Differential Microstrip Traces above FR-4 0.385 0.180 0 -0.180 -0.385 0 XT1 XT2 1-XT2 1-XT1 0.525 0.055 0 -0.055 -0.525 1 0 Normalized Bit Time (UI) (a) XT1 1-XT1 1 Normalized Bit Time (UI) (b) Figure 6. Eye Mask Requirements for the JESD204B Physical Layer Standard, LV-OIF-11G-SR Electrical Variant for the (a) Transmitted Signal and (b) Received Signal (Channel Output) Table 3. Optimization Procedure Values for Various Lengths of Microstrip Traces on FR-4 Dielectric Trace Length Loss Gradient Calculated DEM VOD Setting 5” 0.67 dB/GHz round(2.6) = 3 0 10” 1.34 dB/GHz round(4.0) = 4 2 15” 1.98 dB/GHz round(5.4) = 5 4 20” 2.55 dB/GHz round(6.6) = 7 7 The eye diagram is measured using a 7.4 Gbps K28.5 symbol pattern as the channel input (generated by the ADC16DX370) and an Agilent Infiniium DCA-J oscilloscope to view the eye. The resulting waveforms at the output of the channel with and without optimization are shown in Figure 7 through Figure 10. At the 10” channel length, the eye opening with no equalization may marginally meet the eye mask while also meeting the required 1e–15 bit error rate (BER) requirement of the link, but a more involved BER test with a pseudo random bit sequence (PRBS) is recommended to verify the BER performance. Longer lengths would certainly yield too many symbol errors. Transmitting over the 20” channel length without equalization results in a completely closed eye. 6 TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated TIDU551 – October 2014 Submit Documentation Feedback Measured Results www.ti.com Applying the derived DEM and VOD settings recovers an eye with significant margin in all cases. The DEM setting applies the equalization and the VOD setting recovers the broadband signal swing loss so that the resulting swing is approximately 450 mVpp-diff. (1) Figure 7. Signal Output from 5” Channel (a) Without Optimization and (b) With DEM = 3, VOD = 0 Figure 8. Signal Output from 10” Channel (a) Without Optimization and (b) With DEM = 4, VOD = 2 (1) Figure 7 through Figure 10 have a y-axis major division of 100 mV and x-axis major division of 22.4 ps. TIDU551 – October 2014 Submit Documentation Feedback TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated 7 Measured Results www.ti.com Figure 9. Signal Output from 15” Channel (a) Without Optimization and (b) With DEM = 5, VOD = 4 Figure 10. Signal Output from 20” Channel (a) Without Optimization and (b) With DEM = 7, VOD = 7 The large amount of margin seen in Figure 10(b) for the 20” length raises the question: How long of a FR4 microstrip channel can be accommodated by the maximum optimization settings (DEM = 7, VOD = 7) while still meeting the JESD204B receive mask eye requirement? Figure 11 offers an interesting data point. A 5-Gbps K28.5 data pattern input into a 40” microstrip channel clearly violates the 110 mVpp-diff vertical requirement of the eye for JESD204B, but this does not discount a successful application under these limitations. From the diagram, one can see the spreading of deterministic jitter at the zero crossing due to incomplete equalization for the longer channel and yet the horizontal eye requirement still has plenty of margin. A simple high-speed gain buffer that adds only a modest amount of jitter can be enough to bring the eye back into compliance. Alternatively, the receiving device may have performance capabilities beyond the JESD204B specification to recover a signal with small amplitude but very low jitter. 8 TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated TIDU551 – October 2014 Submit Documentation Feedback Conclusion www.ti.com Figure 11. 5 Gbps Signal Output from 40” Channel with DEM = 7, VOD = 7: Violates the JESD204B Eye Requirements 6 Conclusion Data converters that utilize the JESD204B interface are quickly becoming common in the industry and applications are increasingly pushing the speed and length limits of the interface, necessitating solutions that correct the non-idealities of the channel. Equalization is an effective solution for increasing the bit-rate and channel length for very high speed data transmission applications. The ADC16DX370 is one such JESD204B-compliant device that offers data transfer on one lane per channel up to 7.4 Gbps. Measurements demonstrate the clean transfer of data over a 20” microstrip channel above FR-4 dielectric by optimizing the de-emphasis and voltage swing features. 7 Works Cited • • • • • • • Bogatin, E. (2004). Signal Integrity - Simplified. Upper Saddle River, New Jersey: Prentice Hall. Isola. (n.d.). 370HR Data Sheet. Chandler, Arizona, USA. Retrieved August 20, 2014, from http://www.isola-group.com/products/370hr/ JEDEC. (2012, January). JESD204B Standard. Retrieved August 20, 2014, from http://www.jedec.org/standards-documents/results/jesd204b Panasonic. (n.d.).Data Sheet Megtron 6. Retrieved 8 20, 2014, from http://www3.panasonic.biz/em/pcbm/en/product/r5775/1_Application_Features/index.html Park Electrochemical Corp. (n.d.). Advanced Electronic Materials Products Selector Guide. Melville, New York, USA. Retrieved August 8, 2014, from http://www.parkelectro.com/ Rogers Corporation. (n.d.). RO4000 Series High Frequency Circuit Materials. Retrieved August 20, 2014, from http://www.rogerscorp.com/acm/products/55/RO4350B-Laminates.aspx Texas Instruments. (2014). ADC16DX370 Data Sheet (SNVSA18). TIDU551 – October 2014 Submit Documentation Feedback TIDA-00353 Equalization Optimization of the ADC16DX370 JESD204B Serial Link Copyright © 2014, Texas Instruments Incorporated 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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