Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 LM3880/-Q1 Simple Power Sequencer 1 Features 3 Description • The LM3880 Simple Power Sequencer offers the easiest method to control power up and power down sequencing of multiple Independent voltage rails. By staggering the startup sequence, it is possible to avoid latch conditions or large in-rush currents that can affect the reliability of the system. 1 • • • • • • • Qualified for Automotive Applications – AEC-Q100 Grade 1 Qualified – Manufactured on an Automotive-Grade Flow Easiest Method to Sequence Rails Power-Up and Power-Down Control Tiny Footprint Low Quiescent Current of 25 µA Input Voltage Range of 2.7 V to 5.5 V Standard Timing Options Available Customization of Timing and Sequence Available Through Factory Programmability 2 Applications • • • • • • • • Advanced Driver Assistance Systems (ADAS) Automotive Camera Modules Security Cameras Servers Networking Elements FPGA Sequencing Microprocessor and Microcontroller Sequencing Multiple Supply Sequencing Available in a 6-pin SOT-23-6 package, the Simple Sequencer contains a precision enable pin and three open-drain output flags. When the LM3880 is enabled, the three output flags will sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags will follow a reverse sequence during power down to avoid latch conditions. EPROM capability allows every delay and sequence to be fully adjustable. Contact Texas Instruments if a nonstandard configuration is required. Device Information(1) PART NUMBER LM880 LM3880-Q1 PACKAGE SOT (6) BODY SIZE (NOM) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical System Application Power Supply 1 Input Supply Enable VCC Power Supply 2 FLAG 1 Enable EN FLAG 2 Enable FLAG 3 GND Power Supply 3 Enable 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... Handling Ratings LM3880......................................... Handling Ratings LM3880-Q1................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 13 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 16 10.1 Layout Guidelines ................................................. 16 10.2 Layout Example .................................................... 16 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (March 2013) to Revision J • Page Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 4 Changes from Revision H (March 2013) to Revision I • 2 Page Changed layout of National Data Sheet to TI format. ............................................................................................................ 6 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 5 Pin Configuration and Functions 6-Pin SOT-23 Package Top View 1 2 3 VCC FLAG1 6 GND FLAG2 EN FLAG3 4 5 Pin Functions PIN NAME NO. DESCRIPTION VCC 1 Input supply GND 2 Ground EN 3 Precision enable pin FLAG3 4 Open-drain output 3 FLAG2 5 Open-drain output 2 FLAG1 6 Open-drain output 1 Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 3 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) (2) MIN MAX UNIT VCC −0.3 6.0 V EN, FLAG1, FLAG2, FLAG3 −0.3 6.0 V Max Flag ON Current 50 mA Max Junction Temperature 150 °C Lead Temperature (Soldering, 5 s) 260 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 6.2 Handling Ratings LM3880 Tstg Storage temperature range V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) MIN MAX UNIT –65 150 °C –2 2 kV JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Handling Ratings LM3880-Q1 Tstg Storage temperature range V(ESD) Electrostatic discharge (1) Human body model (HBM), per AEC Q100-002 (1) MIN MAX −65 150 UNIT °C –2 2 kV AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC to GND NOM MAX UNIT 2.7 5.5 EN, FLAG1, FLAG2, FLAG3 −0.3 VCC + 0.3 V V Junction Temperature −40 125 °C 6.5 Thermal Information LM3880/ LM3880Q-1 THERMAL METRIC (1) DBV UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 187.6 RθJC(top) Junction-to-case (top) thermal resistance 127.4 RθJB Junction-to-board thermal resistance 31.5 ψJT Junction-to-top characterization parameter 23.3 ψJB Junction-to-board characterization parameter 31.0 (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 6.6 Electrical Characteristics TJ = –40°C to 125°C, over operating free-air temperature range (unless otherwise noted) PARAMETER IQ TEST CONDITIONS MIN (1) Operating Quiescent current TYP (2) MAX (1) 25 80 µA 20 nA 0.4 V UNIT OPEN-DRAIN FLAGS IFLAG FLAGx Leakage Current VFLAGx = 3.3 V VOL FLAGx Output Voltage Low IFLAGx = 1.2 mA 1 POWER-UP SEQUENCE td1 Timer delay 1 accuracy –15% 15% –20% 20% –15% 15% –20% 20% –15% 15% –20% 20% –15% 15% –20% 20% –15% 15% –20% 20% –15% 15% –20% 20% For x = 1 or 4 95% 105% For x = 1 or 4, 2 ms option 90% 110% For x = 2 or 5 95% 105% For x = 2 or 5, 2 ms option 90% 110% 2 ms Timing Option td2 Timer delay 2 accuracy 2 ms Timing Option td3 Timer delay 3 accuracy 2 ms Timing Option POWER-DOWN SEQUENCE td4 Timer delay 4 accuracy 2 ms Timing Option td5 Timer delay 5 accuracy 2 ms Timing Option td6 Timer delay 6 accuracy 2 ms Timing Option TIMING DELAY ERROR (td(x) – 400 µs) / td(x+1) Ratio of timing delays td(x) / td(x+1) Ratio of timing delays ENABLE PIN VEN EN pin threshold IEN EN pin pullup current (1) (2) 1.0 VEN = 0 V 1.25 7 1.4 V µA Limits are 100% production tested at 25°. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 5 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com 6.7 Timing Requirements Table 1. Sequence Designator Table FLAG ORDER SEQUENCE NUMBER POWER UP POWER DOWN 1 1-2-3 3-2-1 2 1-2-3 3-1-2 3 1-2-3 2-3-1 4 1-2-3 2-1-3 5 1-2-3 1-3-2 6 1-2-3 1-2-3 Table 2. Timing Designator Table (1) TIMING DESIGNATOR td1 td2 td3 td4 td5 td6 16 ms (1) AF 16 ms 16 ms 16 ms 16 ms 16 ms AE 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms AA 10 ms 10 ms 10 ms 10 ms 10 ms 10 ms AB 30 ms 30 ms 30 ms 30 ms 30 ms 30 ms AC 60 ms 60 ms 60 ms 60 ms 60 ms 60 ms AD 120 ms 120 ms 120 ms 120 ms 120 ms 120 ms See timing diagrams for more information EN FLAG1 FLAG2 FLAG3 td1 td2 td3 Sequence 1: All standard options use this sequence for output flags rise and fall order. Figure 1. Power-Up Sequence EN FLAG1 FLAG2 FLAG3 td4 td5 td6 Sequence 1: All standard options use this sequence for output flags rise and fall order. Figure 2. Power-Down Sequence 6 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 6.8 Typical Characteristics 30 26 29 25 28 24 26 IQ (PA) IQ (PA) 27 25 23 24 22 23 22 21 21 20 2.5 3 3.5 4 4.5 5 5.5 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) VCC (V) Figure 3. Quiescent Current vs VCC Figure 4. Quiescent Current vs Temperature (VCC = 3.3 V) 1.232 1.230 1.228 VEN (V) 1.226 1.224 RISING FALLING 1.222 1.220 1.218 1.216 1.214 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 5. Enable Threshold vs Temperature Figure 6. Time Delay (30 ms) vs Vcc Figure 7. Time Delay Ratio vs Temperature Figure 8. Time Delay (30 ms) vs Temperature Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 7 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com Typical Characteristics (continued) Figure 9. Flag VOL vs Vcc (RFLAG = 100 kΩ) 8 Submit Documentation Feedback Figure 10. Flag Voltage vs Current Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 7 Detailed Description 7.1 Overview The LM3880 Simple Power Sequencer provides a simple solution for sequencing multiple rails in a controlled manner. Six independent timers are integrated to control the timing sequence (power up and power down) of three open-drain output flags. These flags permit connection to either a shutdown or enable pin of linear regulators and switchers to control the operation of the power supplies. This allows design of a complete power system without concern for large inrush currents or latch-up conditions that can occur. The timing sequence of the LM3880 is controlled entirely by the enable (EN) pin. Upon power up, all the flags are held low until this precision enable is pulled high. When the EN pin is asserted, the power-up sequence starts. An internal counter delays the first flag (FLAG1) from rising until a fixed time period has expired. When the first flag is released, another timer will begin to delay the release of the second flag (FLAG2). This process repeats until all three flags have sequentially been released. The three timers that control the delays are independent of each other and can be individually programmed if needed. (See the Customized Timing and Sequencing section.) The power-down sequence is the same as power-up sequence, but in reverse. When the EN pin is deasserted a timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate delays. The three timers that are used to control the power-down scheme can also be individually programmed and are completely independent of the power-up timers. Additional sequence patterns are also available in addition to customizable timers. For more information, see the Customized Timing and Sequencing section. 7.2 Functional Block Diagram VCC FLAG1 7 PA td1 + - EN td2 FLAG2 Timing Delay Generation 1.25V td3 td4 Sequence Control td5 td6 Master Clock FLAG3 EPROM (Factory Set) GND Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 9 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com 7.3 Feature Description 7.3.1 Enable Pin Operation The timing sequence of the LM3880 is controlled by the assertion of the enable signal. The enable pin is designed with an internal comparator, referenced to a bandgap voltage (1.25 V), to provide a precision threshold. This allows a delayed timing to be externally set using a capacitor or to start the sequencing based on a certain event, such as a line voltage reaching 90% of nominal. For an additional delayed sequence from the rail powering VCC, simply attach a capacitor to the EN pin as shown in Figure 11. 7 PA EN + 1.25V CEN Enable - Figure 11. Capacitor Timing Using the internal pullup current source to charge the external capacitor (CEN) the enable pin delay can be calculated by Equation 1: tenable_delay = 1.25V x CEN 7 PA (1) A resistor divider can also be used to enable the LM3880 based on a certain voltage threshold. Take care when sizing the resistor divider to include the effects of the internal current source. One of the features of the EN pin is that it provides glitch free operation. The first timer will start counting at a rising threshold, but will always reset if the EN pin is deasserted before the first output flag is released. This can be shown in Figure 12: EN FLAG1 td1 Figure 12. EN Glitch 7.3.2 Incomplete Sequence Operation If the enable signal remains high for the entire power-up sequence, then the part will operate as shown in the standard timing diagrams. However, if the enable signal is de-asserted before the power-up sequence is completed the part will enter a controlled shutdown. This allows the system to walk through a controlled power cycling, preventing any latch conditions from occurring. This state only occurs if the enable pin is deasserted after the completion of timer 1, but before the entire power-up sequence is completed. 10 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 Feature Description (continued) When this event occurs, the falling edge of EN pin resets the current timer and will allow the remaining power-up cycle to complete before beginning the power-down sequence. The power down sequence starts approximately 120 ms after the final power-up flag. This allows output voltages in the system to stabilize before everything is shut down. An example of this operation can be seen in Figure 13: EN FLAG1 FLAG2 FLAG3 td1 td2 td3 120 ms td4 td5 td6 Figure 13. Incomplete Power-Up Sequence When the enable signal is deasserted, the part will commence its power-down sequence. If the enable signal is pulled high before the power-down sequence is completed, the part will ensure completion of the power-down sequence before starting power-up. This ensures that the system does not partially power down and power up and helps prevent latch-up events, such as in FPGAs and microprocessors. This state only occurs if the enable pin is pulled high after the completion of timer 1, but before the entire power-down sequence is completed. When this event occurs, the rising edge of enable pin resets the current timer and will allow the remaining powerdown cycle to complete before beginning the power-up sequence. The power-up sequence starts approximately 120 ms after the final power-down flag. This allows the system to fully shut down before it is powered up. An example of this operation can be seen in Figure 14: EN FLAG1 FLAG2 FLAG3 td1t t td2t t td3t t t120 mst td4t td5t t t td6t t Figure 14. Incomplete Power-Down Sequence All the internal timers are generated by a master clock that has an extremely low tempco. This allows for tight accuracy across temperature and a consistent ratio between the individual timers. There is a slight additional delay of approximately 400 µs to timers 1 and 4, which is a result of the EPROM refresh. This refresh time is in addition to the programmed delay time and will be almost insignificant to all but the shortest of timer delays. Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 11 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) 7.3.3 Customized Timing and Sequencing The LM3880 Simple Power Sequencer is based on a CMOS process using an EPROM that can be custom programmed at the factory. Approximately 500,000,000 different options are available allowing even the most complex system to be simply sequenced. Because of the vast options that are possible, customization is limited to orders of a certain quantity. For more information, please contact Texas Instruments. The variables that can be programmed include the six delay timers and the reverse sequence order. For the timers, each can be individually selected from one of the timer selector columns in Table 3. However, all six time delays must be from the same column. Table 3. Timer Options (1) TIMER OPTIONS 1 (1) TIMER OPTIONS 2 (1) TIMER OPTIONS 3 (1) TIMER OPTIONS 4 (1) 0 0 0 0 2 4 6 8 4 8 12 16 6 12 18 24 8 16 24 32 10 20 30 40 12 24 36 48 14 28 42 56 16 32 48 64 18 36 54 72 20 40 60 80 22 44 66 88 24 48 72 96 26 52 78 104 28 56 84 112 30 60 90 120 All times listed are in milliseconds The sequencing order for power up is always controlled by layout. The flag number translates directly into the sequence order during power up (that is, FLAG1 will always be first). However, for some systems a different power down order could be required. To allow flexibility for this aspect in a design, the Simple Power Sequencer incorporates six different options for controlling the power-down sequence. These options can be seen in Figure 16 and Figure 17. This ability can be programmed in addition to the custom timers. 7.4 Device Functional Modes 7.4.1 Power Up With EN Pin The timing sequence of the Simple Power Sequencer is controlled entirely by the enable (EN) pin. Upon power up, all the flags are held low until this precision enable is pulled high. After the EN pin is asserted, the power-up sequence will commence. 7.4.2 Power Down With EN Pin When EN pin is deasserted, the power down sequence will commence. A timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate delays. 12 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Open Drain Flags Pullup The Simple Power Sequencer contains three open-drain output flags which need to be pulled up for proper operation. 100-kΩ resistors can be used as pullup resistors. 8.1.2 Enable the Device See Enable Pin Operation. 8.2 Typical Application 8.2.1 Simple Sequencing of Three Power Supplies The Simple Power Sequencer is used to implement a power-up (1 - 2 - 3) and power-down (3 - 2 - 1) sequence of three power supplies. Figure 15. Typical Application Circuit Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 13 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 4 as the input parameters. Table 4. Design Parameters Design Parameter Example Value Input Supply voltage range 2.7 V to 5.5 V Flag Output voltage, EN high Input Supply Flag Output voltage, EN low 0V Flag Timing Delay 30 ms Power-Up Sequence 1-2-3 Power-Down Sequence 3-2-1 8.2.1.2 Detailed Design Procedure Table 5. Bill of Materials Designator Description Part # Quantity Manufacturer U1 LM3880, Sequence 1, 30 ms timing LM3880 1 Texas Instruments R1 100K Resistor, 0603 CRCW0603100KFKEA 1 Vishay R2 100K Resistor, 0603 CRCW0603100KFKEA 1 Vishay R3 100K Resistor, 0603 CRCW0603100KFKEA 1 Vishay This application uses the Sequence 1 and 30-ms timing options of the Simple Power Sequencer. See Timing Requirements for details on the sequence and timing option. 8.2.1.3 Application Curves Figure 16. Power-Up Sequence 14 Submit Documentation Feedback Figure 17. Power-Down Sequence Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 8.2.2 Sequencing Using Independent Flag Supply For applications requiring a flag output voltage that is different from the VCC, a separate Flag Supply may be used to pullup the open-drain outputs of the Simple Power Sequencer. This is useful when interfacing the flag outputs with inputs that require a different voltage than VCC. The designer must ensure the Flag Supply voltage is within the range specified in the Recommended Operating Conditions. Figure 18. Sequencing Using Independent Flag Supply Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 15 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com 9 Power Supply Recommendations The VCC pin should be located as close as possible to the input supply (2.7V - 5.5V). An input capacitor is not required but is recommended when noise might be present on the VCC pin. A 0.1 μF ceramic capacitor may be used to bypass this noise. 10 Layout 10.1 Layout Guidelines • • Pullup resistors should be connected between the flag output pins and a positive input supply, usually VCC. An independent flag supply may also be used. These resistors should be placed as close as possible to the Simple Power Sequencer and the flag supply. Minimal trace length is recommended to make the connections. A typical value for the pullup resistors is 100kΩ. For very tight sequencing requirements, minimal and equal trace lengths should be used to connect the flag outputs to the desired inputs. This will reduce any propagation delay and timing errors between the flag outputs along the line. 10.2 Layout Example Figure 19 and Figure 20 are layout examples for the LM3880/LM3880-Q1. These examples are taken from the LM3880EVAL. Figure 19. LM3880 Top 16 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 LM3880, LM3880-Q1 www.ti.com SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 Layout Example (continued) Figure 20. LM3880 Bottom Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 Submit Documentation Feedback 17 LM3880, LM3880-Q1 SNVS451J – AUGUST 2006 – REVISED DECEMBER 2014 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 6. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LM3880 Click here Click here Click here Click here Click here LM3880-Q1 Click here Click here Click here Click here Click here 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2006–2014, Texas Instruments Incorporated Product Folder Links: LM3880 LM3880-Q1 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3880MF-1AA NRND SOT-23 DBV 6 1000 TBD Call TI Call TI -40 to 125 F20A LM3880MF-1AA/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F20A LM3880MF-1AB/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F21A LM3880MF-1AC/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F22A LM3880MF-1AD/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F23A LM3880MF-1AE/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F25A LM3880MF-1AF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F31A LM3880MFE-1AA/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F20A LM3880MFE-1AB/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F21A LM3880MFE-1AC/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F22A LM3880MFE-1AD/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F23A LM3880MFE-1AE/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F25A LM3880MFE-1AF/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F31A LM3880MFX-1AA/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F20A LM3880MFX-1AB/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F21A LM3880MFX-1AC/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F22A LM3880MFX-1AD/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F23A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Aug-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3880MFX-1AE/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F25A LM3880MFX-1AF/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F31A LM3880QMF-1AA/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F27A LM3880QMF-1AB/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F28A LM3880QMF-1AC/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F29A LM3880QMF-1AD/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F30A LM3880QMF-1AE/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F24A LM3880QMF-1AF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F32A LM3880QMFE-1AA/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F27A LM3880QMFE-1AB/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F28A LM3880QMFE-1AC/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F29A LM3880QMFE-1AD/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F30A LM3880QMFE-1AE/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F24A LM3880QMFE-1AF/NOPB ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F32A LM3880QMFX-1AA/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F27A LM3880QMFX-1AB/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F28A LM3880QMFX-1AC/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F29A LM3880QMFX-1AD/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F30A Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Aug-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3880QMFX-1AE/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F24A LM3880QMFX-1AF/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 F32A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2015 OTHER QUALIFIED VERSIONS OF LM3880, LM3880-Q1 : • Catalog: LM3880 • Automotive: LM3880-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM3880MF-1AA SOT-23 DBV 6 1000 178.0 8.4 LM3880MF-1AA/NOPB SOT-23 DBV 6 1000 178.0 LM3880MF-1AB/NOPB SOT-23 DBV 6 1000 178.0 LM3880MF-1AC/NOPB SOT-23 DBV 6 1000 LM3880MF-1AD/NOPB SOT-23 DBV 6 LM3880MF-1AE/NOPB SOT-23 DBV LM3880MF-1AF/NOPB SOT-23 DBV LM3880MFE-1AA/NOPB SOT-23 W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFE-1AB/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFE-1AC/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFE-1AD/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFE-1AE/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFE-1AF/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFX-1AA/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFX-1AB/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFX-1AC/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFX-1AD/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880MFX-1AE/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2015 Device LM3880MFX-1AF/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMF-1AA/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMF-1AB/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMF-1AC/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMF-1AD/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMF-1AE/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMF-1AF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFE-1AA/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFE-1AB/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFE-1AC/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFE-1AD/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFE-1AE/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFE-1AF/NOPB SOT-23 DBV 6 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFX-1AA/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFX-1AB/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFX-1AC/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFX-1AD/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFX-1AE/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LM3880QMFX-1AF/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3880MF-1AA SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MF-1AA/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MF-1AB/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MF-1AC/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MF-1AD/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MF-1AE/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MF-1AF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880MFE-1AA/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880MFE-1AB/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880MFE-1AC/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880MFE-1AD/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880MFE-1AE/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880MFE-1AF/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880MFX-1AA/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880MFX-1AB/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880MFX-1AC/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880MFX-1AD/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880MFX-1AE/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880MFX-1AF/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880QMF-1AA/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880QMF-1AB/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880QMF-1AC/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880QMF-1AD/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880QMF-1AE/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880QMF-1AF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LM3880QMFE-1AA/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880QMFE-1AB/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880QMFE-1AC/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880QMFE-1AD/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880QMFE-1AE/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880QMFE-1AF/NOPB SOT-23 DBV 6 250 210.0 185.0 35.0 LM3880QMFX-1AA/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880QMFX-1AB/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880QMFX-1AC/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880QMFX-1AD/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880QMFX-1AE/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 LM3880QMFX-1AF/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated