DAC8565IAPW - Texas Instruments

DAC8565
DA
C8
565
www.ti.com.......................................................................................................................................................... SBAS411B – JUNE 2007 – REVISED MARCH 2008
16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference
FEATURES
DESCRIPTION
1
• Relative Accuracy: 4LSB
• Glitch Energy: 0.15nV-s
• Internal Reference:
– 2.5V Reference Voltage (enabled by default)
– 0.004% Initial Accuracy (typ)
– 2ppm/°C Temperature Drift (typ)
– 5ppm/°C Temperature Drift (max)
– 20mA Sink/Source Capability
• Power-On Reset to Zero-Scale or Midscale
• Asynchronous Clear to Zero-Scale or Midscale
• Ultra-Low Power Operation: 1mA at 5V
• Wide Power Supply Range: +2.7V to +5.5V
• 16-Bit Monotonic Over Temperature Range
• Settling Time: 10µs to ±0.003% Full-Scale
Range (FSR)
• Low-Power Serial Interface with
Schmitt-Triggered Inputs: Up to 50MHz
• On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
• 1.8V to 5.5V Logic Compatibility
• Temperature Range: –40°C to +105°C
234
APPLICATIONS
•
•
•
•
•
•
Portable Instrumentation
Closed-Loop Servo-Control
Process Control, PLCs
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
RELATED
DEVICES
Pin and
Functionally
Compatible
Functionally
Compatible
The DAC8565 is a low-power, voltage-output,
four-channel, 16-bit digital-to-analog converter (DAC).
The device includes a 2.5V, 2ppm/°C internal
reference (enabled by default), giving a full-scale
output voltage range of 2.5V. The internal reference
has an initial accuracy of 0.004% and can source up
to 20mA at the VREFH/VREFOUT pin. The device is
monotonic, provides very good linearity, and
minimizes undesired code-to-code transient voltages
(glitch). The DAC8565 use a versatile 3-wire serial
interface that operates at clock rates up to 50MHz. It
is compatible with standard SPI™, QSPI™,
Microwire™, and digital signal processor (DSP)
interfaces.
The DAC8565 incorporates a power-on-reset circuit
that ensures the DAC output powers up at either
zero-scale or midscale until a valid code is written to
the device. The device contains a power-down
feature, accessed over the serial interface, that
reduces the current consumption of the device to
1.3µA at 5V. The low power consumption, internal
reference, and small footprint make this device ideal
for portable, battery-operated equipment. The power
consumption is 2.9mW at 3V, reducing to 1.5µW in
power-down mode.
The DAC8565 is drop-in and functionally compatible
with the DAC7564 and DAC8164, and functionally
compatible with the DAC7565, DAC8165, and
DAC8564. All these devices are available in a
TSSOP-16 package.
IOVDD
16-BIT
14-BIT
12-BIT
DAC8565
DAC8165
DAC7565
DAC8164
VREFL
DAC7564
Data Buffer A
DAC Register A
16-Bit DAC
VOUTA
Data Buffer B
DAC Register B
16-Bit DAC
VOUTB
Data Buffer C
DAC Register C
16-Bit DAC
VOUTC
Data Buffer D
DAC Register D
16-Bit DAC
VOUTD
Buffer
Control
Register
Control
SYNC
SCLK
DAC8564
AVDD
DAC8565
24-Bit Shift Register
DIN
2.5V
Reference
Control Logic
GND
RST
RSTSEL
LDAC
ENABLE
Power-Down
Control Logic
VREFH/VREFOUT
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
DAC8565
SBAS411B – JUNE 2007 – REVISED MARCH 2008.......................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
REFERENCE
DRIFT
(ppm/°C)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
DAC8565A
±12
±1
25
TSSOP-16
PW
–40°C to +105°C
DAC8565
DAC8565B
±8
±1
25
TSSOP-16
PW
–40°C to +105°C
DAC8565B
DAC8565C
±12
±1
5
TSSOP-16
PW
–40°C to +105°C
DAC8565
DAC8565D
±8
±1
5
TSSOP-16
PW
–40°C to +105°C
DAC8565D
(1)
PACKAGE
MARKING
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DAC8565
UNIT
–0.3 to +6
V
Digital input voltage to GND
–0.3 to +VDD + 0.3
V
VOUT to GND
–0.3 to +VDD + 0.3
V
VREF to GND
–0.3 to +VDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
+150
°C
(TJ max – TA)/θJA
W
Thermal impedance, θJA
+118
°C/W
Thermal impedance, θJC
+29
°C/W
Human body model (HBM)
4000
V
Charged device model (CDM)
1500
V
AVDD to GND
Junction temperature range (TJ max)
Power dissipation
ESD rating
(1)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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www.ti.com.......................................................................................................................................................... SBAS411B – JUNE 2007 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V, –40°C to +105°C range, and data format is straight binary (unless otherwise noted).
DAC8565
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC8565A, DAC8565C
±4
±12
LSB
DAC8565B, DAC8565D
±4
±8
LSB
±0.5
±1
LSB
±5
±8
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by the line
passing through
codes 485 and 64714
Differential nonlinearity
16-bit monotonic
Offset error
Offset error drift
Gain error
Gain temperature coefficient
PSRR
Power-supply rejection ratio
mV
µV/°C
±1
Measured by the line passing through codes 485 and
64714.
Full-scale error
Bits
±0.2
±0.5
% of FSR
±0.05
±0.2
% of FSR
AVDD = 5V
±1
AVDD = 2.7V
±2
ppm of
FSR/°C
1
mV/V
Output unloaded
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ,
0pF < CL < 200pF
8
RL = 2kΩ, CL = 500pF
V
10
µs
12
Slew rate
Capacitive load stability
VREF
2.2
RL = ∞
V/µs
470
pF
RL = 2kΩ
1000
Code change glitch impulse
1LSB change around major carry
0.15
nV-s
Digital feedthrough
SCLK toggling, SYNC high
0.15
nV-s
Channel-to-channel dc crosstalk
Full-scale swing on adjacent channel
0.25
LSB
Channel-to-channel ac crosstalk
1kHz full-scale sine wave, outputs unloaded
–100
dB
DC output impedance
At mid-code input
Short-circuit current
Power-up time
1
Ω
50
mA
Coming out of power-down mode, AVDD = 5V
2.5
Coming out of power-down mode, AVDD = 3V
5
µs
AC PERFORMANCE (2)
SNR
90
dB
THD
–77
dB
78
dB
SFDR
TA = +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz.
First 19 harmonics removed for SNR calculation.
SINAD
DAC output noise density
TA = +25°C, at mid-code input, fOUT = 1kHz
DAC output noise
TA = +25°C, at mid-code input, 0.1Hz to 10Hz
77
dB
120
nV/√Hz
µVPP
6
REFERENCE
Internal reference current consumption
AVDD = 5.5V
360
µA
AVDD = 3.6V
348
µA
80
µA
External reference current
External VREF = 2.5V, if internal reference is disabled,
all four channels active
Reference input range VREFH Voltage
VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V
0
AVDD
Reference input range VREFL Voltage
VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V
0
AVDD/2
Reference input impedance
(1)
(2)
31
V
V
kΩ
Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
Ensured by design or characterization; not production tested.
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DAC8565
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ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V, –40°C to +105°C range, and data format is straight binary (unless otherwise noted).
DAC8565
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE OUTPUT
Output voltage
TA = +25°C
2.4995
2.5
2.5005
V
Initial accuracy
TA = +25°C
–0.02
%
Output voltage temperature drift
Output voltage noise
±0.004
0.02
DAC8565A, DAC8565B (3)
5
25
DAC8565C, DAC8565D (4)
2
5
ppm/°C
µVPP
f = 0.1Hz to 10Hz
12
TA = +25°C, f = 1MHz, CL = 0µF
50
TA = +25°C, f = 1MHz, CL = 1µF
20
TA = +25°C, f = 1MHz, CL = 4µF
16
Load regulation, sourcing (5)
TA = +25°C
30
µV/mA
Load regulation, sinking (5)
TA = +25°C
15
µV/mA
Output voltage noise density
(high-frequency noise)
Output current load capability (6)
Line regulation
TA = +25°C
Long-term stability/drift (aging) (5)
TA = +25°C, time = 0 to 1900 hours
Thermal hysteresis (5)
First cycle
nV/√Hz
±20
mA
10
µV/V
50
ppm
100
Additional cycles
ppm
25
LOGIC INPUTS (6)
Input current
µA
±1
VINL
Logic input LOW voltage
VINH
Logic input HIGH voltage
2.7V ≤ IOVDD ≤ 5.5V
0.3 × IOVDD
1.8V ≤ IOVDD ≤ 2.7V
0.1 × IOVDD
2.7V ≤ IOVDD ≤ 5.5V
0.7 × IOVDD
1.8V ≤ IOVDD ≤ 2.7V
0.95 × IOVDD
V
V
Pin capacitance
3
pF
V
POWER REQUIREMENTS
AVDD
2.7
5.5
IOVDD
1.8
5.5
V
10
20
µA
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
1
1.6
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
0.95
1.5
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
1.3
3.5
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
0.5
2.5
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
3.6
8.8
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
2.6
5.4
AVDD = IOVDD = 3.6V to 5.5V
VINH = IOVDD and VINL = GND
4.7
19
AVDD = IOVDD = 2.7V to 3.6V
VINH = IOVDD and VINL = GND
1.4
9
IOIDD (6)
Normal mode
IDD (7)
All power-down modes
Normal mode
Power
Dissipation
(7)
All power-down modes
mA
µA
mW
µW
TEMPERATURE RANGE
Specified performance
(3)
(4)
(5)
(6)
(7)
4
–40
+105
°C
Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +120°C.
Explained in more detail in the Application Information section of this data sheet.
Ensured by design or characterization; not production tested.
Input code = 32768, reference current included, no load.
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PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
VOUTA
1
16 LDAC
VOUTB
2
15 ENABLE
VREFH/VREFOUT
3
14 RSTSEL
AVDD
4
13 RST
DAC8565
VREFL
5
12 IOVDD
GND
6
11 DIN
VOUTC
7
10 SCLK
VOUTD
8
9
SYNC
PIN DESCRIPTIONS
PIN
NAME
1
VOUTA
Analog output voltage from DAC A
DESCRIPTION
2
VOUTB
Analog output voltage from DAC B
3
VREFH/
VREFOUT
4
AVDD
Power-supply input, 2.7V to 5.5V
5
VREFL
Negative reference input
6
GND
Ground reference point for all circuitry on the part
7
VOUTC
Analog output voltage from DAC C
8
VOUTD
Analog output voltage from DAC D
9
SYNC
Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8565. Schmitt-Trigger logic Input.
10
SCLK
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic Input.
11
DIN
12
IOVDD
13
RST
Positive reference input / reference output 2.5V if internal reference used.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic Input.
Digital input-output power supply
Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or to
midscale (RSTSEL = 1).
14
RSTSEL
Reset select. If RSTSEL is low, input coding is binary; if high = two's complement.
15
ENABLE
The enable pin (active low) connects the SPI interface to the serial port
16
LDAC
Load DACs; rising edge triggered, loads all DAC registers
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DAC8565
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DB0
6
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RST
LDAC
DIN
SYNC
SCLK
ENABLE
t17
t16
t8
1
t11
t4
DB23
t5
t6
t3
t1
t2
t10
24
t7
t13
t12
t14
t9
t15
DB23
SERIAL WRITE OPERATION
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): DAC8565
DAC8565
www.ti.com.......................................................................................................................................................... SBAS411B – JUNE 2007 – REVISED MARCH 2008
TIMING REQUIREMENTS (1) (2)
At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8565
PARAMETER
TEST CONDITIONS
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
t11
ENABLE falling edge to SYNC falling edge
t12
24th SCLK falling edge to ENABLE rising edge
t13
24th SCLK falling edge to LDAC rising edge
t14
LDAC rising edge to ENABLE rising edge
t15
LDAC HIGH time
t16
RST rising edge to SYNC falling edge
t17
RST HIGH time
(1)
(2)
(3)
MIN
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
20
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
5
IOVDD = AVDD = 3.6V to 5.5V
5
IOVDD = AVDD = 2.7V to 3.6V
4.5
IOVDD = AVDD = 3.6V to 5.5V
4.5
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
130
IOVDD = AVDD = 3.6V to 5.5V
130
IOVDD = AVDD = 2.7V to 3.6V
15
IOVDD = AVDD = 3.6V to 5.5V
15
IOVDD = AVDD = 2.7V to 3.6V
15
IOVDD = AVDD = 3.6V to 5.5V
15
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
50
IOVDD = AVDD = 3.6V to 5.5V
50
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
35
IOVDD = AVDD = 3.6V to 5.5V
35
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See the Serial Write Operation timing diagram.
Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
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TYPICAL CHARACTERISTICS: Internal Reference
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades A and B)
2.503
2.503
2.502
2.502
2.501
2.501
VREF (V)
VREF (V)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades C and D)
2.500
2.499
2.500
2.499
2.498
2.498
10 Units Shown
2.497
-40
-20
0
20
40
80
60
100
13 Units Shown
2.497
-40
120
-20
0
20
Temperature (°C)
40
60
80
100
120
Temperature (°C)
Figure 1.
Figure 2.
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°C, Grades C and D)
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°, Grades A and B)
40
30
Typ: 5ppm/°C
Max: 25ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
Population (%)
Population (%)
30
20
20
10
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
5.0
5
7
9
11
13
15
Temperature Drift (ppm/°C)
Figure 3.
Figure 4.
REFERENCE OUTPUT TEMPERATURE DRIFT
(0°C to +120°C, Grades C and D)
LONG-TERM
STABILITY/DRIFT (1)
17
19
200
40
Typ: 1.2ppm/°C
Max: 3ppm/°C
150
100
Drift (ppm)
30
Population (%)
3
Temperature Drift (ppm/°C)
20
10
50
0
-50
Average
-100
-150
-200
0.5
(1)
8
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
300
600
900
1200
Temperature Drift (ppm/°C)
Time (Hours)
Figure 5.
Figure 6.
1500
1800
1900
20 Units Shown
0
Explained in more detail in the Application Information section of this data sheet.
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TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY
vs FREQUENCY
INTERNAL REFERENCE NOISE
0.1Hz TO 10Hz
300
250
VNOISE (5mV/div)
VN (nV/ÖHz)
12mV (peak-to-peak)
200
Reference Unbuffered
CREF = 0mF
150
100
50
CREF = 4.8mF
0
10
100
1k
10k
100k
Time (2s/div)
1M
Frequency (Hz)
Figure 7.
Figure 8.
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades A and B)
2.505
2.505
2.504
2.504
2.503
2.503
2.502
+120°C
2.501
VREF (V)
VREF (V)
2.502
2.500
2.499
+25°C
2.498
2.501
+25°C
2.500
2.499
2.498
-40°C
2.497
+120°C
2.497
-40°C
2.496
2.496
2.495
-25
-20 -15 -10
0
-5
5
10
15
20
2.495
-25
25
-20 -15 -10
0
-5
ILOAD (mA)
5
10
15
20
25
ILOAD (mA)
Figure 9.
Figure 10.
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades A and B)
2.503
2.503
+120°C
2.502
-40°C
+120°C
2.501
VREF (V)
VREF (V)
2.502
2.500
2.501
+25°C
2.500
+25°C
2.499
2.499
2.498
2.498
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40°C
2.5
3.0
3.5
4.0
AVDD (V)
AVDD (V)
Figure 11.
Figure 12.
4.5
5.0
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
Channel A
AVDD = 5.0V, External VREF = 4.99V
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
-0.5
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LE (LSB)
Digital Input Code
Channel C
AVDD = 5.0V, External VREF = 4.99V
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
0
-0.5
Channel D
AVDD = 5.0V, External VREF = 4.99V
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 15.
Figure 16.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
2
0
-2
-4
-6
Channel A
AVDD = 5.0V, External VREF = 4.99V
LE (LSB)
0
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
0
57344 65536
DLE (LSB)
LE (LSB)
DLE (LSB)
6
4
2
0
-2
-4
-6
8192
-1.0
DLE (LSB)
Channel B
AVDD = 5.0V, External VREF = 4.99V
-1.0
0
0
-0.5
-1.0
Channel B
AVDD = 5.0V, External VREF = 4.99V
0
-0.5
-1.0
0
10
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 17.
Figure 18.
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57344 65536
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
Channel C
AVDD = 5.0V, External VREF = 4.99V
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
0
-0.5
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 19.
Figure 20.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
6
4
2
0
-2
-4
-6
Channel A
AVDD = 5.0V, External VREF = 4.99V
LE (LSB)
Digital Input Code
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
DLE (LSB)
8192
0
-0.5
-1.0
Channel B
AVDD = 5.0V, External VREF = 4.99V
0
-0.5
-1.0
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 21.
Figure 22.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LE (LSB)
0
Channel C
AVDD = 5.0V, External VREF = 4.99V
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
Channel D
AVDD = 5.0V, External VREF = 4.99V
-1.0
0
DLE (LSB)
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
0
-0.5
-1.0
Channel D
AVDD = 5.0V, External VREF = 4.99V
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 23.
Figure 24.
57344 65536
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
OFFSET ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
4
0.50
AVDD = 5V
Internal VREF Enabled
Full-Scale Error (mV)
3
Offset Error (mV)
AVDD = 5V
Internal VREF Enabled
Ch C
2
1
Ch D
Ch A
0
Ch B
-1
-40
-20
0
20
40
60
80
100
Ch C
0.25
Ch D
0
-0.50
-40
120
-20
0
Temperature (°C)
Figure 26.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
80
100
120
5.5
DAC Loaded with FFFFh
4.5
3.5
AVDD = 5V, Ch A
Internal Reference Disabled
2.5
1.5
0.5
DAC Loaded with FFFFh
4.5
3.5
AVDD = 5V, Ch B
Internal Reference Disabled
2.5
1.5
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
-0.5
-0.5
0
5
10
15
20
0
5
10
15
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 27.
Figure 28.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
5.5
20
5.5
DAC Loaded with FFFFh
4.5
3.5
Analog Output Voltage (V)
Analog Output Voltage (V)
60
Figure 25.
Analog Output Voltage (V)
Analog Output Voltage (V)
40
20
Temperature (°C)
5.5
AVDD = 5V, Ch C
Internal Reference Disabled
2.5
1.5
0.5
DAC Loaded with FFFFh
4.5
3.5
AVDD = 5V, Ch D
Internal Reference Disabled
2.5
1.5
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
-0.5
-0.5
0
12
Ch B
Ch A
-0.25
5
10
15
20
0
5
10
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 29.
Figure 30.
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20
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1400
AVDD = 5.5V
Internal VREF Included
1200
Power-Supply Current (mA)
Power-Supply Current (mA)
1300
1100
1000
900
800
0
1300
1200
1100
1000
900
800
-40
8192 16384 24576 32768 40960 49152 57344 65536
0
-20
60
80
Temperature (°C)
Figure 31.
Figure 32.
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE
100
120
1.2
AVDD = 2.7V to 5.5V
Internal VREF Included
1090
Power-Down Current (mA)
AVDD = 2.7V to 5.5V
Internal VREF Included
DAC Loaded with 8000h
1080
1070
1060
1.0
0.8
0.6
0.4
0.2
1050
2.7
3.1
3.5
4.3
3.9
4.7
5.1
2.7
5.5
3.1
3.5
3.9
AVDD (V)
4.7
Figure 33.
Figure 34.
POWER-DOWN CURRENT
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
3200
5.1
5.5
AVDD = IOVDD = 5.5V, Internal VREF Included
AVDD = 5.5V
Power-Supply Current (mA)
2.5
2.0
1.5
1.0
0.5
0
-40
4.3
AVDD (V)
3.0
Power-Down Current (mA)
40
20
Digital Input Code
1100
Power-Supply Current (mA)
AVDD = 5.5V
Internal VREF Included
DAC Loaded with 8000h
SYNC Input (all other digital inputs = GND)
2800
2400
Sweep from
0V to 5.5V
2000
1600
Sweep from
5.5V to 0V
1200
800
-20
0
20
40
60
80
100
120
0
1
2
3
4
5
6
VLOGIC (V)
Temperature (°C)
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
AVDD = 5V, External VREF = 4.9V, Ch A
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
-50
-60
-70
THD (dB)
-60
THD (dB)
AVDD = 5V, External VREF = 4.9V, Ch B
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
THD
THD
-70
2nd Harmonic
-80
-80
3rd Harmonic
-90
-90
3rd Harmonic
2nd Harmonic
-100
-100
0
-40
1
2
4
3
5
0
2
3
4
fOUT (kHz)
Figure 37.
Figure 38.
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
AVDD = 5V, External VREF = 4.9V, Ch C
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
1
fOUT (kHz)
5
AVDD = 5V, External VREF = 4.9V, Ch D
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
-60
THD (dB)
THD (dB)
-60
-70
THD
-70
THD
2nd Harmonic
-80
-80
-90
3rd Harmonic
3rd Harmonic
-90
-100
2nd Harmonic
-100
-110
0
1
2
4
3
5
0
1
2
3
fOUT (kHz)
fOUT (kHz)
Figure 39.
Figure 40.
4
5
POWER-SUPPLY CURRENT
HISTOGRAM
60
Occurrence (%)
50
AVDD = 5.5V
Internal VREF Included
40
30
20
10
0
950
1000
1050
1100
1150
1200
Power-Supply Current (mA)
Figure 41.
14
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
POWER SPECTRAL DENSITY
0
94
AVDD = 5V, External VREF = 4.9V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
92
Ch D
-40
Gain (dB)
SNR (dB)
Ch A
90
Ch C
Ch B
88
AVDD = 5V, External VREF = 4.9V
fOUT = 1kHz, fS = 225kSPS
Measurement Bandwidth = 20kHz
-20
-60
-80
-100
-120
86
-140
0
1
2
3
4
5
0
5
10
15
Figure 42.
Figure 43.
FULL-SCALE SETTLING TIME:
5V RISING EDGE
FULL-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
AVDD = 5V
Ext VREF = 4.096V
From Code: 0000h
To Code: FFFFh
Rising Edge
1V/div
20
Frequency (Hz)
fOUT (kHz)
Zoomed Rising Edge
1mV/div
Trigger Pulse 5V/div
AVDD = 5V
Ext VREF = 4.096V
From Code: FFFFh
To Code: 0000h
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 44.
Figure 45.
HALF-SCALE SETTLING TIME:
5V RISING EDGE
HALF-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
AVDD = 5V
Ext VREF = 4.096V
From Code: C000h
To Code: 4000h
Rising
Edge
1V/div
AVDD = 5V
Ext VREF = 4.096V
From Code: 4000h
To Code: C000h
Zoomed Rising Edge
1mV/div
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 46.
Figure 47.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
AVDD = 5V
Int VREF = 2.5V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
AVDD = 5V
Int VREF = 2.5V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Figure 48.
Figure 49.
GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 16LSB STEP, FALLING EDGE
AVDD = 5V
Int VREF = 2.5V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
VOUT (500mV/div)
Time (400ns/div)
VOUT (500mV/div)
Time (400ns/div)
AVDD = 5V
Int VREF = 2.5V
From Code: 8010h
To Code: 8000h
Glitch: 0.08nV-s
Time (400ns/div)
Figure 50.
Figure 51.
GLITCH ENERGY:
5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 256LSB STEP, FALLING EDGE
AVDD = 5V
Int VREF = 2.5V
From Code: 8000h
To Code: 8100h
Glitch: Not Detected
VOUT (5mV/div)
Time (400ns/div)
VOUT (5mV/div)
16
GLITCH ENERGY:
5V, 1LSB STEP, FALLING EDGE
VOUT (500mV/div)
VOUT (500mV/div)
GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE
AVDD = 5V
Int VREF = 2.5V
From Code: 8100h
To Code: 8000h
Glitch: Not Detected
Time (400ns/div)
Time (400ns/div)
Figure 52.
Figure 53.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued)
At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless
otherwise noted.
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (1)
1200
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (2)
400
Internal Reference Enabled
No Load at VREFH/VREFOUT Pin
1000
DAC = Full-Scale
Internal Reference Enabled
4.8mF versus No Load at VREFH/VREFOUT Pin
350
Noise (nV/ÖHz)
Noise (nV/ÖHz)
300
800
600
Mid-Scale
400
Full Scale
250
200
No Load on Reference
150
100
Zero Scale
200
4.8mF Capacitor
On Reference
50
0
0
10
100
1k
10k
100k
1M
10
Frequency (Hz)
100
1k
10k
100k
1M
Frequency (Hz)
Figure 54.
Figure 55.
DAC OUTPUT NOISE
0.1Hz TO 10Hz
VNOISE (2mV/div)
6mV (peak-to-peak)
DAC = Mid-Scale
Internal Reference Enabled
Time (2s/div)
Figure 56.
(1)
(2)
Explained in more detail in the Application Information section of this data sheet.
See the Application Information section for more information.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
vs TEMPERATURE
1400
2400
Power-Supply Current (mA)
Power-Supply Current (mA)
AVDD = IOVDD = 3.6V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
2000
1600
Sweep from 0V to 3.6V
1200
Sweep from
3.6V to 0V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
AVDD = 3.6V
Internal VREF Included
DAC Loaded with 8000h
1200
1100
1000
900
800
-40
800
0
1300
4.0
-20
0
20
40
60
80
100
120
Temperature (°C)
VLOGIC (V)
Figure 57.
Figure 58.
POWER-SUPPLY CURRENT
HISTOGRAM
80
AVDD = 3.6V
Internal VREF Included
Occurrence (%)
60
40
20
0
900
950
1000
1050
1100
1150
1200
Power-Supply Current (mA)
Figure 59.
18
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
Channel A
AVDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
0
-0.5
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 60.
Figure 61.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
LE (LSB)
Digital Input Code
Channel C
AVDD = 2.7V, Internal VREF = 2.5V
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
DLE (LSB)
6
4
2
0
-2
-4
-6
8192
0
-0.5
-1.0
Channel D
AVDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 62.
Figure 63.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
2
0
-2
-4
-6
Channel A
AVDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
0
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
Channel B
AVDD = 2.7V, Internal VREF = 2.5V
-1.0
0
DLE (LSB)
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
0
-0.5
-1.0
Channel B
AVDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 64.
Figure 65.
57344 65536
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
LE (LSB)
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
Channel C
AVDD = 2.7V, Internal VREF = 2.5V
1.0
0.5
0.5
0
-0.5
-1.0
16384 24576 32768 40960 49152
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Figure 66.
Figure 67.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
Channel A
AVDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
Digital Input Code
6
4
2
0
-2
-4
-6
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
0
-0.5
Channel B
AVDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
Digital Input Code
Figure 68.
Figure 69.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
6
4
2
0
-2
-4
-6
Channel C
AVDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
0
6
4
2
0
-2
-4
-6
1.0
1.0
0.5
0.5
DLE (LSB)
LE (LSB)
0
-0.5
57344 65536
DLE (LSB)
LE (LSB)
DLE (LSB)
8192
-1.0
DLE (LSB)
Channel D
AVDD = 2.7V, Internal VREF = 2.5V
-1.0
0
0
-0.5
-1.0
Channel D
AVDD = 2.7V, Internal VREF = 2.5V
0
-0.5
-1.0
0
20
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 70.
Figure 71.
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57344 65536
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
OFFSET ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
4
0.50
AVDD = 2.7V
Internal VREF Enabled
Full-Scale Error (mV)
Ch C
3
Offset Error (mV)
AVDD = 2.7V
Internal VREF Enabled
2
1
Ch D
Ch B
0
Ch A
-1
-40
-20
0
40
20
60
80
100
Ch C
0.25
Ch D
0
-0.50
-40
120
-20
0
Temperature (°C)
20
40
Figure 72.
Figure 73.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
80
100
120
3.0
DAC Loaded with FFFFh
DAC Loaded with FFFFh
2.5
2.0
Analog Output Voltage (V)
Analog Output Voltage (V)
60
Temperature (°C)
3.0
AVDD = 2.7V, Ch A
Internal Reference Enabled
1.5
1.0
0.5
2.5
2.0
AVDD = 2.7V, Ch B
Internal Reference Enabled
1.5
1.0
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
0
0
0
5
10
15
20
0
5
10
15
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 74.
Figure 75.
SOURCE AND SINK
CURRENT CAPABILITY
SOURCE AND SINK
CURRENT CAPABILITY
3.0
20
3.0
DAC Loaded with FFFFh
DAC Loaded with FFFFh
2.5
2.0
Analog Output Voltage (V)
Analog Output Voltage (V)
Ch B
Ch A
-0.25
AVDD = 2.7V, Ch C
Internal Reference Enabled
1.5
1.0
0.5
2.5
2.0
AVDD = 2.7V, Ch D
Internal Reference Enabled
1.5
1.0
0.5
DAC Loaded with 0000h
DAC Loaded with 0000h
0
0
0
5
10
15
20
0
5
10
ISOURCE/SINK (mA)
ISOURCE/SINK (mA)
Figure 76.
Figure 77.
15
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
1600
AVDD = 2.7V
Internal VREF Included
1200
AVDD = 2.7V, Internal VREF Included
SYNC Input (all other digital inputs = GND)
Power-Supply Current (mA)
Power-Supply Current (mA)
1300
1100
1000
900
800
1400
1200
Sweep from 0V to 2.7V
Sweep from
2.7V to 0V
1000
800
0
8192 16384 24576 32768 40960 49152 57344 65536
0
Digital Input Code
0.5
1.0
1.5
2.0
2.5
3.0
VLOGIC (V)
Figure 78.
Figure 79.
FULL-SCALE SETTLING TIME:
2.7V RISING EDGE
FULL-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
AVDD = 2.7V
Int VREF = 2.5V
From Code: FFFFh
To Code: 0000h
Rising
Edge
0.5V/div
AVDD = 2.7V
Int VREF = 2.5V
From Code: 0000h
To Code: FFFFh
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 80.
Figure 81.
HALF-SCALE SETTLING TIME:
2.7V RISING EDGE
HALF-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
AVDD = 2.7V
Int VREF = 2.5V
From Code: C000h
To Code: 4000h
AVDD = 2.7V
Int VREF = 2.5V
From Code: 4000h
To Code: C000h
Rising
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Time (2ms/div)
Figure 82.
22
Zoomed Falling Edge
1mV/div
Figure 83.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
GLITCH ENERGY:
2.7V, 1LSB STEP, FALLING EDGE
VOUT (200mV/div)
AVDD = 2.7V
Int VREF = 2.5V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
AVDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Time (400ns/div)
Figure 84.
Figure 85.
GLITCH ENERGY:
2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 16LSB STEP, FALLING EDGE
AVDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
VOUT (200mV/div)
Time (400ns/div)
VOUT (200mV/div)
AVDD = 2.7V
Int VREF = 2.5V
From Code: 8010h
To Code: 8000h
Glitch: 0.12nV-s
Time (400ns/div)
Figure 86.
Figure 87.
GLITCH ENERGY:
2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 256LSB STEP, FALLING EDGE
VOUT (5mV/div)
Time (400ns/div)
AVDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 8100h
Glitch: Not Detected
VOUT (5mV/div)
VOUT (200mV/div)
GLITCH ENERGY:
2.7V, 1LSB STEP, RISING EDGE
AVDD = 2.7V
Int VREF = 2.5V
From Code: 8100h
To Code: 8000h
Glitch: Not Detected
Time (400ns/div)
Time (400ns/div)
Figure 88.
Figure 89.
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TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless
otherwise noted
POWER-SUPPLY CURRENT
vs TEMPERATURE
POWER-DOWN CURRENT
vs TEMPERATURE
1300
2.0
AVDD = 2.7V
Internal VREF Included
DAC Loaded with 8000h
1200
1100
1000
900
800
-40
24
AVDD = 2.7V
Power-Down Current (mA)
Power-Supply Current (mA)
1400
-20
0
20
40
60
80
100
120
1.5
1.0
0.5
0
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 90.
Figure 91.
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80
100
120
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THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The DAC8565 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 92
shows a block diagram of the DAC architecture.
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
VREF
VREFH
50kW
50kW
62kW
RDIVIDER
VOUTX
REF(+)
Resistor String
REF(-)
DAC
Register
VREF
2
R
VREFL
Figure 92. DAC8565 Architecture
To Output Amplifier
(2x Gain)
R
The input coding to the DAC8565 can be straight
binary or two's complement, so the ideal output
voltage is given by Equation 1.
DIN
V OUTX + 2 V REFL ) (V REFH * V REFL)
65536 (1)
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535. X represents channel A, B, C, or D.
R
DATA FORMAT
The data format can be straight binary or two’s
complement. Table 1 illustrates the differences
between USB (unsigned straight binary) and BTC
(binary two’s complement) data formats.
R
Table 1. USB and BTC Codes
USB CODE
BTC CODE
DESCRIPTION
FFFFh
7FFFh
+Full-Scale – 1LSB
Figure 93. Resistor String
...
8001h
0001h
Midscale + 1LSB
8000h
0000h
Midscale
7FFFh
FFFFh
Midscale – 1LSB
...
0000h
8000h
Zero Scale
RESISTOR STRING
The resistor string section is shown in Figure 93. It is
simply a string of resistors, each of value R. The
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to AVDD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 2.2V/µs,
with a full-scale settling time of 8µs with the output
unloaded.
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INTERNAL REFERENCE
VREF
The DAC8565 includes a 2.5V internal reference that
is enabled by default. The internal reference is
externally available at the VREFH/VREFOUT pin. A
minimum 100nF capacitor is recommended between
the reference output and GND for noise filtering.
Reference
Disable
The internal reference of the DAC8565 is a bipolar
transistor-based,
precision
bandgap
voltage
reference. Figure 94 shows the basic bandgap
topology. Transistors Q1 and Q2 are biased such that
the current density of Q1 is greater than that of Q2.
The difference of the two base-emitter voltages
(VBE1 – VBE2) has a positive temperature coefficient
and is forced across resistor R1. This voltage is
gained up and added to the base-emitter voltage of
Q2, which has a negative temperature coefficient. The
resulting output voltage is virtually independent of
temperature. The short-circuit current is limited by
design to approximately 100mA.
Enable/Disable Internal Reference
The internal reference in the DAC8565 is enabled by
default and operates in automatic mode; however, the
reference can be disabled for debugging, evaluation
purposes, or when using an external reference. A
serial command that requires a 24-bit write sequence
(see the Serial Interface section) must be used to
disable the internal reference, as shown in Table 2.
During the time that the internal reference is disabled,
the DAC functions normally using an external
reference. At this point, the internal reference is
disconnected from the VREFH/VREFOUT pin (3-state
output). Do not attempt to drive the VREFH/VREFOUT
pin externally and internally at the same time
indefinitely.
Q1
1
N
Q2
R1
R2
Figure 94. Simplified Schematic of the Bandgap
Reference
To then enable the internal reference, either perform
a power-cycle to reset the device, or write the 24-bit
serial command shown in Table 3. These actions put
the internal reference back into the default mode. In
the default mode, the internal reference powers down
automatically when all DACs power down in any of
the power-down modes (see the Power-Down Modes
section); the internal reference powers up
automatically when any DAC is powered up.
The DAC8565 also provides the option of keeping the
internal reference powered on all the time, regardless
of the DAC(s) state (powered up or down). To keep
the internal reference powered on, regardless of the
DAC(s) state, write the 24-bit serial command shown
in Table 4.
Table 2. Write Sequence for Disabling Internal Reference
(internal reference always powered down—012000h)
DB23
0
DB16
0
0
0
0
0
0
1
DB13
0
0
1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
|—————————————————–– Data Bits ––—————————————————|
Table 3. Write Sequence for Enabling Internal Reference
(internal reference powered up to default mode—010000h)
DB23
0
DB16
0
0
0
0
0
0
1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
|—————————————————–– Data Bits ––—————————————————|
Table 4. Write Sequence for Enabling Internal Reference
(internal reference always powered up—011000h)
DB23
0
DB16
0
0
0
0
0
0
1
DB12
0
0
0
1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
|—————————————————–– Data Bits ––—————————————————|
26
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SERIAL INTERFACE
The DAC8565 has a 3-wire serial interface (SYNC,
SCLK, and DIN) compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram for an
example of a typical write sequence.
The DAC8565 input shift register is 24 bits wide,
consisting of eight control bits (DB23 to DB16) and 16
data bits (DB15 to DB0). All 24 bits of data are
loaded into the DAC under the control of the serial
clock input, SCLK. DB23 (MSB) is the first bit that is
loaded into the DAC shift register, and is followed by
the rest of the 24-bit word pattern, left-aligned. This
configuration means that the first 24 bits of data are
latched into the shift register and any further clocking
of data is ignored. The DAC8565 receives all 24 bits
of data and decodes the first eight bits to determine
the DAC operating/control mode. The 16 bits of data
that follow are decoded by the DAC to determine the
equivalent analog output. The data format is straight
binary with all '0's corresponding to 0V output and all
'1's corresponding to full-scale output (that is, VREF –
1 LSB); see the Data Format section for more details.
The write sequence begins by bringing the SYNC line
low. Data from the DIN line are clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
the DAC8565 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked into the shift register and the shift
register locks. Further clocking does not change the
shift register data. Once 24 bits are locked into the
shift register, the eight MSBs are used as control bits
and the 16 LSBs are used as data. After receiving the
24th falling clock edge, the DAC8565 decodes the
eight control bits and 16 data bits to perform the
required function, without waiting for a SYNC rising
edge. A new write sequence starts at the next falling
edge of SYNC. A rising edge of SYNC before the
24-bit sequence is complete resets the SPI interface;
no data transfer occurs. After the 24th falling edge of
SCLK is received, the SYNC line may be kept LOW
or brought HIGH. In either case, the minimum delay
time from the 24th falling SCLK edge to the next
falling SYNC edge must be met in order to properly
begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that
the levels are as close to each rail as possible. Refer
to the Typical Characteristics section for Figure 36,
Figure 57, and Figure 79 (Supply Current vs Logic
Input Voltage).
IOVDD AND VOLTAGE TRANSLATORS
The IOVDD pin powers the the digital input structures
of the DAC8565. For single-supply operation, it can
be tied to AVDD. For dual-supply operation, the IOVDD
pin provides interface flexibility with various CMOS
logic families and should be connected to the logic
supply of the system. Analog circuits and internal
logic of the DAC8565 use AVDD as the supply
voltage. The external logic high inputs translate to
AVDD by level shifters. These level shifters use the
IOVDD voltage as a reference to shift the incoming
logic HIGH levels to AVDD. IOVDD is ensured to
operate from 2.7V to 5.5V regardless of the AVDD
voltage, assuring compatibility with various logic
families. Although specified down to 2.7V, IOVDD
operates at as low as 1.8V with degraded timing and
temperature performance. For lowest power
consumption, logic VIH levels should be as close as
possible to IOVDD, and logic VIL levels should be as
close as possible to GND voltages.
ASYNCHRONOUS RESET
The DAC8565 output is asynchronously set to
zero-scale voltage or midscale voltage (depending on
RSTSEL) immediately after the RST pin is brought
low. The RST signal resets all internal registers, and
therefore, behaves like the Power-On Reset. The
RST pin must be brought back to high before a write
sequence starts. If the RSTSEL pin is high, the RST
signal going low resets all outputs to midscale. If the
RSTSEL pin is low, the RST signal going low resets
all outputs to zero-scale. RSTSEL should be set at
power-up.
INPUT SHIFT REGISTER
The input shift register (SR) of the DAC8565 is 24
bits wide, as shown in Table 5. It consists of eight
control bits (DB23 to DB16) and 16 data bits (DB15
to DB0). DB23 and DB22 should always be '0'.
Table 5. DAC8565 Data Input Register Format
DB23
0
DB12
0
LD1
LD0
0
DAC Select 1
DAC Select 0
PD0
D15
D14
D13
DB11
D11
D12
DB0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
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LD1 (DB21) and LD0 (DB20) control the updating of
each analog output with the specified 16-bit data
value or power-down command. Bit DB19 must
always be '0'. The DAC channel select bits (DB18,
DB17) control the destination of the data (or
power-down command) from DAC A to DAC D. The
final control bit, PD0 (DB16), selects the power-down
mode of the DAC8565 channels as well as the
power-down mode of the internal reference.
DB21 = 0 and DB20 = 1: Single-channel update.
The temporary register and DAC register
corresponding to a DAC selected by DB18 and DB17
are updated with the contents of SR data (or
power-down).
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 updates with
the SR data; simultaneously, all the other channels
update with previously stored data (or power-down)
from temporary registers.
The DAC8565 supports a number of different load
commands. The load commands include broadcast
commands to address all the DAC8565s on an SPI
bus. The load commands are summarized as follows:
DB21 = 1 and DB20 = 1: Broadcast update. If
DB18 = 0, then SR data are ignored and all channels
are updated with previously stored data (or
power-down). If DB18 = 1, then SR data (or
power-down) updates all channels. Refer to Table 6
for more information.
DB21 = 0 and DB20 = 0: Single-channel store. The
temporary register (data buffer) corresponding to a
DAC selected by DB18 and DB17 updates with the
contents of SR data (or power-down).
Table 6. Control Matrix for the DAC8565
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13-DB0
0
0
LD 1
LD 0
0
DAC Sel 1
DAC Sel 0
PD0
MSB
MSB-1
MSB-2...LSB
0
0
0
0
0
0
Data
Write to buffer A with data
0
0
0
0
1
0
Data
Write to buffer B with data
0
0
0
1
0
0
Data
Write to buffer C with data
0
0
0
1
1
0
Data
Write to buffer D with data
0
0
0
(00, 01, 10, or 11)
1
0
1
0
(00, 01, 10, or 11)
0
0
1
0
(00, 01, 10, or 11)
1
1
0
0
(00, 01, 10, or 11)
0
1
0
0
(00, 01, 10, or 11)
1
See Table 7
0
0
Write to buffer with power-down command and load
DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and DB18)
and then load all DACs simultaneously from their
corresponding buffers
Data
See Table 7
Write to buffer (selected by DB17 and DB18) with
power-down command
Write to buffer with data and load DAC (selected by
DB17 and DB18)
Data
See Table 7
DESCRIPTION
0
Write to buffer with power-down command (selected by
DB17 and DB18) and then load all DACs
simultaneously from their corresponding buffers
Broadcast Modes
28
X
X
1
1
0
X
X
1
1
0
X
X
1
1
0
0
X
X
X
Simultaneously update all channels of DAC8565 with
data stored in each channels temporary register
1
X
0
Data
Write to all channels and load all DACs with SR data
1
X
1
See Table 7
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0
Write to all channels and load all DACs with
power-down command in SR
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SYNC INTERRUPT
LDAC FUNCTIONALITY
In a normal write sequence, the SYNC line stays low
for at least 24 falling edges of SCLK and the
addressed DAC register updates on the 24th falling
edge. However, if SYNC is brought high before the
24th falling edge, it acts as an interrupt to the write
sequence; the shift register resets and the write
sequence is discarded. Neither an update of the data
buffer contents, DAC register contents, nor a change
in the operating mode occurs (as shown in
Figure 95).
The DAC8565 offer both a software and hardware
simultaneous
update
function.
The
DAC
double-buffered architecture has been designed so
that new data can be entered for each DAC without
disturbing the analog outputs.
POWER-ON RESET TO ZERO-SCALE OR
MIDSCALE
The DAC8565 contains a power-on reset circuit that
controls the output voltage during power-up.
Depending on the RSTSEL signal, on power-up, the
DAC registers are reset and the output voltages are
set to zero-scale (RSTSEL = 0) or midscale (RSTSEL
= 1); they remain that way until a valid write
sequence and load command are made to the
respective DAC channel. The power-on reset is
useful in applications where it is important to know
the state of the output of each DAC while the device
is in the process of powering up.
No device pin should be brought high before power is
applied to the device. The internal reference is
powered on by default and remains that way until a
valid reference-change command is executed.
DAC8565 data updates are synchronized with the
falling edge of the 24th SCLK cycle, which follows a
falling edge of SYNC. For such synchronous updates,
the LDAC pin is not required and it must be
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
asynchronous DAC updates. To do an LDAC
operation, single-channel store(s) should be done
(loading DAC buffers) by setting LD0 and LD1 to '0'.
Multiple single-channel updates can be done in order
to set different channel buffers to desired values and
then make a rising edge on LDAC. Data buffers of all
channels must be loaded with desired data before an
LDAC rising edge. After a low-to-high LDAC
transition, all DACs are simultaneously updated with
the contents of the corresponding data buffers. If the
contents of a data buffer are not changed by the
serial interface, the corresponding DAC output
remains unchanged after the LDAC trigger.
ENABLE PIN
For normal operation, the enable pin must be driven
to a logic low. If the enable pin is driven high, the
DAC8565 stops listening to the serial port. However,
SCLK, SYNC, and DIN must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB0
DB23
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
DB0
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 95. SYNC Interrupt Facility
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POWER-DOWN MODES
The DAC8565 has two separate sets of power-down
commands. One set is for the DAC channels and the
other set is for the internal reference. For more
information on powering down the reference, see the
Enable/Disable Internal Reference section.
DAC Power-Down Commands
The DAC8565 use four modes of operation. These
modes are accessed by setting three bits (PD2, PD1,
and PD0) in the shift register. Table 7 shows how to
control the operating mode with data bits PD0
(DB16), PD1 (DB15), and PD2 (DB14).
Table 7. DAC Operating Modes
PD0
(DB16)
PD1
(DB15)
PD2
(DB14)
0
X
X
Normal operation
1
0
1
Output typically 1kΩ to GND
1
1
0
Output typically 100 kΩ to GND
1
1
1
Output high-impedance
DAC OPERATING MODES
The DAC8565 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a power-down
condition to all the DAC8565s in a system; it is also
possible to simultaneously power-down a channel
while updating data on other channels.
When the PD0 bit is set to '0', the device works
normally with its typical current consumption of 1mA
at 5.5V with an input code = 32768. The reference
current is included with the operation of all four
30
DACs. However, for the three power-down modes,
the supply current falls to 1.3µA at 5.5V (0.5µA at
3.6V). Not only does the supply current fall, but the
output stage also switches internally from the output
of the amplifier to a resistor network of known values.
The advantage of this switching is that the output
impedance of the device is known while it is in
power-down mode. As described in Table 7, there are
three different power-down options. VOUT can be
connected internally to GND through a 1kΩ resistor, a
100kΩ resistor, or open circuited (High-Z). The output
stage is shown in Figure 96. In other words, DB16,
DB15, and DB14 = '111' represent a power-down
condition with Hi-Z output impedance for a selected
channel. '101' represents a power-down condition
with 1kΩ output impedance, and '110' represents a
power-down condition with 100kΩ output impedance.
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
VOUTX
Resistor
Network
Figure 96. Output Stage During Power-Down
All analog channel circuitries are shut down when the
power-down mode is exercised. However, the
contents of the DAC register are unaffected when in
power down. The time required to exit power-down is
typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V.
See the Typical Characteristics for more information.
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OPERATING EXAMPLES: DAC8565
For the following examples, X = don't care. Value can be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
• 1st: Write to data buffer A:
•
•
•
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
2nd: Write to data buffer B:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
3rd: Write to data buffer C:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
4th: Write to data buffer D and simultaneously update all DACs:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
• 1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
•
•
•
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
After completion of each write cycle, DAC analog output settles to the voltage specified.
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Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ
Simultaneously
• 1st: Write power-down command to data buffer A: DAC A to 1kΩ.
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
•
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
1
X
X
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
1
X
X
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
0
X
X
X
2nd: Write power-down command to data buffer B: DAC B to 1kΩ.
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
•
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
3rd: Write power-down command to data buffer C: DAC C to 100kΩ.
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
•
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
4th: Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
0
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
• 1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
•
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
•
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
•
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
32
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Example 5: Power-Down All Channels Simultaneously while Reference is Always Powered Up
• 1st: Write sequence for enabling the DAC8565 internal reference all the time:
•
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
0
0
1
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
2nd: Write sequence to power-down all DACs to high-impedance:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first and second write sequences, respectively.
Example 6: Write a Specific Value to All DACs while Reference is Always Powered Down
• 1st: Write sequence for disabling the DAC8565 internal reference all the time (after this sequence, the
DAC8565 requires an external reference source to function):
•
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
0
1
0
X
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
2nd: Write sequence to write specified data to all DACs:
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the fourth write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling
edge of the fourth write cycle). Reference is always powered-down.
Example 7: Write a Specific Value to DAC A, while Reference is Placed in Default Mode and All Other
DACs are Powered Down to High-Impedance
• 1st: Write sequence for placing the DAC8565 internal reference into default mode. Alternately, this step can
be replaced by performing a power-on reset (see the Power-On Reset section):
•
•
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
0
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
0
0
0
0
X
2nd: Write sequence to power-down all DACs to high-impedance (after this sequence, the DAC8565 internal
reference powers down automatically):
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
1
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
1
1
1
X
X
X
3rd: Write sequence to power-up DAC A to a specified value (after this sequence, the DAC8565 internal
reference powers up automatically):
DB23
DB22
DB21
(LD1)
DB20
(LD0)
DB19
0
0
0
1
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
DB15
DB14
DB13
DB12
DB11–DB0
0
D15
D14
D13
D12
D11–D0
The DAC B, DAC C, and DAC D analog outputs simultaneously power-down to high-impedance, and DAC A
settles to the specified value upon completion.
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APPLICATION INFORMATION
INTERNAL REFERENCE
The internal reference of the DAC8565 does not
require an external load capacitor for stability
because it is stable with any capacitive load.
However, for improved noise performance, an
external load capacitor of 150nF or larger connected
to the VREFH/VREFOUT output is recommended.
Figure 97 shows the typical connections required for
operation of the DAC8565 internal reference. A
supply bypass capacitor at the AVDD input is also
recommended.
DAC8565
150nF
AVDD
1
VOUTA
LDAC 16
2
VOUTB
ENABLE 15
3
VREFH/VREFOUT
RSTSEL 14
4
AVDD
5
VREFL
6
GND
7
VOUTC
SCLK 10
8
VOUTD
SYNC
RST 13
0.1mF
IOVDD 12
DIN 11
9
Temperature Drift
The internal reference is designed to exhibit minimal
drift error, defined as the change in reference output
voltage over varying temperature. The drift is
calculated using the box method described by
Equation 2:
Drift Error =
VREF_MAX - VREF_MIN
VREF ´ TRANGE
6
´ 10 (ppm/°C)
(2)
Where:
VREF_MAX = maximum reference voltage observed
within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed
within temperature range TRANGE.
VREF = 2.5V, target value for reference output
voltage.
The internal reference (grades C and D) features an
exceptional typical drift coefficient of 2ppm/°C from
–40°C to +120°C. Characterizing a large number of
units, a maximum drift coefficient of 5ppm/°C (grades
C and D) is observed. Temperature drift results are
summarized in the Typical Characteristics.
Noise Performance
Figure 97. Typical Connections for Operating the
DAC8565 Internal Reference
Supply Voltage
The internal reference features an extremely low
dropout voltage. It can be operated with a supply of
only 5mV above the reference output voltage in an
unloaded condition. For loaded conditions, refer to
the Load Regulation section. The stability of the
internal reference with variations in supply voltage
(line regulation, dc PSRR) is also exceptional. Within
the specified supply voltage range of 2.7V to 5.5V,
the variation at VREFH/VREFOUT is less than 10µV/V;
see the Typical Characteristics.
34
Typical 0.1Hz to 10Hz voltage noise can be seen in
Figure 8, Internal Reference Noise. Additional filtering
can be used to improve output noise levels, although
care should be taken to ensure the output impedance
does not degrade the ac performance. The output
noise spectrum at VREFH/VREFOUT without any
external components is depicted in Figure 7, Internal
Reference Noise Density vs Frequency. Another
noise density spectrum is also shown in Figure 7.
This spectrum was obtained using a 4.8µF load
capacitor at VREFH/VREFOUT for noise filtering.
Internal reference noise impacts the DAC output
noise; see the DAC Noise Performance section for
more details.
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Load Regulation
Thermal Hysteresis
Load regulation is defined as the change in reference
output voltage as a result of changes in load current.
The load regulation of the internal reference is
measured using force and sense contacts as shown
in Figure 98. The force and sense lines reduce the
impact of contact and trace resistance, resulting in
accurate measurement of the load regulation
contributed solely by the internal reference.
Measurement results are summarized in the Typical
Characteristics. Force and sense lines should be
used for applications that require improved load
regulation.
Thermal hysteresis for a reference is defined as the
change in output voltage after operating the device at
+25°C, cycling the device through the operating
temperature range, and returning to +25°C.
Hysteresis is expressed by Equation 3:
Output Pin
Contact and
Trace Resistance
VOUT
Force Line
IL
|VREF_PRE - VREF_POST|
VREF_NOM
6
´ 10 (ppm/°C)
(3)
Where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at +25°C
pre-temperature cycling.
VREF_POST = output voltage measured after the
device cycles through the temperature range of
–40°C to +120°C, and returns to +25°C.
DAC NOISE PERFORMANCE
Sense Line
Meter
VHYST =
Load
Figure 98. Accurate Load Regulation of the
DAC8565 Internal Reference
Long-Term Stability
Long-term stability/aging refers to the change of the
output voltage of a reference over a period of months
or years. This effect lessens as time progresses (see
Figure 6, the typical long-term stability curve). The
typical drift value for the internal reference is 50ppm
from 0 hours to 1900 hours. This parameter is
characterized by powering-up and measuring 20 units
at regular intervals for a period of 1900 hours.
Typical noise performance for the DAC8565 with the
internal reference enabled is shown in Figure 54 to
Figure 56. Output noise spectral density at the VOUT
pin versus frequency is depicted in Figure 54 for
full-scale, midscale, and zero-scale input codes. The
typical noise density for midscale code is 120nV/√Hz
at 1kHz and 100nV/√Hz at 1MHz. High-frequency
noise can be improved by filtering the reference noise
as shown in Figure 55, where a 4.8µF load capacitor
is connected to the VREFH/VREFOUT pin and
compared to the no-load condition. Integrated output
noise between 0.1Hz and 10Hz is close to 6µVPP
(midscale), as shown in Figure 56.
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BIPOLAR OPERATION USING THE DAC8565
The DAC8565 is designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in either Figure 99 or Figure 100.
The circuit shown gives an output voltage range of
±VREF. Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
The output voltage for any input code can be
calculated with Equation 4:
VO =
VREF ´
D
65536
R 1 + R2
´
R1
- VREF ´
V
H
R2
10kW
AV
REF
DD
OPA703
AVDD
0.1mF
VREFL
-6V
GND
3-Wire
Serial Interface
R1
Figure 99. Bipolar Output Range Using External
Reference at 5V
where D represents the input code in decimal
(0–65535).
R2
10kW
AV
With VREFH = 5V, R1 = R2 = 10kΩ.
10 ´ D
65536
±5V
VOUT
VREFH DAC8565
10mF
R2
(4)
VO =
+6V
R1
10kW
DD
+6V
R1
10kW
- 5V
(5)
This result has an output voltage range of ±5V with
0000h corresponding to a –5V output and FFFFh
corresponding to a +5V output, as shown in
Figure 99. Similarly, using the internal reference, a
±2.5V output voltage range can be achieved, as
Figure 100 shows.
OPA703
AVDD
±2.5V
VOUT
VREFH DAC8565
150nF
VREFL
GND
-6V
3-Wire
Serial Interface
Figure 100. Bipolar Output Range Using Internal
Reference
36
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DAC8565
www.ti.com.......................................................................................................................................................... SBAS411B – JUNE 2007 – REVISED MARCH 2008
MICROPROCESSOR INTERFACING
Microwire(1)
DAC8565(1)
DAC8565 to an 8051 Interface
CS
SYNC
Figure 101 shows a serial interface between the
DAC8565 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8565, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051; in this case, port line P3.3 is used. When
data are to be transmitted to the DAC8565, P3.3 is
taken low. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken high following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8565 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
take this requirement into account, and mirror the
data as needed.
SK
SCLK
SO
DIN
80C51/80L51(1)
DAC8565(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 101. DAC8565 to 80C51/80L51 Interface
DAC8565 to Microwire Interface
Figure 102 shows an interface between the DAC8565
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
are clocked into the DAC8565 on the rising edge of
the SK signal.
NOTE: (1) Additional pins omitted for clarity.
Figure 102. DAC8565 to Microwire Interface
DAC8565 to 68HC11 Interface
Figure 103 shows a serial interface between the
DAC8565 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8565, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal derives from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
DAC8565(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 103. DAC8565 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8565, PC7 is left low after the first eight bits are
transferred; then, a second and third serial write
operation are performed to the DAC. PC7 is taken
high at the end of this procedure.
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SBAS411B – JUNE 2007 – REVISED MARCH 2008.......................................................................................................................................................... www.ti.com
LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8565 offers single-supply operation, and is
often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
As a result of the single ground pin of the DAC8565,
all return currents (including digital and analog return
currents for the DAC) must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
38
The power applied to VDD should be well-regulated
and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
As with the GND connection, VDD should be
connected to a power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1µF to 10µF capacitor and 0.1µF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100µF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the supply and
remove the high-frequency noise.
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www.ti.com.......................................................................................................................................................... SBAS411B – JUNE 2007 – REVISED MARCH 2008
PARAMETER DEFINITIONS
With the increased complexity of many different
specifications listed in product data sheets, this
section summarizes selected specifications related to
digital-to-analog converters.
STATIC PERFORMANCE
Static performance parameters are specifications
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and
provide information on the accuracy of the DAC. They
are most important in applications where the signal
changes slowly and accuracy is required.
Resolution
Generally, the DAC resolution can be expressed in
different forms. Specifications such as IEC 60748-4
recognize the numerical, analog, and relative
resolution. The numerical resolution is defined as the
number of digits in the chosen numbering system
necessary to express the total number of steps of the
transfer characteristic, where a step represents both
a digital input code and the corresponding discrete
analogue output value. The most commonly-used
definition of resolution provided in data sheets is the
numerical resolution expressed in bits.
Least Significant Bit (LSB)
Full-Scale Error
Full-scale error is defined as the deviation of the real
full-scale output voltage from the ideal output voltage
while the DAC register is loaded with the full-scale
code (0xFFFF). Ideally, the output should be VDD – 1
LSB. The full-scale error is expressed in percent of
full-scale range (%FSR).
Offset Error
The offset error is defined as the difference between
actual output voltage and the ideal output voltage in
the linear region of the transfer function. This
difference is calculated by using a straight line
defined by two codes (code 485 and 64714). Since
the offset error is defined by a straight line, it can
have a negative or positve value. Offset error is
measured in mV.
Zero-Code Error
The zero-code error is defined as the DAC output
voltage, when all '0's are loaded into the DAC
register. Zero-scale error is a measure of the
difference between actual output voltage and ideal
output voltage (0V). It is expressed in mV. It is
primarily caused by offsets in the output amplifier.
Gain Error
The least significant bit (LSB) is defined as the
smallest value in a binary coded system. The value of
the LSB can be calculated by dividing the full-scale
output voltage by 2n, where n is the resolution of the
converter.
Gain error is defined as the deviation in the slope of
the real DAC transfer characteristic from the ideal
transfer function. Gain error is expressed as a
percentage of full-scale range (%FSR).
Most Significant Bit (MSB)
Full-Scale Error Drift
The most significant bit (MSB) is defined as the
largest value in a binary coded system. The value of
the MSB can be calculated by dividing the full-scale
output voltage by 2. Its value is one-half of full-scale.
Full-scale error drift is defined as the change in
full-scale error with a change in temperature.
Full-scale error drift is expressed in units of
%FSR/°C.
Relative Accuracy or Integral Nonlinearity (INL)
Offset Error Drift
Relative accuracy or integral nonlinearity (INL) is
defined as the maximum deviation between the real
transfer function and a straight line passing through
the endpoints of the ideal DAC transfer function. DNL
is measured in LSBs.
Offset error drift is defined as the change in offset
error with a change in temperature. Offset error drift
is expressed in µV/°C.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is defined as the
maximum deviation of the real LSB step from the
ideal 1LSB step. Ideally, any two adjacent digital
codes correspond to output analog voltages that are
exactly one LSB apart. If the DNL is less than 1LSB,
the DAC is said to be monotonic.
Zero-Code Error Drift
Zero-code error drift is defined as the change in
zero-code error with a change in temperature.
Zero-code error drift is expressed in µV/°C.
Gain Temperature Coefficient
The gain temperature coefficient is defined as the
change in gain error with changes in temperature.
The gain temperature coefficient is expressed in ppm
of FSR/°C.
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Power-Supply Rejection Ratio (PSRR)
Channel-to-Channel DC Crosstalk
Power-supply rejection ratio (PSRR) is defined as the
ratio of change in output voltage to a change in
supply voltage for a full-scale output of the DAC. The
PSRR of a device indicates how the output of the
DAC is affected by changes in the supply voltage.
PSRR is measured in decibels (dB).
Channel-to-channel dc crosstalk is defined as the dc
change in the output level of one DAC channel in
response to a change in the output of another DAC
channel. It is measured with a full-scale output
change on one DAC channel while monitoring
another DAC channel remains at midscale. It is
expressed in LSB.
Monotonicity
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output
changes in the same direction or remains at least
constant for each step increase (or decrease) in the
input code.
DYNAMIC PERFORMANCE
Dynamic performance parameters are specifications
such as settling time or slew rate, which are important
in applications where the signal rapidly changes
and/or high frequency signals are present.
Slew Rate
The output slew-rate (SR) of an amplifier or other
electronic circuit is defined as the maximum rate of
change of the output voltage for all possible input
signals.
SR = max
Channel-to-Channel AC Crosstalk
AC crosstalk in a multi-channel DAC is defined as the
amount of ac interference experienced on the output
of a channel at a frequency (f) (and its harmonics),
when the output of an adjacent channel changes its
value at the rate of frequency (f). It is measured with
one channel output oscillating with a sine wave of
1kHz frequency, while monitoring the amplitude of
1kHz harmonics on an adjacent DAC channel output
(kept at zero scale). It is expressed in dB.
Signal-to-Noise Ratio (SNR)
Signal-to-noise ratio (SNR) is defined as the ratio of
the root mean-squared (RMS) value of the output
signal divided by the RMS values of the sum of all
other spectral components below one-half the output
frequency, not including harmonics or dc. SNR is
measured in dB.
DVOUT(t)
Total Harmonic Distortion (THD)
Dt
Where ΔVOUT(t) is the output produced by the
amplifier as a function of time t.
Output Voltage Settling Time
Settling time is the total time (including slew time) for
the DAC output to settle within an error band around
its final value after a change in input. Settling times
are specified to within ±0.003% (or whatever value is
specified) of full-scale range (FSR).
Total harmonic distortion + noise is defined as the
ratio of the RMS values of the harmonics and noise
to the value of the fundamental frequency. It is
expressed in a percentage of the fundamental
frequency amplitude at sampling rate fS.
Spurious-Free Dynamic Range (SFDR)
Digital-to-analog glitch impulse is the impulse injected
into the analog output when the input code in the
DAC register changes state. It is normally specified
as the area of the glitch in nanovolts-second (nV-s),
and is measured when the digital input code changes
by 1LSB at the major carry transition.
Spurious-free dynamic range (SFDR) is the usable
dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is
the measure of the difference in amplitude between
the fundamental and the largest harmonically or
non-harmonically related spur from dc to the full
Nyquist bandwidth (half the DAC sampling rate, or
fS/2). A spur is any frequency bin on a spectrum
analyzer, or from a Fourier transform, of the analog
output of the DAC. SFDR is specified in decibels
relative to the carrier (dBc).
Digital Feedthrough
Signal-to-Noise plus Distortion (SINAD)
Digital feedthrough is defined as impulse seen at the
output of the DAC from the digital inputs of the DAC.
It is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale
code change on the data bus; that is, from all '0's to
all '1's and vice versa.
SINAD includes all the harmonic and outstanding
spurious components in the definition of output noise
power in addition to quantizing any internal random
noise power. SINAD is expressed in dB at a specified
input frequency and sampling rate, fS.
Code Change/Digital-to-Analog Glitch Energy
40
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DAC8565
www.ti.com.......................................................................................................................................................... SBAS411B – JUNE 2007 – REVISED MARCH 2008
DAC Output Noise Density
Full-Scale Range (FSR)
Output
noise
density
is
defined
as
internally-generated random noise. Random noise is
characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to midscale and
measuring noise at the output.
Full-scale range (FSR) is the difference between the
maximum and minimum analog output values that the
DAC is specified to provide; typically, the maximum
and minimum values are also specified. For an n-bit
DAC, these values are usually given as the values
matching with code 0 and 2n.
DAC Output Noise
DAC output noise is defined as any voltage deviation
of DAC output from the desired value (within a
particular frequency band). It is measured with a DAC
channel kept at midscale while filtering the output
voltage within a band of 0.1Hz to 10Hz and
measuring its amplitude peaks. It is expressed in
terms of peak-to-peak voltage (Vpp).
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41
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8565IAPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
DAC8565IAPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
DAC8565IAPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
DAC8565IBPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
B
DAC8565IBPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
B
DAC8565IBPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
B
DAC8565IBPWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
B
DAC8565ICPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
DAC8565ICPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
DAC8565ICPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
DAC8565IDPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
D
DAC8565IDPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
D
DAC8565IDPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
DAC
8565
D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8565IAPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8565IBPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8565ICPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DAC8565IDPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8565IAPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
DAC8565IBPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
DAC8565ICPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
DAC8565IDPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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