19-0810; Rev 0; 4/07 Overvoltage Protectors with External pFET Features The MAX4923–MAX4926 overvoltage protection (OVP) controllers protect low-voltage systems against high-voltage faults of up to +28V with an appropriate external pFET. When the input voltage exceeds the overvoltage lockout (OVLO) threshold, or falls below the undervoltage lockout (UVLO) threshold, these devices turn off the pFET to prevent damage to protected components and issue a flag to notify the processor of a fault condition. The typical overvoltage trip level is set to 7.18V (MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and 4.46V (MAX4926). The undervoltage trip level is set to 2.44V (typ) for all devices. o Overvoltage Protection Up to +28V o Preset 7.18V, 6.16V, 5.65V, and 4.46V Typical Overvoltage Trip Levels o Preset 2.44V Typical Undervoltage Trip Level o ±2.5% Accurate Overvoltage/Undervoltage Trip Levels o Low 13µA (typ) Supply Current o Drives External pFET o 20ms Adapter Debounce Time o Fault Flag Indicator The input (IN) is ESD protected to ±15kV HBM when bypassed to ground with a 1µF ceramic capacitor. All devices are offered in a small, 6-pin (1.5mm x 1.0mm) µDFN package and are specified over the extended -40°C to +85°C temperature range. o 6-Pin (1.5mm x 1.0mm) µDFN Package Typical Operating Circuit Applications Cell Phones Digital Still Cameras INPUT +1.8V TO 28V PDAs and Palmtop Devices OUTPUT P MP3 Players Pin Configuration 1 4 IN GATE 1μF TOP VIEW N.C N.C GATE 6 5 4 2 MA4923–MAX4926 1 IN 2 3 GND FLAG VIO MAX4923–MAX4926 3 GND FLAG μDFN Ordering Information/Selector Guide PART PIN-PACKAGE OVLO (V) UVLO (V) TOP MARK PKG CODE MAX4923ELT+* 6 μDFN 7.18 2.44 LB L611-1 MAX4924ELT+ 6 μDFN 6.16 2.44 LC L611-1 MAX4925ELT+ 6 μDFN 5.65 2.44 LD L611-1 MAX4926ELT+ 6 μDFN 4.46 2.44 LE L611-1 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes lead-free package. *Future Product—contact factory for availability. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX4923–MAX4926 General Description MAX4923–MAX4926 Overvoltage Protectors with External pFET ABSOLUTE MAXIMUM RATINGS IN, GATE to GND....................................................-0.3V to +30V FLAG to GND ...........................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 6-µDFN (derate 2.1mW/°C above 70°C) .......................168mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300 °C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +5V for MAX4923/MAX4924/MAX4925, VIN = +4V for MAX4926, CGATE = 500pF to IN, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Input Voltage Range Overvoltage Lockout Level SYMBOL CONDITIONS VIN OVLO Overvoltage Lockout Hysteresis MIN VIN rising UVLO GATE Voltage High UNITS 28.0 V 7.00 7.18 7.36 MAX4924 6.00 6.16 6.31 MAX4925 5.50 5.65 5.79 MAX4926 4.35 4.46 4.57 MAX4923 65 MAX4924 55 MAX4925 50 VIN falling mV 2.439 2.500 20 IIN V 40 2.378 Undervoltage Lockout Hysteresis IN Supply Current MAX MAX4923 MAX4926 Undervoltage Lockout Level TYP 1.8 mV MAX4923/MAX4924/MAX4925 14 25 MAX4926 13 23 VIN 0.2 VOH VIN > 8V, ISOURCE = 0.1mA GATE Pulldown Current IPD VGATE = VIN FLAG Low Voltage VOL ISINK = 1mA FLAG Leakage Current ILKG VFLAG = 5.5V -1 Debounce Time tDEB VUVLO < VIN < VOVLO, time for GATE to go low (Figure 1) 10 Gate Turn-on Time tGON VGATE = 5V to 0.5V (MAX4923/MAX4924/MAX4925) or VGATE = 4V to 0.5V (MAX4926) (Figure 1) 0.6 tGOFF VIN rising at 1V/µs from 5V to 8V (MAX4923/MAX4924/MAX4925) or from 4V to 7V (MAX4926) to VGATE = VIN -0.5V (Figure 1) 5 tFLAG VIN rising at 1V µs from 5V to 8V (MAX4923/MAX4924/MAX4925) or from 4V to 7V (MAX4926), to VFLAG = 2.4V, RFLAG = 10kΩ to 3V (Figure 1) 4.5 6.5 V µA V 12 mA 0.4 V +1 µA 34 ms TIMING CHARACTERISTICS Gate Turn-Off Time Flag Assertion Delay 20 µs 20 µs µs Note 1: All devices are 100% tested at +25°C. Electrical limits across the full temperature range are guaranteed by design and characterization. 2 _______________________________________________________________________________________ Overvoltage Protectors with External pFET GATE VOLTAGE (V) 60 MAX4926 6 4 2 20 0 4 8 12 16 20 24 VCC = +2.5V 150 VCC = +3.3V 100 50 VCC = +5.5V 0 2 28 4 0 8 6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE 200 400 600 800 GATE SINK CURRENT (μA) MAX4923 toc04 MAX4926 VCC = +4V 14 1000 POWER-UP RESPONSE POWER-UP RESPONSE MAX4923 toc05 15 SUPPLY CURRENT (μA) 200 0 0 MAX4923 toc03 8 250 GATE OUTPUT LOW VOLTAGE (mV) MAX4925 MAX4925 40 MAX4923 toc02 80 SUPPLY CURRENT (μA) 10 MAX4923 toc01 100 GATE-OUTPUT LOW VOLTAGE vs. GATE SINK CURRENT GATE VOLTAGE vs. INPUT VOLTAGE SUPPLY CURRENT vs. INPUT VOLTAGE MAX4923 toc06 VIN 5V/div 5V/div VIN VOUT 5V/div 13 5V/div VGATE 12 IIN 5V/div 5V/div 11 1A/div VFLAG VFLAG 10 -40 -15 10 35 60 20.0 ms 85 10.0ms TEMPERATURE (°C) POWER-UP OVERVOLTAGE RESPONSE OVERVOLTAGE RESPONSE MAX4923 toc08 MAX4923 toc07 5V/div VIN VIN 5V/div 5V/div VGATE VGATE 5V/div 10mA/div IGATE 5V/div VFLAG 5V/div VFLAG 20.0μs 10.0ms _______________________________________________________________________________________ 3 MAX4923–MAX4926 Typical Operating Characteristics (VIN = +5V for MAX4923/MAX4924/MAX4925, VIN = +4V for MAX4926 (pFET = Si6991DQ), TA = +25°C, unless otherwise noted.) Overvoltage Protectors with External pFET MAX4923–MAX4926 Pin Description PIN NAME FUNCTION 1 IN 2 GND Ground 3 FLAG Fault Indication Open-Drain Output. FLAG deasserts high during undervoltage and overvoltage lockout conditions. FLAG asserts low during normal operation. 4 GATE pFET Gate Drive Output. GATE is driven high during a fault condition to turn off the external pFET. When VUVLO < VIN < VOVLO, GATE is driven low and the external pFET is turned on. 5, 6 N.C. Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage sense input. Bypass IN to GND with a 1µF ceramic capacitor as close as possible to the device to enable ±15kV (HBM) ESD protection on IN. No Connection. Not internally connected. Leave N.C. unconnected. Functional Diagram IN GATE GATE DRIVER MAX4923–MAX4926 CONTROL LOGIC AND TIMER OVLO AND UVLO DETECTOR GND FLAG VOVLO VUVLO VIN tDEB tDEB tGOFF tGOFF VIN - 0.5V VIN - 0.5V VGATE O.5V O.5V tGON tGON tFLAG tFLAG 3V VFLAG Figure 1. Timing Diagram 4 _______________________________________________________________________________________ Overvoltage Protectors with External pFET ADAPTER WITH BUILT-IN BATTERY CHARGER VUVLO < VIN < VOVLO INPUT VIN < VUVLO OUTPUT + 1 TIME STARTS COUNTING P IN GATE LITHIUM ION BATTERY 4 VIN > VOVLO SYSTEM LOADS - VI0 MAX4926 t = 20ms 2 GND FLAG 3 ON GATE = LOW FLAG = LOW Figure 2. State Machine Figure 3. MAX4926 Typical Operating Circuit Detailed Description The MAX4923–MAX4926 overvoltage protection controllers protect low-voltage systems against highvoltage faults of up to +28V when used with a -30V pFET. When the input voltage exceeds the OVLO threshold, these devices turn off the external pFET to prevent damage to protected components. The typical overvoltage trip level is set to 7.18V (MAX4923), 6.16V (MAX4924), 5.65V (MAX4925), and 4.46V (MAX4926). When the supply drops below the UVLO threshold, the devices turn off the external pFET. IN is ESD protected to +15kV (Human Body Model) when bypassed with a 1µF ceramic capacitor to ground. Undervoltage Lockout (UVLO) The MAX4923–MAX4926 have a fixed 2.44V (typ) UVLO level. When VIN is less than VUVLO, GATE is high and FLAG is high. Overvoltage Lockout (OVLO) The MAX4923 has a 7.18V (typ) OVLO; the MAX4924 has a 6.16V (typ) OVLO; the MAX4925 has a 5.65V (typ) OVLO; and the MAX4926 has a 4.46V (typ) OVLO. When VIN is greater than VOVLO, GATE is high and FLAG is high. FLAG Output The open-drain FLAG output is used to signal to the host system that there is a fault with the input voltage. FLAG goes high during an overvoltage or undervoltage fault. Connect a pullup resistor from FLAG to the logic I/O voltage of the host system. Device Operation The MAX4923–MAX4926 have an on-board state machine to control device operation. A flowchart is shown in Figure 2. At initial power up, if VIN < VUVLO or if VIN > VOVLO, both GATE and FLAG are high. When VUVLO < VIN < VOVLO, an internal timer starts counting and the device enters its on state after a 20ms delay. At any time if VIN drops below VUVLO or above VOVLO, both GATE and FLAG transition high. Application Information MAX4926 Application In a typical application for the MAX4926, an external adapter with built-in battery charger is connected to IN and a battery is connected to the drain of the external FET. When the adapter is unplugged, IN is directly connected to the battery through the external FET. Since the battery voltage is typically greater than VUVLO, the GATE voltage stays low and the device remains powered by the battery. MOSFET Selection The MAX4923–MAX4926 are designed for use with either a single pFET or dual pFETs in parallel. MOSFETs with RDS(ON) specified for a VGS of -4.5V are recommended. For input supplies near the UVLO maximum of 2.5V, use a MOSFET specified for a lower VGS voltage. Also, the VDS must be -30V and the VGS (max) must be higher than the VOVLO (max) for the MOSFET to withstand the full +28V input range of the MAX4923–MAX4926. _______________________________________________________________________________________ 5 MAX4923–MAX4926 STANDBY GATE = HIGH FLAG = HIGH MAX4923–MAX4926 Overvoltage Protectors with External pFET Table 1. MOSFETS Suggestions CONFIGURATON/ PACKAGE PART VDS MAX (V) RON MAX (mΩ) at VGS = -4.5V 245 each Si3993DV Dual/TSOP-6 -30 Si1433DH Single/SOT-363 -30 260 Si3983DV Dual/TSOP-6 -20 110 each Si1413DH Single/SOT-363 -20 115 Si5933DC Dual/1206-8 -20 110 each Si6991DQ Dual/TSSOP-8 -30 68 each RC 1MΩ CHARGE-CURRENT LIMIT RESISTOR RD 1.5kΩ MANUFACTURER Vishay Siliconix www.vishay.com IP 100% 90% DISCHARGE RESISTANCE Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES HIGHVOLTAGE DC SOURCE Cs 100pF STORAGE CAPACITOR DEVICE UNDER TEST 36.8% 10% 0 0 Figure 4. Human Body ESD Test Model IN Bypass Consideration For most applications, bypass IN to GND with a 1µF ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit and provide protection if necessary to prevent exceeding the 30V absolute maximum rating on IN. tRL TIME tDL CURRENT WAVEFORM Figure 5. Human Body Model Current Waveform Human Body Model Figure 4 shows the Human Body Model and Figure 5 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5kΩ resistor. ESD Test Conditions The MAX4923–MAX4926 are ESD protected to ±15kV (typ) Human Body Model on IN when IN is bypassed to ground with a 1µF ceramic capacitor as close as possible to IN. Chip Information PROCESS: BiCMOS 6 _______________________________________________________________________________________ Overvoltage Protectors with External pFET 3 2 5 e A 4 b 5 4 6 PIN 1 0.075x45∞ AA L E 1 PIN 1 MARK 6L UDFN.EPS TOPMARK A2 D A1 3 A 1 L2 BOTTOM VIEW SIDE VIEW TOP VIEW 2 A L1 COMMON DIMENSIONS b MIN. 0.65 -0.00 1.45 0.95 0.30 0.00 0.05 0.17 A A1 A2 D E L L1 L2 b e Pkg. Code SECTION A-A NOM. 0.72 0.20 -1.50 1.00 0.35 --0.20 0.50 BSC. MAX. 0.80 -0.05 1.55 1.05 0.40 0.08 0.10 0.23 L611-1, L611-2 TITLE: PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm APPROVAL DOCUMENT CONTROL NO. 21-0147 -DRAWING NOT TO SCALE- REV. E 1 2 Translation Table for Calendar Year Code TABLE 1 Calendar Year 2005 2006 Marked with bar Legend: 2007 2008 2009 2010 2011 2012 2013 42-47 48-51 52-05 2014 Blank space - no bar required Translation Table for Payweek Binary Coding TABLE 2 Payweek Legend: 06-11 12-17 Marked with bar 18-23 24-29 30-35 36-41 Blank space - no bar required TITLE: PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm APPROVAL -DRAWING NOT TO SCALE- DOCUMENT CONTROL NO. 21-0147 REV. E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX4923–MAX4926 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)