Application Note - Eon Silicon Solution Inc.

Eon Silicon Solution Inc.
Application Note
EON EN25Q128
vs
MXIC MX25L12845E
Specification Comparison
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
1. INTRODUCTION
The application note introduces how to implement a system design from MXIC
MX25L12845E Flash to Eon EN25Q128 Flash.
2. GENERAL FUNCTION COMPARISON TABLE:
2-1
The following table highlights the major features of these two devices.
Features
Voltage Range
EN25Q128
2.7 ~ 3.6
MX25L12845E
2.7 ~ 3.6
8-WSON (6x8mm)
8-pin VDFN (6x8mm)
Pin to Pin Compatible
16-pins SOP 300mil (except pin 4, 5,
(standard SPI mode) 16-pins SOP 300mil (except pin 4,
6 = PO2, PO1, PO0; pin 11, 12, 13,
5, 6, 11, 12, 13, 14 = NC)
14 = PO3, PO4, PO5, PO6)
104MHz (standard mode)
104MHz (standard mode)
SPI frequency
80MHz @ Dual & Quad mode
70MHz @ Dual & Quad mode
Secured Silicon Sector
512 Byte
512 Byte
Region
Uniform
Uniform
4096 sectors of 4K byte
4096 sectors of 4K byte
Sector Architecture
512 blocks of 32K byte
256 blocks of 64K byte
256 blocks of 64K byte
Mode 0 / Mode 3
Mode 0 / Mode 3
SPI mode
For Double Transfer
No
Yes
Rate serial read mode
EQIO mode
Yes
No
(Full Quad mode)
Yes
Yes
Page program
No
Yes
Continuous program
Block erase
Yes
Yes
64K byte
Block erase
No
Yes
32K Byte
Sector erase
Yes
Yes
4K byte
No
Yes
Parallel Mode
Conventional
Enhanced protect (*)
BP table
Advanced individual
No
Yes
block protect
No
Yes
DMC table
Minimum
100K
100K
Endurance Cycle
8-pin VDFN (5x6mm)
8-pins SOP 200mil
8-pin VDFN (6x8mm)
8-WSON (6x8mm)
Package
16-pins SOP 300mil
16-pins SOP 300mil
24-ball BGA (6x8mm)
(*) Please refer to page 5
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
3. HARDWARE CONSIDERATIONS
3-1
ICC comparison
Current (Max)
EN25Q128
MX25L12845E
Unit
45 @ 104MHz
40 @ 70MHz
25
mA
Page Program (PP) ICC4
25 @ 104MHz
20 @ 80MHz
28
Sector Erase (SE) ICC6
25
25
mA
Standby ICC1
20
100
μA
Read ICC3
3-2
mA
Pin configuration (16-pin package)
Pin number
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
Pin 15
Pin 16
EN25Q128
NC (DQ3)
VCC
NC
NC
NC
NC
CS#
DO (DQ1)
WP# (DQ2)
VSS
NC
NC
NC
NC
DI (DQ0)
CLK
MX25L12845E
NC / SIO3
VCC
NC
PO2
PO1
PO0
CS#
SO / SIO1 / PO7
WP# / SIO2
GND
PO3
PO4
PO5
PO6
SI / SIO0
SCLK
Note:
1. Eon EN25Q128 Flash can support the general standard / Dual / Quad SPI mode (Need specific SPI
controller), but don’t support the Parallel Mode (PO0~PO7).
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
4. SOFTWARE CONSIDERATIONS
4-1
Manufacturer, Memory Type & Device Identification comparison
(M7~M0: manufacture ID, D15~ID0: memory type, ID7~ID0: memory density)
EN25Q128:
OP Code
(M7-M0)
(ID15-ID0)
ABh
(ID7-ID0)
17h
90h
1Ch
9Fh
1Ch
17h
3018h
MX25L12845E:
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
4-2
Instruction Set Comparison
4-2.1
Different block protection area
EN25Q128:
Status Register Content
BP3
Bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
Bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Memory Content
Protect Areas
Addresses
None
Block 0 to 254
Block 0 to 253
Block 0 to 251
Block 0 to 247
Block 0 to 239
Block 0 to 223
All
None
Block 255 to 1
Block 255 to 2
Block 255 to 4
Block 255 to 8
Block 255 to 16
Block 255 to 32
All
None
000000h-FEFFFFh
000000h-FDFFFFh
000000h-FBFFFFh
000000h-F7FFFFh
000000h-EFFFFFh
000000h-DFFFFFh
000000h-FFFFFFh
None
FFFFFFh-010000h
FFFFFFh-020000h
FFFFFFh-040000h
FFFFFFh-080000h
FFFFFFh-100000h
FFFFFFh-200000h
FFFFFFh-000000h
Density(KB)
None
16320KB
16256KB
16128KB
15872KB
15360KB
14336KB
16384KB
None
16320KB
16256KB
16128KB
15872KB
15360KB
14336KB
16384KB
Portion
None
Lower 255/256
Lower 254/256
Lower 252/256
Lower 248/256
Lower 240/256
Lower 224/256
All
None
Upper 255/256
Upper 254/256
Upper 252/256
Upper 248/256
Upper 240/256
Upper 224/256
All
MX25L12845E:
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
4-2.2
Different RDSR bit definition
EN25Q128:
S7
SRP
OTP_LOCK
Status
Register
Protect
(note 1)
1 = status
register write
disable
1 = OTP
sector is
protected
bit
Non-volatile bit
S6
S5
S4
S3
S2
S1
WPDIS
BP3
BP2
BP1
BP0
WEL
(WP# disable)
1 = WP#
disable
0 = WP#
enable
S0
(Block
(Block
(Block
(Block
(Write Enable
Protected bits) Protected bits) Protected bits) Protected bits)
Latch)
(note 2)
(note 2)
(note 2)
(note 2)
Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit
WIP
(Write In
Progress bit)
(Note 3)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
volatile bit
volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
MX25L12845E:
Bit 7 is only used for SRWD (status register write protect).
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
4-2.3
Security Register definition
EN25Q128: None
MX25L12845E:
4-2.4
EQIO mode (Enable Quad I/O) (38h)
EN25Q128:
This command will enable device enter Full Quad mode.
MX25L12845E: Only support the page program under Quad mode.
4-2.5
Enter Secured OTP command
EN25Q128:
Support.
(3Ah)
MX25L12845E: Support.
(B1h)
4-2.6
Exit Secured OTP command
EN25Q128:
Support.
(04h)
MX25L12845E: Support.
(C1h)
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
7
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
4-2.7
Secured OTP Addresses
EN25Q128:
Sector
Sector Size
Address Range
4095
512 byte
FFF000h – FFF1FFh
MX25L12845E:
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
4-2.8
The other instructions comparison
Instructions
RSTQIO (Reset Quad I/O)
RSTEN (Reset Enable)
RST (Reset)
Dual Output
Fast Read
BE 32K (block erase 32KB)
CP (Continuously Program
mode)
REMS2
(Read ID for 2x I/O mode)
REMS4
(Read ID for 4x I/O mode)
REMS4D
(Read ID for 4 x I/O DT mode)
RDSCUR
(Read Security register)
WRSCUR
(Write Security register)
ESRY (Enable SO to output
RY/BY#)
DSRY (Disable SO to output
RY/BY#)
ENPLM
(Enter Parallel Mode)
EXPLM
(Exit Parallel Mode)
CLSR (Clear SR Fail Flags)
HPM (High Performance
Enable Mode)
WPSEL
(write protection selection)
SBLK
(single block lock)
SBULK
(single block unlock)
RDBLOCK
(block protect read)
GBLK
(gang block lock)
GBULK
(gang block unlock)
RDDMC
(Read DMC)
Command
FFh
66h
99h
EN25Q128
Yes
Yes
Yes
MX25L12845E
No
No
No
3Bh
Yes
No
52h
No
Yes
ADh
No
Yes
EFh
No
Yes
DFh
No
Yes
CFh
No
Yes
2Bh
No
Yes
2Fh
No
Yes
70h
No
Yes
80h
No
Yes
55h
No
Yes
45h
No
Yes
30h
No
Yes
A3h
No
Yes
68h
No
Yes
36h
No
Yes
39h
No
Yes
3Ch
No
Yes
7Eh
No
Yes
98h
No
Yes
5A
No
Yes
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
5. PERFORMANCE DIFFERENCES
5-1
Erase and program performance
EN25Q128
Parameter
MX25L12845E
Unit
Typ
Max
Typ
Max
Page Programming Time
0.8
5
1.4
5
ms
Sector Erase Time
50
300
60
300
ms
Block Erase Time (32KB)
N/A
N/A
0.5
2
sec
Block Erase Time (64KB)
0.2
2
0.7
2
sec
Chip (Bulk) Erase Time
45
90
80
200
sec
5-2
Key AC parameter PERFORMANCE
Parameter
EN25Q128
MX25L12845E
tCH (serial clock high time)
Min @ 4ns
Min @ 4.5ns
tCL (serial clock low time)
Min @ 4ns
Min @ 4.5ns
tCLCH(serial clock rise time)
Min @ 0.1V / ns
Min @ 0.1V / ns
tCHCL(serial clock fall time)
Min @ 0.1V / ns
Min @ 0.1V / ns
[email protected] 5ns
Min, read @15ns
Program/Erase @50ns
Min @ 5ns
Min, read @15ns
Program/Erase @50ns
tDSU(Data in setup time)
Min @ 2ns
Min @ 2ns
tDH(Data in hold time)
Min @ 5ns
Min @ 5ns
tCHSH(CS# active setup / hold time)
tSHSL(CS# high time)
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
10
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com
Eon Silicon Solution Inc.
Revisions List
Revision No Description
Date
A
2010/09/14
Initial Release
This Application Note may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2005 Eon Silicon Solution Inc.
Rev. A, Issue Date: 2010/ 09/14
www.eonssi.com