AN2232C-01 Command Processor for MPSSE and MCU Host

Future Technology Devices
International Ltd.
AN2232C-01 Command Processor
for MPSSE and MCU Host Bus
Emulation Modes
Copyright © 2006 Future Technology Devices International Ltd.
2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
1
Command Processor for MPSSE and MCU Host Bus
Emulation
1.1
Overview
The FT2232 incorporates a command processor called the Multi-Protocol Synchronous Serial
Engine (MPSSE). The purpose of the MPSSE command processor is to communicate with
devices which use synchronous protocols (such as JTAG or SPI) in an efficient manner. The
FT2232's MCU Host Bus Emulation mode also uses the MPSSE technology to make the chip
emulate a standard 8048/8051 MCU host bus.
The MPSSE Command Processor unit is controlled using a SETUP command. Various
commands are used to clock data out of and into the chip, as well as controlling the other I/O lines.
If disabled the MPSSE is held reset and will not have any effect on the rest of the chip. When
enabled, it will take its commands and data from the OUT data written to the OUT pipe in the chip.
This is done by simply using the normal WRITE command, as if data were being writen to a COM
port. Any data read will be passed back in the normal IN pipe. This is done using the normal
READ command, as if data were being read from a COM port.
Copyright © 2006 Future Technology Devices International Ltd.
Data and Clock Definition
2
Data and Clock Definition
2.1
Data Bit Defintion
Data bits are defined according to the following table:
Data Bit
Signal
FT2232 Pin
Type
Description
Bit0
TCK/SK
ADBUS0
Output
Clock Signal Output
Bit1
TDI/DO
ADBUS1
Output
Serial Data Out
Bit2
TDO/DI
ADBUS2
Input
Bit3
TMS/CS
ADBUS3
Output
Bit4
GPIOL0
ADBUS4
Input/Output
General Purpose I/O
Bit5
GPIOL1
ADBUS5
Input/Output
General Purpose I/O
Bit6
GPIOL2
ADBUS6
Input/Output
General Purpose I/O
Bit7
GPIOL3
ADBUS7
Input/Output
General Purpose I/O
Bit8
GPIOH0
ACBUS0
Input/Output
General Purpose I/O
Bit9
GPIOH1
ACBUS1
Input/Output
General Purpose I/O
Bit10
GPIOH2
ACBUS2
Input/Output
General Purpose I/O
Bit11
GPIOH3
ACBUS3
Input/Output
General Purpose I/O
Copyright © 2006 Future Technology Devices International Ltd.
Serial Data In
Select Signal Out
3
4
2.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Operation
The clock will do an XOR of the current state of the TCK/SK pin twice. This means that if the clock
pin is set low, then the clock will go high then low to be 1 clock cycle. If the clock pin were set high,
then the clock will go low then high to be 1 clock cycle.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3
Command Definitions
3.1
Bad Commands
5
If the device detects a bad command it will send back 2 bytes to the PC:
0xFA,
followed by the bad command byte.
If the data has got out of sequence then this can be used to determine what that the first pattern
was and that an error was detected. The error may have occurred before this (for example
sending the wrong amount of data after a write command) and will only trigger when bit 7 of the
rogue command is high.
Copyright © 2006 Future Technology Devices International Ltd.
6
3.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Data Shifting Command Overview
The data shifting commands are made up of the following definitions :
Data Bit
Definition
Bit 0
-ve TCK/SK on write
Bit 1
bit mode = 1 else byte mode
Bit 2
-ve TCK/SK on read
Bit 3
LSB first = 1 else MSB first
Bit 4
Do write TDI/DO
Bit 5
Do read TDO/DI
Bit 6
Do write TMS/CS
Bit 7
0
The write commands to TDI/DO take effect when bits 7 and 6 are '0'. Read TDO/DI will operate
with TMS/CS output or TDI/DO output or on its own.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.3
MSB First
3.3.1
Clock Data Bytes Out on +ve Clock Edge MSB First (no Read)
7
Use if TCK/SK starts at '1'.
0x10,
LengthL,
LengthH,
Byte1
..
Byte65536 (max)
This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte, and a length of 0xFFFF will do 65536 bytes. The data is sent MSB first. Bit 7
of the first byte is placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the
next bit on the rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
8
3.3.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bytes Out on -ve Clock Edge MSB First (no read)
Use if TCK/SK starts at '0'.
0x11,
LengthL,
LengthH,
Byte1
..
Byte65536 (max)
This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The data is sent MSB first. Bit 7
of the first byte is placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the
next bit on the falling edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.3.3
9
Clock Data Bits Out on +ve Clock Edge MSB First (no Read)
Use if TCK/SK starts at '1'.
0x12,
Length,
Byte1
This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data is sent MSB first. Bit 7 of the data byte is
placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the next bit on the
rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
10
3.3.4
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bits Out on -ve Clock Edge MSB First (no Read)
Use if TCK/SK starts at '0'.
0x13,
Length,
Byte1
This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data is sent MSB first. Bit 7 of the data byte is
placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the next bit on the
falling edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.3.5
11
Clock Data Bytes In on +ve Clock Edge MSB First (no Write)
0x20,
LengthL,
LengthH
This will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The first bit clocked in will be
the MSB of the first byte and so on. The data will be sampled on the rising edge of the TCK/SK
pin.
Copyright © 2006 Future Technology Devices International Ltd.
12
3.3.6
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bytes In on -ve Clock Edge MSB First (no Write)
0x24,
LengthL,
LengthH
This will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The first bit clocked in will be
the MSB of the first byte and so on. The data will be sampled on the falling edge of the TCK/SK
pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.3.7
13
Clock Data Bits In on +ve Clock Edge MSB First (no Write)
TDO/DI sampled just prior to rising edge
0x22,
Length
This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted up so that the first bit in may not
be in bit 7, but from 6 downwards depending on the number of bits to shift (i.e. a length of 1 bit will
have the data bit sampled in bit 0 of the byte sent back to the PC). The data will be sampled on the
rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
14
3.3.8
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bits In on -ve Clock Edge MSB First (no Write)
TDO/DI sampled just prior to falling edge
0x26,
Length
This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit, and a length of 0x07 will do 8 bits. The data will be shifted up so that the first bit in may
not be in bit 7, but from 6 downwards depending on the number of bits to shift (i.e. a length of 1 bit
will have the data bit sampled in bit 0 of the byte sent back to the PC). The data will be sampled on
the falling edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.3.9
Clock Data Bytes In and Out MSB First
Out on positive edge, in on positive edge
0x30,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
or
Out on negative edge, in on positive edge
0x31,
LengthL,
LengthH,
Byte1
..
Byte65536 (max)
or
Out on positive edge, in on negative edge
0x34,
LengthL,
LengthH,
Byte1
..
Byte65536 (max)
or
Out on negative edge, in on negative edge
0x35,
LengthL,
LengthH,
Byte1
..
Byte65536 (max)
Copyright © 2006 Future Technology Devices International Ltd.
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16
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
3.3.10 Clock Data Bits In and Out MSB First
Out on positive edge, in on positive edge
0x32,
Length,
Byte
or
Out on negative edge, in on positive edge
0x33,
Length,
Byte
or
Out on positive edge, in on negative edge
0x36,
Length,
Byte
or
Out on negative edge, in on negative edge
0x37,
Length,
Byte
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.4
LSB First
3.4.1
Clock Data Bytes Out on +ve Clock Edge LSB First (no Read)
17
Use if TCK/SK starts at '1'
0x18,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The data is sent LSB first. Bit 0
of the first byte is placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the
next bit on the rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
18
3.4.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bytes Out on -ve Clock Edge LSB First (no Read)
Use if TCK/SK starts at '0'.
0x19,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The data is sent LSB first. Bit 0
of the first byte is placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the
next bit on the falling edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.4.3
19
Clock Data Bits Out on +ve Clock Edge LSB First (no Read)
Use if TCK/SK starts at '1'.
0x1A,
Length,
Byte1
This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data is sent LSB first. Bit 0 of the data byte is
placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the next bit on the
rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
20
3.4.4
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bits Out on -ve Clock Edge LSB First (no Read)
Use if TCK/SK starts at '0'.
0x1B,
Length,
Byte1
This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data is sent LSB first. Bit 0 of the data byte is
placed on TDI/DO then the TCK/SK pin is clocked. The data will change to the next bit on the
falling edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.4.5
21
Clock Data Bytes In on +ve Clock Edge LSB First (no Write)
0x28,
LengthL,
LengthH
This will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The first bit clocked in will be
the LSB of the first byte and so on. The data will be sampled on the rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
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3.4.6
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bytes In on -ve Clock Edge LSB First (no Write)
0x2C,
LengthL,
LengthH
This will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of
0x0000 will do 1 byte and a length of 0xFFFF will do 65536 bytes. The first bit clocked in will be
the LSB of the first byte and so on. The data will be sampled on the falling edge of the TCK/SK
pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.4.7
23
Clock Data Bits In on +ve Clock Edge LSB First (no Write)
TDO/DI sampled just prior to rising edge
0x2A,
Length
This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted down so that the first bit in may
not be in bit 0, but from 1 upwards depending on the number of bits to shift (i.e. a length of 1 bit will
have the data bit sampled in bit 7 of the byte sent back to the PC). The data will be sampled on the
rising edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
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3.4.8
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data Bits In on -ve Clock Edge LSB First (no Write)
TDO/DI sampled just prior to falling edge
0x2E,
Length
This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will
do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted down so that the first bit in may
not be in bit 0, but from 1 upwards depending on the number of bits to shift (i.e. a length of 1 bit will
have the data bit sampled in bit 7 of the byte sent back to the PC). The data will be sampled on the
falling edge of the TCK/SK pin.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.4.9
Clock Data Bytes In and Out LSB First
Out on positive edge, in on positive edge
0x38,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
or
Out on negative edge, in on positive edge
0x39,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
or
Out on positive edge, in on negative edge
0x3C,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
or
Out on negative edge, in on negative edge
0x3D,
LengthL,
LengthH,
Byte1,
..
Byte65536 (max)
Copyright © 2006 Future Technology Devices International Ltd.
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26
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
3.4.10 Clock Data Bits In and Out LSB First
Out on positive edge, in on positive edge
0x3A,
Length,
Byte
or
Out on negative edge, in on positive edge
0x3B,
Length,
Byte
or
Out on positive edge, in on negative edge
0x3E,
Length,
Byte
or
Out on negative edge, in on negative edge
0x3F,
Length,
Byte
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.5
TMS Commands
3.5.1
Clock Data to TMS/CS Pin (no Read)
27
0x4A or 0x4B,
Length,
Byte1
This will send data bits 6 down to 0 to the TMS/CS pin using the LSB or MSB and -ve or +ve
TCK/SK, depending on which of the lower bits have been set.
0x4A
0x4B
: TMS/CS with LSB first on +ve TCK/SK edge - use if TCK/SK is set to '1'
: TMS/CS with LSB first on -ve TCK/SK edge - use if TCK/SK is set to '0'
Bit 7 of the Byte1 is passed on to TDI/DO before the first TCK/SK of TMS/CS and is held static for
the duration of TMS/CS clocking. No read operation will take place.
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28
3.5.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Clock Data to TMS/CS Pin with Read
0x6A or 0x6B or 0x6E or 0x6F
Length,
Byte1
This will send data bits 6 down to 0 to the TMS/CS pin using the LSB or MSB and -ve or +ve
TCK/SK, depending on which of the lower bits have been set.
0x6A
'1'
0x6B
'0'
0x6E
'1'
0x6F
: TMS/CS with LSB first on +ve TCK/SK edge, read on +ve edge - use if TCK/SK is set to
: TMS/CS with LSB first on -ve TCK/SK edge, read on +ve edge - use if TCK/SK is set to
: TMS/CS with LSB first on +ve TCK/SK edge, read on -ve edge - use if TCK/SK is set to
: TMS/CS with LSB first on -ve TCK/SK edge, read on -ve edge - use if TCK/SK is set to '0'
Bit 7 of the Byte1 is passed on to TDI/DO before the first TCK/SK of TMS/CS and is held static for
the duration of TMS/CS clocking. The TDO/DI pin is sampled for the duration of TMS/CS and a
byte containing the data is passed back at the end of TMS/CS clocking.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.6
Set / Read Data Bits High / Low Bytes
3.6.1
Set Data Bits Low Byte
29
0x80,
0xValue,
0xDirection
This will setup the direction of the first 8 lines and force a value on the bits that are set as output. A
'1' in the Direction byte will make that bit an output.
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3.6.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Set Data Bits High Byte
0x82,
0xValue,
0xDirection
This will setup the direction of the high 4 lines and force a value on the bits that are set as output.
A '1' in the Direction byte will make that bit an output.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.6.3
Read Data Bits Low Byte
0x81
This will read the current state of the first 8 pins and send back 1 byte.
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32
3.6.4
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Read Data Bits High Byte
0x83
This will read the current state of the high 4 pins and send back 1 byte.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.7
Loopback Commands
3.7.1
Connect TDI/DO to TDO/DI for Loopback
0x84
This will connect the TDI/DO output to the TDO/DI input for loopback testing.
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34
3.7.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Disconnect TDI/DO to TDO/DI for Loopback
0x85
This will disconnect the TDI/DO output from the TDO/DI input for loopback testing.
Copyright © 2006 Future Technology Devices International Ltd.
Command Definitions
3.8
Clock Divisor
3.8.1
Set TCK/SK Divisor
35
0x86,
0xValueL,
0xValueH
This will set the clock divisor.
The TCK/SK always has a duty cycle of 50%, except between commands where it will remain in its
initial state. The initial state is set using the 23. Set Data Bits Low Byte command. For example,
to use it in JTAG mode you would issue:$80
$08
$0B
Set Data Bits Low Byte
TCK/SK, TDI/DU low, TMS/CS high
TCK/SK, TDI/DU, TMS/CS output, TDO/D1 and GPIOL1 -> 14 input
The clock will then start low. When the MPSSE is sent a command to clock bits (or bytes) it will
make the clock go high and then back low again as 1 clock period. For TMS/CS commands, a
$4B command would be used for no read, and a $6B command for TMS/CS with read. For
clocking data out on TDI/DU with no read of TDO/D1, a $19 command would be used for bytes and
$1B for bits. To read from TDO/D1 with no data sent on TDI/DU a $28 command would be used
for bytes and $2A for bits. To scan in and out at the same time a $39 command would be used for
bytes and $3B for bits.
The TCK/SK frequency can be worked out using the following algorithm :
TCK/SK period = 12MHz / (( 1 +[(0xValueH * 256) OR 0xValueL] ) * 2)
For example:
Value
0x0000
0x0001
0x0002
0x0003
0x0004
............
0xFFFF
TCK/SK Max
6 MHz
3 MHz
2 MHz
1.5 MHz
1.2 MHz
..............
91.553 Hz
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AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
4
Instructions for MCU Host Bus Emulation Mode
4.1
Overview
MCU Host Bus Emulation mode makes the chip emulate a CPU with:
a) a multiplexed 8 bit address and data bus
b) an extended 8 bit address bus
c) CS# , ALE, WR# , RD# and OSC signals
d) 2 I/O lines that can be used as extra I/O or to wait for IRQs. These are defined as I/O0 and
I/O1.
Copyright © 2006 Future Technology Devices International Ltd.
Instructions for MCU Host Bus Emulation Mode
4.2
MCU Host Emulation Mode Read Short Address
0x90,
0xAddrLow
This will read 1 byte.
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38
4.3
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
MCU Host Emulation Mode Read Extended Address
0x91,
0xAddrHigh,
0xAddrLow
This will read 1 byte.
Copyright © 2006 Future Technology Devices International Ltd.
Instructions for MCU Host Bus Emulation Mode
4.4
MCU Host Emulation Mode Write Short Address
0x92,
0xAddrLow,
0xData
This will write 1 byte.
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40
4.5
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
MCU Host Emulation Mode Write Extended Address
0x93,
0xAddrHigh,
0xAddrLow,
0xData
This will write 1 byte.
Copyright © 2006 Future Technology Devices International Ltd.
Instructions for use in both MPSSE and MCU Host Emulation Modes
5
Instructions for use in both MPSSE and MCU Host
Emulation Modes
5.1
Send Immediate
0x87
This will make the chip flush its buffer back to the PC.
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42
5.2
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Wait On I/O High
0x88
This will cause the controller to wait until GPIOH1 (MPSSE) or I/O1 (MCU Host Bus Emulation) is
high. Once it is detected as high, it will move on to process the next instruction. The only way out
of this will be to disable the controller if the I/O line never goes high.
Copyright © 2006 Future Technology Devices International Ltd.
Instructions for use in both MPSSE and MCU Host Emulation Modes
5.3
43
Wait On I/O Low
0x89
This will cause the controller to wait until GPIOH1 (MPSSE) or I/O1 (MCU Host Emulation) is low.
Once the pin is detected as low, it will move on to process the next instruction. The only way out of
this will be to disable the controller if the I/O line never goes low.
Copyright © 2006 Future Technology Devices International Ltd.
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AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
6
History, Disclaimer, Contact Information
6.1
Document Revision History
Version
Release Date
Comments
1.0
March 2004
Initial release.
1.1
April 2004
2.0
December 2005
2.1
March 2006
Overview rewritten.
Signal names made consistent.
FT2232C pin and signal names added to data bit definition
table.
MSB and LSB command names updated.
Set TCK/SK Divisor expanded. Further examples added.
Command 2. Clock Data Bytes Out on -ve Clock Edge MSB
First (no Read) was missing
Minor corrections.
New format.
Data bit definition signals corrected.
2.2
October 2006
References to FT2232C changed to FT2232 after release of
FT2232D.
Copyright © 2006 Future Technology Devices International Ltd.
History, Disclaimer, Contact Information
6.2
45
Disclaimer
Copyright © 2006 Future Technology Devices International Ltd.
Neither the whole nor any part of the information contained in, or the product described in this
manual, may be adapted or reproduced in any material or electronic form without the prior written
consent of the copyright holder.
This product and its documentation are supplied on an as-is basis and no warranty as to their
suitability for any particular purpose is either made or implied.
Future Technology Devices International Ltd. will not accept any claim for damages howsoever
arising as a result of use or failure of this product. Your statutory rights are not affected.
This product or any variant of it is not intended for use in any medical appliance, device or system
in which the failure of the product might reasonably be expected to result in personal injury.
This document provides preliminary information that may be subject to change without notice.
Copyright © 2006 Future Technology Devices International Ltd.
46
6.3
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
Contact Information
Head Office - Glasgow, UK
Future Technology Devices International Limited
373 Scotland Street
Glasgow
G5 8QB
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-Mail (Sales): sales1@ftdichip.com
E-Mail (Support): support2@ftdichip.com
E-Mail (General Enquiries): admin1@ftdichip.com
Web Site URL: http://www.ftdichip.com
Web Shop URL: http://apple.clickandbuild.com/cnb/shop/ftdichip
Branch Office - Taiwan
Future Technology Devices International Limited (Taiwan)
4F, No 16-1, Sec. 6 Mincyuan East Road
Neihu District
Taipei 114
Taiwan
ROC
Tel: +886 2 8791 3570
Fax: +886 2 8791 3576
E-Mail (Sales): tw.sales1@ftdichip.com
E-Mail (Support): tw.support1@ftdichip.com
E-Mail (General Enquiries): tw.admin1@ftdichip.com
Web Site URL: http://www.ftdichip.com
Branch Office - Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)
5285 NE Elam Young Parkway
Suite B800
Hillsboro, OR 97124-6499
USA
Tel: +1 (503) 547-0988
Fax: +1 (503) 547-0987
E-Mail (Sales): us.sales@ftdichip.com
E-Mail (Support): support2@ftdichip.com
E-Mail (General Enquiries): admin1@ftdichip.com
Web Site URL: http://www.ftdichip.com
Agents and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our
distributor(s) in your country.
Copyright © 2006 Future Technology Devices International Ltd.
Index
Index
-00x10
0x11
0x12
0x13
0x18
0x19
0x1A
0x1B
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x4A
0x4B
0x6A
0x6B
0x6E
0x6F
0x80
7
8
9
10
17
18
19
20
11
13
12
14
21
23
22
24
15
15
16
16
15
15
16
16
25
25
26
26
25
25
26
26
27
27
28
28
28
28
29
Copyright © 2006 Future Technology Devices International Ltd.
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x90
0x91
0x92
0x93
0xFA
31
30
32
33
34
35
41
42
43
37
38
39
40
5
-AALE
36
-BBad Commands
bit mode 6
5
-CCLK 3, 4, 6
CLK Divisor 35
Clock 4
Clock Divisor 35
Command Processor
Contact 46
CS# 36
2
-DD0 3
Data Bits 3
Data Shifting commands 6
DI 3
Disclaimer 45
Document Revision History 44
Duty Cycle 35
47
AN2232C-01 Command Processor for MPSSE and MCU Host Bus Emulation Modes
48
-EE-mail
-S46
-FFT2232
2
-GGPIO11
GPIO12
GPIO13
GPIO14
GPIO21
GPIO22
GPIO23
GPIO24
3
3
3
3
3
3
3
3
-IIRQ
Send Immediate 41
SETUP Command 2
SPI Bus 2
-TTCLK 35
TDI 6, 27, 33, 34
TDO 6, 28, 33, 34
TMS 3, 6, 27, 28
-WWR#
36
-XXOR
4
36
-JJTAG
2
-LLSB
6, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28
-MMCU Host Bus Emulation 2, 36, 41, 42, 43
MPSSE 2, 41, 42, 43
MSB 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 28
Multi-Protocol Synchronous Serial Engine 2
-OOSC
36
-RRD#
36
Copyright © 2006 Future Technology Devices International Ltd.