Future Technology Devices
International Ltd
UMFT4222EV USB2.0 to QuadSPI/I2C
Bridge Development Module
Datasheet
Document Reference No.: FT_001057
Version 1.0
Issue Date: 2014-09-26
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
1
Clearance No.: FTDI#407
Introduction
The UMFT4222EV is a development module which uses FTDI’s FT4222H, a Hi-Speed USB2.0 to QuadSPI/I2C
bridge in compact 32-pin QFN package. FT4222H requires an external Crystal (12MHz) for the internal PLL to
operate. It supports multi-voltage IO, 3.3V, 2.5V or 1.8V. It also provides 128 Bytes one-time-programmable
(OTP) memory space for storing vendor specific information. The FT4222H contains SPI/I2C configurable
interfaces. The SPI interface can be configured as master mode with single, dual, or quad bits data width transfer
or slave mode with single bit data width transfer. The I2C interface can be configured as master or slave mode.
The UMFT4222EV is supplied as a small PCB which is designed to plug into a standard 0.8” wide 24 pin DIP
socket. All components are Pb-free (RoHS compliant).
Figure 1.1 – UMFT4222EV USB2.0 to QuadSPI/I2C Bridge Development Module
1.1
USB Compliant
The UMFT4222EV is fully compliant with the USB 2.0 specification
© Copyright 2014 Future Technology Devices International Ltd
2
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
Table of Contents
1
Introduction .................................................................... 2
1.1
2
USB Compliant .......................................................................... 2
Features .......................................................................... 5
2.1
Typical Applications .................................................................. 6
2.2
Driver Support .......................................................................... 6
3
FT4222H Features and Enhancement .............................. 7
4
UMFT4222EV Pin Out and Signal Descriptions ................. 9
5
4.1
UMFT4222EV Pin Out ................................................................ 9
4.2
Signal Descriptions ................................................................. 10
4.3
Jumper Configuration Options ................................................ 13
UMFT4222EV Mode Configuration ................................. 14
5.1
Mode Configuration ................................................................. 14
5.2
SPI Pin Definition .................................................................... 16
5.3
I2C Pin Definition .................................................................... 17
5.4
GPIO Pin Definition ................................................................. 17
5.5
Other Pin Definitions ............................................................... 18
6
Module Dimensions ....................................................... 19
7
Power Configurations .................................................... 20
7.1
BUS Powered Configuration .................................................... 20
7.2
Self Powered Configuration .................................................... 21
7.3
Using internal regulator of FT4222H ....................................... 22
7.4
Using external power source for FT4222H IO Supply Voltage . 23
8
UMFT4222EV Module Circuit Schematic......................... 24
9
Internal OTP Memory Configuration .............................. 25
9.1
Method of Programming the OTP Memory ............................... 25
10 Contact Information ...................................................... 26
© Copyright 2014 Future Technology Devices International Ltd
3
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
Appendix A – List of Tables and Figures .......................................... 27
Appendix B – Revision History ......................................................... 28
© Copyright 2014 Future Technology Devices International Ltd
4
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
2
Clearance No.: FTDI#407
Features
The UMFT4222EV has the following features:
Single Hi-Speed USB 2.0 chip (FT4222H) to
2
flexible and configurable SPI/I C interfaces.
SPI interface support for Single / Dual / Quad
self-powered.
mode, USB power configuration and VCCIO
operating speed.
source selection
Up to 28Mbps data transfer rate in SPI mode
Integrated power-on-reset circuit.
with quad data mode.
True 3.3V CMOS drive output and TTL input.
Support up to 4 slave selection control pins
(operates down to 1.8V with external 1.8V
in SPI master mode.
power input to VCCIO)
Support Single SPI Slave Mode with SCK
Support wide supply voltage range.
operating frequency up to 20MHz.
USB2.0 Low operating and suspend current;
2
I C interface support 7-bits address and fully
68mA (active-typ.) and 375uA
compatible to v2.1 and v3 specification for
(suspend-typ.).
I C Master/Slave Mode with configurable
target operating speed for 100kbit/S
Configurable I/O pin output drive strength: 4
mA(min) and 16 mA(max)
standard mode, 400kbit/S fast mode 1Mbit/S
Fast mode plus and 3.4Mbit/S high speed
mode.
On board jumper for FT4222H configuration
SPI Master Mode with configurable target
2
USB Power Configurations; bus-powered and
UHCI / OHCI / EHCI / XHCI host controller
compatible
FTDI’s royalty-free Direct (D2XX) drivers
Configurable GPIOs controlled by application
eliminate the requirement for USB driver
software via USB bus
development in most cases
Fully support USB2.0 suspend/resume and
Supplied PCB designed to fit a standard
remote wakeup
20.2mm (0.8”) wide 24 pin DIP socket. Pins
Support Battery Charger Detection
are on a 2.54mm (0.1”) pitch.
OTP memory inside for USB Vendor ID
(VID),
Product
ID
(PID),
device
serial
On board USB Micro-B receptacle allows
module to be connected to a PC.
number, product description string and
various other vendor specific data.
© Copyright 2014 Future Technology Devices International Ltd
5
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
2.1 Typical Applications
USB to single mode SPI master controller
USB to dual mode SPI master controller
USB to quad mode SPI master controller
USB to single SPI slave controller
USB to I2C master interface controller
USB to I2C slave interface controller
Utilising USB to add system modularity
Incorporate USB interface to enable PC
transfers for development system
communication
USB Industrial Control
USB Data Acquisition
USB dongle implementations for Software/
Hardware Encryption and Wireless Modules
Detect USB dedicated charging ports, to
allow for high current battery charging in
portable devices.
2.2 Driver Support
Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface)
Windows8.1
32,64-bit
Windows 8
32,64-bit
Windows 7
32,64-bit
Win XP, Server 2003 and Server 2008
The drivers listed above are all available to download for free from FTDI website
(www.ftdichip.com).
For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm
© Copyright 2014 Future Technology Devices International Ltd
6
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
3
Clearance No.: FTDI#407
FT4222H Features and Enhancement
Functional Integration: The FT4222H is a USB 2.0 Hi-Speed (480Mbits/s) to flexible and
configurable SPI/I2C interfaces device. The FT4222H includes an integrated +1.8V and +3.3V Low
Drop-Out (LDO) regulator and a 12MHz to 480MHz PLL. It also includes Power-On-Reset (POR),
VBUS detection with 5V-tolerance and 128 bytes one-time-programmable (OTP) memory which
simplifies external circuit design and reduces external component count.
USB2.0 Hi-Speed Device Controller: The FT4222H integrates a USB protocol engine which
controls the physical Universal Transceiver Macro cell Interface (UTMI) and handles all aspects of
the USB 2.0 Hi-Speed interface. The device contains one control endpoint and 4 IN and OUT
endpoint pairs. These endpoints can be configured to implement up to 4 independent
interfaces/applications mapped to I2C+GPIO or SPI+GPIO.
Highly Integrated USB2.0 to Configurable SPI Bridge: The FT4222H provides the bridge
function between a USB2.0 and SPI Master/Slave.
The support library, LibFT4222, based on FTDI’s D2XX driver, enables easy configuration of the SPI
as a master or slave. Operating clock frequency on the SPI bus, clock phase and polarity, transfer
data bit width mode, and the number of slave selection controls are also configurable.
The max SPI interface operating clock can be set up to 30MHz in master mode and 20MHz in slave
mode. With quad mode (4-bits) data bus width, the max data transfer throughput can be up to
28Mbps.
USB to Configurable I2C Controller: The FT4222H also provides the bridge function between a
USB2.0 and an I2C Master/Slave.
The support library, LibFT4222, based on FTDI’s D2XX driver, enables easy configuration of the I2C
as either a master or slave, including target operating speed and bus protocol on I2C bus.
The device can run at common I2C bus speeds, 100kbit/s standard mode (SM), 400 Kbit/s fast
mode (FM), 1 Mbit/s Fast mode plus (FM+), and 3.4 Mbit/s High Speed mode (HS). Clock stretching
is also supported to conform to v2.1 and v3.0 of the I2C specification.
Configurable GPIOs: The GPIOs in the FT4222H can be fully controlled by an application utility
over USB. There are 4 GPIO pins that can be configured for different purposes, such as a suspend
indicator output, and remote wake up input.
The signal drive strength and slew rate can be configured via USB vendor commands for different
design needs.
© Copyright 2014 Future Technology Devices International Ltd
7
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
Embedded OTP memory: The internal OTP memory in the FT4222H is used to store USB Vendor
ID (VID), Product ID (PID), device serial number, product description string and various other USB
configuration descriptors. With this embedded OTP memory, the device can store vendor specific
information and save BOM cost. The descriptors can be programmed using the FTDI utility software
called FT_PROG, which can be downloaded from FTDI Utilities on the FTDI website
(www.ftdichip.com).
Power management: Fully supports USB2.0 suspend/resume and remote wakeup. The PHY will
be put to a power saving mode and the clock to most of the digital circuits will be stopped when the
device is suspended.
Source Power and Power Consumption: The FT4222H is capable of operating at a voltage
supply +3.3V or +5.0V with a nominal operational mode current of 68mA and a nominal USB
suspend mode current of 375µA. This allows greater margin for peripheral designs to meet the USB
suspend mode current limit of 2.5mA. An integrated level converter within the FT4222H allows the
interface logic to run at +1.8V, 2.5V or +3.3V. (Note: External pull-ups are recommended for IO
<3V3).
© Copyright 2014 Future Technology Devices International Ltd
8
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
4
4.1
Clearance No.: FTDI#407
UMFT4222EV Pin Out and Signal Descriptions
UMFT4222EV Pin Out
Figure 4.1 Module Pin Out and Jumper Locations
© Copyright 2014 Future Technology Devices International Ltd
9
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
4.2 Signal Descriptions
Pin No.
Name
Type
Description
5V Power output from USB Connector. For a low power USB bus powered design, up to
JP4. 1
VBUS
Output
100mA can be sourced from the 5V supply on the USB bus. A maximum of 500mA can
be sourced from the USB bus in a high power USB bus powered design.
To power the module from the 5V supply on the USB bus, need to connect jumper JP9
pin 1 and pin 2 together (this is the module default configuration). In this case this pin
would have the same description as JP4 pin 1.
JP4. 2
VCCIN
PWR
To use the UMFT4222EV module in a self-powered configuration ensure that jumper J9
pins 1 and 2 are not connected together, and apply an external 3.3V or 4.0V to 5.25V
supply to this pin ( 3.3V input for self-power low power configuration ).
This Pin is also connected to JP1 Pin 1.
JP4. 3
GND
PWR
Module Ground Supply Pins
JP4. 4
GPIO0
I/O
JP4. 5
GPIO1
I/O
JP4. 6
GPIO2
I/O
JP4. 7
GPIO3
I/O
GPIO3(default) can be configured as USB remote wakeup input pin or interrupt input
JP4. 8
GND
PWR
Module Ground Supply Pins
JP4. 9
SS0O
Output
Slave selection 0, output pin for SPI master mode.
JP4. 10
BCD_DET
Output
JP4. 11
SS
Input
JP4. 12
GND
PWR
GPIO0(default) can be configured as slave selection 1, output pin for SPI master mode
or serial clock for I2C mode
GPIO1(default) can be configured as slave selection 2, output pin for SPI master mode
or serial data for I2C mode
GPIO2(default) can be configured as slave selection 3, output pin for SPI master mode
or USB suspend output indicator
Battery charger detection asserted when the device is connected to a dedicated
charging port. Polarity can be defined
SPI slave selection indicator from SPI master. This pin is active in SPI slave mode. It
must be tied to high when SPI master mode enabled.
Module Ground Supply Pins
© Copyright 2014 Future Technology Devices International Ltd
10
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Pin No.
Name
Type
Clearance No.: FTDI#407
Description
+3.3V/2.5V/1.8V supply voltage for all the FT4222H I/O pins.
JP5. 1
VCCIO
PWR
Input
For 3.3V application, this pin can use FT4222H VOUT3V3 power supply by connecting
JP8 pins 1 and 2.
This pin can also be supplied with an external 1.8V or 2.5V supply in order to drive out
at lower levels.
3.3V output from integrated LDO regulator. This pin is decoupled from ground on the
JP5. 2
VOUT3V3
PWR
module. The prime purpose of this pin is to provide the internal 3.3V supply to USB
Output
transceiver cell. Up to 100mA can be drawn from this pin to power FT4222H and
or
external logic if required. This pin can also be used to supply the FT4222H VCCIO pin
Input
by connecting JP8 pins 1 and 2.
If VCCIN is supplied with 3.3V, this pin must also be driven with 3.3V power source.
JP5. 3
GND
PWR
Module Ground Supply Pins
JP5. 4
IO3
I/O
Quad SPI data bus bit 3
JP5. 5
IO2
I/O
Quad SPI data bus bit 2
JP5. 6
GND
PWR
Module Ground Supply Pins
In SPI master single mode, it is master serial data output.
JP5. 7
MOSI
I/O
In SPI master dual/quad mode, it is SPI data bus bit 1.
In SPI slave mode, it is slave serial data input.
In SPI master single mode, it is master serial data input.
JP5. 8
MISO
I/O
In SPI master dual/quad mode, it is SPI data bus bit 1.
In SPI slave mode, it is slave serial data output.
SPI interface clock. In SPI master mode, it is Serial clock output. In SPI Slave mode,
JP5. 9
SCK
I/O
JP5. 10
GND
PWR
Module Ground Supply Pins
JP5. 11
Reset#
Input
Reset input for normal operation, active low.
JP5. 12
GND
PWR
Module Ground Supply Pins
it is Serial clock input.
Table 4.1 Module Pin out Description
© Copyright 2014 Future Technology Devices International Ltd
11
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Type
Clearance No.: FTDI#407
Pin No.
Name
JP1. 1
-
JP1. 2
TEST_M
Input
Test Pin, leave floating.
JP1. 3
GND
PWR
Module Ground Supply Pins
VPP
PWR
It is a power source for Programming FT4222H embedded OTP with 6.5V voltage.
JP1. 4
Input
Leave floating or 0V when not in programming mode.
-
Description
Not connected.
Table 4.2 Module JP1 Pin out Description
© Copyright 2014 Future Technology Devices International Ltd
12
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
4.3 Jumper Configuration Options
Pin No.
Name
Type
Description
1
VCCIO
PWR
Set DCNF0 mode configuration bit High.
2
DCNF0
Input
USB endpoint configuration selection bit 0. Refer to FT4222H datasheet.
3
GND
PWR
Set DCNF0 mode configuration bit Low.
Table 4.3 Jumper JP2 Pin Description
Pin No.
Name
Type
Description
1
VCCIO
PWR
Set DCNF1 mode configuration bit High.
2
DCNF1
Input
USB endpoint configuration selection bit 1. Refer to FT4222H datasheet.
3
GND
PWR
Set DCNF1 mode configuration bit Low.
Table 4.4 Jumper JP3 Pin Description
Pin No.
Name
1
VCCIO
2
VOUT3V3
Type
Description
PWR
Connect to jumper JP8 pin 2 in order to supply the board from the USB FT4222H.
Input
Otherwise, VCCIO should have external power supply on JP5 pin 1.
PWR
FT4222H 3.3V regulator output. Connect to jumper JP8 pin 1 in order to supply the IO
Output
voltage with 3.3V tolerance.
Table 4.5 Jumper JP8 Pin Description
Pin No.
Name
Type
Description
1
VBUS
PWR
Connect to jumper JP9 pin 2 in order to supply power for FT4222H from the USB port.
PWR
2
VCCIN
Input
FT4222H 5V power input, connect to jumper JP9 pin 1 to supply power from the USB
port.
Otherwise, VCCIN should have external 3.3V/5V power supply on JP4 pin 2.
Table 4.6 Jumper JP9 Pin Description
© Copyright 2014 Future Technology Devices International Ltd
13
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
5
Clearance No.: FTDI#407
UMFT4222EV Mode Configuration
5.1 Mode Configuration
The FT4222H has 4 configuration modes selected by {DCNF1, DCNF0}. The chip configuration
mode will determine the number of USB interfaces for data streams and for GPIOs control. The data
stream interface is for data transfer between the USB2.0 host and the SPI/ I2C device. The purpose
of the GPIO interface is for fully controlling the GPIOs.
With UMFT4222EV module, user can easily configure chip mode through jumpers (JP2 and JP3).
Please refer to Table 4.3 and 4.4 for detail. A chip reset or power cycling is required after
configuration changing. The following table shows the pin functions corresponding to chip
configuration mode.
Table 5.1 FT4222H Pin Functions on Chip Configuration Mode
*One of the SPIM, SPIS, I2C function is selected, the other 2 functions will be disable
Note that GPIO pins can’t be controlled by driver when GPIO pins play the role as SPIM SSxO, I2C
SCL/SDA, SUSP or WAKE.
Chip Configuration only determines the number of interface/function supported but do not decide
which bus interface (SPI/ I2C /GPIO) or which role (master/slave) that the FT4222H will take.
© Copyright 2014 Future Technology Devices International Ltd
14
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
Figure 5.1 JP2/JP3 configuration example: Mode 3 (DCNF0 = 1, DCNF1 = 1)
Figure 5.2 JP2/JP3 configuration example: Mode 0 (DCNF0 = 0, DCNF1 = 0)
© Copyright 2014 Future Technology Devices International Ltd
15
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
5.2 SPI Pin Definition
The QuadSPI function in FT4222H is a fully configurable SPI master/slave device. Users can call the
LibFT4222 APIs, FT4222_SPIMaster_Init or FT4222_SPISlave_init, to select which function (master
or slave) the FT4222H will be. When FT4222H is set as USB-to-SPI bridge function, and chip
configuration is set as 1 or 3 or 4 data streams, the pins of UMFT4222EV will be mapped accordingly.
The SPI related pins are
Clock – SCK
JP5 pin 9.
Clock output in SPI master mode.
It will become clock input in SPI slave mode.
Data
– MISO
JP5 pin 8.
Data transfer from slave to master for single mode.
It can also become data bus bit-1 for dual and quad mode.
– MOSI
JP5 pin 7.
Data transfer from master to slave for single mode.
It can also become data bus bit-0 for dual and quad mode.
– IO2
JP5 pin 5.
Data bus bit-2 for quad mode
– IO3
JP5 pin 4.
Data bus bit-3 for quad mode
Slave Selection when QuadSPI acts as SPI master
– SS0O JP4 pin 9.
Slave selection to slave device-0.
– SS1O JP4 pin 4.
Slave selection to slave device-1.
– SS2O JP4 pin 5.
Slave selection to slave device-2.
– SS3O JP4 pin 6.
Slave selection to slave device-3.
Slave Selection when QuadSPI acts as SPI slave
– SS
JP4 pin 11.
Slave selection for SPI master control.
This pin must tie to high when QuadSPI acts as SPI master.
© Copyright 2014 Future Technology Devices International Ltd
16
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
5.3 I2C Pin Definition
The I2C function in the FT4222H is a fully configurable I2C master/slave device. When the chip
configuration is set as CNFMODE0 or CNFMODE3 and USB-to-I2C bridge function is enabled, the I2C
related pins of the FT4222H are:
Clock – SCL
JP4 pin 4.
It is a clock output with open-drain design when the I2C
is set as master.
It is a clock input when the I2C is set as a slave.
Data
– SDA
JP4 pin 5.
It is command/address/data transfer between master and
slave with open-drain design.
5.4 GPIO Pin Definition
The FT4222H contains 4 GPIO pins for various functions. The driving strength, slew rate control and
pull high/low resistors can be controlled.
GPIO0
JP4 pin 4.
This pin can be configured as GPIO0 or I2C SCL in I2C mode
or SPI master mode slave selection SS1O.
GPIO1
JP4 pin 5.
This pin can be configured as GPIO1 or I2C SDA in I2C mode
or SPI master mode slave selection SS2O.
GPIO2
JP4 pin 6.
This pin can be configured as GPIO2 or USB suspend status
output(SUSP) or SPI master mode slave selection SS3O.
GPIO3
JP4 pin 7.
This pin can be configured as GPIO3 or USB remote wake-up
input(WAKE).
© Copyright 2014 Future Technology Devices International Ltd
17
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
5.5 Other Pin Definitions
UMFT4222EV contains BCD_DET and RESET# signals for user use.
BCD_DET
JP4 pin 10.
Battery charger detection asserted when the device is
connected to a dedicated charging port. The polarity of this
pin can be defined.
RESET#
JP5 pin 11.
This pin used to reset the FT4222H, it is active low.
© Copyright 2014 Future Technology Devices International Ltd
18
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
6
Clearance No.: FTDI#407
Module Dimensions
Figure 6.1 UMFT4222EV Module Dimensions
All dimensions are in millimetres. Tolerance is +/-0.2mm.
© Copyright 2014 Future Technology Devices International Ltd
19
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
7
Clearance No.: FTDI#407
Power Configurations
7.1 BUS Powered Configuration
Figure 7.1 Bus Powered Configuration: Short JP9
Figure 7.1 illustrates the UMFT4222EV module in a typical USB bus powered design configuration. This is done
by fitting the jumpers on JP8 and JP9, as shown above. The UMFT4222EV is supplied in this configuration by
default.
A USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus Power devices are as
follows:
i) On plug-in to USB, the device must draw no more than 100mA.
ii) On USB suspend the device must draw no more than 2500μA.
iii) A device that consumes more than 100mA cannot be plugged into a USB Bus Powered Hub.
iv)
No device can draw more that 500mA from the USB Bus.
Interfacing the UMFT4222EV module to a SPI Flash, microcontroller (MCU), or other logic for a bus powered
design would be done in exactly the same way as for a self-powered design, except that the MCU or external
logic would take its power supply from the USB bus (either the 5V on the USB pin, or 3.3V on the VCCIO pin).
© Copyright 2014 Future Technology Devices International Ltd
20
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
7.2 Self Powered Configuration
Figure 7.2 Self-Powered Configuration: Remove Jumper on JP9
Figure 7.2 illustrates the UMFT4222EV in a typical USB self-powered configuration. In this case the jumper on
JP9 is removed, and an external supply is connected to the module JP4 pin 2 (VCCIN).
A USB Self Powered device gets its power from its own power supply and does not draw current from the USB
bus. The basic rules for USB Self powered devices are as follows:
i) A Self Powered device should not force current down the USB bus when the USB Host or Hub Controller
bus powered down.
ii) A Self Powered Device can use as much current as it likes during normal operation and USB suspend as
it has its own power supply.
iii) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hub. In this
case the power descriptor in the internal EEPROM should be programmed to a value of zero
(self-powered).
In order to meet above rule (i), the USB Bus Power is connected to the VBUS_DET Pin which is a 5V tolerance
input pin even when FT4222H works at low power mode and VCCIN is supply with 3.3V. When USB Bus Power
is down, VBUS_DET will be 0V and FT4222H will enter suspend mode.
© Copyright 2014 Future Technology Devices International Ltd
21
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
7.3 Using internal regulator of FT4222H
Figure 7.3 Use FT4222H internal regulator: Short JP8
Figure 7.3 shows a configuration for USB bus powered and using internal regulator of FT4222H
The Jumper JP8 allows the FT4222H to use the internal regulator in FT4222H.
The FT4222H VCCIO pin is supplied from FT4222H internal 3.3V regulator output pin(VOUT3V3) when it
connects JP8 pins 1 and 2 with jumper.
FT4222H can provide VOUT3V3 up to 100mA which includes the power consumption of the FT4222H. It can
also be used to supply external logic, but the total power consumption of FT4222H and external logic should
not exceed 100mA.
© Copyright 2014 Future Technology Devices International Ltd
22
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
7.4 Using external power source for FT4222H IO Supply Voltage
Figure 7.4 Use external power source for FT4222H IO Supply Voltage: Remove Jumper on JP8
Figure 7.4 shows a configuration for using an external power source for the FT4222H IO supply voltage.
When removing the jumper JP8 on UMFT4222EV module, the FT4222H can use an external power source to
FT4222H VCCIO pin through JP5 pin 1.
FT4222H VCCIO pin can accept 3.3V/2.5V/1.8V supply voltage for all the FT4222H I/O pins include SPI
interface. User can implement an external regulator to generate 3.3V from the USB Bus Power.
User can use a discrete low dropout regulator supplied by the USB Bus power to generate 3.3V or 1.8V output
for UMFT4222EV JP5 Pin 1(VCCIO) and the external logic. UMFT4222EV also provide JP4 Pin 1(VBUS) to supply
5V source for external regulator. With the external regulator connected, UMFT4222EV I/O pins will drive out
3.3V or 1.8V logic levels.
The quiescent current of the regulator must be low in order to meet the USB suspend total current requirement
of <= 2500 μA during USB suspend.
© Copyright 2014 Future Technology Devices International Ltd
23
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
UMFT4222EV Module Circuit Schematic
8
CN1
VBUS
VBUS
DD+
ID
GND
CN MICRO
VCCIN
GPIO0
GPIO1
GPIO2
GPIO3
SS0O
BCD_DET
SS
10nF
C5
VBUS
FB1
600R/1A
1
2
3
4
5
GND
JP4
1
2
3
4
5
6
7
8
9
10
11
12
C2 C1
4.7uF 0.1uF
GND
R2
R3
0R
0R
VCCIO
USB_D_N
USB_D_P
HEADER 12
1
2
3
4
5
6
7
8
9
10
11
12
JP5
USB Connector
VOUT3V3
IO3
IO2
MOSI
MISO
SCK
RESET#
Green
10K
VCCIO
GPIO2
GND
HEADER 12
LED1
GND
360R
IO Connecting for FT4222
R26
FT4222HQ Indicated LED
R25
12 Pin 2.54mm Male Header
VOUT3V3
TEST_M
Test Pin Pull High Res.
VCCIO
R5
47k
GND
R4
10K
C6
0.47uF
GND
VBUS
R11
C4
R1
0R
FT4222 QFN-32
0.1uF
C9
VCCIN
C12
4.7uF
GND
NC/100pF
RREF
XSCO
XSCI
VBUS_DET
BCD_DET
RESET
STEST_RESETN
DEBUGGER
DCNF1
DCNF0
DM
DP
RREF
VCCIO VOUT3V3
21
5
4
22
23
DCNF1
DCNF0
3
2
1
12K 1%
USB_D_N
USB_D_P
RESET#
STEST
TEST_M
XSCI
19
18
VBUS_DET 30
BCD_DET 31
XSCO
R10
1M
R12
0R Y1
GND
C14
4.7uF
0.1uF
C11
VOUT3V3
GND
C7 12MHz C8
27pF
27pF
GND
0.1uF
C10
VCCIO
C13
4.7uF
GND
FT4222 Bypass Cap.
R13
R14
R15
R16
R17
32
8
9
10
11
12
SS0O
GPIO0
GPIO1
GPIO2
GPIO3
U1
FT4222HQ
SS
FT_SCK
FT_MISO
FT_MOSI
FT_IO2
FT_IO3
33
0R
0R
0R
0R
0R
NC/1K
NC/1K
VCCIO
10K
NC/10K
NC/10K
NC/10K
NC/10K
NC/10K
VCCIO
FT_SCK
FT_MISO
FT_MOSI
FT_IO2
FT_IO3
17
13
14
15
16
VPP
R27
R20
R21
R22
R23
R24
Gnd
SS0O
GPIO0
GPIO1
GPIO2
GPIO3
SS
SCK
MISO
MOSI
IO2
IO3
VCCIN
GND
SCK
MISO
MOSI
IO2
IO3
SS
SCK
MISO
MOSI
IO2
IO3
R18
R19
SPI Pull High Res.
GPIO0
GPIO1
I2C Pull High Res.
VPP
VCCIN
GND
TEST_M
C3
NC/4.7uF
R7
10K
R6
10K
GND
JP1
1
2
3
4
HEADER 4
JP3
1 Jumper 2.0mm
2
3
VCCIO
GND
JP2
1 Jumper 2.0mm
2
3
VCCIO
Program Board Connector
DCNF0
DCNF1
Default : 00
VCCIO
VCCIN
JP9
1
Jumper 2.0mm
2
JP8
1
Jumper 2.0mm
2
FT4222 Mode Select
VOUT3V3
VBUS
Power connector
XL1
SHUNT-2.0mm
XL2
SHUNT-2.0mm
XL5
SHUNT-2.0mm
XL6
SHUNT-2.0mm
24
© Copyright 2014 Future Technology Devices International Ltd
7
25
26
29
VCCIO
VOUT3V3
VCCIN
VPP
DGND
UGND
UGND
AGND
DGND
6
20
24
27
28
Clearance No.: FTDI#407
Document Reference No.: FT_001057
Version 1.0
Figure 8.1 Module Circuit Schematic
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
9
Clearance No.: FTDI#407
Internal OTP Memory Configuration
The FT4222H includes an internal OTP memory which holds the USB configuration descriptors,
other configuration data for the chip and also user data areas. Following a power-on reset or a USB
reset the FT4222H will scan its internal OTP memory and read the USB configuration descriptors
stored there.
In many cases, the default values in OTP memory are suitable and no necessary to do
re-programming. The defaults can be found in FT4222H datasheet.
The OTP memory in the FT4222H can be programmed over USB if the values need to be changed for
a particular application. Further details of this are provided from Section 9.1 onwards.
Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in
their design can apply to FTDI for a free block of unique PIDs. See TN_100 – USB Vendor ID/Product
ID Guidelines for more details.
9.1 Method of Programming the OTP Memory
The OTP memory on a FT4222H device can be programmed over USB.
For the UMFT4222EV module, another module, named UMFT4222PROG, is required for
programming the FT4222H. In order to program the OTP memory, the FT4222H requires an
additional programming voltage (6.5V) on its VPP pin from JP1 pin 4. The UMFT4222PROG will
generate the 6.5V.
The datasheet of UMFT4222PROG module is available at this link.
http://www.ftdichip.com/Support/DS_UMFT4222PROG.pdf
© Copyright 2014 Future Technology Devices International Ltd
25
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
10 Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Branch Office – Tigard, Oregon, USA
Future Technology Devices International Limited
(USA)
7130 SW Fir Loop
Tigard, OR 97223
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
E-Mail (Support)
E-Mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Branch Office – Taipei, Taiwan
Future Technology Devices International Limited
(Taiwan)
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan , R.O.C.
Tel: +886 (0) 2 8791 3570
Fax: +886 (0) 2 8791 3576
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Branch Office – Shanghai, China
Future Technology Devices International Limited
(China)
Room 408, 317 Xianxia Road,
Shanghai, 200051
China
Tel: +86 21 62351596
Fax: +86 21 62351595
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
[email protected]
[email protected]
[email protected]
Web Site
http://ftdichip.com
System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology
Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level
performance requirements. All application-related information in this document (including application descriptions, suggested
FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this
information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications
assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the
user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from
such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is
implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product
described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent
of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640
© Copyright 2014 Future Technology Devices International Ltd
26
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
Appendix A – List of Tables and Figures
List of Tables
Table 4.1 Module Pin out Description ....................................................................... 11
Table 4.2 Module JP1 Pin out Description ................................................................. 12
Table 5.1 FT4222H Pin Functions on Chip Configuration Mode ................................. 14
Table 9.1 Default Internal OTP Memory Configuration ............................................. 25
List of Figures
Figure 1.1 – UMFT4222EV USB2.0 to QuadSPI/I2C Bridge Development Module ........ 2
Figure 4.1 Module Pin Out and Jumper Locations ....................................................... 9
Figure 5.1 Mode configuration example: Mode 3 (DCNF0 = 1, DCNF1 = 1) ............... 15
Figure 5.2 Mode configuration example: Mode 0 (DCNF0 = 0, DCNF1 = 0) ............... 15
Figure 6.1 UMFT4222EV Module Dimensions ............................................................ 19
Figure 7.1 Bus Powered Configuration ..................................................................... 20
Figure 7.2 Self-Powered Configuration ..................................................................... 21
Figure 7.3 Using FT4222H internal regulator ............................................................ 22
Figure 7.4 Use external power source for FT4222H IO Supply Voltage ..................... 23
Figure 8.1 Module Circuit Schematic ......................................................................... 24
© Copyright 2014 Future Technology Devices International Ltd
27
DS_UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge
Development Module
Version 1.0
Document Reference No.: FT_001057
Clearance No.: FTDI#407
Appendix B – Revision History
DS_UMFT4222EV USB2.0 to QuadSPI/I2C Bridge Development Module
Document Title:
Document Reference No.:
FT_001057
Clearance No.:
FTDI#407
Product Page:
http://www.ftdichip.com/FTProducts.htm
Document Feedback:
Version 1.0
DS_UMFT4222EV
Initial Release
© Copyright 2014 Future Technology Devices International Ltd
2014/09/26
28