Future Technology Devices International Ltd. Application Note AN_165 Establishing Synchronous 245 FIFO Communications using a MorphIC-II Document Reference No.: FT_000387 Version 1.1 Issue Date: 2012-06-26 The Morph-IC-II module is an FPGA-USB development platform that supports a number of serial communications interfaces including Synchronous 245 FIFO. A number of supporting source code samples have been provided by FTDI to assist in the development of Morph-IC-II applications. One of these examples is a Synchronous 245 FIFO application. This HDL application illustrates how to establish communications between the on board FT2232H of the Morph-IC-II and another synchronous 245 FIFO slave device. The FTDI UM232H is a module that can support synchronous 245 FIFO. This application note illustrates how to establish Synchronous 245 communications between a UM232H and a Morph-IC-II module. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such Future Technology Devices International Limited (FTDI) Unit 1, 2 Seaward Place, Glasgow G41 1HH, United Kingdom Tel.: +44 (0) 141 429 2777 Fax: + 44 (0) 141 429 2758 E-Mail (Support): [email protected] Web: http://www.ftdichip.com Copyright © 2012 Future Technology Devices International Limited Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Table of Contents 1 2 3 4 Introduction .................................................................... 2 1.1 What is a UM232H? ................................................................... 2 1.2 What is Morph-IC-II? ................................................................ 3 1.3 What is Synchronous 245 FIFO? ............................................... 3 Using and Understanding Synchronous 245 FIFO ............ 4 2.1 Syncronous 245 FIFO Signal Flow ............................................. 4 2.2 Synchronous 245 between Two Slave Devices via a Master ...... 6 Example Synchronous 245 FIFO Application ................... 7 3.1 An Outline of the Synchronous 245 Application ........................ 7 3.2 RTL Code ................................................................................... 8 3.3 Reset Polarity ........................................................................... 9 Example Application Procedure ..................................... 10 4.1 Configuring the EEPROM of the UM232H ................................. 10 4.2 Connecting the Morph-IC-II and UM232H ............................... 11 4.3 Editing the HDL Project ........................................................... 13 4.4 Load RBF ................................................................................. 13 4.5 Test for communications ......................................................... 15 5 Summary....................................................................... 20 6 Contact Information ...................................................... 21 Appendix A – Abbreviations ............................................... 22 Appendix B – References ................................................... 23 Appendix C – Revision History ........................................... 24 Copyright © 2012 Future Technology Devices International Limited 1 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 1 Introduction The aim of this application note is to illustrate the synchronous 245 FIFO capabilities of the Morph-IC-II and UM232H, by providing a synchronous 245 FIFO application, including source code, and giving step by step instructions on how to verify the application. The following equipment used in this application : 1 x FTDI Morph-IC-II – A USB-FPGA development module 1 x FTDI UM232H – A Hi-Speed USB to Serial/FIFO Module A proto-typing setup and USB cables Synchronous 245 application project files – The HDL collateral supplied for this application can be downloaded from here: http://www.ftdichip.com/Products/Files/Synchronous 245 Morph-IC-II Application.zip FT_Prog – A Programming Utility for FTDI devices MorphLd-II – Programming utility for the Morph-IC-II Quartus-II – A HDL Tool-Chain for Altera FPGAs Terminal.x – An FTDI utility for transferring data over different interfaces Note: All sample code and utilities provided in this note are for illustration purposes and are not guaranteed or supported. On completion of reading this app note the reader should be able to: Configure a FT2232H device for synchronous 245 FIFO mode Configure a FT232H device for synchronous 245 FIFO mode Program an Altera based FPGA to host the synchronous 245 FIFO devices 1.1 What is a UM232H? The UM232H is an evaluation module containing the FT232H chip. This module provides access to the serial/FIFO data channel. This module may be used to convert one USB port to either: UART, Synchronous 245 FIFO, Asynchronous 245 FIFO, FT1248 or MPSSE. For more information on the modules please see: UM232H Datasheet http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_UM232H.pdf FT232H Datasheet http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf Copyright © 2012 Future Technology Devices International Limited 2 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 1.2 What is Morph-IC-II? Morph-IC-II is an FTDI low cost USB-FPGA development platform. The major components of this module are the FTDI FT2232H and an Altera Cyclone II FPGA. The FT2232H is a dual channel USB communications device which converts USB data into a range of different interfaces including UART, Synchronous 245 FIFO, Asynchronous 245 FIFO and more. The FT2232H provides one programing channel for the FPGA (passive serial) and one application data channel to access data after configuration of the FPGA. Passive serial is an interface widely used by Altera FPGAs for programming and configuration. This interface is supported by the FT2232H’s MPSSE (Multi-Protocol Synchronous Serial Engine). For additional information please refer to the following documentation: Morph-IC-II Datasheet http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_Morph-IC-II.pdf MorphLd and MorphIO-II Utilities for Morph-IC-II http://www.ftdichip.com/Support/Documents/AppNotes/AN_141_MorphIOII%20and%20MorphLd%20Utilities%20for%20Morph-IC-II.pdf 1.3 What is Synchronous 245 FIFO? Synchronous 245 FIFO is a half-duplex point-to-point communications interface. This interface is synchronised to transmit data at a fixed clock rate of 60MHz, and can support data flow rates up to 35MByte per second. Synchronous 245 FIFO contains all the signals used by Asynchronous 245 FIFO plus an additional 2 lines: clock out which is a 60MHz clock signal and output enable used to enable the outputs of a slave device. Synchronous 245 FIFO can transfer data at much higher data rates than Asynchronous 245 FIFO. Synchronous 245 FIFO requires the master and the slave devices to be synchronised to the same 60MHz clock. Using this application note and the supporting hardware and application files, establishing a successful Synchronous 245 communication link can be made easy. For additional information please see: AN_130 FT2232H Used In An FT245 Style Synchronous FIFO Mode http://www.ftdichip.com/Support/Documents/AppNotes/AN_130_FT2232H_Used_In_FT245%20Synchron ous%20FIFO%20Mode.pdf DS_FT2232H http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf Located at www.ftdichip.com Copyright © 2012 Future Technology Devices International Limited 3 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 2 Using and Understanding Synchronous 245 FIFO 2.1 Syncronous 245 FIFO Signal Flow Synchronous 245 FIFO mode can be used to transfer data from two points: master and slave. The slave synchronous 245 system generates the 60MHz clock signal synchronised to a USB interface. This clock signal is used to synchronise the data sample rate and phase of the data being sent. The slave device indicates when it is prepared for beginning a read or a write process by setting the levels of the status lines RXF# and TXE#. A logic low RXF# indicates that the slave has data that can be transferred, the master can respond to this by setting OE# (output enable) to logic low which changes the direction of the slave’s data port to be in output mode. The slave’s data port is in input mode most of the time, but when the master requires data, the port of slave can be set to output mode. Once this data port is in output mode it only then becomes reasonable for the master to demand data from the slave. A logic low TXE# indicates that the slave device will allow for data to be written to its registers. The master can respond to this indication by initiating the transfer of data from the master to the slave device. The master controls the two strobe commands RD# and WR#. A logic low RD# will command that on the next rising clock edge; the master samples the transferring data and the slave to begin transferring the next byte of data. A logic low WR# commands that on the next rising clock edge; the slave samples the transferring data and the master to begin to transfer the next byte of data. The port direction of both master and slave synchronous 245 interfaces are shown in Figure 1. A signal plot of a read operation is given in Figure 2 and a write operation is given in Figure 3. Synchronous 245 FIFO contains a SI/WU (Send Immediate/WakeUp) signal which combines two functions. If the FT2232H USB is in suspend mode and remote wakeup is enabled in the EEPROM, strobing this line low will cause the device to request a resume on the USB BUS. Normally, this can be used to wake up the Host PC. When the FT2232H device is not in suspend mode, if the SI/WU line is strobed low any data in the device TX buffer will be sent out over USB on the next Bulk-IN request from the USB host regardless of the pending packet size. This can be used to optimise USB transfer speed for some applications. Synchronous 245 FIFO MASTER D0 D1 D2 D3 D4 D5 D6 D7 RXF# TXE# RD# WR# SI/WUA CLKOUT OE# D0 SLAVE D1 D2 D3 D4 D5 D6 D7 RXF# TXE# RD# WR# SI/WUA CLKOUT OE# Figure 1 – Synchronous 245 FIFO Data Flow Directions Copyright © 2012 Future Technology Devices International Limited 4 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 2 – Read Timing Figure 3 – Write Timing Copyright © 2012 Future Technology Devices International Limited 5 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Time Description Min Max 1 14 Units ns T1 RD# inactive to RXF# T2 RXF# inactive after RD# cycle T3 RD# to DATA T4 RD# active pulse width 30 ns T5 RD# active after RXF# 0 ns T6 WR# active to TXE# inactive 1 T7 TXE# active to TXE# after WR# cycle T8 T9 49 ns 1 14 14 ns ns 49 ns DATA to WR# active setup time 5 ns DATA hold time after WR# inactive 5 ns 30 ns T10 WR# active pulse width T11 WR# active after TXE# 0 Table 2.1 Asynchronous FIFO Timings (based on standard drive level outputs) ns 2.2 Synchronous 245 between Two Slave Devices via a Master Direct communications between two slave Synchronous 245 devices is not possible without the introduction of an intermediary master device to control both systems. The FPGA of the Morph-IC-II provides this master function as noted in Figure 4. SLAVE D0 D1 D2 D3 D4 D5 D6 D7 RXF# TXE# RD# WR# SI/WUA CLKOUT OE# Example Synchronous 245 Configuration D0 D0 MASTER D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 RXF# RXF# TXE# TXE# RD# RD# WR# WR# SI/WUA SI/WUA CLKOUT CLKOUT OE# OE# D0 SLAVE D1 D2 D3 D4 D5 D6 D7 RXF# TXE# RD# WR# SI/WUA CLKOUT OE# Figure 4 – Synchronous 245 Interface Block Diagram Copyright © 2012 Future Technology Devices International Limited 6 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 3 Example Synchronous 245 FIFO Application Included in the Morph-IC-II download is a Quartus-II Archive File labelled “MorphIC_HS_245_Sync_fifo.qar”. Contained in this file are a collection of RTL files used to synthesize a master synchronous 245 device that controls communication between two synchronous 245 slave devices. Also contained in this archive folder is a Quartus-II project folder that is ready to compile. This project file configures all the device settings, the pin-map and calls for a RBF file containing the entire project to be outputted after the project compiles. This RBF file can be loaded to the Morph-IC-II to synthesize the Synchronous 245 FIFO application hardware in the FPGA. Links for all the necessary utilities and applications are given in Appendix B. 3.1 An Outline of the Synchronous 245 Application An outline of the Synchronous 245 application is illustrated in Figure 5. This diagram illustrates the components used and their functions. FT2232H Cyclone II FPGA Sync245 HDL Application Loaded via USB or JTAG USB Connector JTAG Port USB Data Flow Morph-IC-II SLAVE MASTER Synchronous 245 FIFO Data Transfer UM232H FT232H USB Connector USB Data Flow SLAVE Figure 5 – A Block Diagram of the Synchronous 245 FIFO Application In this example, a synchronous 245 application RBF file is first loaded to the FPGA via USB or JTAG, this application HDL creates 2 master Synchronous 245 devices. When the master device is synthesised, synchronous 245 data can be transferred from one slave device to another slave device via the master. In this application USB data can be transmitted to either of the FT2232H or FT232H chips. The USB data is then translated to the synchronous 245 interface. In order to transfer the synchronous 245 data, communications between the synchronous 245 master device and the transmitting slave device the master device synchronises to the 60MHz clkout signal output by the transmitting slave device. When the master has synchronised to clkout, it can then read the status lines of the slave and respond by setting the control lines to allow for the transfer of data from the slave to the master. In a similar manner the master device can transfer synchronous 245 data to the other slave device. Here the master is synchronised to clkout of the receiving slave device, it sets the control lines and reads status lines then begins the transfer of data. Copyright © 2012 Future Technology Devices International Limited 7 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 3.2 RTL Code The following code sample lists the ports of the Synchronous 245 Interface application which is available in the “Morph-IC-II Application and Utilities” download. These ports include a reset line, the synchronous 245 FIFO data interface of the on board FT2232H of the Morph-IC-II and the synchronous 245 FIFO data interface of UM232H. entity morphic_hs_245_sync_fifo is generic ( loopback_to_hsext : integer := 0 ); port ( -- Inputs rst : in std_logic; -- Morphic on board FT2232H signals mdata : inout std_logic_vector(7 downto 0); mclk60 : in std_logic; mrxfn : in std_logic; mtxen : in std_logic; mrdn : out std_logic; mwrn : out std_logic; moen : out std_logic; msndimm : out std_logic; -- unused -- High speed Synchronous 245 signals hsndimm : out std_logic; hclk60 : in std_logic; hdata : inout std_logic_vector(7 hrxfn : in std_logic; htxen : in std_logic; hoen : out std_logic; hrdn : out std_logic; hwrn : out std_logic ); end morphic_hs_245_sync_fifo; -- Port A Data Bus -- unused -- 60MHz clock input downto 0); -- RX Full # -- TX Full # -- OE# HBDBUS6 -- RD# -- WR# The following VHDL files are comprised to the application RBF file when the Quartus-II project for this application is compiled: add8.vhd – An eight bit full adder dncntlg.vhd – A generic n-bit down counter dpram4.vhd – A four byte dual port RAM fadd1.vhd – A one bit full adder hs245_sif.vhd – 245 Fast Serial Interface for testing MorphIC-HS-245_Sync_fifo.vhd – Top level entity used to communicate between two Synchronous 245 devices seq_trig.vhd – Monitors Bus and triggers when presend value does not match the previous value + 1 sync_fifo.vhd – FIFO to Buffer with two different clock domains. Syncflop.vhd – Synchronises signals with different clock domains upcntg.vhd – A generic n-bit up counter The name of the Quartus-II project is MorphIC_HS_245_Sync_fifo.qpf Copyright © 2012 Future Technology Devices International Limited 8 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 3.3 Reset Polarity When programming the Morph-IC-II with the default USB-to-FPGA utilities an active high reset needs to be used. When programming the Morph-IC-II over JTAG an active low reset should be used. For programming over USB, set the HDL as follows: MorphIC_HS_245_Sync_fifo.vhd193 –reset_n <= rst; -- polarity to programme over JTAG 194 reset_n <= not rst; -- polarity to programme over USB Note this is the default setting. For programming over JTAG, set the HDL as follows: MorphIC_HS_245_Sync_fifo.vhd193 reset_n <= rst; -- polarity to programme over JTAG 194 –reset_n <= not rst; -- polarity to programme over USB Copyright © 2012 Future Technology Devices International Limited 9 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 4 Example Application Procedure In this section a step by step guide is given for establishing Synchronous 245 FIFO communications between a Morph-IC-II and a UM232H. This guide covers the following processes: - Configuring the EEPROM of the UM232H - Connecting the UM232H to the Morph-IC-II - Compiling the Quartus-II project and editing the Pin-Map of the application - Loading the application to the FPGA - Verification of Synchronous 245 FIFO communications 4.1 Configuring the EEPROM of the UM232H The EEPROM of the UM232H is set to UART mode by default. To establish Synchronous 245 FIFO communications the Serial/FIFO is required to be set into in 245 FIFO mode by setting the parameters as shown in bold in the table below The default EEPROM configuration of the Morph-IC-II is suitable for Synchronous 245 FIFO applications. Parameter Value Notes USB Vendor ID (VID) 0403h FTDI default VID (hex) USB Product UD (PID) 6014h FTDI default PID (hex) bcd Device 009h Pull down I/O Pins in USB Suspend Disabled Manufacturer Name FTDI Max Bus Power Current 150mA Power Source Bus Powered Device Type FT232H USB Version 0200 Enabling this option will make the device pull down on the UART interface lines when in USB suspend mode (PWREN# is high). Returns USB 2.0 device description to the host. Note: The device is a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 Hi-Speed device (480Mb/s). Remote Wake Up Enabled Taking RI# low will wake up the USB host controller from suspend in approximately 20 ms. High Current I/Os Disabled Enables the high drive level on the UART and ACBUS I/O pins. Load VCP Driver Enabled Makes the device load the VCP driver interface for the device. Hardware Specific 245 FIFO Port A Driver D2XX Direct Select 245 FIFO mode to communicate in 245 FIFO signals through Port A. Suppresses loading of VCP driver. Table 4.1 Recommended EEPROM Configuration For a detailed guide in how to programme and EEPROM: FT_PROG User Guide: http://www.ftdichip.com/Support/Documents/AppNotes/AN_124_User_Guide_For_FT_PROG.pdf Copyright © 2012 Future Technology Devices International Limited 10 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 4.2 Connecting the Morph-IC-II and UM232H In order to establish communications between a UM232H and a Morph-IC-II, both devices need to be correctly connected to each other as shown in Figure 6 where the pin labels along with the pin designators of each connected pin are given. The pins of the Morph-IC-II can be relocated since they are all general purpose I/O pins, the Morph-IC-II pin locations illustrated here are chosen to be in a simple location and they all correlate with the pin-map in the Quartus-II project supplied for this application. It should be noted that in the UM232H VBUS is connected to VCC to power the chip and V3V3 is connected to VIO to allow the IOs of the FT232H to be powered; these connections are illustrated in Figure 6. Morph-IC-II to UM232H Connections Master 16 J4-2 17 J4-4 18 J4-6 19 J4-8 21 J4-10 22 J4-12 23 J4-14 Morph-IC-II 24 J4-16 J4-19 26 27 J4-17 28 J4-15 29 J4-13 30 J4-11 32 J4-9 GND 33 J4-7 IOD13 D0 IOD14 D1 IOG13 D2 IOC14 D3 IOG16 D4 IOA12 D5 IOA13 D6 IOA14 D7 IOE14 RXF# IOD15 TXE# IOB14 RD# IOB13 WR# IOB12 SI/WUA IOJ12 CLKOUT IOJ11 OE# CN J2-7 2-7 Slave J1-3 USB E1 J2-8 J1-2 5V0 D3 J2-9 J2-3 V3V3 F3 J2-10 J2-2 VIO P2 J2-11 P1 J2-12 M4 J2-13 N1 J2-14 UM232H M2 J1-14 M1 J1-13 L2 J1-12 J4 J1-11 L1 J1-10 J2 J1-9 K2 J1-8 GND Figure 6 – Morph-IC-II and FT232H wire scheme Copyright © 2012 Future Technology Devices International Limited 11 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 The basic wire configuration of the Morph-IC-II is illustrated in Figure 7. In this diagram it can be seen that there is another synchronous 245 FIFO network to that of the UM232H. This Synchronous 245 interface is found between the FT2232H and the FPGA and is internally wired on the Morph-IC-II. Communications Interface Slave 16 16 17 17 18 18 19 19 21 21 22 22 23 23 FT2232HQ USB INTERFACE 24 24 26 26 27 27 28 28 29 29 30 30 32 32 33 33 AD0 IO AD1 IO AD2 IO AD3 IO AD4 IO AD5 IO AD6 IO AD7 IO RXF# IO TXE# IO RD# IO WR# IO SI/WUB IO CLKOUT IO OE# IO Master E2 E2 E1 E1 D3 D3 F3 F3 P2 P2 P1 P1 M4 N2 N1 N1 ALTERA CYCLONE II EP2C5F256C8N FPGA M2 M2 M1 M1 L2 L2 J4 J4 L1 L1 J2 J2 K2 K2 Morph-IC-II Figure 7 – Communications between the FT2232H of the Morph-IC-II and the FPGA of the Morph-IC-II Copyright © 2012 Future Technology Devices International Limited 12 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 4.3 Editing the HDL Project The Synchronous 245 application contains a Quartus II archive file containing all the source code and compiling parameters. A pre-compiled RBF is also included thus the Quartus II software package is not required for this project, however if any editing is required, the archived project file can be opened and edited using Quartus II. For Quartus II download and support, please refer to www.altera.com 4.4 Load RBF This section will describe how an application is programmed onto the Morph-IC-II. The Morph-IC-II uses a *.RBF (Raw Binary File) as a standard format. Included in the Synchronous 245 Application download file is a utility called MorphLd-II.exe. This utility can be used to load RBF files to the Morph-IC-II. The icon is illustrated in Figure 8. To load the featured Synchronous 245 application to the Morph-IC-II; open the MorphLd-II.exe utility and select Morph-IC-II B as the subject device port. The next step it to click on the Browse button inside the MorphLd-II.exe panel, and then open the file “MorphIC_HS_245_Sync_fifo.rbf” as illustrated in Figure 9. With the suitable RFB file and subject device port selected the Morph-IC-II can be programmed by clicking “Program” as shown Figure 10. Figure 8 – Opening the MorphLd-II Utility Copyright © 2012 Future Technology Devices International Limited 13 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 9 – Select the RBF File to be Loaded Figure 10 – Program the Morph-IC-II Copyright © 2012 Future Technology Devices International Limited 14 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 4.5 Test for communications In this section a description of how to set up two terminal programs which will be used to enter text to be sent from one device to the other and to display the received text from the receiving device. The two terminals used to do this are shown in Figure 11. To set these terminals the following steps should be completed: Select the devices required for communication. It can be seen in Figure 11 that each terminal communicates with one specific device, the top terminal communicates with Channel A of the Morph-IC-II (a channel dedicated for communications) and the bottom terminal communicates with the UM232H. In this experiment both terminals should be set up to communicate with Channel A of the Morph-IC-II and the UM232H respectively. Define the mode of communications. The mode of communications can be specified by selecting “Special Modes” and checking the “Enable Synchronous 245” checkbox as illustrated in Figure 11. Once this is completed open the ports of both devices by clicking open. Send text from one device and read that text with the other device. To carry out a basic test of communications from one device to another type anything in to the ASCII format box on one terminal then click return, it can be seen in Figure 12 the string “hi” was typed in one terminal and retrieved by the other and similarly for the string “hello” but in the opposite direction. Set a location and a name for a received file. In order to send a large amount of data using this terminal utility the location and a name must be defined for the file that will be received. It is essential that the file name has the same extension as the transmitted file. To set the location and name of a file open the “File Xfer” tab, open the “RCV file” panel, in this panel select a directory and a name for the received file. An example this is shown in Figure 13. Sending a file. To send a file to the location set by other terminal’s RCV file function, open the “File Xfer” tab, select “Send File”, select a file with the same extension as the file set by the RCV file and click on “Open”. An example this is shown in Figure 14. Close File and Verify. Once the transfer has completed the received file can be closed thus completing the transfer and receive process. At this stage it is possible to verify all the data has been transferred correctly without corruption. An example of this step is shown in Figure 15. Copyright © 2012 Future Technology Devices International Limited 15 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 11 – Configuring the Terminals for Synchronous 245 Communications Copyright © 2012 Future Technology Devices International Limited 16 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 12 – Sending text from one terminal to the other Copyright © 2012 Future Technology Devices International Limited 17 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 13 – Setting the Location for a Received File Copyright © 2012 Future Technology Devices International Limited 18 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 14 – Sending a File Copyright © 2012 Future Technology Devices International Limited 19 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Figure 15 – Close File and Verify 5 Summary This application note provides a background explanation of synchronous 245 FIFO mode and illustrates an example of establishing synchronous 245 FIFO communications between two slave devices via a master using an FTDI Morph-IC-II. Copyright © 2012 Future Technology Devices International Limited 20 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 6 Contact Information Head Office – Glasgow, UK Branch Office – Hillsboro, Oregon, USA Future Technology Devices International Limited Future Technology Devices International Limited (USA) Unit 1, 2 Seaward Place, Centurion Business Park 7235 NW Evergreen Parkway, Suite 600 Glasgow G41 1HH Hillsboro, OR 97123-5803 United Kingdom USA Tel: +44 (0) 141 429 2777 Tel: +1 (503) 547 0988 Fax: +44 (0) 141 429 2758 Fax: +1 (503) 547 0987 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) [email protected] [email protected] [email protected] E-Mail (Sales) E-Mail (Support) E-Mail (General Enquiries) [email protected] [email protected] [email protected] Branch Office – Taipei, Taiwan Branch Office – Shanghai, China Future Technology Devices International Limited (Taiwan) Future Technology Devices International Limited (China) 2F, No. 516, Sec. 1, NeiHu Road Room 1103, No. 666 West Huaihai Road, Taipei 114 Shanghai, 200052 Taiwan , R.O.C. China Tel: +886 (0) 2 8791 3570 Tel: +86 21 62351596 Fax: +886 (0) 2 8791 3576 Fax: +86 21 62351595 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) [email protected] [email protected] m [email protected] m E-mail (Sales) E-mail (Support) E-mail (General Enquiries) [email protected] [email protected] [email protected] Web Site http://ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Legal Disclaimer: System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All application-related information in this document (including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640 Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. Copyright © 2012 Future Technology Devices International Limited 21 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Appendix A – Abbreviations Terms Description EEPROM Electrically Erasable Programmable Read Only Memory FIFO First In First Out FPGA Field Programmable Gate Array FTDI Future Technology Devices International Ltd. MPSSE Multi-Protocol Synchronous Serial Engine RBF Raw Binary Format UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus Copyright © 2012 Future Technology Devices International Limited 22 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Appendix B – References Synchronous 245 Morph-IC-II Application http://www.ftdichip.com/Products/Files/Synchronous 245 Morph-IC-II Application.zip “Morph-IC-II Applications and Utilities” download http://www.ftdichip.com/Support/Utilities/MorphIC-II%20Package.zip Hi-Speed Mini Modules http://www.ftdichip.com/Products/EvaluationKits/HiSpeedModules.htm FT_Prog http://www.ftdichip.com/Resources/Utilities/FT_PROG.zip D2xx Programmers Guide http://www.ftdichip.com/Documents/ProgramGuides/D2XX_Programmer’s_Guide(FT_000071).pdf Interfacing FT2232H device to SPI http://www.ftdichip.com/Projects/MPSSE/AN_114_FTDI_Hi_Speed_USB_To_SPI_Example.pdf Recovery utility http://www.ftdichip.com/Resources/Utilities/SPITest.zip Quartus-II http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html Copyright © 2012 Future Technology Devices International Limited 23 Document Reference No.: FT_000387 AN_165 Establishing Synchronous 245 FIFO Communications using a Morph-IC-II Version 1.1 Clearance No.: FTDI# 221 Appendix C – Revision History Revision Changes Date 1.0 First Issue 2011-09-12 1.1 Corrected Figure 6 – Morph-IC-II and FT232H wire scheme 2012-06-26 Updated contact information Copyright © 2012 Future Technology Devices International Limited 24