1 product overview

20-S3-CK11F/FK11F-052003
USER'S MANUAL
S3CK11F/FK11F
CalmRISC
8-Bit CMOS
Microcontroller
Revision 0
S3CK11F/FK11F (Preliminary Spec)
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3CK11F/FK11F single-chip CMOS microcontroller is designed for high performance using Samsung's new
8-bit CPU core, CalmRISC.
CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has
separate program memory and data memory. Both instruction and data can be fetched simultaneously without
causing a stall, using separate paths for memory access. Represented below is the top block diagram of the
CalmRISC microcontroller.
1-1
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
20
PA[19:0]
Program Memory Address
Generation Unit
PD[15:0]
PC[19:0]
20
8
8
HS[0]
Hardware
Stack
TBH
HS[15]
TBL
DO[7:0]
ABUS[7:0]
BBUS[7:0]
DI[7:0]
ALUL
R0
ALUR
R1
R2
ALU
Flag
R3
GPR
RBUS
SR1
SR0
ILH
ILL
ILX
DA[15:0]
Data Memory
Address
Generation Unit
IDL0
IDH
IDL1
SPR
Figure 1-1. Top Block Diagram
1-2
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
The CalmRISC building blocks consist of:
— An 8-bit ALU
— 16 general purpose registers (GPR)
— 11 special purpose registers (SPR)
— 16-level hardware stack
— Program memory address generation unit
— Data memory address generation unit
Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2,
and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions,
and data memory index registers. The data memory address generation unit provides the data memory address
(denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are
accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address
generation unit contains a program counter, PC[19:0], and supplies the program memory address through
PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory
access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage
area.
Instruction Fetch
(IF)
Instruction Decode/
Data Memory Access
(ID/MEM)
Execution/Writeback
(EXE/WB)
Figure 1-2. CalmRISC Pipeline Diagram
CalmRISC has a 3-stage pipeline as described below:
As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data
memory where R is a GPR can be one operand of an ALU instruction as shown below:
The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program
counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode
and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and
data memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB),
where the required ALU operation is executed and the result is written back into the destination registers.
Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction
is completely finished but is performed immediately after completing the current instruction fetch. The pipeline
stream of instructions is illustrated in the following diagram.
1-3
PRODUCT OVERVIEW
/1
IF
/2
S3CK11F/FK11F (Preliminary Spec)
ID/MEM
EXE/WB
IF
ID/MEM
EXE/WB
IF
ID/MEM
EXE/WB
IF
IF
/3
/4
/5
ID/MEM
EXE/WB
IF
ID/MEM
EXE/WB
IF
ID/MEM
/6
EXE/WB
Figure 1-3. CalmRISC Pipeline Stream Diagram
Most CalmRISC instructions are 1-word instructions, while same branch instructions such as long "call" and "jp"
instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction, and it takes two
clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction
(CPI) is 1 except for long branches, which take 2 clock cycles per instruction.
1-4
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
FEATURES
CPU
LCD Controller/Driver
•
•
64 segments and 16 common terminals
•
8, 12, and 16 common selectable
•
Internal resistor circuit for LCD bias
CalmRISC core (8-bit RISC architecture)
Memory
•
32K × 16 bits program memory
•
192K × 8 bits data memory (Data ROM)
8-Bit Serial Interface
•
1K × 8bits data memory (Excluding LCD ROM)
•
Four programmable operating modes
Stack
8 × 8 Multiplier
•
•
Size: maximum 16 word-level
Signed by signed, unsigned by unsigned
90 I/O Pins
Two OP-Amps and PGC
•
I/O: 10 pins
•
External filter circuit needed
•
I/O: 80 pins (Sharing with LCD signal outputs)
•
-12, -6, 0, 6, or 12 dB selectable (PGC)
8-Bit Basic Timer
Low Voltage Reset (LVR)
•
8 kinds of clock source
•
•
Watch-dog timer function
VLVR = 2.1 V
A/D Converter
One 8-bit Timer/Counter 0
•
10-bit conversion resolution
•
Programmable interval timer
•
Sample and hold circuit
•
External event counter function
•
ADC operating voltage: 2.7 V to 3.6 V
•
PWM function and Capture function
D/A Converter (1 CHANNEL)
One 16-bit Timer/Counter 1
•
10-bit conversion resolution (R-2R, R = 7 kΩ)
•
One 16-bit Timer/Counter mode
•
DAC operating voltage: 2.7 V to 3.6 V
•
Two 8-bit Timer/Counters A/B mode
Two PWM Modules for Audio Output
One 8-bit Timer/Counter 2
•
5/6/78-bit PWM selectable
•
•
Direct speaker drive
•
2-bit extendable
Programmable interval timer
Watch Timer
•
3.91 mS, 0.25S, 0.5S, and 1S at 32.768 kHz
Two Power-Down Mode
•
0.5/1/2/4 kHz buzzer output selectable
•
Idle: only CPU clock stops
•
Stop: selected system clock and CPU clock stop
1-5
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
FEATURES (Continued)
Oscillation Sources
Operating Voltage Range
•
Crystal, ceramic, or RC for main clock
•
2.0 V to 3.6 V at 6.0 MHz
•
32.768 kHz Crystal for sub clock
•
3.0 V to 3.6 V at 8.0 MHz
•
CPU clock divider circuit
(divided by 1, 2, 4, 8, 16, 32, 64, or 128)
Operating Temperature Range
•
- 25 °C to 85 °C
Interrupts
•
2 Vectors, 15 interrupts sources
Package Type
•
Instruction Execution Times
•
Main Clocks:
125 ns at 8 MHz when 1 cycle instructions
250 ns at 8 MHz when 2 cycle instructions
•
Sub clocks (32.768 kHz)
30.52 us when 1 cycle instructions
61.04 us when 2 cycle instructions
1-6
117-pin pellet, 160-QFP-2828B(ES only)
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
BLOCK DIAGRAM
VDD
VSS
RESET
TEST
RC/X-TAL XOUT XTin XTout
XIN
MAIN OSC. SUB OSC.
WDT
BASIC
TIMER
P9.0-P9.7/
SEG0-SEG7
PORT 9
PORT 10
P10.0-P10.7/
COM8-COM15
P8.0-P8.7/
SEG8-SEG15
PORT 8
PORT 11
P11.0-P11.7/
COM0-COM7
P7.0-P7.7/
SEG16-SEG23
PORT 7
P6.0-P6.7/
SEG24-SEG31
PORT 6
P5.0-P5.7/
SEG32-SEG39
PORT 5
P4.0-P4.7/
SEG40-SEG47
PORT 4
TIMER 2
T2OUT/P2.4/SEG59
P3.0-P3.6/
SEG48-SEG54
P3.7/BUZ/SEG55
WATCH
TIMER
BUZ/P3.7/SEG55
PORT 3
P2.0/DAO/SEG63
P2.1/SO/SEG62
P2.2/SI/SEG61
P2.3/SCK/SEG60
P2.4/T2OUT/SEG59
P2.5/T1CLK/SEG58
P2.6/TAOUT/SEG57
P2.7/TBOUT/SEG56
P1.0/T0CLK
P1.1/T0OUT/T0PWM/
T0CAP
P0.0-P0.7/
INT0-INT7
PORT 2
Calm8 CPU
SI/P2.2/SEG61
SO/P2.1/SEG62
SCK/P2.3/SEG60
SIO
TIMER A
TIMER B
RAM
(1024 Bytes)
Data ROM
(192 K x 8)
TIMER1
TIMER 0
LVR
Control
register
(128 Bytes)
Multiplier
ROM
(32 K x 16)
2-PWM
Modules
T0CLK/P1.0
T0OUT/T0PWM/
T0CAP/P1.1
T1CLK/P2.5/SEG58
TAOUT/P2.6/SEG57
TBOUT/P2.7/SEG56
LVREN
PVDD
PVSS
PWM0
PWM1
PORT 1
10-bit D/A
Converter
DAO/P2.0/SEG63
PORT 0
10-bit A/D
Convterter
ADCIN
AVDD, AV SS
VMIC
OP1P, OP1N, PGCIN
OP1OUT, OP2OUT, PGCOUT
VREF
2 OP-Amps
and
PGC
LCD DRIVER/
CONTROLLER
COM0-COM15/P11.0-P10.7
SEG0-SEG63/P9.0-P2.0
Figure 1-4. Block Diagram
1-7
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
S3CK11F(S3FK11F)
160-QFP-2828B
NC
COM11/P10.3
COM10/P10.2
COM9/P10.1
COM8/P10.0
COM7/P11.7
COM6/P11.6
COM5/P11.5
COM4/P11.4
COM3/P11.3
COM2/P11.2
COM1/P11.1
COM0/P11.0
PVDD
PWM0
PVSS
PWM1
P1.0/T0CLK
P1.1/T0OUT/T0PWM/T0CAP
VDD
VSS
XOUT
XIN
TEST
XT IN
XTOUT
RESET
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3
P0.4/INT4
P0.5/INT5
P0.6/INT6
P0.7/INT7
LVREN
RC/X-TAL
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
SEG18/P7.2
SEG17/P7.1
SEG16/P7.0
SEG15/P8.7
SEG14/P8.6
SEG13/P8.5
SEG12/P8.4
SEG11/P8.3
SEG10/P8.2
SEG9/P8.1
SEG8/P8.0
SEG7/P9.7
SEG6/P9.6
SEG5/P9.5
SEG4/P9.4
SEG3/P9.3
SEG2/P9.2
SEG1/P9.1
SEG0/P9.0
COM15/P10.7
COM14/P10.6
COM13/P10.5
COM12/P10.4
NC
NC
NC
NC
NC
NC
NC
NC
NC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
SEG19/P7.3
SEG20/P7.4
SEG21/P7.5
SEG22/P7.6
SEG23/P7.7
SEG24/P6.0
SEG25/P6.1
SEG26/P6.2
SEG27/P6.3
SEG28/P6.4
SEG29/P6.5
SEG30/P6.6
SEG31/P6.7
SEG32/P5.0
SEG33/P5.1
SEG34/P5.2
SEG35/P5.3
SEG36/P5.4
SEG37/P5.5
SEG38/P5.6
SEG39/P5.7
SEG40/P4.0
SEG41/P4.1
SEG42/P4.2
SEG43/P4.3
SEG44/P4.4
SEG45/P4.5
SEG46/P4.6
SEG47/P4.7
SEG48/P3.0
SEG49/P3.1
SEG50/P3.2
SEG51/P3.3
SEG52/P3.4
SEG53/P3.5
NC
NC
PIN ASSIGNMENT
NOTE:
The package of S3CK11F is only for Engineer sample
Figure 1-5. Pin Assignment (160-QFP-2828B)
1-8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG54/P3.6
SEG55/P3.7/BUZ
SEG56/P2.7/TBOUT
SEG57/P2.6/TAOUT
SEG58/P2.5/T1CLK
SEG59/P2.4/T2OUT
SEG60/P2.3/SCK
SEG61/P2.2/SI
SEG62/P2.1/SO
SEG63/P2.0/DAO
AVSS
ADCIN
PGCOUT
PGCIN
OP2P
OP2N
OP2OUT
OP1OUT
OP1N
OP1P
VREF
VMIC
AVDD
NC
NC
NC
NC
NC
NC
NC
NC
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin
Numbers
Share
Pins
P0.0–P0.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input, push-pull or opendrain output, and software assignable
pull-ups; P0 is alternatively used for
external interrupt input (noise filters).
E–9
28–35
INT0–INT7
P1.0
P1.1
I/O
I/O port with bit-programmable pins;
Schmitt trigger input, pusn-pull or opendrain output, and software assignable
pull-ups.
E–4
18
19
T0CLK
T0OUT/T0PWM/
T0CAP
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input, push-pull or oepndrain output, and software assignable
pull-ups.
H–42
H–41
62
63
64
65
66
67
68
69
SEG63/DAO
SEG62/SO
SEG61/SI
SEG60/SCK
SEG59/T2OUT
SEG58/T1CLK
SEG57/TAOUT
SEG56/TBOUT
P3.0–P3.5
P3.6
P3.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input, push-pull, or opendrain output, and software assignable
pull-ups.
H–41
88–83
71
70
SEG48–SEG53
SEG54
SEG55/BUZ
P4.0–P4.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input, push-pull, or opendrain output, and software assignable
pull-ups.
H–41
96–89
SEG40–SEG47
P5.0–P5.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input, push-pull, or opendrain output, and software assignable
pull-ups.
H–41
104–97
SEG32–SEG39
P6.0–P6.7
I/O
I/O port with nibble-programmable pins;
Schmitt trigger input, push-pull output,
and software assignable pull-ups.
H–40
112–105
SEG24–SEG31
P7.0–P7.2
P7.3–P7.7
I/O
Same general characteristics as port 6.
H–40
131–129
117–113
SEG16–SEG18
SEG19–SEG23
P8.0–P8.7
I/O
Same general characteristics as port 6.
H–40
139–132
SEG8–SEG15
P9.0–P9.7
I/O
Same general characteristics as port 6.
H–40
147–140
SEG0–SEG7
P10.0–P10.3
P10.4–P10.7
I/O
Same general characteristics as port 6.
H–40
5–2
151–148
COM8–COM11
COM12–COM15
P11.0–P11.7
I/O
Same general characteristics as port 6.
H–40
13–6
COM0–COM7
1-9
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
Table 1-1. Pin Descriptions (Continued)
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin
Numbers
Share
Pins
PWM0, PWM1
O
PWM output pins for audio.
C
15, 17
–
PVDD, PVSS
–
Power pins for PWM block.
–
14, 16
–
LVREN
I
LVR enable pin (must be connected to
VDD or VSS)
A
36
–
VMIC
O
Microphone voltage output pin
D
50
–
OP1P, OP1N
I
OP-AMP1 non-invert and invert input
pins
–
52, 53
–
OP1OUT
O
OP-AMP1 output pin
–
54
–
OP2P, OP2N
I
OP-AMP2 non-invert and invert input
pins
–
57, 56
–
OP2OUT
O
OP-AMP2 output pin
–
55
–
PGCIN
I
Programmable gain controller input pin.
–
58
–
PGCOUT
O
Programmable gain controller output pin
–
59
–
ADCIN
I
Analog to digital converter input pin
–
60
–
VREF
O
Reference voltage output pin.
–
51
–
AVDD, AVSS
–
Power pins for analog block.
–
49, 61
–
COM0–COM7
COM8–COM11
COM12–COM15
I/O
LCD common data output pins
H–40
13–6
5–2
151–148
P11.0–P11.7
P10.0–P10.3
P10.4–P10.7
SEG0-SEG18
SEG19–SEG31
SEG32–SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
I/O
LCD segment data output pins
H–40
H–42
147–129
117–105
104–83
71
70
69
68
67
66
65
64
63
62
P9.0–P7.2
P7.3–P6.7
P5.0–P3.5
P3.6
P3.7/BUZ
P2.7/TBOUT
P2.6/TAOUT
P2.5/T1CLK
P2.4/T2OUT
P2.3/SCK
P2.2/SI
P2.1/SO
P2.0/DAO
INT0–INT7
I/O
External interrupt input pins
E–9
28–35
P0.0–P0.7
T0CLK
I/O
Timer0's external clock input pin.
E–4
18
P1.0
T0OUT
I/O
Timer0's interval output pin.
E–4
19
P1.1/T0PWM/
T0CAP
T0PWM
I/O
Timer0's PWM output pin.
E–4
19
P1.1/T0OUT
/T0CAP
T0CAP
I/O
Timer0's capture input pin.
E–4
19
P1.1/T0OUT
/T0PWM
1-10
H–41
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
Table 1-1. Pin Descriptions (Continued)
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Pin
Numbers
Share
Pins
DAO
I/O
D/A converter output
H–42
62
P2.0/SEG63
T1CLK
I/O
Timer 1/A external clock input pin
H–41
67
P2.5/SEG58
TAOUT
TBOUT
I/O
Timer A and 1/B clock outputs pins
H–41
68
69
P2.6/SEG57
P2.7/SEG56
T2OUT
I/O
Timer2's interval output pin
H–41
66
P2.4/SEG59
BUZ
I/O
Buzzer signal output pin
H–41
70
P3.7/SEG55
SI
I/O
Serial data input pin
H–41
64
P2.2/SEG61
SO
I/O
Serial data output pin
H–41
63
P2.1/SEG62
SCK
I/O
Serial I/O interface clock signal pin
H–41
65
P2.3/SEG60
RESET
I
System reset pin
B
27
–
XTin, XTout
–
Crystal oscillator pins for sub clock
–
25, 26
–
Xin, Xout
–
Main oscillator pins
–
23, 22
–
RC/X-TAL
–
Main oscillator type selection pin
("High" for RC osc, and "Low" for X-tal)
–
37
–
TEST
I
Input pin for test (must be connected by
VSS)
–
24
–
VDD, VSS
–
Power input pins
–
20, 21
–
1-11
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
PIN CIRCUITS
VDD
VDD
P-CHANNEL
PULL-UP
RESISTOR
IN
N-CHANNEL
IN
SCHMITT TRIGGER
Figure 1-6. Pin Circuit Type A (LVREN)
Figure 1-7. Pin Circuit Type B (RESET
RESET)
VDD
VDD
Data
Out
Output
Disable
N-Channel
Figure 1-8. Pin Circuit Type C (PWM0, PWM1)
1-12
P-CHANNEL
P-Channel
DATA
N-CHANNEL
Figure 1-9. Pin Circuit Type D (VMIC)
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open Drain
P-CH
Data
I/O
N-CH
Output
Disable
Figure 1-10. Pin Circuit Type E-4 (P1)
VDD
VDD
Pull-up
Resistor
Resistor
Enable
Open Drain
P-CH
Data
I/O
N-CH
Output
Disable
External
Interrupt
Input
Noise
Filter
Figure 1-11. Pin Circuit Type E-9 (P0)
1-13
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
VLC1
VLC2/3
OUT
VLC4/5
VSS
Figure 1-12. Pin Circuit Type H-29
VDD
Pull-up
Resistor
Resistor
Enable
Data
Output
Disable 1
COM/SEG
Output
Disable 2
Circuit
Type C
I/O
Circuit
Type H-29
Figure 1-13. Pin Circuit Type H-40 (P6, P7, P8, P9, P10, P11)
1-14
S3CK11F/FK11F (Preliminary Spec)
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open-Drain
P-CH
Data
Output
Disable 1
SEG
Output
Disable 2
I/O
N-CH
Circuit
Type H-29
Figure 1-14. Pin Circuit Type H-41 (P2.1–P2.7, P3, P4, P5)
VDD
VDD
Pull-up
Resistor
Resistor
Enable
Open-Drain
P-CH
Data
Output
Disable 1
SEG
Output
Disable 2
I/O
N-CH
Circuit
Type H-29
DAO
Output
Disable 3
Figure 1-15. Pin Circuit Type H-42 (P2.0)
1-15
PRODUCT OVERVIEW
S3CK11F/FK11F (Preliminary Spec)
NOTES
1-16
S3CK11F/FK11F (Preliminary Spec)
2
ADDRESS SPACES
ADDRESS SPACES
OVERVIEW
CalmRISC has 20-bit program address lines, PA[19:0], which supports up to 1M words of program memory. The
1M word program memory space is divided into 256 pages and each page is 4K word long as shown in the figure
2-1. The upper 8 bits of the program counter, PC[19:12], points to a specific page and the lower 12 bits, PC[11:0],
specify the offset address of the page.
CalmRISC also has 16-bit data memory address lines, DA[15:0], which supports up to 64K bytes of data memory.
The 64K byte data memory space is divided into 256 pages and each page has 256 bytes. The upper 8 bits of the
data address, DA[15:8], points to a specific page and the lower 8 bits, DA[7:0], specify the offset address of the
page.
PROGRAM MEMORY (ROM)
FFFH
1 Mword
FFFH
4 Kword
000H
256 page
000H
Figure 2-1. Program Memory Organization
2-1
ADDRESS SPACES
S3CK11F/FK11F (Preliminary Spec)
For example, if PC[19:0] = 5F79AH, the page index pointed to by PC is 5FH and the offset in the page is 79AH.
If the current PC[19:0] = 5EFFFH and the instruction pointed to by the current PC, i.e., the instruction at the
address 5EFFFH is not a branch instruction, the next PC becomes 5E000H, not 5F000H. In other words, the
instruction sequence wraps around at the page boundary, unless the instruction at the boundary (in the above
example, at 5EFFFH) is a long branch instruction. The only way to change the program page is by long branches
(LCALL, LLNK, and LJP), where the absolute branch target address is specified. For example, if the current
PC[19:0] = 047ACH (the page index is 04H and the offset is 7ACH) and the instruction pointed to by the current
PC, i.e., the instruction at the address 047ACH, is "LJP A507FH" (jump to the program address A507FH), then
the next PC[19:0] = A507FH, which means that the page and the offset are changed to A5H and 07FH,
respectively. On the other hand, the short branch instructions cannot change the page indices.
Suppose the current PC is 6FFFEH and its instruction is "JR 5H" (jump to the program address PC + 5H). Then
the next instruction address is 6F003H, not 70003H. In other words, the branch target address calculation also
wraps around with respect to a page boundary. This situation is illustrated below:
Page 6FH
000H
001H
002H
003H
004H
005H
FFEH
JR 5H
FFFH
Figure 2-2. Relative Jump Around Page Boundary
Programmers do not have to manually calculate the offset and insert extra instructions for a jump instruction
across page boundaries. The compiler and the assembler for CalmRISC are in charge of producing appropriate
codes for it.
2-2
S3CK11F/FK11F (Preliminary Spec)
ADDRESS SPACES
FFFFFH
~
~
~
~
1FFFFH
Program Memory Area
(4K words x 256 page = 1 Mword)
Data ROM
96K words
(192K bytes)
08000H
07FFFH
Program ROM
32K words
(64K bytes)
00020H
0001FH
00000H
NOTE:
Vector and
Option Area
The total size of ROM (Program ROM + Data ROM) is the 128k x 16-bit.
The program ROM's address is 0000H - 7FFFH and the data ROM's address is
8000H - 1FFFFH.
Figure 2-3. Program Memory Layout
From 00000H to 00004H addresses are used for the vector address of exceptions, and 0001EH, 0001FH are
used for the option only. Aside from these addresses others are reserved in the vector and option area. Program
memory area from the address 00020H to FFFFFH can be used for normal programs.
The Program memory size of S3CK11F is 32K word (64K byte), so from the address 00020H to 07FFFH are the
program memory area.
The data ROM size of S3CK11F is 96K word (192K bytes), so total ROM size is 128K words (256K bytes).
2-3
ADDRESS SPACES
S3CK11F/FK11F (Preliminary Spec)
ROM CODE OPTION (RCOD_OPT)
Just after power on, the ROM data located at 0001EH and 0001FH is used as the ROM code option.
S3CK11F has ROM code options like the Reset value of Basic timer and Watchdog timer enable.
For example, if you program as below:
RCOD_OPT
1EH, 0x0000
RCOD_OPT
1FH, 0xbfff
 fxx/32 is used as Reset value of basic timer (by bit.14, 13, 12)
 Watchdog timer is enabled (by bit.11)
If you don't program any values in these option areas, then the default value is "1".
In these cases, the address 0001EH would be the value of "FFFFH".
2-4
S3CK11F/FK11F (Preliminary Spec)
ADDRESS SPACES
ROM_Code Option (RCOD_OPT)
ROM Address: 0001FH
MSB
.15
.14
.13
.12
.11
.10
.9
.8
LSB
Not used
Not used
Reset value of basic timer
clock selection bits
(WDTCON.6, .5, .4):
000 = fxx/2
001 = fxx/4
010 = fxx/16
Watch-dog timer enable selection bit:
011 = fxx/32
0 = Disable WDT
100 = fxx/128
1 = Enable WDT
101 = fxx/256
110 = fxx/1024
111 = fxx/2048
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
.10
.9
.8
LSB
.2
.1
.0
LSB
Not used
ROM Address: 0001EH
MSB
.15
.14
.13
.12
.11
Not used
MSB
.7
.6
.5
.4
.3
Not used
Figure 2-4. ROM Code Option (RCOD_OPT)
2-5
ADDRESS SPACES
S3CK11F/FK11F (Preliminary Spec)
DATA MEMORY ORGANIZATION
The total data memory address space is 64K bytes, addressed by DA[15:0], and divided into 256 pages, Each
page consists of 256 bytes as shown below.
FFH
64K bytes
FFH
FFHFFFH
00H
256 Byte
256 page
00H
00H
5 page
Figure 2-5. Data Memory Map of CalmRISC8
The data memory page is indexed by SPR and IDH. In data memory index addressing mode, 16-bit data memory
address is composed of two 8-bit SPRs, IDH[7:0] and IDL0[7:0] (or IDH[7:0] and IDL1[7:0]). IDH[7:0] points to a
page index, and IDL0[7:0] (or IDL1[7:0]) represents the page offset. In data memory direct addressing mode, an
8-bit direct address, adr[7:0], specifies the offset of the page pointed to by IDH[7:0] (See the details for direct
addressing mode in the instruction sections). Unlike the program memory organization, data memory address
does not wrap around. In other words, data memory index addressing with modification performs an addition or a
subtraction operation on the whole 16-bit address of IDH[7:0] and IDL0[7:0] (or IDL1[7:0]) and updates IDH[7:0]
and IDL0[7:0] (or IDL1[7:0]) accordingly. Suppose IDH[7:0] is 0FH and IDL0[7:0] is FCH and the modification on
the index registers, IDH[7:0] and IDL0[7:0], is increment by 5H, then, after the modification (i.e., 0FFCH + 5 =
1001H), IDH[7:0] and IDL0[7:0] become 10H and 01H, respectively.
2-6
S3CK11F/FK11F (Preliminary Spec)
ADDRESS SPACES
The S3CK11F has 1,152 bytes of data register address from 0080H to 04FFH.
The area from 0000H to 007FH is for peripheral control, and LCD RAM area is from 0480H to 04FFH.
4FFH
FFH
in Byte
Page4
Page4
Page3
Page2
Page1
Page 0
LCD
Display
Register
Area
Data Memory
480H
80H
7FH
Control Register
00H
8-bit
Figure 2-6. Data Memory Map of S3CK11F
2-7
ADDRESS SPACES
S3CK11F/FK11F (Preliminary Spec)
NOTES
2-8
S3CK11F/FK11F (Preliminary Spec)
3
REGISTERS
REGISTERS
OVERVIEW
The registers of CalmRISC are grouped into 2 parts: general purpose registers and special purpose registers.
Table 3-1. General and Special Purpose Registers
Registers
Mnemonics
General Purpose
R0
General Register 0
Unknown
Registers (GPR)
R1
General Register 1
Unknown
R2
General Register 2
Unknown
R3
General Register 3
Unknown
IDL0
Lower Byte of Index Register 0
Unknown
IDL1
Lower Byte of Index Register 1
Unknown
IDH
Higher Byte of Index Register
Unknown
SR0
Status Register 0
ILX
Instruction Pointer Link Register for
Extended Byte
Unknown
ILH
Instruction Pointer Link Register for
Higher Byte
Unknown
ILL
Instruction Pointer Link Register for
Lower Byte
Unknown
SR1
Status Register 1
Unknown
Special Purpose
Group 0 (SPR0)
Registers (SPR)
Group 1 (SPR1)
Description
Reset Value
00H
GPR's can be used in most instructions such as ALU instructions, stack instructions, load instructions, etc (See
the instruction set sections). From the programming standpoint, they have almost no restriction whatsoever.
CalmRISC has 4 banks of GPR's and each bank has 4 registers, R0, R1, R2, and R3. Hence, 16 GPR's in total
are available. The GPR bank switching can be done by setting an appropriate value in SR0[4:3] (See SR0 for
details). The ALU operations between GPR's from different banks are not allowed.
SPR's are designed for their own dedicated purposes. They have some restrictions in terms of instructions that
can access them. For example, direct ALU operations cannot be performed on SPR's. However, data transfers
between a GPR and an SPR are allowed and stack operations with SPR's are also possible (See the instruction
sections for details).
3-1
REGISTERS
S3CK11F/FK11F (Preliminary Spec)
INDEX REGISTERS: IDH, IDL0 AND IDL1
IDH in concatenation with IDL0 (or IDL1) forms a 16-bit data memory address. Note that CalmRISC's data
memory address space is 64 K byte (addressable by 16-bit addresses). Basically, IDH points to a page index and
IDL0 (or IDL1) corresponds to an offset of the page. Like GPR's, the index registers are 2-way banked. There are
2 banks in total, each of which has its own index registers, IDH, IDL0 and IDL1. The banks of index registers can
be switched by setting an appropriate value in SR0[2] (See SR0 for details). Normally, programmers can reserve
an index register pair, IDH and IDL0 (or IDL1), for software stack operations.
LINK REGISTERS: ILX, ILH AND ILL
The link registers are specially designed for link-and-branch instructions (See LNK and LRET instructions in the
instruction sections for details). When an LNK instruction is executed, the current PC[19:0] is saved into ILX, ILH
and ILL registers, i.e., PC[19:16] into ILX[3:0], PC[15:8] into ILH [7:0], and PC[7:0] into ILL[7:0], respectively.
When an LRET instruction is executed, the return PC value is recovered from ILX, ILH, and ILL, i.e., ILX[3:0] into
PC[19:16], ILH[7:0] into PC[15:8] and ILL[7:0] into PC[7:0], respectively. These registers are used to access
program memory by LDC/LDC+ instructions. When an LDC or LDC+ instruction is executed, the (code) data
residing at the program address specified by ILX:ILH:ILL will be read into TBH:TBL. LDC+ also increments ILL
after accessing the program memory.
There is a special core input pin signal, nP64KW, which is reserved for indicating that the program memory
address space is only 64 K word. By grounding the signal pin to zero, the upper 4 bits of PC, PC[19:16], is
deactivated and therefore the upper 4 bits, PA[19:16], of the program memory address signals from CalmRISC
core are also deactivated. By doing so, power consumption due to manipulating the upper 4 bits of PC can be
totally eliminated (See the core pin description section for details). From the programmer’s standpoint, when
nP64KW is tied to the ground level, then PC[19:16] is not saved into ILX for LNK instructions and ILX is not read
back into PC[19:16] for LRET instructions. Therefore, ILX is totally unused in LNK and LRET instructions when
nP64KW = 0.
3-2
S3CK11F/FK11F (Preliminary Spec)
REGISTERS
STATUS REGISTER 0: SR0
SR0 is mainly reserved for system control functions and each bit of SR0 has its own dedicated function.
Table 3-2. Status Register 0 configuration
Flag Name
Bit
Description
eid
0
Data memory page selection in direct addressing
ie
1
Global interrupt enable
idb
2
Index register banking selection
grb[1:0]
4,3
exe
5
Stack overflow/underflow exception enable
ie0
6
Interrupt 0 enable
ie1
7
Interrupt 1 enable
GPR bank selection
SR0[0] (or eid) selects which page index is used in direct addressing. If eid = 0, then page 0 (page index = 0) is
used. Otherwise (eid = 1), IDH of the current index register bank is used for page index. SR0[1] (or ie) is the
global interrupt enable flag. As explained in the interrupt/exception section, CalmRISC has 3 interrupt sources
(non-maskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. Both interrupt 0 and interrupt 1 are
masked by setting SR0[1] to 0 (i.e., ie = 0). When an interrupt is serviced, the global interrupt enable flag ie is
automatically cleared. The execution of an IRET instruction (return from an interrupt service routine)
automatically sets ie = 1. SR0[2] (or idb) and SR0[4:3] (or grb[1:0]) selects an appropriate bank for index registers
and GPR's, respectively as shown below:
R3
R3 R2
R3 R2
R1
R3 R2
R1
R0
R2 R1
Bank 3
R0
R1 R0
Bank 2
Bank
1
R0
Bank 0
grb [1:0]
11
10
01
00
idb
1
0
IDH
IDH
IDL0
IDL0 IDL1
IDL1
Figure 3-1. Bank Selection by Setting of GRB Bits and IDB Bit
SR0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. If exe = 0, the stack
exception is disabled. The stack exception can be used for program debugging in the software development
stage. SR0[6] (or ie0) and SR0[7] (or ie1) are enabled, by setting them to 1. Even though ie0 or ie1 are enabled,
the interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0.
3-3
REGISTERS
S3CK11F/FK11F (Preliminary Spec)
STATUS REGISTER 1: SR1
SR1 is the register for status flags such as ALU execution flag and stack full flag.
Table 3-3. Status Register 1: SR1
Flag Name
Bit
Description
C
0
Carry flag
V
1
Overflow flag
Z
2
Zero flag
N
3
Negative flag
SF
4
Stack Full flag
–
5,6,7
Reserved
SR1[0] (or C) is the carry flag of ALU executions. SR1[1] (or V) is the overflow flag of ALU executions. It is set to
1 if and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th
bit position. SR1[2] (or Z) is the zero flag, which is set to 1 if and only if the ALU result is zero. SR1[3] (or N) is
the negative flag. Basically, the most significant bit (MSB) of ALU results becomes N flag. Note a load instruction
into a GPR is considered an ALU instruction. However, if an ALU instruction touches the overflow flag (V) like
ADD, SUB, CP, etc, N flag is updated as exclusive-OR of V and the MSB of the ALU result. This implies that
even if an ALU operation results in overflow, N flag is still valid. SR1[4] (or SF) is the stack overflow flag. It is set
when the hardware stack is overflowed or under flowed. Programmers can check if the hardware stack has any
abnormalities by the stack exception or testing if SF is set (See the hardware stack section for great details).
NOTE
When an interrupt occurs, SR0 and SR1 are not saved by hardware, so SR0, and SR1 register values
must be saved by software.
3-4
S3CK11F/FK11F (Preliminary Spec)
4
MEMORY MAP
MEMORY MAP
OVERVIEW
To support the control of peripheral hardware, the address for peripheral control registers are memory-mapped to
page 0 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the
specific memory location.
In this section, detailed descriptions of the control registers are presented in an easy-to-read format.
You can use this section as a quick-reference source when writing application programs.
This memory area can be accessed with the whole method of data memory access.
— If SR0 bit 0 is "0" then the accessed register area is always page 0.
— If SR0 bit 0 is "1" then the accessed register page is controlled by the proper IDH register's value.
So if you want to access the memory map area, clear the SR0.0 and use the direct addressing mode.
This method is used for most cases.
This control register is divided into five areas. Here, the system control register area is same in every device.
Control Register
7FH
Peripheral Control Register ( 1x 16 or 2 x 8)
70H
6FH
Peripheral Control Register (4 x 8)
40H
3FH
Port Control Register Area (4 x 8)
20H
1FH
Port Data Register Area
10H
0FH
System Control Register Area
Standard exhortative area
Standard area
00H
Figure 4-1. Memory Map Area
4-1
MEMORY MAP
S3CK11F/FK11F (Preliminary Spec)
Table 4-1. Registers
Register Name
Mnemonic
Decimal
Hex
Reset
R/W
Locations 1CH–1FH are not mapped
Port 11 data register
P11
27
1BH
00H
R/W
Port 10 data register
P10
26
1AH
00H
R/W
Port 9 data register
P9
25
19H
00H
R/W
Port 8 data register
P8
24
18H
00H
R/W
Port 7 data register
P7
23
17H
00H
R/W
Port 6 data register
P6
22
16H
00H
R/W
Port 5 data register
P5
21
15H
00H
R/W
Port 4 data register
P4
20
14H
00H
R/W
Port 3 data register
P3
19
13H
00H
R/W
Port 2 data register
P2
18
12H
00H
R/W
Port 1 data register
P1
17
11H
00H
R/W
Port 0 data register
P0
16
10H
00H
R/W
Locations 0EH–0FH are not mapped.
Watchdog timer control register
WDTCON
13
0DH
X0H
R/W
BTCNT
12
0CH
00H
R
Interrupt ID register 1
IIR1
11
0BH
–
R/W
Interrupt priority register 1
IPR1
10
0AH
–
R/W
Interrupt mask register 1
IMR1
9
09H
00H
R/W
Interrupt request register 1
IRQ1
8
08H
–
R
Interrupt ID register 0
IIR0
7
07H
–
R/W
Interrupt priority register 0
IPR0
6
06H
–
R/W
Interrupt mask register 0
IMR0
5
05H
00H
R/W
Interrupt request register 0
IRQ0
4
04H
–
R
OSCCON
3
03H
00H
R/W
PCON
2
02H
04H
R/W
Basic timer counter
Oscillator control register
Power control register
Locations 00H–01H are not mapped.
NOTES:
1. '–' means undefined.
2. If you want to clear the bit of IRQx, then write the number that you want to clear to IIRx. For example, when clear
IRQ0.4 then LD Rx, #04H and LD IIR0, Rx.
4-2
S3CK11F/FK11F (Preliminary Spec)
MEMORY MAP
Table 4-1. Registers (Continued)
Register Name
Mnemonic
Decimal
Hex
Reset
R/W
Location 43H is not mapped
Timer 0 control register
T0CON
66
42H
00H
R/W
Timer 0 data register
T0DATA
65
41H
FFH
R/W
T0CNT
64
40H
00H
R
D/A converter data register low
DATATAL
63
3FH
00H
R/W
D/A converter data register high
DATATAH
62
3EH
00H
R/W
D/A converter control register
DACON
61
3DH
00H
R/W
Port 11 control register
P11CON
60
3CH
00H
R/W
Port 10 control register
P10CON
59
3BH
00H
R/W
Port 9 control register
P9CON
58
3AH
00H
R/W
Port 8 control register
P8CON
57
39H
00H
R/W
Port 7 control register
P7CON
56
38H
00H
R/W
Port 6 control register
P6CON
55
37H
00H
R/W
Port 5 pull-up control register
P5PUR
54
36H
00H
R/W
Port 5 control register low
P5CONL
53
35H
00H
R/W
Port 5 control register high
P5CONH
52
34H
00H
R/W
P4PUR
50
32H
00H
R/W
Port 4 control register low
P4CONL
49
31H
00H
R/W
Port 4 control register high
P4CONH
48
30H
00H
R/W
P3PUR
46
2EH
00H
R/W
Port 3 control register low
P3CONL
45
2DH
00H
R/W
Port 3 control register high
P3CONH
44
2CH
00H
R/W
Port 2 alternative function selection register
P2FUNC
43
2BH
00H
R/W
P2PUR
42
2AH
00H
R/W
Port 2 control register low
P2CONL
41
29H
00H
R/W
Port 2 control register high
P2CONH
40
28H
00H
R/W
Timer 0 counter register
Location 33H is not mapped
Port 4 pull-up control register
Location 2FH is not mapped
Port 3 pull-up control register
Port 2 pull-up control register
Locations 25H–27H are not mapped
Port 1 control register
P1CON
36
24H
00H
R/W
Port 0 interrupts enable register
P0INT
35
23H
00H
R/W
Port 0 pull-up control register
P0PUR
34
22H
00H
R/W
Port 0 control register low
P0CONL
33
21H
00H
R/W
Port 0 control register high
P0CONH
32
20H
00H
R/W
4-3
MEMORY MAP
S3CK11F/FK11F (Preliminary Spec)
Table 4-1. Registers (Continued)
Register Name
Mnemonic
Decimal
Hex
Reset
R/W
Internal data ROM buffer 0 - 15
IDRBUF0-15
112–127
70H–7FH
00H
R
A/D converter data register 0 - 3
ADDATA0-3
104–111
68H–6FH
–
R
A/D converter control register
ADCON
103
67H
00H
R/W
OP-Amp control register
OPCON
102
66H
00H
R/W
IDRPS
101
65H
00H
R/W
Internal data ROM buffer address
IDRBUFAR
100
64H
7EH
R
Internal data ROM address 0 -2
IDRAR0-2
97-99
61H-63H
00H
R/W
IDRCON
96
60H
00H
R/W
PWM1 counter
PWM1CNT
95
5FH
00H
R
PWM0 counter
PWM0CNT
94
5EH
00H
R
PWM1 data register
PWM1DATA
93
5DH
FFH
R/W
PWM0 data register
PWM0DATA
92
5CH
FFH
R/W
PWM1 mode register
PWM1MOD
91
5BH
00H
R/W
PWM0 mode register
PWM0MOD
90
5AH
00H
R/W
PWM modules extend register
EXDREG
89
59H
00H
R/W
PWM modules control register
PWMCON
88
58H
00H
R/W
Internal data ROM pre-scaler register
Internal data ROM control register
Location 57H is not mapped
Multiplier control register
MULCON
86
56H
00H
R/W
Multipler X input register
MXINP
85
55H
00H
R/W
Multipler Y input register
MYINP
84
54H
00H
R/W
Multiplication result register high
MRH
83
53H
00H
R
Multiplication result register low
MRL
82
52H
00H
R
LCON
81
51H
00H
R/W
Watch timer control register
WTCON
80
50H
00H
R/W
SIO data register
SIODATA
79
4FH
00H
R/W
SIOPS
78
4EH
00H
R/W
SIO control register
SIOCON
77
4DH
00H
R/W
Timer 2 control register
T2CON
76
4CH
00H
R/W
Timer 2 data register
T2DATA
75
4BH
FFH
R/W
Timer 2 counter register
T2CNT
74
4AH
00H
R
Timer 1/B control register
TBCON
73
49H
00H
R/W
Timer A control register
TACON
72
48H
00H
R/W
Timer B data register
TBDATA
71
47H
FFH
R/W
Timer A data register
TADATA
70
46H
FFH
R/W
Timer B counter register
TBCNT
69
45H
00H
R
Timer A counter register
TACNT
68
44H
00H
R
LCD control register
SIO pre-scaler register
4-4
S3CK11F/FK11F (Preliminary Spec)
5
HARDWARE STACK
HARDWARE STACK
OVERVIEW
The hardware stack in CalmRISC has two usages:
— To save and restore the return PC[19:0] on LCALL, CALLS, RET, and IRET instructions.
— Temporary storage space for registers on PUSH and POP instructions.
When PC[19:0] is saved into or restored from the hardware stack, the access should be 20-bit wide. On the other
hand, when a register is pushed into or popped from the hardware stack, the access should be 8-bit wide. Hence,
to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank
(XSTACK, 4-bit wide), the odd bank (8-bit wide), and the even bank (8-bit wide).
Hardware Stack
5
3
0
7
0
7
Stack Pointer
SPTR [5:0]
1
0
0
Level 0
Level 1
Level 2
Stack Level
Pointer
Odd or Even
Bank Selector
Level 14
Level 15
XSTACK
Odd Bank
Even Bank
Figure 5-1. Hardware Stack
5-1
HARDWARE STACK
S3CK11F/FK11F (Preliminary Spec)
The top of the stack (TOS) is pointed to by a stack pointer, called sptr[5:0]. The upper 5 bits of the stack pointer,
sptr[5:1], points to the stack level into which either PC[19:0] or a register is saved. For example, if sptr[5:1] is 5H
or TOS is 5, then level 5 of XSTACK is empty and either level 5 of the odd bank or level 5 of the even bank is
empty. In fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. If sptr[0] = 0, both level 5 of
the even and the odd banks are empty. On the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but
level 5 of the even bank is occupied. This situation is well illustrated in the figure below.
Level 0
Level 1
Level 2
Level 3
SPTR [5:0]
5
1 0
0 0 1 0 1 0
Stack Level
Pointer
Level 4
Level 5
Bank Selector
Level 15
XSTACK Odd Bank Even Bank
Level 0
Level 1
Level 2
Level 3
SPTR [5:0]
5
1 0
0 0 1 0 1 1
Stack Level
Pointer
Level 4
Level 5
Bank Selector
Level 15
XSTACK Odd Bank Even Bank
Figure 5-2. Even and Odd Bank Selection Example
As can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when PC[19:0] is pushed or
popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. Note that XSTACK is
used only for storing and retrieving PC[19:16]. Let us consider the cases where PC[19:0] is pushed into the
hardware stack (by executing LCALL/CALLS instructions or by interrupts/exceptions being served) or is retrieved
from the hardware stack (by executing RET/IRET instructions). Regardless of the stack bank selection bit
(sptr[0]), TOS of the even bank and the odd bank store or return PC[7:0] or PC[15:8], respectively. This is
illustrated in the following figures.
5-2
S3CK11F/FK11F (Preliminary Spec)
HARDWARE STACK
SPTR [5:0]
Level 0
5
SPTR [5:0]
Level 0
1 0
5
0 0 1 0 1 0
1 0
0 0 1 0 1 1
Stack Level
Pointer
Stack Level
Pointer
Level 5
Level 5
Bank Selector
Level 6
Level 15
Bank Selector
Level 6
Level 15
XSTACK Odd Bank Even Bank
by Executing RET, IRET
XSTACK Odd Bank Even Bank
by Executing CALL, CALLS
or Interrupts/Exceptions
SPTR [5:0]
Level 0
5
by Executing RET, IRET
by Executing CALL, CALLS
or Interrupts/Exceptions
SPTR [5:0]
Level 0
1 0
5
Stack Level
Pointer
Level 5 PC[19:16]
PC[15:8]
Bank Selector
Level 6
Stack Level
Pointer
Level 5 PC[19:16]
PC[7:0]
1 0
0 0 1 1 0 1
0 0 1 1 0 0
PC[7:0]
Level 6
PC[15:8]
Bank Selector
Level 15
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
Figure 5-3. Stack Operation with PC [19:0]
As can be seen in the figures, when stack operations with PC[19:0] are performed, the stack level pointer
sptr[5:1] (not sptr[5:0]) is either incremented by 1 (when PC[19:0] is pushed into the stack) or decremented by 1
(when PC[19:0] is popped from the stack). The stack bank selection bit (sptr[0]) is unchanged. If a CalmRISC
core input signal nP64KW is 0, which signifies that only PC[15:0] is meaningful, then any access to XSTACK is
totally deactivated from the stack operations with PC. Therefore, XSTACK has no meaning when the input pin
signal, nP64KW, is tied to 0. In that case, XSTACK doesn't have to even exist. As a matter of fact, XSTACK is
not included in CalmRISC core itself and it is interfaced through some specially reserved core pin signals
(nPUSH, nSTACK, XHSI[3:0], XSHO[3:0]), if the program address space is more than 64 K words (See the core
pin signal section for details).
With regards to stack operations with registers, a similar argument can be made. The only difference is that the
data written into or read from the stack are a byte. Hence, the even bank and the odd bank are accessed
alternately as shown below.
5-3
HARDWARE STACK
S3CK11F/FK11F (Preliminary Spec)
SPTR [5:0]
Level 0
5
SPTR [5:0]
Level 0
1 0
5
0 0 1 0 1 0
Stack Level
Pointer
Stack Level
Pointer
Level 5
Level 5
Bank Selector
Level 6
Level 15
Bank Selector
Level 6
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
POP Register
POP Register
PUSH Register
SPTR [5:0]
Level 0
5
PUSH Register
SPTR [5:0]
Level 0
1 0
5
Stack Level
Pointer
Stack Level
Pointer
Level 5
Register
Bank Selector
Level 6
1 0
0 0 1 1 0 0
0 0 1 0 1 1
Level 5
1 0
0 0 1 0 1 1
Register
Level 6
Bank Selector
Level 15
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
Figure 5-4. Stack Operation with Registers
When the bank selection bit (sptr[0]) is 0, then the register is pushed into the even bank and the bank selection
bit is set to 1. In this case, the stack level pointer is unchanged. When the bank selection bit (sptr[0]) is 1, then
the register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is
incremented by 1. Unlike the push operations of PC[19:0], any data are not written into XSTACK in the register
push operations. This is illustrated in the example figures. When a register is pushed into the stack, sptr[5:0] is
incremented by 1 (not the stack level pointer sptr[5:1]). The register pop operations are the reverse processes of
the register push operations. When a register is popped out of the stack, sptr[5:0] is decremented by 1 (not the
stack level pointer sptr[5:1]).
Hardware stack overflow/underflow happens when the MSB of the stack level pointer, sptr[5], is 1. This is obvious
from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level
pointer in a normal case.
Suppose the stack level pointer sptr[5:1] = 15 (or 01111B in binary format) and the bank selection bit sptr[0] = 1.
Here if either PC[19:0] or a register is pushed, the stack level pointer is incremented by 1. Therefore, sptr[5:1] =
16 (or 10000B in binary format) and sptr[5] = 1, which implies that the stack is overflowed. The situation is
depicted in the following.
5-4
S3CK11F/FK11F (Preliminary Spec)
HARDWARE STACK
SPTR [5:0]
5
1 0
0 1 1 1 1 1
Level 0
Level 1
Level 14
Level 15
XSTACK Odd Bank Even Bank
PUSH Register
SPTR [5:0]
PUSH PC [19:0]
5
1 0
1 0 0 0 0 0
Level 0
Level 0
Level 1
Level 1
Level 14
Level 15
SPTR [5:0]
5
1 0
1 0 0 0 0 1
PC[7:0]
Level 14
Register
Level 15 PC[19:16]
XSTACK Odd Bank Even Bank
PC[15:8]
XSTACK Odd Bank Even Bank
Figure 5-5. Stack Overflow
5-5
HARDWARE STACK
S3CK11F/FK11F (Preliminary Spec)
The first overflow happens due to a register push operation. As explained earlier, a register push operation
increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. As indicated by
sptr[5] = 1, an overflow happens. Note that this overflow doesn’t overwrite any data in the stack. On the other
hand, when PC[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow
results. Unlike the first overflow, PC[7:0] is pushed into level 0 of the even bank and the data that has been there
before the push operation is overwritten. A similar argument can be made about stack underflows. Note that any
stack operation, which causes the stack to overflow or underflow, doesn’t necessarily mean that any data in the
stack are lost, as is observed in the first example.
In SR1, there is a status flag, SF (Stack Full Flag), which is exactly the same as sptr[5]. In other words, the value
of sptr[5] can be checked by reading SF (or SR1[4]). SF is not a sticky flag in the sense that if there was a stack
overflow/underflow but any following stack access instructions clear sptr[5] to 0, then SF = 0 and programmers
cannot tell whether there was a stack overflow/underflow by reading SF. For example, if a program pushes a
register 64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. Therefore, special
attention should be paid.
Another mechanism to detect a stack overflow/underflow is through a stack exception. A stack exception
happens only when the execution of any stack access instruction results in SF = 1 (or sptr[5] = 1). Suppose a
register push operation makes SF = 1 (the SF value before the push operation doesn’t matter). Then the stack
exception due to the push operation is immediately generated and served If the stack exception enable flag (exe
of SR0) is 1. If the stack exception enable flag is 0, then the generated interrupt is not served but pending.
Sometime later when the stack exception enable flag is set to 1, the pending exception request is served even if
SF = 0. More details are available in the stack exception section.
5-6
S3CK11F/FK11F (Preliminary Spec)
6
EXCEPTIONS
EXCEPTIONS
OVERVIEW
Exceptions in CalmRISC are listed in the table below. Exception handling routines, residing at the given
addresses in the table, are invoked when the corresponding exception occurs. The start address of each
exception routine is specified by concatenation 0H (leading 4 bits of 0) and the 16-bit data in the exception vector
listed in the table. For example, the interrupt service routine for IRQ[0] starts from 0H:PM[00002H]. Note that
":"means concatenation and PM[*] stands for the 16-bit content at the address * of the program memory. Aside
from the exception due to reset release, the current PC is pushed in the stack on an exception. When an
exception is executed due to IRQ[1:0]/IEXP, the global interrupt enable flag, ie bit (SR0[1]), is set to 0, whereas
ie is set to 1 when IRET or an instruction that explicitly sets ie is executed.
Table 6-1. Exceptions
Name
Address
Priority
Description
Reset
00000H
1st
–
00001H
–
IRQ[0]
00002H
3rd
Exception due to nIRQ[0] signal. Maskable by setting ie/ie0.
IRQ[1]
00003H
4th
Exception due to nIRQ[1] signal. Maskable by setting ie/ie1.
IEXP
00004H
2nd
Exception due to stack full. Maskable by setting exe.
–
00005H
–
Reserved.
–
00006H
–
Reserved.
–
00007H
–
Reserved.
Exception due to reset release.
Reserved
NOTE: Break mode due to BKREQ has a higher priority than all the exceptions above. That is, when BKREQ is active,
even the exception due to reset release is not executed.
HARDWARE RESET
When Hardware Reset is active (the reset input signal pin nRES = 0), the control pins in the CalmRISC core are
initialized to be disabled, and SR0 and sptr (the hardware stack pointer) are initialized to be 0. Additionally, the
interrupt sensing block is cleared. When Hardware Reset is released (nRES = 1), the reset exception is executed
by loading the JP instruction in IR (Instruction Register) and 0h:0000h in PC. Therefore, when Hardware Reset is
released, the "JP {0h:PM[00000h]}" instruction is executed.
6-1
EXCEPTIONS
S3CK11F/FK11F (Preliminary Spec)
IRQ[0] EXCEPTION
When a core input signal nIRQ[0] is low, SR0[6] (ie0) is high, and SR0[1] (ie) is high, IRQ[0] exception is
generated, and this will load the CALL instruction in IR (Instruction Register) and 0h:0002h in PC. Therefore, on
an IRQ[0] exception, the "CALL {0h:PM[00002h]}" instruction is executed. When the IRQ[0] exception is
executed, SR0[1] (ie) is set to 0.
IRQ[1] EXCEPTION (LEVEL-SENSITIVE)
When a core input signal nIRQ[1] is low, SR0[7] (ie1) is high, and SR0[1] (ie) is high, IRQ[1] exception is
generated, and this will load the CALL instruction in IR (Instruction Register) and 0h:0003h in PC. Therefore, on
an IRQ[1] exception, the "CALL {0h:PM[00003h]}" instruction is executed. When the IRQ[1] exception is
executed, SR0[1] (ie) is set to 0.
HARDWARE STACK FULL EXCEPTION
A Stack Full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5]
(SF) is set to 1. If the stack exception enable bit, exe (SR0[5]), is 1, the Stack Full exception is served. One
exception to this rule is when nNMI causes a stack operation that sets sptr[5] (SF), since it has higher priority.
Handling a Stack Full exception may cause another Stack Full exception. In this case, the new exception is
ignored. On a Stack Full exception, the CALL instruction is loaded in IR (Instruction Register) and 0h:0004h in
PC. Therefore, when the Stack Full exception is activated, the "CALL {0h:PM[00004h]}" instruction is executed.
When the exception is executed, SR0[1] (ie) is set to 0.
BREAK EXCEPTION
Break exception is reserved only for an in-circuit debugger. When a core input signal, BKREQ, is high, the
CalmRISC core is halted or in the break mode, until BKREQ is deactivated. Another way to drive the CalmRISC
core into the break mode is by executing a break instruction, BREAK. When BREAK is fetched, it is decoded in
the fetch cycle (IF stage) and the CalmRISC core output signal nBKACK is generated in the second cycle
(ID/MEM stage). An in-circuit debugger generates BKREQ active by monitoring nBKACK to be active. BREAK
instruction is exactly the same as the NOP (no operation) instruction except that it does not increase the program
counter and activates nBKACK in the second cycle (or ID/MEM stage of the pipeline). There, once BREAK is
encountered in the program execution, it falls into a deadlock. BREAK instruction is reserved for in-circuit
debuggers only, so it should not be used in user programs.
6-2
S3CK11F/FK11F (Preliminary Spec)
EXCEPTIONS
EXCEPTIONS (or INTERRUPTS)
LEVEL
VECTOR
SOURCE
RESET
00000H
RESET
-
NMI
00001H
Not used
-
IVEC0
00002H
Timer 0 match/capture
H/W, S/W
Timer 0 overflow
H/W, S/W
Timer A match
H/W, S/W
Timer 1/B match
H/W, S/W
Timer 2 match
H/W, S/W
Basic Timer overflow
H/W, S/W
Internal Data ROM
H/W, S/W
SIO
H/W, S/W
Watch timer
H/W, S/W
PWM0
H/W, S/W
PWM1
H/W, S/W
A/D converter
H/W, S/W
D/A converter
H/W, S/W
Ext INT0
H/W, S/W
IVEC1
00003H
RESET (CLEAR)
Ext INT1
Ext INT2
Ext INT3
Ext INT4
H/W, S/W
Ext INT5
Ext INT6
Ext INT7
(Not used)
SF_EXCEP
00004H
Stack Full INT
H/W
NOTES:
1. RESET has the highest priority for an interrupt level, followed by SF_EXCEP, IVEC0 and IVEC1.
2. In the case of IVEC0 and IVEC1, one interrupt vector has several interrupt sources.
The priority of the sources is controlled by setting the IPR register.
3. External interrupts are triggered by rising or falling edge, depending on the corresponding control
register setting, Ext INT0 - Ext INT7 have no interrupt pending bit but have an enable bit.
4. By the system reset, Timer 0 match/capture has the highest priority in the IVEC0 level, followed by
Timer 0 overflow, and other interrupt sources.
After reset, the interrupt priority can be changed by setting of IPR registers.
5. The pending bit is cleared by hardware when CPU reads the IIR registser value.
Figure 6-1. Interrupt Structure
6-3
EXCEPTIONS
S3CK11F/FK11F (Preliminary Spec)
Clear (when write bit clear value to bit .2 - .0)
ex)
LD R0, #x5H
LD IIR0, R0
IRQ0.5 is cleared
Timer 0 match/capture
IRQ0.0
Timer 0 overflow
IRQ0.1
Timer A match
IRQ0.2
Timer 1/B match
IRQ0.3
Timer 2 match
IRQ0.4
Basic timer overflow
IRQ0.5
Internal data ROM
IRQ0.6
SIO
IRQ0.7
IMR0
Logic
IIR0
IPR0
Logic
IVEC0
IMR0
IPR0
STOP & IDLE
CPU
Release
P0INT.0
Ext INT0
P0INT.1
Ext INT1
Watch timer
IRQ1.0
PWM0
IRQ1.1
PWM1
IRQ1.2
A/D Converter
IRQ1.3
D/A Converter
IRQ1.4
IRQ1.5
IRQ1.6
IMR1
IPR1
IVEC1
IMR1
Logic
IPR1
Logic
IRQ1.7
P0INT.2
Ext INT2
P0INT.3
Ext INT3
P0INT.4
Ext INT4
IIR1
Clear (when write bit clear value to bit .2 - .0)
P0INT.5
Ext INT5
P0INT.6
ex)
LD R0, #x5H
LD IIR1, R0
IRQ1.5 is cleared
Ext INT6
P0INT.7
Ext INT7
NOTE:
The IRQ register value is cleared by H/W when the IIR register is readed by programmer in an interrupt
service routine. However, if you want to clear by S/W, then write the proper value to the IIR register like
in the above example. To clear all the bits of IRQx register at one time should be written "#08h" to the
IIRx register.
Figure 6-2. Interrupt Block Diagram
6-4
S3CK11F/FK11F (Preliminary Spec)
EXCEPTIONS
INTERRUPT MASK REGISTERS
Interrupt Mask Register0 (IMR0)
05H, R/W, Reset: 00H
.7
.6
.5
.4
.3
.2
.1
IRQ0.4
.0
IRQ0.0
IRQ0.5
IRQ0.1
IRQ0.6
IRQ0.2
IRQ0.3
IRQ0.7
Interrupt Mask Register1 (IMR1)
09H, R/W, Reset: 00H
.7
.6
.5
.4
.3
.2
.1
.0
IRQ1.0
IRQ1.4
IRQ1.1
IRQ1.5
IRQ1.2
IRQ1.6
Not used
IRQ1.3
Interrupt request enable bits:
0 = Disable interrupt request
1 = Enable interrupt request
NOTE:
If you want to change the value of the IMR register, then you first
make disable global INT by DI instruction, and change the value
of the IMR register.
Figure 6-3. Interrupt Mask Register
6-5
EXCEPTIONS
S3CK11F/FK11F (Preliminary Spec)
INTERRUPT PRIORITY REGISTER
IPR
GROUP B
IPR
GROUP A
IRQx.0
IRQx.1
IPR
GROUP C
IRQx.2 IRQx.3 IRQx.4
IRQx.5 IRQx.6 IRQx.7
Interrupt Priority Registers
(IPR0:06H,IPR1:0AH, R/W )
.7
.6
.5
.4
.3
.2
.1
.0
Group priority:
GROUP A
0 = IRQx.0 > IRQx.1
1 = IRQx.1 > IRQx.0
.7 .4 .1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Not used
B>C>A
A>B>C
B>A>C
C>A>B
C>B>A
A>C>B
Not used
GROUP B
0 = IRQx.2 > (IRQx.3, IRQx.4)
1 = (IRQx.3,IRQx.4) > IRQx.2
SUBGROUP B
0 = IRQx.3 > IRQx.4
1 = IRQx.4 > IRQx.3
GROUP C
0 = IRQx.5 > (IRQx.6, IRQx.7)
1 = (IRQx.6, IRQx.7) > IRQx.5
SUBGROUP C
0 = IRQx.6 > IRQx.7
1 = IRQx.7 > IRQx.6
NOTE:
If you want to change the value of the IPR register, then you first
make disable global INT by DI instruction, and change the value
of the IPR register. After reset, IPR register is unknown status,
so user must set the IPR register with proper value.
Figure 6-4. Interrupt Priority Register
6-6
S3CK11F/FK11F (Preliminary Spec)
F
EXCEPTIONS
PROGRAMMING TIP — Interrupt Programming Tip 1
Jumped from vector 2
LTE05
LTE03
LTE01
PUSH
PUSH
LD
CP
JR
CP
JR
CP
JP
JP
CP
JP
JP
CP
JR
CP
JP
JP
CP
JP
JP
SR1
R0
R0, IIR00
R0, #03h
ULE, LTE03
R0, #05h
ULE, LTE05
R0, #06h
EQ, IRQ6_srv
T, IRQ7_srv
R0, #04
EQ, IRQ4_srv
T, IRQ5_srv
R0, #01
ULE, LTE01
R0, #02
EQ, IRQ2_srv
T, IRQ3_srv
R0, #00h
EQ, IRQ0_srv
T, IRQ1_srv
IRQ0_srv
; → service for IRQ0
•
POP
POP
IRET
R0
SR1
; → service for IRQ1
IRQ1_srv
•
•
POP
POP
IRET
R0
SR1
•
•
; → service for IRQ7
IRQ7_srv
•
•
POP
POP
IRET
R0
SR1
NOTE
If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and
popped in the interrupt service routine.
6-7
S3CK11F/FK11F (Preliminary Spec)
7
INSTRUCTION SET
INSTRUCTION SET
OVERVIEW
GLOSSARY
This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical
order. The following notations are used for the description.
Table 7-1. Instruction Notation Conventions
Notation
<opN>
Interpretation
Operand N. N can be omitted if there is only one operand. Typically, <op1> is the
destination (and source) operand and <op2> is a source operand.
GPR
General Purpose Register
SPR
Special Purpose Register (IDL0, IDL1, IDH, SR0, ILX, ILH, ILL, SR1)
adr:N
N-bit address specifier
@idm
Content of memory location pointed by ID0 or ID1
(adr:N)
Content of memory location specified by adr:N
cc:4
4-bit condition code. Table 7-6 describes cc:4.
imm:N
N-bit immediate number
&
Bit-wise AND
|
Bit-wise OR
~
Bit-wise NOT
^
Bit-wise XOR
N**M
Mth power of N
(N)M
M-based number N
As additional note, only the affected flags are described in the tables in this section. That is, if a flag is not
affected by an operation, it is NOT specified.
7-1
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET MAP
Table 7-2.Overall Instruction Set Map
IR
[12:10]000
001
010
011
100
101
110
111
ADD GPR,
#imm:8
SUB
GPR,
#imm:8
CP GPR,
#imm8
LD GPR,
#imm:8
TM GPR,
#imm:8
AND
GPR,
#imm:8
OR GPR,
#imm:8
XOR
GPR,
#imm:8
001 xxxxxx
ADD GPR,
@idm
SUB
GPR,
@idm
CP GPR,
@idm
LD GPR,
@idm
LD @idm,
GPR
AND
GPR,
@idm
OR GPR,
@idm
XOR
GPR,
@idm
010 xxxxxx
ADD GPR,
adr:8
SUB
GPR,
adr:8
CP GPR,
adr:8
LD GPR,
adr:8
BITT adr:8.bs
BITS adr:8.bs
011 xxxxxx
ADC GPR,
adr:8
SBC
GPR,
adr:8
CPC
GPR,
adr:8
LD adr:8,
GPR
BITR adr:8.bs
BITC adr:8.bs
100 000000
ADD GPR,
GPR
SUB
GPR,
GPR
CP GPR,
GPR
BMS/
BMC
100 000001
ADC GPR,
GPR
SBC
GPR,
GPR
CPC
GPR,
GPR
invalid
100 000010
invalid
invalid
invalid
invalid
100 000011
AND GPR,
GPR
OR GPR,
GPR
XOR
GPR,
GPR
invalid
100 00010x
SLA/SL/
RLC/RL/
SRA/SR/
RRC/RR/
GPR
INC/INCC
/DEC/
DECC/
COM/
COM2/
COMC
GPR
invalid
invalid
100 00011x
LD SPR,
GPR
LD GPR,
SPR
SWAP
GPR,
SPR
LD
TBH/TBL,
GPR
PUSH SPR POP SPR
invalid
invalid
LD GPR,
GPR
LD GPR,
TBH/TBL
[15:13,7:2]
000 xxxxxx
100 00100x
100 001010
7-2
PUSH
GPR
POP GPR
LD SPR0,
#imm:8
AND
GPR,
adr:8
OR GPR,
adr:8
XOR
GPR,
adr:8
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
Table 7-2. Overall Instruction Set Map (Continued)
IR
[12:10]000
001
010
011
100
101
110
111
100 001011
POP
invalid
LDC
invalid
LD SPR0,
#imm:8
AND
GPR,
adr:8
OR GPR,
adr:8
XOR
GPR,
adr:8
100 00110x
RET/LRET/
IRET/NOP/
BREAK
invalid
invalid
invalid
100 00111x
invalid
invalid
invalid
invalid
100 01xxxx
LD
GPR:bank,
GPR:bank
AND
SR0,
#imm:8
OR SR0,
#imm:8
BANK
#imm:2
100 100000
invalid
invalid
invalid
invalid
100 110011
100 1101xx
LCALL cc:4, imm:20 (2-word instruction)
100 1110xx
LLNK cc:4, imm:20 (2-word instruction)
100 1111xx
LJP cc:4, imm:20 (2-word instruction)
[15:10]
101 xxx
JR cc:4, imm:9
110 0xx
CALLS imm:12
110 1xx
LNKS imm:12
111 xxx
CLD GPR, imm:8 / CLD imm:8, GPR / JNZD GPR, imm:8 / SYS #imm:8 / COP #imm:12
NOTE:
"invalid" - invalid instruction.
7-3
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
Table 7-3. Instruction Encoding
Instruction
ADD GPR, #imm:8
15
14
000
13
12
11
000
SUB GPR, #imm:8
001
CP GPR, #imm:8
010
LD GPR, #imm:8
011
TM GPR, #imm:8
100
AND GPR, #imm:8
101
OR GPR, #imm:8
110
XOR GPR, #imm:8
111
ADD GPR, @idm
001
000
SUB GPR, @idm
001
CP GPR, @idm
010
LD GPR, @idm
011
LD @idm, GPR
100
AND GPR, @idm
101
OR GPR, @idm
110
XOR GPR, @idm
111
ADD GPR, adr:8
010
000
SUB GPR, adr:8
001
CP GPR, adr:8
010
LD GPR, adr:8
011
BITT adr:8.bs
10
BITS adr:8.bs
11
ADC GPR, adr:8
011
000
SBC GPR, adr:8
001
CPC GPR, adr:8
010
LD adr:8, GPR
011
BITR adr:8.bs
10
BITC adr:8.bs
11
7-4
10
9
8
7
6
5
GPR
GPR
GPR
4
3
bs
1
imm[7:0]
idx
mod
offset[4:0]
adr[7:0]
bs
GPR
2
adr[7:0]
0
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
Table 7-3. Instruction Encoding (Continued)
Instruction
15
ADD GPRd, GPRs
14
100
13
12
11
10
000
9
8
GPRd
7
6
5
4
3
2
000000
1
0
GPRs
SUB GPRd, GPRs
001
CP GPRd, GPRs
010
BMS/BMC
011
ADC GPRd, GPRs
000
SBC GPRd, GPRs
001
CPC GPRd, GPRs
010
invalid
011
invalid
ddd
000010
AND GPRd, GPRs
000
000011
OR GPRd, GPRs
001
XOR GPRd, GPRs
010
invalid
011
ALUop1
000
GPR
ALUop2
001
GPR
ALUop2
010–011
xx
xxx
LD SPR, GPR
000
GPR
LD GPR, SPR
001
GPR
SPR
SWAP GPR, SPR
010
GPR
SPR
LD TBL, GPR
011
GPR
invalid
000001
00010
ALUop1
00011
LD TBH, GPR
x
0
x
x
1
x
PUSH SPR
000
xx
POP SPR
001
xx
SPR
010–011
xx
xxx
PUSH GPR
000
GPR
POP GPR
001
GPR
GPR
LD GPRd, GPRs
010
GPRd
GPRs
LD GPR, TBL
011
GPR
invalid
00100
SPR
001010
LD GPR, TBH
POP
000
LDC @IL
010
LDC @IL+
Invalid
001, 011
xx
SPR
GPR
0
x
1
x
001011
xx
0
x
1
x
xx
NOTE: "x" means not applicable.
7-5
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
Table 7-3. Instruction Encoding (Concluded)
Instruction
MODop1
15-13
12
100
11
10
9
8
000
xx
Invalid
001–011
xx
Invalid
000
xx
AND SR0, #imm:8
001
imm[7:6]
OR SR0, #imm:8
010
imm[7:6]
BANK #imm:2
011
xx
7
6
5
4
3
2
00110
1
MODop1
0
2nd word
–
xxx
01
xxxxxx
imm[5:0]
x
imm
xxx
[1:0]
Invalid
0
xxxx
LCALL cc, imm:20
10000000–11001111
cc
1101
LLNK cc, imm:20
1110
LJP cc, imm:20
1111
LD SPR0, #imm:8
00
SPR0
IMM[7:0]
AND GPR, adr:8
01
GPR
ADR[7:0]
OR GPR, adr:8
10
XOR GPR, adr:8
11
JR cc, imm:9
1
imm[19:16]
101
cc
imm
imm[7:0]
[8]
CALLS imm:12
110
LNKS imm:12
CLD GPR, imm:8
0
imm[11:0]
1
00
GPR
CLD imm:8, GPR
01
GPR
JNZD GPR, imm:8
10
GPR
SYS #imm:8
11
xx
COP #imm:12
111
0
1
imm[7:0]
imm[11:0]
NOTES:
1. "x" means not applicable.
2. There are several MODop1 codes that can be used, as described in table 7-9.
3. The operand 1(GPR) of the instruction JNZD is Bank 3's register.
7-6
imm[15:0]
–
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
Table 7-4. Index Code Information ("idx")
Symbol
Code
Description
ID0
0
Index 0 IDH:IDL0
ID1
1
Index 1 IDH:IDL1
Table 7-5. Index Modification Code Information ("mod")
Symbol
Code
Function
@IDx + offset:5
00
DM[IDx], IDx ← IDx + offset
@[IDx - offset:5]
01
DM[IDx + (2's complement of offset:5)],
IDx ← IDx + (2's complement of offset:5)
@[IDx + offset:5]!
10
DM[IDx + offset], IDx ← IDx
@[IDx - offset:5]!
11
DM[IDx + (2's complement of offset:5)], IDx ← IDx
NOTE: Carry from IDL is propagated to IDH. In case of @[IDx - offset:5] or @[IDx - offset:5]!, the assembler should convert
offset:5 to the 2's complement format to fill the operand field (offset[4:0]).
Furthermore, @[IDx - 0] and @[IDx - 0]! are converted to @[IDx + 0] and @[IDx + 0]!, respectively.
Table 7-6. Condition Code Information ("cc")
Symbol (cc:4)
Code
Function
Blank
0000
always
NC or ULT
0001
C = 0, unsigned less than
C or UGE
0010
C = 1, unsigned greater than or equal to
Z or EQ
0011
Z = 1, equal to
NZ or NE
0100
Z = 0, not equal to
OV
0101
V = 1, overflow - signed value
ULE
0110
~C | Z, unsigned less than or equal to
UGT
0111
C & ~Z, unsigned greater than
ZP
1000
N = 0, signed zero or positive
MI
1001
N = 1, signed negative
PL
1010
~N & ~Z, signed positive
ZN
1011
Z | N, signed zero or negative
SF
1100
Stack Full
EC0-EC2
1101-1111
EC[0] = 1/EC[1] = 1/EC[2] = 1
NOTE: EC[2:0] is an external input (CalmRISC core's point of view) and used as a condition.
7-7
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
Table 7-7. "ALUop1" Code Information
Symbol
Code
Function
SLA
000
arithmetic shift left
SL
001
shift left
RLC
010
rotate left with carry
RL
011
rotate left
SRA
100
arithmetic shift right
SR
101
shift right
RRC
110
rotate right with carry
RR
111
rotate right
Table 7-8. "ALUop2" Code Information
Symbol
Code
Function
INC
000
increment
INCC
001
increment with carry
DEC
010
decrement
DECC
011
decrement with carry
COM
100
1's complement
COM2
101
2's complement
COMC
110
1's complement with carry
111
reserved
–
Table 7-9. "MODop1" Code Information
Symbol
Code
Function
LRET
000
return by IL
RET
001
return by HS
IRET
010
return from interrupt (by HS)
NOP
011
no operation
BREAK
100
reserved for debugger use only
–
101
reserved
–
110
reserved
–
111
reserved
7-8
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
QUICK REFERENCE
Operation
op1
op2
AND
GPR
adr:8
Flag
# of word / cycle
op1 ← op1 & op2
z,n
1W1C
#imm:8
op1 ← op1 | op2
z,n
XOR
GPR
op1 ← op1 ^ op2
z,n
ADD
@idm
op1 ← op1 + op2
c,z,v,n
SUB
op1 ← op1 + ~op2 + 1
c,z,v,n
CP
op1 + ~op2 + 1
c,z,v,n
GPR
op1 ← op1 + op2 + c
c,z,v,n
adr:8
op1 ← op1 + ~op2 + c
c,z,v,n
op1 + ~op2 + c
c,z,v,n
OR
ADC
GPR
SBC
CPC
TM
op1 & op2
z,n
adr:8.bs op1 ← (op2[bit] ← 1)
z
BITR
op1 ← (op2[bit] ← 0)
z
BITC
op1 ← ~(op2[bit])
z
BITT
z ← ~(op2[bit])
z
BITS
BMS/BMC
PUSH
GPR
R3
#imm:8
Function
–
–
TF ← 1 / 0
–
GPR
–
HS[sptr] ← GPR, (sptr ← sptr + 1)
–
GPR ← HS[sptr - 1], (sptr ← sptr - 1)
POP
PUSH
SPR
–
HS[sptr] ← SPR, (sptr ← sptr + 1)
1W1C
(1W2C
When TF =1)
1W1C
z,n
–
SPR ← HS[sptr - 1], (sptr ← sptr - 1)
POP
POP
–
–
sptr ← sptr – 2
SLA
GPR
–
c ← op1[7], op1 ← {op1[6:0], 0}
c,z,v,n
SL
c ← op1[7], op1 ← {op1[6:0], 0}
c,z,n
RLC
c ← op1[7], op1 ← {op1[6:0], c}
c,z,n
RL
c ← op[7], op1 ← {op1[6:0], op1[7]}
c,z,n
SRA
c ← op[0], op1 ← {op1[7],op1[7:1]}
c,z,n
SR
c ← op1[0], op1 ← {0, op1[7:1]}
c,z,n
RRC
c ← op1[0], op1 ← {c, op1[7:1]}
c,z,n
RR
c ← op1[0], op1 ← {op1[0], op1[7:1]}
c,z,n
INC
op1 ← op1 + 1
c,z,v,n
INCC
op1 ← op1 + c
c,z,v,n
DEC
op1 ← op1 + 0FFh
c,z,v,n
DECC
op1 ← op1 + 0FFh + c
c,z,v,n
COM
op1 ← ~op1
COM2
op1 ← ~op1 + 1
c,z,v,n
COMC
op1 ← ~op1 + c
c,z,v,n
–
z,n
7-9
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
QUICK REFERENCE (Continued)
Operation
op1
op2
Function
Flag
# of word / cycle
LD
GPR
:bank
GPR
:bank
op1 ← op2
z,n
1W1C
LD
SPR0
#imm:8
op1 ← op2
–
LD
GPR
LD
SPR
TBH/TBL
GPR
op1 ← op2
–
LD
adr:8
GPR
op1 ← op2
–
LD
@idm
GPR
op1 ← op2
–
LDC
@IL
@IL+
–
(TBH:TBL) ← PM[(ILX:ILH:ILL)],
ILL++ if @IL+
–
1W2C
AND
OR
SR0
#imm:8
SR0 ← SR0 & op2
SR0 ← SR0 | op2
–
1W1C
BANK
#imm:2
–
SR0[4:3] ← op2
–
SWAP
GPR
SPR
op1 ← op2, op2 ← op1 (excluding
SR0/SR1)
–
LCALL cc
imm:20
–
If branch taken, push XSTACK,
HS[15:0] ← {PC[15:12],PC[11:0] + 2} and
PC ← op1
else PC[11:0] ← PC[11:0] + 2
–
LLNK cc
imm:20
–
If branch taken, IL[19:0] ← {PC[19:12],
PC[11:0] + 2} and PC ← op1
else PC[11:0] ← PC[11:0] + 2
–
CALLS
imm:12
–
push XSTACK, HS[15:0] ← {PC[15:12],
PC[11:0] + 1} and PC[11:0] ← op1
–
LNKS
imm:12
–
IL[19:0] ← {PC[19:12], PC[11:0] + 1} and
PC[11:0] ← op1
–
JNZD
Rn
imm:8
if (Rn == 0) PC ← PC[delay slot] - 2's
complement of imm:8, Rn-else PC ← PC[delay slot]++, Rn--
–
LJP cc
imm:20
–
If branch taken, PC ← op1
else PC[11:0] < PC[11:0] + 2
–
2W2C
JR cc
imm:9
–
If branch taken, PC[11:0] ← PC[11:0] + op1
else PC[11:0] ← PC[11:0] + 1
–
1W2C
GPR
op1 ← op2
SPR
adr:8
@idm
#imm:8
TBH/TBL
z,n
2W2C
1W2C
NOTE: op1 - operand1, op2 - operand2, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word 2-Cycle instruction, 2W2C 2-Word 2-Cycle instruction. The Rn of instruction JNZD is Bank 3's GPR.
7-10
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
QUICK REFERENCE (Concluded)
Operation
LRET
op1
op2
–
–
Function
PC ← IL[19:0]
Flag
# of word / cycle
–
1W2C
RET
PC ← HS[sptr - 2], (sptr ← sptr - 2)
1W2C
IRET
PC ← HS[sptr - 2], (sptr ← sptr - 2)
1W2C
NOP
no operation
1W1C
BREAK
no operation and hold PC
1W1C
SYS
#imm:8
–
no operation but generates SYSCP[7:0] and
nSYSID
–
CLD
imm:8
GPR
op1 ← op2, generates SYSCP[7:0], nCLDID,
and CLDWR
–
CLD
GPR
imm:8
op1 ← op2, generates SYSCP[7:0], nCLDID,
and CLDWR
z,n
COP
#imm:12
–
generates SYSCP[11:0] and nCOPID
1W1C
–
NOTES:
1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word
2-Cycle instruction
2. Pseudo instructions
— SCF/RCF
Carry flag set or reset instruction
— STOP/IDLE
MCU power saving instructions
— EI/DI
Exception enable and disable instructions
— JP/LNK/CALL
If JR/LNKS/CALLS commands (1 word instructions) can access the target address, there is no conditional code
in the case of CALL/LNK, and the JP/LNK/CALL commands are assembled to JR/LNKS/CALLS in linking time, or
else the JP/LNK/CALL commands are assembled to LJP/LLNK/LCALL (2 word instructions) instructions.
7-11
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION GROUP SUMMARY
ALU INSTRUCTIONS
“ALU instructions” refer to the operations that use ALU to generate results. ALU instructions update the values in
Status Register 1 (SR1), namely carry (C), zero (Z), overflow (V), and negative (N), depending on the operation
type and the result.
ALUop GPR, adr:8
Performs an ALU operation on the value in GPR and the value in DM[adr:8] and stores the result into GPR.
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPR+(not DM[adr:8])+1 is performed.
adr:8 is the offset in a specific data memory page.
The data memory page is 0 or the value of IDH (Index of Data Memory Higher Byte Register), depending on the
value of eid in Status Register 0 (SR0).
Operation
GPR ← GPR ALUop DM[00h:adr:8] if eid = 0
GPR ← GPR ALUop DM[IDH:adr8] if eid = 1
Note that this is an 7-bit operation.
Example
ADD R0, 80h
// Assume eid = 1 and IDH = 01H
// R0 ← R0 + DM[0180h]
ALUop GPR, #imm:8
Stores the result of an ALU operation on GPR and an 7-bit immediate value into GPR.
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPR+(not #imm:8)+1 is performed.
#imm:8 is an 7-bit immediate value.
Operation
GPR ← GPR ALUop #imm:8
Example
ADD R0, #7Ah
7-12
// R0 ← R0 + 7Ah
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
ALUop GPRd, GPRs
Store the result of ALUop on GPRs and GPRd into GPRd.
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPRd + (not GPRs) + 1 is performed.
GPRs and GPRd need not be distinct.
Operation
GPRd ← GPRd ALUop GPRs
GPRd - GPRs when ALUop = CP (comparison only)
Example
ADD R0, R1
// R0 ← R0 + R1
ALUop GPR, @idm
Performs ALUop on the value in GPR and DM[ID] and stores the result into GPR. Index register ID is IDH:IDL
(IDH:IDL0 or IDH:IDL1).
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPR+(not DM[idm])+1 is performed.
idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]!
(IDx = ID0 or ID1)
Operation
GPR - DM[idm] when ALUop = CP (comparison only)
GPR ← GPR ALUop DM[IDx], IDx ← IDx + offset:5 when idm = IDx + offset:5
GPR ← GPR ALUop DM[IDx - offset:5], IDx ← IDx - offset:5 when idm = [IDx - offset:5]
GPR ← GPR ALUop DM[IDx + offset:5] when idm = [IDx + offset:5]!
GPR ← GPR ALUop DM[IDx - offset:5] when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH.
Example
ADD R0, @ID0+2
ADD R0, @[ID0-2]
ADD R0, @[ID1+2]!
ADD R0, @[ID1-2]!
// assume ID0 = 02FFh
// R0 ← R0 + DM[02FFh], IDH ← 03h and IDL0 ← 01h
// assume ID0 = 0201h
// R0 ← R0 + DM[01FFh], IDH ← 01h and IDL0 ← FFh
// assume ID1 = 02FFh
// R0 ← R0 + DM[0301], IDH ← 02h and IDL1 ← FFh
// assume ID1 = 0200h
// R0 ← R0 + DM[01FEh], IDH ← 02h and IDL1 ← 00h
7-13
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
ALUopc GPRd, GPRs
Performs ALUop with carry on GPRd and GPRs and stores the result into GPRd.
ALUopc = ADC, SBC, CPC
GPRd and GPRs need not be distinct.
Operation
GPRd ← GPRd + GPRs + C when ALUopc = ADC
GPRd ← GPRd + (not GPRs) + C when ALUopc = SBC
GPRd + (not GPRs) + C when ALUopc = CPC (comparison only)
Example
ADD R0, R2
ADC R1, R3
// assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers.
// to add two 16-bit numbers, use ADD and ADC.
SUB R0, R2
SBC R1, R3
// assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers.
// to subtract two 16-bit numbers, use SUB and SBC.
CP R0, R2
CPC R1, R3
// assume both R1:R0 and R3:R2 are 16-bit unsigned numbers.
// to compare two 16-bit unsigned numbers, use CP and CPC.
ALUopc GPR, adr:8
Performs ALUop with carry on GPR and DM[adr:8].
Operation
GPR ← GPR + DM[adr:8] + C when ALUopc = ADC
GPR ← GPR + (not DM[adr:8]) + C when ALUopc = SBC
GPR + (not DM[adr:8]) + C when ALUopc = CPC (comparison only)
CPLop GPR (Complement Operations)
CPLop = COM, COM2, COMC
Operation
COM GPR
COM2 GPR
COMC GPR
not GPR (logical complement)
not GPR + 1 (2's complement of GPR)
not GPR + C (logical complement of GPR with carry)
Example
COM2 R0
COMC R1
7-14
// assume R1:R0 is a 16-bit signed number.
// COM2 and COMC can be used to get the 2's complement of it.
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
IncDec GPR (Increment/Decrement Operations)
IncDec = INC, INCC, DEC, DECC
Operation
INC GPR
INCC GPR
Increase GPR, i.e., GPR ← GPR + 1
Increase GPR if carry = 1, i.e., GPR ← GPR + C
DEC GPR
DECC GPR
Decrease GPR, i.e., GPR ← GPR + FFh
Decrease GPR if carry = 0, i.e., GPR ← GPR + FFh + C
Example
INC R0
INCC R1
// assume R1:R0 is a 16-bit number
// to increase R1:R0, use INC and INCC.
DEC R0
DECC R1
// assume R1:R0 is a 16-bit number
// to decrease R1:R0, use DEC and DECC.
7-15
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
SHIFT/ROTATE INSTRUCTIONS
Shift (Rotate) instructions shift (rotate) the given operand by 1 bit. Depending on the operation performed, a
number of Status Register 1 (SR1) bits, namely Carry (C), Zero (Z), Overflow (V), and Negative (N), are set.
SL GPR
Operation
7
0
C
0
GPR
Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
SLA GPR
Operation
7
0
C
0
GPR
Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) will be 1 if the MSB of the result is different from C. Z will be 1 if the result is 0.
RL GPR
Operation
7
0
C
GPR
Carry (C) is the MSB of GPR before rotating. Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
RLC GPR
Operation
7
0
GPR
C
Carry (C) is the MSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
7-16
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
SR GPR
Operation
7
0
0
C
GPR
Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
SRA GPR
Operation
7
0
C
GPR
Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) is not affected. Z will be 1 if the result is 0.
RR GPR
Operation
7
0
C
GPR
Carry (C) is the LSB of GPR before rotating. Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
RRC GPR
Operation
7
0
GPR
C
Carry (C) is the LSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
7-17
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LOAD INSTRUCTIONS
Load instructions transfer data from data memory to a register or from a register to data memory, or assigns an
immediate value into a register. As a side effect, a load instruction placing a value into a register sets the Zero
(Z) and Negative (N) bits in Status Register 1 (SR1), if the placed data is 00h and the MSB of the data is 1,
respectively.
LD GPR, adr:8
Loads the value of DM[adr:8] into GPR. Adr:8 is offset in the page specified by the value of eid in Status Register
0 (SR0).
Operation
GPR ← DM[00h:adr:8] if eid = 0
GPR ← DM[IDH:adr:8] if eid = 1
Note that this is an 7-bit operation.
Example
LD R0, 80h
// assume eid = 1 and IDH= 01H
// R0 ← DM[0180h]
LD GPR, @idm
Loads a value from the data memory location specified by @idm into GPR.
idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]!
(IDx = ID0 or ID1)
Operation
GPR ← DM[IDx], IDx ← IDx + offset:5 when idm = IDx + offset:5
GPR ← DM[IDx - offset:5], IDx ← IDx - offset:5 when idm = [IDx - offset:5]
GPR ← DM[IDx + offset:5] when idm = [IDx + offset:5]!
GPR ← DM[IDx - offset:5] when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH.
Example
LD R0, @[ID0 + 03h]!
7-18
// assume IDH:IDL0 = 0270h
// R0 ← DM[0273h], IDH:IDL0 ← 0270h
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LD REG, #imm:8
Loads an 7-bit immediate value into REG. REG can be either GPR or an SPR0 group register - IDH (Index of
Data Memory Higher Byte Register), IDL0 (Index of Data Memory Lower Byte Register)/ IDL1, and Status
Register 0 (SR0). #imm:8 is an 7-bit immediate value.
Operation
REG ← #imm:8
Example
LD R0 #7Ah
LD IDH, #03h
// R0 ← 7Ah
// IDH ← 03h
LD GPR:bs:2, GPR:bs:2
Loads a value of a register from a specified bank into another register in a specified bank.
Example
LD R0:1, R2:3
// R0 in bank 1, R2 in bank 3
LD GPR, TBH/TBL
Loads the value of TBH or TBL into GPR. TBH and TBL are 7-bit long registers used exclusively for LDC
instructions that access program memory. Therefore, after an LDC instruction, LD GPR, TBH/TBL instruction will
usually move the data into GPRs, to be used for other operations.
Operation
GPR ← TBH (or TBL)
Example
LDC @IL
LD R0, TBH
LD R1, TBL
// gets a program memory item residing @ ILX:ILH:ILL
LD TBH/TBL, GPR
Loads the value of GPR into TBH or TBL. These instructions are used in pair in interrupt service routines to save
and restore the values in TBH/TBL as needed.
Operation
TBH (or TBL) ← GPR
LD GPR, SPR
Loads the value of SPR into GPR.
Operation
GPR ← SPR
Example
LD R0, IDH
// R0 ← IDH
7-19
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LD SPR, GPR
Loads the value of GPR into SPR.
Operation
SPR ← GPR
Example
LD IDH, R0
// IDH ← R0
LD adr:8, GPR
Stores the value of GPR into data memory (DM). adr:8 is offset in the page specified by the value of eid in
Status Register 0 (SR0).
Operation
DM[00h:adr:8] ← GPR if eid = 0
DM[IDH:adr:8] ← GPR if eid = 1
Note that this is an 7-bit operation.
Example
LD 7Ah, R0
// assume eid = 1 and IDH = 02h.
// DM[027Ah] ← R0
LD @idm, GPR
Loads a value into the data memory location specified by @idm from GPR.
idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]!
(IDx = ID0 or ID1)
Operation
DM[IDx] ← GPR, IDx ← IDx + offset:5 when idm = IDx + offset:5
DM[IDx - offset:5] ← GPR, IDx ← IDx - offset:5 when idm = [IDx - offset:5]
DM[IDx + offset:5] ← GPR when idm = [IDx + offset:5]!
DM[IDx - offset:5] ← GPR when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH.
Example
LD @[ID0 + 03h]!, R0
7-20
// assume IDH:IDL0 = 0170h
// DM[0173h] ← R0, IDH:IDL0 ← 0170h
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
BRANCH INSTRUCTIONS
Branch instructions can be categorized into jump instruction, link instruction, and call instruction. A jump
instruction does not save the current PC, whereas a call instruction saves ("pushes") the current PC onto the
stack and a link instruction saves the PC in the link register IL. Status registers are not affected. Each instruction
type has a 2-word format that supports a 20-bit long jump.
JR cc:4, imm:9
imm:9 is a signed number (2's complement), an offset to be added to the current PC to compute the target
(PC[19:12]:(PC[11:0] + imm:9)).
Operation
PC[11:0] ← PC[11:0] + imm:9
PC[11:0] ← PC[11:0] + 1
if branch taken (i.e., cc:4 resolves to be true)
otherwise
Example
L18411:
JR Z, 107h
// assume current PC = 18411h.
// next PC is 18518 (18411h + 107h) if Zero (Z) bit is set.
LJP cc:4, imm:20
Jumps to the program address specified by imm:20. If program size is less than 64K word, PC[19:16] is not
affected.
Operation
PC[15:0] ← imm[15:0] if branch taken and program size is less than 64K word
PC[19:0] ← imm[19:0] if branch taken and program size is equal to 64K word or more
PC [11:0] ← PC[11:0] + 1 otherwise
Example
L18411:
LJP Z, 10107h
// assume current PC = 18411h.
// next instruction's PC is 10107h If Zero (Z) bit is set
JNZD Rn, imm:8
Jumps to the program address specified by imm:8 if the value of the bank 3 register Rn is not zero. JNZD
performs only backward jumps, with the value of Rn automatically decreased. There is one delay slot following
the JNZD instruction that is always executed, regardless of whether JNZD is taken or not.
Operation
If (Rn == 0) PC ← PC[delay slot] (-) 2's complement of imm:8, Rn ← Rn - 1
else PC ← PC[delay slot] + 1, Rn ← Rn - 1.
7-21
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
Example
LOOP_A:
// start of loop body
•
•
•
JNZD R0, LOOP_A
ADD R1, #2
// jump back to LOOP_A if R0 is not zero
// delay slot, always executed (you must use one cycle instruction only)
CALLS imm:12
Saves the current PC on the stack ("pushes" PC) and jumps to the program address specified by imm:12. The
current page number PC[19:12] is not changed. Since this is a 1-word instruction, the return address pushed onto
the stack is (PC + 1). If nP64KW is low when PC is saved, PC[19:16] is not saved in the stack.
Operation
HS[sptr][15:0] ← current PC + 1 and sptr ← sptr + 2 (push stack)
HS[sptr][19:0] ← current PC + 1 and sptr ← sptr + 2 (push stack)
PC[11:0] ← imm:12
if nP64KW = 0
if nP64KW = 1
Example
L18411:
CALLS 107h
// assume current PC = 18411h.
// call the subroutine at 18107h, with the current PC pushed
// onto the stack (HS ← 18412h) if nP64KW = 1.
LCALL cc:4, imm:20
Saves the current PC onto the stack (pushes PC) and jumps to the program address specified by imm:20. Since
this is a 2-word instruction, the return address saved in the stack is (PC + 2). If nP64KW, a core input signal is
low when PC is saved, 0000111111PC[19:16] is not saved in the stack and PC[19:16] is not set to imm[19:16].
Operation
HS[sptr][15:0] ← current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 0
HS[sptr][19:0] ← current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 1
PC[15:0] ← imm[15:0] if branch taken and nP64KW = 0
PC[19:0] ← imm[19:0] if branch taken and nP64KW = 1
PC[11:0] ← PC[11:0] + 2 otherwise
Example
L18411:
LCALL NZ, 10107h
7-22
// assume current PC = 18411h.
// call the subroutine at 10107h with the current PC pushed
// onto the stack (HS ← 18413h)
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LNKS imm:12
Saves the current PC in IL and jumps to the program address specified by imm:12. The current page number
PC[19:12] is not changed. Since this is a 1-word instruction, the return address saved in IL is (PC + 1). If the
program size is less than 64K word when PC is saved, PC[19:16] is not saved in ILX.
Operation
IL[15:0] ← current PC + 1
IL[19:0] ← current PC + 1
PC[11:0] ← imm:12
if program size is less than 64K word
if program size is equal to 64K word or more
Example
L18411:
LNKS 107h
// assume current PC = 18411h.
// call the subroutine at 18107h, with the current PC saved
// in IL (IL[19:0] ← 18412h) if program size is 64K word or more.
LLNK cc:4, imm:20
Saves the current PC in IL and jumps to the program address specified by imm:20. Since this is a 2-word
instruction, the return address saved in IL is (PC + 2). If the program size is less than 64K word when PC is
saved, PC[19:16] is not saved in ILX.
Operation
IL[15:0] ← current PC + 2
IL[19:0] ← current PC + 2
PC[15:0] ← imm[15:0]
PC[19:0] ← imm[19:0]
PC[11:0] ← PC[11:0] + 2
if branch taken and program size is less than 64K word
if branch taken and program size is 64K word or more
if branch taken and program size is less than 64K word
if branch taken and program size is 64K word or more
otherwise
Example
L18411:
LLNK NZ, 10107h
// assume current PC = 18411h.
// call the subroutine at 10107h with the current PC saved
// in IL (IL[19:0] ← 18413h) if program size is 64K word or more
RET, IRET
Returns from the current subroutine. IRET sets ie (SR0[1]) in addition. If the program size is less than 64K word,
PC[19:16] is not loaded from HS[19:16].
Operation
PC[15:0] ← HS[sptr - 2] and sptr ← sptr - 2 (pop stack) if program size is less than 64K word
PC[19:0] ← HS[sptr - 2] and sptr ← sptr - 2 (pop stack) if program size is 64K word or more
Example
RET
// assume sptr = 3h and HS[1] = 18407h.
// the next PC will be 18407h and sptr is set to 1h
7-23
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LRET
Returns from the current subroutine, using the link register IL. If the program size is less than 64K word,
PC[19:16] is not loaded from ILX.
Operation
PC[15:0] ← IL[15:0]
PC[19:0] ← IL[19:0]
if program size is less than 64K word
if program size is 64K word or more
Example
LRET
// assume IL = 18407h.
// the next instruction to execute is at PC = 18407h
// if program size is 64K word or more
JP/LNK/CALL
JP/LNK/CALL instructions are pseudo instructions. If JR/LNKS/CALLS commands (1 word instructions) can
access the target address, there is no conditional code in the case of CALL/LNK and the JP/LNK/CALL
commands are assembled to JR/LNKS/CALLS in linking time or else the JP/LNK/CALL commands are
assembled to LJP/LLNK/LCALL (2 word instructions) instructions.
7-24
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
BIT MANIPULATION INSTRUCTIONS
BITop adr:8.bs
Performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result
into R3 of current GPR bank or back into memory depending on the value of TF bit.
BITop = BITS, BITR, BITC, BITT
BITS: bit set
BITR: bit reset
BITC: bit complement
BITT: bit test (R3 is not touched in this case)
bs: bit location specifier, 0 - 7.
Operation
R3 ← DM[00h:adr:8] BITop bs if eid = 0
R3 ← DM[IDH:adr:8] BITop bs if eid = 1 (no register transfer for BITT)
Set the Zero (Z) bit if the result is 0.
Example
BITS 25h.3
BITT 25h.3
// assume eid = 0. set bit 3 of DM[00h:25h] and store the result in R3.
// check bit 3 of DM[00h:25h] if eid = 0.
BMC/BMS
Clears or sets the TF bit, which is used to determine the destination of BITop instructions. When TF bit is clear,
the result of BITop instructions will be stored into R3 (fixed); if the TF bit is set, the result will be written back to
memory.
Operation
TF ← 0
TF ← 1
(BMC)
(BMS)
TM GPR, #imm:8
Performs AND operation on GPR and imm:8 and sets the Zero (Z) and Negative (N) bits. No change in GPR.
Operation
Z, N flag ← GPR & #imm:8
BITop GPR.bs
Performs a bit operation on GPR and stores the result in GPR.
Since the equivalent functionality can be achieved using OR GPR, #imm:8, AND GPR, #imm:8, and XOR GPR,
#imm:8, this instruction type doesn't have separate op codes.
7-25
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
AND SR0, #imm:8/OR SR0, #imm:8
Sets/resets bits in SR0 and stores the result back into SR0.
Operation
SR0 ← SR0 & #imm:8
SR0 ← SR0 | #imm:8
BANK #imm:2
Loads SR0[4:3] with #imm[1:0].
Operation
SR0[4:3] ← #imm[1:0]
MISCELLANEOUS INSTRUCTION
SWAP GPR, SPR
Swaps the values in GPR and SPR. SR0 and SR1 can NOT be used for this instruction.
No flag is updated, even though the destination is GPR.
Operation
temp ← SPR
SPR ← GPR
GPR ← temp
Example
SWAP R0, IDH
// assume IDH = 00h and R0 = 08h.
// after this, IDH = 08h and R0 = 00h.
PUSH REG
Saves REG in the stack (Pushes REG into stack).
REG = GPR, SPR
Operation
HS[sptr][7:0] ← REG and sptr ← sptr + 1
Example
PUSH R0
7-26
// assume R0 = 08h and sptr = 2h
// then HS[2][7:0] ← 08h and sptr ← 3h
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
POP REG
Pops stack into REG.
REG = GPR, SPR
Operation
REG ← HS[sptr-1][7:0] and sptr ← sptr – 1
Example
POP R0
// assume sptr = 3h and HS[2] = 18407h
// R0 ← 07h and sptr ← 2h
POP
Pops 2 bytes from the stack and discards the popped data.
NOP
Does no work but increase PC by 1.
BREAK
Does nothing and does NOT increment PC. This instruction is for the debugger only. When this instruction is
executed, the processor is locked since PC is not incremented. Therefore, this instruction should not be used
under any mode other than the debug mode.
SYS #imm:8
Does nothing but increase PC by 1 and generates SYSCP[7:0] and nSYSID signals.
CLD GPR, imm:8
GPR ← (imm:8) and generates SYSCP[7:0], nCLDID, and nCLDWR signals.
CLD imm:8, GPR
(imm:8) ← GPR and generates SYSCP[7:0], nCLDID, and nCLDWR signals.
COP #imm:12
Generates SYSCP[11:0] and nCOPID signals.
7-27
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LDC
Loads program memory item into register.
Operation
[TBH:TBL] ← PM[ILX:ILH:ILL]
[TBH:TBL] ← PM[ILX:ILH:ILL], ILL++
(LDC @IL)
(LDC @IL+)
TBH and TBL are temporary registers to hold the transferred program memory items. These can be accessed
only by LD GPR and TBL/TBH instruction.
Example
LD ILX, R1
LD ILH, R2
LD ILL, R3
LDC @IL
7-28
// assume R1:R2:R3 has the program address to access
// get the program data @(ILX:ILH:ILL) into TBH:TBL
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
PSEUDO INSTRUCTIONS
EI/DI
Exceptions enable and disable instruction.
Operation
SR0 ← OR SR0,#00000010b (EI)
SR0 ← AND SR0,#11111101b (DI)
Exceptions are enabled or disabled through this instruction. If there is an EI instruction, the SR0.1 is set and
reset, when DI instruction.
Example
DI
•
•
•
EI
SCF/RCF
Carry flag set and reset instruction.
Operation
CP R0,R0
AND R0,R0
(SCF)
(RCF)
Carry flag is set or reset through this instruction. If there is an SCF instruction, the SR1.0 is set and reset, when
RCF instruction.
Example
SCF
RCF
STOP/IDLE
MCU power saving instruction.
Operation
SYS #0Ah
SYS #05h
(STOP)
(IDLE)
The STOP instruction stops the both CPU clock and system clock and causes the microcontroller to enter STOP
mode. The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue.
Example
STOP(or IDLE)
NOP
NOP
NOP
•
•
•
7-29
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
ADC — Add with Carry
Format:
ADC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:
<op1> ← <op1> + <op2> + C
ADC adds the values of <op1> and <op2> and carry (C) and stores the result back into <op1>
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
exclusive OR of V and MSB of result.
Example:
ADC
R0, 80h
// If eid = 0, R0 ← R0 + DM[0080h] + C
// If eid = 1, R0 ← R0 + DM[IDH:80h] + C
ADC
R0, R1
// R0 ← R0 + R1 + C
ADD
ADC
R0, R2
R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of "ADD R0, R2" is not zero, Z flag can be set to '1' if the
result of "ADC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit addition, take care of the change of Z flag.
7-30
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
ADD — Add
Format:
ADD <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ← <op1> + <op2>
ADD adds the values of <op1> and <op2> and stores the result back into <op1>.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
exclusive OR of V and MSB of result.
Example:
Given: IDH:IDL0 = 80FFh, eid = 1
ADD
R0, 80h
// R0 ← R0 + DM[8080h]
ADD
R0, #12h
// R0 ← R0 + 12h
ADD
R1, R2
// R1 ← R1 + R2
ADD
ADD
ADD
ADD
R0, @ID0 + 2
R0, @[ID0 – 3]
R0, @[ID0 + 2]!
R0, @[ID0 – 2]!
// R0 ← R0 + DM[80FFh], IDH ← 81h, IDL0 ← 01h
// R0 ← R0 + DM[80FCh], IDH ← 80h, IDL0 ← FCh
// R0 ← R0 + DM[8101h], IDH ← 80h, IDL0 ← FFh
// R0 ← R0 + DM[80FDh], IDH ← 80h, IDL0 ← FFh
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-31
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
AND — Bit-wise AND
Format:
AND <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ← <op1> & <op2>
AND performs bit-wise AND on the values in <op1> and <op2> and stores the result in <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: set if the MSB of result is 1. Reset if not.
Example:
Given: IDH:IDL0 = 01FFh, eid = 1
AND
R0, 7Ah
// R0 ← R0 & DM[017Ah]
AND
R1, #40h
// R1 ← R1 & 40h
AND
R0, R1
// R0 ← R0 & R1
AND
AND
AND
AND
R1, @ID0 + 3
R1, @[ID0 – 5]
R1, @[ID0 + 7]!
R1, @[ID0 – 2]!
// R1 ← R1 & DM[01FFh], IDH:IDL0 ← 0202h
// R1 ← R1 & DM[01FAh], IDH:IDL0 ← 01FAh
// R1 ← R1 & DM[0206h], IDH:IDL0 ← 01FFh
// R1 ← R1 & DM[01FDh], IDH:IDL0 ← 01FFh
In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data
memory DM[0051h-007Fh] are not mapped in S3CB519/S3FB519. In the last two instructions,
the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this
addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-32
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
AND SR0 — Bit-wise AND with SR0
Format:
AND SR0, #imm:8
Operation:
SR0 ← SR0 & imm:8
AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the
result in SR0.
Flags:
–
Example:
Given: SR0 = 11000010b
nIE
nIE0
nIE1
EQU
EQU
EQU
~02h
~40h
~80h
AND
SR0, #nIE | nIE0 | nIE1
AND
SR0, #11111101b
In the first example, the statement "AND SR0, #nIE|nIE0|nIE1" clear all of bits of the global
interrupt, interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to '1' by instruction
"OR SR0, #imm:8". Refer to instruction OR SR0 for more detailed explanation about enabling
bit.
In the second example, the statement "AND SR0, #11111101b" is equal to instruction DI, which
is disabling interrupt globally.
7-33
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
BANK — GPR Bank selection
Format:
BANK #imm:2
Operation:
SR0[4:3] ← imm:2
Flags:
–
NOTE:
For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3.
Example:
7-34
BANK
LD
#1
R0, #11h
// Select register bank 1
// Bank1's R0 ← 11h
BANK
LD
#2
R1, #22h
// Select register bank 2
// Bank2's R1 ← 22h
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
BITC — Bit Complement
Format:
BITC adr:8.bs
bs: 3-digit bit specifier
Operation:
R3 ← ((adr:8) ^ (2**bs))
(adr:8) ← ((adr:8) ^ (2**bs))
if (TF == 0)
if (TF == 1)
BITC complements the specified bit of a value read from memory and stores the result in R3 or
back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
NOTE:
Since the destination register R3 is fixed, it is not specified explicitly.
Example:
Given: IDH = 01, DM[0180h] = FFh, eid = 1
BMC
BITC
80h.0
// TF ← 0
// R3 ← FEh, DM[0180h] = FFh
BMS
BITC
80h.1
// TF ← 1
// DM[0180h] ← FDh
7-35
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
BITR — Bit Reset
Format:
BITR adr:8.bs
bs: 3-digit bit specifier
Operation:
R3 ← ((adr:8) & ((11111111)2 - (2**bs)))
(adr:8) ← ((adr:8) & ((11111111)2 - (2**bs)))
if (TF == 0)
if (TF == 1)
BITR resets the specified bit of a value read from memory and stores the result in R3 or back
into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
NOTE:
Since the destination register R3 is fixed, it is not specified explicitly.
Example:
Given: IDH = 01, DM[0180h] = FFh, eid = 1
7-36
BMC
BITR
80h.1
// TF ← 0
// R3 ← FDh, DM[0180h] = FFh
BMS
BITR
80h.2
// TF ← 1
// DM[0180h] ← FBh
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
BITS — Bit Set
Format:
BITS adr:8.bs
bs: 3-digit bit specifier.
Operation:
R3 ← ((adr:8) | (2**bs))
(adr:8) ← ((adr:8) | (2**bs))
if (TF == 0)
if (TF == 1)
BITS sets the specified bit of a value read from memory and stores the result in R3 or back into
memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
NOTE:
Since the destination register R3 is fixed, it is not specified explicitly.
Example:
Given: IDH = 01, DM[0180h] = F0h, eid = 1
BMC
BITS
80h.1
// TF ← 0
// R3 ← 0F2h, DM[0180h] = F0h
BMS
BITS
80h.2
// TF ← 1
// DM[0180h] ← F4h
7-37
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
BITT — Bit Test
Format:
BITT adr:8.bs
bs: 3-digit bit specifier.
Operation:
Z ← ~((adr:8) & (2**bs))
BITT tests the specified bit of a value read from memory.
Flags:
Z: set if result is zero. Reset if not.
Example:
Given: DM[0080h] = F7h, eid = 0
BITT
JR
80h.3
Z, %1
•
•
•
%1
BITS
NOP
•
•
•
7-38
80h.3
// Z flag is set to '1'
// Jump to label %1 because condition is true.
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
BMC/BMS – TF bit clear/set
Format:
BMS/BMC
Operation:
BMC/BMS clears (sets) the TF bit.
TF ← 0 if BMC
TF ← 1 if BMS
TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR,
and BITS.
Flags:
–
NOTE:
BMC/BMS are the only instructions that modify the content of the TF bit.
Example:
// TF ← 1
BMS
BITS
81h.1
BMC
BITR
LD
81h.2
R0, R3
// TF ← 0
7-39
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
CALL — Conditional Subroutine Call (Pseudo Instruction)
Format:
CALL cc:4, imm:20
CALL imm:12
Operation:
If CALLS can access the target address and there is no conditional code (cc:4), CALL command is
assembled to CALLS (1-word instruction) in linking time, else the CALL is assembled to LCALL (2-word
instruction).
Example:
CALL
C, Wait
// HS[sptr][15:0] ← current PC + 2, sptr ← sptr + 2
// 2-word instruction
0088h
// HS[sptr][15:0] ← current PC + 1, sptr ← sptr + 2
// 1-word instruction
•
•
•
CALL
•
•
•
Wait:
7-40
NOP
NOP
NOP
NOP
NOP
RET
// Address at 0088h
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
CALLS — Call Subroutine
Format:
CALLS imm:12
Operation:
HS[sptr][15:0] ← current PC + 1, sptr ← sptr + 2 if the program size is less than 64K word.
HS[sptr][19:0] ← current PC + 1, sptr ← sptr + 2 if the program size is equal to or over 64K word.
PC[11:0] ← imm:12
CALLS unconditionally calls a subroutine residing at the address specified by imm:12.
Flags:
–
Example:
CALLS
Wait
•
•
•
Wait:
NOP
NOP
NOP
RET
Because this is a 1-word instruction, the saved returning address on stack is (PC + 1).
7-41
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
CLD — Load into Coprocessor
Format:
CLD imm:8, <op>
<op>: GPR
Operation:
(imm:8) ← <op>
CLD loads the value of <op> into (imm:8), where imm:8 is used to access the external
coprocessor's address space.
Flags:
–
Example:
AH
AL
BH
BL
EQU
EQU
EQU
EQU
00h
01h
02h
03h
•
•
•
CLD
CLD
AH, R0
AL, R1
// A[15:8] ← R0
// A[7:0] ← R1
CLD
CLD
BH, R2
BL, R3
// B[15:8] ← R2
// B[7:0] ← R3
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.
Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
7-42
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
CLD — Load from Coprocessor
Format:
CLD <op>, imm:8
<op>: GPR
Operation:
<op> ← (imm:8)
CLD loads a value from the coprocessor, whose address is specified by imm:8.
Flags:
Z: set if the loaded value in <op1> is zero. Reset if not.
N: set if the MSB of the loaded value in <op1> is 1. Reset if not.
Example:
AH
AL
BH
BL
EQU
EQU
EQU
EQU
00h
01h
02h
03h
•
•
•
CLD
CLD
R0, AH
R1, AL
// R0 ← A[15:8]
// R1 ← A[7:0]
CLD
CLD
R2, BH
R3, BL
// R2 ← B[15:8]
// R3 ← B[7:0]
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.
Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
7-43
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
COM — 1's or Bit-wise Complement
Format:
COM <op>
<op>: GPR
Operation:
<op> ← ~<op>
COM takes the bit-wise complement operation on <op> and stores the result in <op>.
Flags:
Z: set if result is zero. Reset if not.
N: set if the MSB of result is 1. Reset if not.
Example:
Given: R1 = 5Ah
COM
7-44
R1
// R1 ← A5h, N flag is set to '1'
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
COM2 — 2's Complement
Format:
COM2 <op>
<op>: GPR
Operation:
<op> ← ~<op> + 1
COM2 computes the 2's complement of <op> and stores the result in <op>.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative.
Example:
Given: R0 = 00h, R1 = 5Ah
COM2
R0
// R0 ← 00h, Z and C flags are set to '1'.
COM2
R1
// R1 ← A6h, N flag is set to '1'.
7-45
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
COMC — Bit-wise Complement with Carry
Format:
COMC <op>
<op>: GPR
Operation:
<op> ← ~<op> + C
COMC takes the bit-wise complement of <op>, adds carry and stores the result in <op>.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
Example:
If register pair R1:R0 is a 16-bit number, then the 2's complement of R1:R0 can be obtained by
COM2 and COMC as following.
COM2
COMC
R0
R1
Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register
pair R1: R0 has value of FF01h, then 2's complement of R1: R0 is made of 00FFh by COM2 and
COMC. At this time, by instruction COMC, zero (Z) flag is set to '1' as if the result of 2's
complement for 16-bit number is zero. Therefore when programming 16-bit comparison, take
care of the change of Z flag.
7-46
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
COP — Coprocessor
Format:
COP #imm:12
Operation:
COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals.
Flags:
–
Example:
COP
COP
#0D01h
#0234h
// generate 1 word instruction code(FD01h)
// generate 1 word instruction code(F234h)
The above two instructions are equal to statement "ELD A, #1234h" for MAC816 operation. The
microcode of MAC instruction "ELD A, #1234h" is "FD01F234", 2-word instruction. In this, code
'F' indicates 'COP' instruction.
7-47
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
CP — Compare
Format:
CP <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> + ~<op2> + 1
CP compares the values of <op1> and <op2> by subtracting <op2> from <op1>. Contents of
<op1> and <op2> are not changed.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero (i.e., <op1> and <op2> are same). Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
Example:
Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1
CP
R0, 80h
// C flag is set to '1'
CP
R0, #73h
// Z and C flags are set to '1'
CP
R0, R1
// V flag is set to '1'
CP
CP
CP
CP
R1, @ID0
R1, @[ID0 – 5]
R2, @[ID0 + 7]!
R2, @[ID0 – 2]!
// Z and C flags are set to '1'
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-48
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
CPC — Compare with Carry
Format:
CPC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:
<op1> ← <op1> + ~<op2> + C
CPC compares <op1> and <op2> by subtracting <op2> from <op1>. Unlike CP, however, CPC
adds (C - 1) to the result. Contents of <op1> and <op2> are not changed.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
Example:
If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC
to compare two 16-bit numbers as follows.
CP
CPC
R0, R1
R2, R3
Because CPC considers C when comparing <op1> and <op2>, CP and CPC can be used in pair
to compare 16-bit operands. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit comparison, take care of the change of Z flag.
7-49
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
DEC — Decrement
Format:
DEC <op>
<op>: GPR
Operation:
<op> ← <op> + 0FFh
DEC decrease the value in <op> by adding 0FFh to <op>.
Flags:
C:
Z:
V:
N:
Example:
Given: R0 = 80h, R1 = 00h
7-50
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
DEC
R0
// R0 ← 7Fh, C, V and N flags are set to '1'
DEC
R1
// R1 ← FFh, N flags is set to '1'
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
DECC — Decrement with Carry
Format:
DECC <op>
<op>: GPR
Operation:
<op> ← <op> + 0FFh + C
DECC decrease the value in <op> when carry is not set. When there is a carry, there is no
change in the value of <op>.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to
decrement 16-bit number as follows.
DEC
DECC
R0
R1
Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when
programming 16-bit decrement, take care of the change of Z flag.
7-51
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
DI — Disable Interrupt (Pseudo Instruction)
Format:
DI
Operation:
Disables interrupt globally. It is same as "AND SR0, #0FDh" .
DI instruction sets bit1 (ie: global interrupt enable) of SR0 register to "0”
Flags:
–
Example:
Given: SR0 = 03h
DI
// SR0 ← SR0 & 11111101b
DI instruction clears SR0[1] to '0', disabling interrupt processing.
7-52
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
EI — Enable Interrupt (Pseudo Instruction)
Format:
EI
Operation:
Enables interrupt globally. It is same as "OR SR0, #02h" .
EI instruction sets the bit1 (ie: global interrupt enable) of SR0 register to "1"
Flags:
–
Example:
Given: SR0 = 01h
EI
// SR0 ← SR0 | 00000010b
The statement "EI" sets the SR0[1] to '1', enabling all interrupts.
7-53
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
IDLE — Idle Operation (Pseudo Instruction)
Format:
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue.
Idle mode can be released by an interrupt or reset operation.
The IDLE instruction is a pseudo instruction. It is assembled as "SYS #05H", and this generates
the SYSCP[7-0] signals. Then these signals are decoded and the decoded signals execute the
idle operation.
Flags:
–
NOTE:
The next instruction of IDLE instruction is executed, so please use the NOP instruction after the IDLE
instruction.
Example:
IDLE
NOP
NOP
NOP
•
•
•
The IDLE instruction stops the CPU clock but not the system clock.
7-54
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
INC — Increment
Format:
INC <op>
<op>: GPR
Operation:
<op> ← <op> + 1
INC increase the value in <op>.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
Example:
Given: R0 = 7Fh, R1 = FFh
INC
R0
// R0 ← 80h, V flag is set to '1'
INC
R1
// R1 ← 00h, Z and C flags are set to '1'
7-55
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
INCC — Increment with Carry
Format:
INCC <op>
<op>: GPR
Operation:
<op> ← <op> + C
INCC increase the value of <op> only if there is carry. When there is no carry, the value of
<op> is not changed.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
exclusive OR of V and MSB of result.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment
16-bit number as following.
INC
INCC
R0
R1
Assume R1:R0 is 0010h, statement "INC R0" increase R0 by one without carry and statement
"INCC R1" set zero (Z) flag to '1' as if the result of 16-bit increment is zero. Note that zero (Z)
flag do not exactly reflect result of 16-bit operation. Therefore when programming 16-bit
increment, take care of the change of Z flag.
7-56
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
IRET — Return from Interrupt Handling
Format:
IRET
Operation:
PC ← HS[sptr - 2], sptr ← sptr - 2
IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to
PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation.
Flags:
–
NOTE:
The program size (indicated by the nP64KW signal) determines which portion of PC is updated.
When the program size is less than 64K word, only the lower 16 bits of PC are updated
(i.e., PC[15:0] ← HS[sptr – 2]).
When the program size is 64K word or more, the action taken is PC[19:0] ← HS[sptr - 2].
Example:
SF_EXCEP:
NOP
// Stack full exception service routine
•
•
•
IRET
7-57
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
JNZD — Jump Not Zero with Delay slot
Format:
JNZD <op>, imm:8
<op>: GPR (bank 3's GPR only)
imm:8 is an signed number
Operation:
PC ← PC[delay slot] - 2's complement of imm:8
<op> ← <op> - 1
JNZD performs a backward PC-relative jump if <op> evaluates to be non-zero. Furthermore,
JNZD decrease the value of <op>. The instruction immediately following JNZD (i.e., in delay slot)
is always executed, and this instruction must be 1 cycle instruction.
Flags:
–
NOTE:
Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however,
that the chosen instruction should be "dead" outside the loop for it executes even when the loop
is exited (i.e., JNZD is not taken).
Example:
Given: IDH = 03h, eid = 1
%1
BANK
LD
LD
LD
JNZD
LD
#3
R0, #0FFh
R1, #0
IDL0, R0
R0, %B1
@ID0, R1
// R0 is used to loop counter
// If R0 of bank3 is not zero, jump to %1.
// Clear register pointed by ID0
•
•
•
This example can be used for RAM clear routine. The last instruction is executed even if the loop
is exited.
7-58
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
JP — Conditional Jump (Pseudo Instruction)
Format:
JP cc:4 imm:20
JP cc:4 imm:9
Operation:
If JR can access the target address, JP command is assembled to JR (1 word instruction) in
linking time, else the JP is assembled to LJP (2 word instruction) instruction.
There are 16 different conditions that can be used, as described in table 7-6.
Example:
%1
LD
R0, #10h
// Assume address of label %1 is 020Dh
JP
Z, %B1
// Address at 0264h
JP
C, %F2
// Address at 0265h
R1, #20h
// Assume address of label %2 is 089Ch
•
•
•
•
•
•
%2
LD
•
•
•
In the above example, the statement "JP Z, %B1" is assembled to JR instruction. Assuming that
current PC is 0264h and condition is true, next PC is made by PC[11:0] ← PC[11:0] + offset,
offset value is "64h + A9h" without carry. 'A9' means 2's complement of offset value to jump
backward. Therefore next PC is 020Dh. On the other hand, statement "JP C, %F2" is assembled
to LJP instruction because offset address exceeds the range of imm:9.
7-59
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
JR — Conditional Jump Relative
Format:
JR cc:4 imm:9
cc:4: 4-bit condition code
Operation:
PC[11:0] ← PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is signextended to 12 bits when added to PC.
There are 16 different conditions that can be used, as described in table 7-6.
Flags:
–
NOTE:
Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to
compute the actual jump address, while LJP directly jumps to imm:20, the target.
Example:
JR
Z, %1
// Assume current PC = 1000h
R0, R1
// Address at 10A5h
•
•
•
%1
LD
•
•
•
After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to '1'. The
range of the relative address is from +255 to –256 because imm:9 is signed number.
7-60
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LCALL — Conditional Subroutine Call
Format:
LCALL cc:4, imm:20
Operation:
HS[sptr][15:0] ← current PC + 2, sptr ← sptr + 2, PC[15:0] ← imm[15:0] if the condition holds
and the program size is less than 64K word.
HS[sptr][19:0] ← current PC + 2, sptr ← sptr + 2, PC[19:0] ← imm:20 if the condition holds and
the program size is equal to or over 64K word.
PC[11:0] ← PC[11:0] + 2 otherwise.
LCALL instruction is used to call a subroutine whose starting address is specified by imm:20.
Flags:
–
Example:
LCALL
L1
LCALL
C, L2
Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word
instruction, the saved returning address on stack is (PC + 2).
7-61
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LD adr:8 — Load into Memory
Format:
LD adr:8, <op>
<op>: GPR
Operation:
DM[00h:adr:8] ← <op> if eid = 0
DM[IDH:adr:8] ← <op> if eid = 1
LD adr:8 loads the value of <op> into a memory location. The memory location is determined by
the eid bit and adr:8.
Flags:
–
Example:
Given: IDH = 01h
LD
80h, R0
If eid bit of SR0 is zero, the statement "LD 80h, R0" load value of R0 into DM[0080h], else eid bit
was set to '1', the statement "LD 80h, R0" load value of R0 into DM[0180h]
7-62
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LD @idm — Load into Memory Indexed
Format:
LD @idm, <op>
<op>: GPR
Operation:
(@idm) ← <op>
LD @idm loads the value of <op> into the memory location determined by @idm. Details of the
@idm format and how the actual address is calculated can be found in chapter 2.
Flags:
–
Example:
Given R0 = 5Ah, IDH:IDL0 = 8023h, eid = 1
LD
LD
LD
LD
LD
@ID0, R0
@ID0 + 3, R0
@[ID0-5], R0
@[ID0+4]!, R0
@[ID0-2]!, R0
// DM[8023h] ← 5Ah
// DM[8023h] ← 5Ah, IDL0 ← 26h
// DM[801Eh] ← 5Ah, IDL0 ← 1Eh
// DM[8027h] ← 5Ah, IDL0 ← 23h
// DM[8021h] ← 5Ah, IDL0 ← 23h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-63
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LD — Load Register
Format:
LD <op1>, <op2>
<op1>: GPR
<op2>: GPR, SPR, adr:8, @idm, #imm:8
Operation:
<op1> ← <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
Given: R0 = 5Ah, R1 = AAh, IDH:IDL0 = 8023h, eid = 1
LD
R0, R1
// R0 ← AAh
LD
R1, IDH
// R1 ← 80h
LD
R2, 80h
// R2 ← DM[8080h]
LD
R0, #11h
// R0 ← 11h
LD
LD
LD
LD
R0, @ID0+1
R1, @[ID0-2]
R2, @[ID0+3]!
R3, @[ID0-5]!
// R0 ← DM[8023h], IDL0 ← 24h
// R1 ← DM[8021h], IDL0 ← 21h
// R2 ← DM[8026h], IDL0 ← 23h
// R3 ← DM[801Eh], IDL0 ← 23h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-64
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LD — Load GPR:bankd, GPR:banks
Format:
LD <op1>, <op2>
<op1>: GPR: bankd
<op2>: GPR: banks
Operation:
<op1> ← <op2>
LD loads a value of a register in a specified bank (banks) into another register in a specified bank
(bankd).
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
LD
R2:1, R0:3
// Bank1's R2 ← bank3's R0
LD
R0:0, R0:2
// Bank0's R0 ← bank2's R0
7-65
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LD — Load GPR, TBH/TBL
Format:
LD <op1>, <op2>
<op1>: GPR
<op2>: TBH/TBL
Operation:
<op1> ← <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
Given: register pair R1:R0 is 16-bit unsigned data.
LDC
LD
LD
7-66
@IL
R1, TBH
R0, TBL
// TBH:TBL ← PM[ILX:ILH:ILL]
// R1 ← TBH
// R0 ← TBL
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LD — Load TBH/TBL, GPR
Format:
LD <op1>, <op2>
<op1>: TBH/TBL
<op2>: GPR
Operation:
<op1> ← <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
–
Example:
Given: register pair R1:R0 is 16-bit unsigned data.
LD
LD
TBH, R1
TBL, R0
// TBH ← R1
// TBL ← R0
7-67
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LD SPR — Load SPR
Format:
LD <op1>, <op2>
<op1>: SPR
<op2>: GPR
Operation:
<op1> ← <op2>
LD SPR loads the value of a GPR into an SPR.
Refer to Table 3-1 for more detailed explanation about kind of SPR.
Flags:
–
Example:
Given: register pair R1:R0 = 1020h
LD
LD
7-68
ILH, R1
ILL, R0
// ILH ← 10h
// ILL ← 20h
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LD SPR0 — Load SPR0 Immediate
Format:
LD SPR0, #imm:8
Operation:
SPR0 ← imm:8
LD SPR0 loads an 7-bit immediate value into SPR0.
Flags:
–
Example:
Given: eid = 1, idb = 0 (index register bank 0 selection)
LD
LD
LD
LD
IDH, #80h
IDL1, #44h
IDL0, #55h
SR0, #02h
// IDH point to page 80h
The last instruction set ie (global interrupt enable) bit to '1'.
Special register group 1 (SPR1) registers are not supported in this addressing mode.
7-69
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LDC — Load Code
Format:
LDC <op1>
<op1>: @IL, @IL+
Operation:
TBH:TBL ← PM[ILX:ILH:ILL]
ILL ← ILL + 1 (@IL+ only)
LDC loads a data item from program memory and stores it in the TBH:TBL register pair.
@IL+ increase the value of ILL, efficiently implementing table lookup operations.
Flags:
–
Example:
LD
LD
LD
LDC
ILX, R1
ILH, R2
ILL, R3
@IL
LD
LD
R1, TBH
R0, TBL
// Loads value of PM[ILX:ILH:ILL] into TBH:TBL
// Move data in TBH:TBL to GPRs for further processing
The statement "LDC @IL" do not increase, but if you use statement "LDC @IL+", ILL register is
increased by one after instruction execution.
7-70
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LJP — Conditional Jump
Format:
LJP cc:4, imm:20
cc:4: 4-bit condition code
Operation:
PC[15:0] ← imm[15:0] if condition is true and the program size is less than 64K word. If the
program is equal to or larger than 64K word, PC[19:0] ← imm[19:0] as long as the condition is
true. There are 16 different conditions that can be used, as described in table 7-6.
Flags:
–
NOTE:
LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target
address of the jump.
Example:
LJP
C, %1
// Assume current PC = 0812h
R0, R1
// Address at 10A5h
•
•
•
%1
LD
•
•
•
After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true.
7-71
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LLNK — Linked Subroutine Call Conditional
Format:
LLNK cc:4, imm:20
cc:4: 4-bit condition code
Operation:
If condition is true, IL[19:0] ← {PC[19:12], PC[11:0] + 2}.
Further, when the program is equal to or larger than 64K word, PC[19:0] ← imm[19:0] as long as
the condition is true. If the program is smaller than 64K word, PC[15:0] ← imm[15:0].
There are 16 different conditions that can be used, as described in table 7-6.
Flags:
–
NOTE:
LLNK is used to conditionally to call a subroutine with the return address saved in the link register
(IL) without stack operation. This is a 2-word instruction.
Example:
LLNK
NOP
Z, %1
•
•
•
%1
LD
•
•
•
LRET
7-72
R0, R1
// Address at 005Ch, ILX:ILH:ILL ← 00:00:5Eh
// Address at 005Eh
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LNK — Linked Subroutine Call (Pseudo Instruction)
Format:
LNK cc:4, imm:20
LNK imm:12
Operation:
If LNKS can access the target address and there is no conditional code (cc:4), LNK command is
assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2
word instruction).
Example:
LNK
LNK
NOP
Z, Link1
Link2
// Equal to "LLNK Z, Link1"
// Equal to "LNKS Link2"
•
•
•
Link2: NOP
•
•
•
LRET
Subroutines
section CODE, ABS 0A00h
Subroutines
Link1: NOP
•
•
•
LRET
7-73
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
LNKS — Linked Subroutine Call
Format:
LNKS imm:12
Operation:
IL[19:0] ← {PC[19:12], PC[11:0] + 1} and PC[11:0] ← imm:12
LNKS saves the current PC in the link register and jumps to the address specified by imm:12.
Flags:
–
NOTE:
LNKS is used to call a subroutine with the return address saved in the link register (IL) without
stack operation.
Example:
LNKS
NOP
•
•
•
Link1: NOP
•
•
•
LRET
7-74
Link1
// Address at 005Ch, ILX:ILH:ILL ← 00:00:5Dh
// Address at 005Dh
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
LRET — Return from Linked Subroutine Call
Format:
LRET
Operation:
PC ← IL[19:0]
LRET returns from a subroutine by assigning the saved return address in IL to PC.
Flags:
–
Example:
LNK
Link1: NOP
Link1
•
•
•
LRET
; PC[19:0] ← ILX:ILH:ILL
7-75
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
NOP — No Operation
Format:
NOP
Operation:
No operation.
When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction
time is delayed by approximately one machine cycle per each NOP instruction encountered.
Flags:
–
Example:
NOP
7-76
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
OR — Bit-wise OR
Format:
OR <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ← <op1> | <op2>
OR performs the bit-wise OR operation on <op1> and <op2> and stores the result in <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
Given: IDH:IDL0 = 031Eh, eid = 1
OR
R0, 80h
// R0 ← R0 | DM[0380h]
OR
R1, #40h
// Mask bit6 of R1
OR
R1, R0
// R1 ← R1 | R0
OR
OR
OR
OR
R0, @ID0
R1, @[ID0-1]
R2, @[ID0+1]!
R3, @[ID0-1]!
// R0 ← R0 | DM[031Eh], IDL0 ← 1Eh
// R1 ← R1 | DM[031Dh], IDL0 ← 1Dh
// R2 ← R2 | DM[031Fh], IDL0 ← 1Eh
// R3 ← R3 | DM[031Dh], IDL0 ← 1Eh
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-77
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
OR SR0 — Bit-wise OR with SR0
Format:
OR SR0, #imm:8
Operation:
SR0 ← SR0 | imm:8
OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0.
Flags:
–
Example:
Given: SR0 = 00000000b
EID
IE
IDB1
IE0
IE1
EQU
EQU
EQU
EQU
EQU
01h
02h
04h
40h
80h
OR
SR0, #IE | IE0 | IE1
OR
SR0, #00000010b
In the first example, the statement "OR SR0, #EID|IE|IE0" set global interrupt(ie), interrupt 0(ie0)
and interrupt 1(ie1) to '1' in SR0. On the contrary, enabled bits can be cleared with instruction
"AND SR0, #imm:8". Refer to instruction AND SR0 for more detailed explanation about disabling
bit.
In the second example, the statement "OR SR0, #00000010b" is equal to instruction EI, which is
enabling interrupt globally.
7-78
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
POP — POP
Format:
POP
Operation:
sptr ← sptr – 2
POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated.
Flags:
–
Example:
Given: sptr[5:0] = 001010b
POP
This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b.
7-79
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
POP — POP to Register
Format:
POP <op>
<op>: GPR, SPR
Operation:
<op> ← HS[sptr - 1], sptr ← sptr - 1
POP copies the value on top of the stack to <op> and decrease sptr by 1.
Flags:
Z: set if the value copied to <op> is zero. Reset if not.
N: set if the value copied to <op> is negative. Reset if not.
When <op> is SPR, no flags are affected, including Z and N.
Example:
POP
R0
// R0 ← HS[sptr-1], sptr ← sptr-1
POP
IDH
// IDH ← HS[sptr-1], sptr ← sptr-1
In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction "POP IDH"
load value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about
POP operations for hardware stack.
7-80
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
PUSH — Push Register
Format:
PUSH <op>
<op>: GPR, SPR
Operation:
HS[sptr] ← <op>, sptr ← sptr + 1
PUSH stores the value of <op> on top of the stack and increase sptr by 1.
Flags:
–
Example:
PUSH
R0
// HS[sptr] ← R0, sptr ← sptr + 1
PUSH
IDH
// HS[sptr] ← IDH, sptr ← sptr + 1
In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction
"PUSH IDH" load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0]
be emptied. Refer to chapter 5 for more detailed explanation about PUSH operations for
hardware stack.
7-81
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
RET — Return from Subroutine
Format:
RET
Operation:
PC ← HS[sptr - 2], sptr ← sptr – 2
RET pops an address on the hardware stack into PC so that control returns to the subroutine call
site.
Flags:
–
Example:
Given: sptr[5:0] = 001010b
CALLS
Wait
// Address at 00120h
•
•
•
Wait:
NOP
NOP
NOP
NOP
NOP
RET
// Address at 01000h
After the first instruction CALLS execution, "PC+1", 0121h is loaded to HS[5] and hardware stack
pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value
0121h on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became
001010b.
7-82
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
RL — Rotate Left
Format:
RL <op>
<op>: GPR
Operation:
C ← <op>[7], <op> ← {<op>[6:0], <op>[7]}
RL rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C).
Flags:
C: set if the MSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R0 = 01001010b, R1 = 10100101b
RL
R0
// N flag is set to '1', R0 ← 10010100b
RL
R1
// C flag is set to '1', R1 ← 01001011b
7-83
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
RLC — Rotate Left with Carry
Format:
RLC <op>
<op>: GPR
Operation:
C ← <op>[7], <op> ← {<op>[6:0], C}
RLC rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C), and the original C bit is copied into <op>[0].
Flags:
C: set if the MSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R2 = A5h, if C = 0
RLC
R2
RL
RLC
R0
R1
// R2 ← 4Ah, C flag is set to '1'
In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are
used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16bit operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
7-84
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
RR — Rotate Right
Format:
RR <op>
<op>: GPR
Operation:
C ← <op>[0], <op> ← {<op>[0], <op>[7:1]}
RR rotates the value of <op> to the right and stores the result back into <op>. The original LSB
of <op> is copied into carry (C).
Flags:
C: set if the LSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R0 = 01011010b, R1 = 10100101b
RR
R0
// No change of flag, R0 ← 00101101b
RR
R1
// C and N flags are set to '1', R1 ← 11010010b
7-85
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
RRC — Rotate Right with Carry
Format:
RRC <op>
<op>: GPR
Operation:
C ← <op>[0], <op> ← {C, <op>[7:1]}
RRC rotates the value of <op> to the right and stores the result back into <op>. The original LSB
of <op> is copied into carry (C), and C is copied to the MSB.
Flags:
C: set if the LSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R2 = A5h, if C = 0
RRC
R2
RR
RRC
R0
R1
// R2 ← 52h, C flag is set to '1'
In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC
are used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of
16-bit operation. Therefore when programming 16-bit decrement, take care of the change of Z
flag.
7-86
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
SBC — Subtract with Carry
Format:
SBC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:
<op1> ← <op1> + ~<op2> + C
SBC computes (<op1> - <op2>) when there is carry and (<op1> - <op2> - 1) when there is no
carry.
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated.
set if result is negative. Reset if not.
Example:
SBC
R0, 80h
// If eid = 0, R0 ← R0 + ~DM[0080h] + C
// If eid = 1, R0 ← R0 + ~DM[IDH:80h] + C
SBC
R0, R1
// R0 ← R0 + ~R1 + C
SUB
SBC
R0, R2
R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of "ADD R0, R2" is not zero, zero (Z) flag can be set to '1' if
the result of "SBC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit addition, take care of the change of Z flag.
7-87
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
SL — Shift Left
Format:
SL <op>
<op>: GPR
Operation:
C ← <op>[7], <op> ← {<op>[6:0], 0}
SL shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).
Flags:
C: set if the MSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = 01001010b, R1 = 10100101b
7-88
SL
R0
// N flag is set to '1', R0 ← 10010100b
SL
R1
// C flag is set to '1', R1 ← 01001010b
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
SLA — Shift Left Arithmetic
Format:
SLA <op>
<op>: GPR
Operation:
C ← <op>[7], <op> ← {<op>[6:0], 0}
SLA shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).
Flags:
C:
Z:
V:
N:
set if the MSB of <op> (before shifting) is 1. Reset if not.
set if result is zero. Reset if not.
set if the MSB of the result is different from C. Reset if not.
set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = AAh
SLA
R0
// C, V, N flags are set to '1', R0 ← 54h
7-89
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
SR — Shift Right
Format:
SR <op>
<op>: GPR
Operation:
C ← <op>[0], <op> ← {0, <op>[7:1]}
SR shifts <op> to the right by 1 bit. The LSB of the original <op> (i.e., <op>[0]) is copied into
carry (C).
Flags:
C: set if the LSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = 01011010b, R1 = 10100101b
7-90
SR
R0
// No change of flags, R0 ← 00101101b
SR
R1
// C flag is set to '1', R1 ← 01010010b
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
SRA — Shift Right Arithmetic
Format:
SRA <op>
<op>: GPR
Operation:
C ← <op>[0], <op> ← {<op>[7], <op>[7:1]}
SRA shifts <op> to the right by 1 bit while keeping the sign of <op>. The LSB of the original <op>
(i.e., <op>[0]) is copied into carry (C).
Flags:
C: set if the LSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
NOTE:
SRA keeps the sign bit or the MSB (<op>[7]) in its original position. If SRA is executed 'N' times, N
significant bits will be set, followed by the shifted bits.
Example:
Given: R0 = 10100101b
SRA
SRA
SRA
SRA
R0
R0
R0
R0
// C, N flags are set to '1', R0 ← 11010010b
// N flag is set to '1', R0 ← 11101001b
// C, N flags are set to '1', R0 ← 11110100b
// N flags are set to '1', R0 ← 11111010b
7-91
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
STOP — Stop Operation (pseudo instruction)
Format:
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter the STOP mode. In the STOP mode, the contents of the on-chip CPU
registers, peripheral registers, and I/O port control and data register are retained. A reset
operation or external or internal interrupts can release stop mode. The STOP instruction is a
pseudo instruction. It is assembled as "SYS #0Ah", which generates the SYSCP[7-0] signals.
These signals are decoded and stop the operation.
NOTE:
The next instruction of STOP instruction is executed, so please use the NOP instruction after the
STOP instruction.
Example:
STOP
NOP
NOP
NOP
•
•
•
In this example, the NOP instructions provide the necessary timing delay for oscillation
stabilization before the next instruction in the program sequence is executed. Refer to the timing
diagrams of oscillation stabilization, as described in Figure 17-3, 17-4
7-92
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
SUB — Subtract
Format:
SUB <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ← <op1> + ~<op2> + 1
SUB adds the value of <op1> with the 2's complement of <op2> to perform subtraction on
<op1> and <op2>
Flags:
C:
Z:
V:
N:
set if carry is generated. Reset if not.
set if result is zero. Reset if not.
set if overflow is generated. Reset if not.
set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 0150h, DM[0143h] = 26h, R0 = 52h, R1 = 14h, eid = 1
SUB
R0, 43h
// R0 ← R0 + ~DM[0143h] + 1 = 2Ch
SUB
R1, #16h
// R1 ← FEh, N flag is set to ‘1’
SUB
R0, R1
// R0 ← R0 + ~R1 + 1 = 3Eh
SUB
SUB
SUB
SUB
R0, @ID0+1
R0, @[ID0-2]
R0, @[ID0+3]!
R0, @[ID0-2]!
// R0 ← R0 + ~DM[0150h] + 1, IDL0 ← 51h
// R0 ← R0 + ~DM[014Eh] + 1, IDL0 ← 4Eh
// R0 ← R0 + ~DM[0153h] + 1, IDL0 ← 50h
// R0 ← R0 + ~DM[014Eh] + 1, IDL0 ← 50h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed
explanation about this addressing mode. The example in the SBC description shows how SUB and
SBC can be used in pair to subtract a 16-bit number from another.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-93
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
SWAP — Swap
Format:
SWAP <op1>, <op2>
<op1>: GPR
<op2>: SPR
Operation:
<op1> ← <op2>, <op2> ← <op1>
SWAP swaps the values of the two operands.
Flags:
–
NOTE:
Among the SPRs, SR0 and SR1 can not be used as <op2>.
Example:
Given: IDH:IDL0 = 8023h, R0 = 56h, R1 = 01h
SWAP
SWAP
R1, IDH
R0, IDL0
// R1 ← 80h, IDH ← 01h
// R0 ← 23h, IDL0 ← 56h
After execution of instructions, index registers IDH:IDL0 (ID0) have address 0156h.
7-94
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
SYS — System
Format:
SYS #imm:8
Operation:
SYS generates SYSCP[7:0] and nSYSID signals.
Flags:
–
NOTE:
Mainly used for system peripheral interfacing.
Example:
SYS
#0Ah
SYS
#05h
In the first example, statement "SYS #0Ah" is equal to STOP instruction and second example
"SYS #05h" is equal to IDLE instruction. This instruction does nothing but increase PC by one
and generates SYSCP[7:0] and nSYSID signals.
7-95
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
TM — Test Multiple Bits
Format:
TM <op>, #imm:8
<op>: GPR
Operation:
TM performs the bit-wise AND operation on <op> and imm:8 and sets the flags. The content of
<op> is not changed.
Flags:
Z: set if result is zero. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: R0 = 01001101b
TM
7-96
R0, #00100010b
// Z flag is set to '1'
S3CK11F/FK11F (Preliminary Spec)
INSTRUCTION SET
XOR — Exclusive OR
Format:
XOR <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ← <op1> ^ <op2>
XOR performs the bit-wise exclusive-OR operation on <op1> and <op2> and stores the result in
<op1>.
Flags:
Z: set if result is zero. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 8080h, DM[8043h] = 26h, R0 = 52h, R1 = 14h, eid = 1
XOR
R0, 43h
// R0 ← 74h
XOR
R1, #00101100b
// R1 ← 38h
XOR
R0, R1
// R0 ← 46h
XOR
XOR
XOR
XOR
R0, @ID0
R0, @[ID0-2]
R0, @[ID0+3]!
R0, @[ID0-5]!
// R0 ← R0 ^ DM[8080h], IDL0 ← 81h
// R0 ← R0 ^ DM[807Eh], IDL0 ← 7Eh
// R0 ← R0 ^ DM[8083h], IDL0 ← 80h
// R0 ← R0 ^ DM[807Bh], IDL0 ← 80h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed
explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
7-97
INSTRUCTION SET
S3CK11F/FK11F (Preliminary Spec)
NOTES
7-98
S3CK11F/FK11F (Preliminary Spec)
8
CLOCK CIRCUIT
CLOCK CIRCUIT
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— External crystal, ceramic resonator, or RC oscillation source (or an external clock source)
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (fOSC divided by 1, 2, 4, 8, 16, 32, 64, 128)
— System clock control register, PCON
— Oscillator control register, OSCCON
C1
XIN
S3CK11F
C2
XOUT
RC/X-tal
Figure 8-1. Main Oscillator Circuit (Crystal or Ceramic Oscillator)
8-1
CLOCK CIRCUIT
S3CK11F/FK11F (Preliminary Spec)
XIN
S3CK11F
XOUT
VDD
RC/X-tal
Figure 8-2. Main Oscillator Circuit (RC Oscillator)
C1
XTIN
S3CK11F
C2
XTOUT
Figure 8-3. Sub Oscillator Circuit (Crystal or Ceramic Oscillator)
8-2
S3CK11F/FK11F (Preliminary Spec)
INT
CLOCK CIRCUIT
Stop Release
Stop Release
Main-System
Oscillator
Circuit
fx
fxt
Sub-System
Oscillator
Circuit
INT
Watch Timer
LCD Controller
Selector 1
Stop
fxx
OSCCON.3
Stop
OSCCON.0
1/1 - 1/4096
Frequency
Dividing
Circuit
1/1
PCON.2 - .0
1/2
1/4
1/8
1/16 1/32 1/64 1/128
OSCCON.2
Basic Timer,
Timer/Counter 0,1,2
Watch Timer
LCD Controller
SIO
A/D Converter
D/A Converter
Amplifiers and PGC
Multiplier
Two PWM modules
Selector 2
CPU
SYS #05H
SYS #0AH
Idle
Stop
Oscillator
Control
Circuit
CPU Stop Signal
by Idle or Stop
Figure 8-4. System Clock Circuit Diagram
8-3
CLOCK CIRCUIT
S3CK11F/FK11F (Preliminary Spec)
Power Control Register (PCON)
02H, R/W, Reset: 04H
MSB
.7
.6
.5
.4
Not used
.3
.2
.1
.0
LSB
System clock selection bits:
000 = fxx/128
001 = fxx/64
010 = fxx/32
011 = fxx/16
100 = fxx/8
101 = fxx/4
110 = fxx/2
111 = fxx/1
Figure 8-5. Power Control Register (PCON)
Oscillator Control Register (OSCCON)
03H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
System clock source selection bit:
0 = Main oscillator select
1 = Sub oscillator select
Not used
Not used
Sub oscillator control bit:
0 = Sub oscillator RUN
1 = Sub oscillator STOP
Main oscillator control bit:
0 = Main oscillator RUN
1 = Main oscillator STOP
Figure 8-6. Oscillator Control Register (OSCCON)
8-4
S3CK11F/FK11F (Preliminary Spec)
9
RESET AND POWER-DOWN
RESET AND POWER-DOWN
OVERVIEW
During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The
RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings MCU into a known operating status.
For the time for CPU clock oscillation to stabilize, the RESET pin must be held to low level for a minimum time
interval after the power supply comes within tolerance. For the minimum time interval, see the electrical
characteristics.
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watchdog function (basic timer) is enabled.
— Ports are set to input mode.
— Peripheral control and data registers are disabled and reset to their default hardware values.
— The program counter (PC) is loaded with the program reset address in the ROM, 00000H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 00000H is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, make the appropriate settings to the
watchdog timer control register, WDTCON, before entering STOP mode.
9-1
RESET AND POWER-DOWN
S3CK11F/FK11F (Preliminary Spec)
NOTES
9-2
S3CK11F/FK11F (Preliminary Spec)
10
I/O PORT
I/O PORTS
PORT 0
Port 0 High-Byte Control Register(P0CONH)
20H, R/W, Reset:00H
MSB
.7
.6
P0.7/
INT7
.5
.4
P0.6/
INT6
.3
.2
P0.5/
INT5
.1
.0
LSB
P0.4/
INT4
P0CONH bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Push-pull output mode
N-channel open-drain output mode
Figure 10-1. Port 0 High-Byte Control Register (P0CONH)
Port 0 Low-Byte Control Register (P0CONL)
21H, R/W, Reset: 00H
MSB
.7
.6
P0.3/
INT3
.5
.4
P0.2/
INT2
.3
.2
P0.1/
INT1
.1
.0
LSB
P0.0/
INT0
P0CONL bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Push-pull output mode
N-channel open-drain output mode
Figure 10-2. Port 0 Low-Byte Control Register (P0CONL)
10-1
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
Port 0 Pull-up Control Register (P0PUR)
22H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
LSB
.0
P0.7/ P0.6/ P0.5/ P0.4/ P0.3/ P0.2/ P0.1/ P0.0/
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
P0 pull-up resistor settings
0
1
NOTE:
Disable pull-up resistor
Enable pull-up resistor
The corresponding pull-up resistor is disabled automatically
when a pin of port 0 is selected only as push-pull output mode.
Figure 10-3. Port 0 Pull-up Control Register (P0PUR)
Port 0 Interrupt Control Register (P0INT)
23H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.7/ P0.6/ P0.5/ P0.4/ P0.3/ P0.2/ P0.1/ P0.0/
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
INTn bit configuration settings:
0
1
NOTE:
Disable interrupt
Enable interrupt
"n" is 0, 1, 2, 3, 4, 5, 6, and 7
Figure 10-4. Port 0 Interrupt Control Register (P0INT)
10-2
S3CK11F/FK11F (Preliminary Spec)
I/O PORT
PORT 1
Port 1 Control Register (P1CON)
24H, R/W, Reset: 00H
MSB
.7
.6
Not used
.5
.4
.3
.2
.1
.0
LSB
P1.0/T0CLK
P1.1/T0OUT/T0PWM/T0CAP
P1CON bit-triple pin configuration settings:
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Schmitt trigger Input mode (T0CAP, T0CLK)
Schmitt trigger Input mode; Pull-up resistor enable (T0CAP, T0CLK)
Push-pull output mode
N-Channel open-drain output mode
Alternative function (T0OUT/T0PWM)
Figure 10-5. Port 1 Control Register (P1CON)
10-3
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
PORT 2
Port 2 High-Byte Control Register (P2CONH)
28H, R/W, Reset: 00H
MSB
.7
.6
P2.7/
SEG56/
TBOUT
.5
.4
P2.6/
SEG57/
TAOUT
.3
.2
.1
P2.5/
SEG58/
T1CLK
.0
LSB
P2.4/
SEG59/
T2OUT
P2CONH bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger Input mode (T1CLK)
Push-pull output mode
N-Channel open-drain output mode
Alternative function
(SEG56 or TBOUT, SEG57 or TAOUT, SEG58, SEG59 or T2OUT)
Figure 10-6. Port 2 High-Byte Control Register (P2CONH)
Port 2 Low-Byte Control Register (P2CONL)
29H, R/W, Reset: 00H
MSB
.7
.6
P2.3/
SEG60/
SCK
.5
.4
P2.2/
SEG61/
SI
.3
.2
P2.1/
SEG62/
SO
.1
.0
LSB
P2.0/
SEG63/
DAO
P2CONL bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger Input mode (SCK, SI)
Push-pull output mode
N-Channel open-drain output mode
Alternative function
(SEG60 or SCK, SEG61, SEG62 or SO, SEG63 or DAO)
Figure 10-7. Port 2 Low-Byte Control Register (P2CONL)
10-4
S3CK11F/FK11F (Preliminary Spec)
I/O PORT
Port 2 Pull-up Control Register (P2PUR)
2AH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
P2.7/SEG56/TBOUT
LSB
P2.0/SEG63/DAO
P2.6/SEG57/TAOUT
P2.1/SEG62/SO
P2.5/SEG58/T1CLK
P2.2/SEG61/SI
P2.4/SEG59/T2OUT P2.3/SEG60/SCK
P2 pull-up resistor settings:
0
1
NOTE:
Disable pull-up resistor
Enable pull-up resistor
The corresponding pull-up resistor is disabled automatically
when a pin of port 2 is selected only as push-pull output mode or
the SEG pin of alternative function.
Figure 10-8. Port 2 Pull-up Control Register (P2PUR)
Port 2 Alternative Function Selection Register (P2FUNC)
2BH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
Not used
.1
.0
LSB
P2.0/SEG63/DAO
P3.7/SEG55/BUZ
P2.7/SEG56/TBOUT
P2.6/SEG57/TAOUT
P2.1/SEG62/SO
P2.3/SEG60/SCK
P2.4/SEG59/T2OUT
P2FUNC bit configuration settings:
0
1
Select SEG63, SEG62, SEG60, SEG59, SEG57, SEG56, and SEG55
Select DAO, SO, SCK, T2OUT, TAOUT, TBOUT, and BUZ
Figure 10-9. Port 2 Alternative Function Selection Register (P2FUNC)
10-5
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
PORT 3
Port 3 High-Byte Control Register (P3CONH)
2CH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.6/SEG54 P3.5/SEG53 P3.4/SEG52
P3.7/
SEG55/BUZ
P3CONH bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Push-pull output mode
N-Channel open-drain output mode
Alternative function (SEG55 or BUZ, SEG54, SEG53, and SEG52)
Figure 10-10. Port 3 High-Byte Control Register (P3CONH)
Port 3 Low-Byte Control Register (P3CONL)
2DH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.3/SEG51 P3.2/SEG50 P3.1/SEG49 P3.0/SEG48
P3CONL bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Push-pull output mode
N-Channel open-drain output mode
Alternative function (SEG51, SEG50, SEG49, and SEG48)
Figure 10-11. Port 3 Low-Byte Control Register (P3CONL)
10-6
S3CK11F/FK11F (Preliminary Spec)
I/O PORT
Port 3 Pull-up Control Register (P3PUR)
2EH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
P3.7/SEG55/BUZ
.0
LSB
P3.0/SEG48
P3.6/SEG54
P3.1/SEG49
P3.5/SEG53
P3.2/SEG50
P3.4/SEG52 P3.3/SEG51
P3 pull-up resistor settings:
0
1
NOTE:
Disable pull-up resistor
Enable pull-up resistor
The corresponding pull-up resistor is disabled automatically
when a pin of port 3 is selected only as push-pull output mode
or the SEG pin of alternative function.
Figure 10-12. Port 3 Pull-up Control Register (P3PUR)
10-7
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
PORT 4
Port 4 High-Byte Control Register (P4CONH)
30H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
P4.7/SEG47 P4.6/SEG46
.3
.2
.1
.0
LSB
P4.5/SEG45 P4.4/SEG44
P4CONH bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Push-pull output mode
N-Channel open-drain output mode
Alternative function (SEG47, SEG46, SEG45, and SEG44)
Figure 10-13. Port 4 High-Byte Control Register (P4CONH)
Port 4 Low-Byte Control Register (P4CONL)
31H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
P4.3/SEG43 P4.2/SEG42
.3
.2
.1
.0
LSB
P4.1/SEG41 P4.0/SEG40
P4CONL bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Push-pull output mode
N-Channel open-drain output mode
Alternative function (SEG43, SEG42, SEG41, and SEG40)
Figure 10-14. Port 4 Low-Byte Control Register (P4CONL)
10-8
S3CK11F/FK11F (Preliminary Spec)
I/O PORT
Port 4 Pull-up Control Register (P4PUR)
32H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
P4.7/SEG47
.0
LSB
P4.0/SEG40
P4.6/SEG46
P4.1/SEG41
P4.5/SEG45
P4.4/SEG44
P4.2/SEG42
P4.3/SEG43
P4 pull-up resistor settings:
0
1
NOTE:
Disable pull-up resistor
Enable pull-up resistor
The corresponding pull-up resistor is disabled automatically
when a pin of port 4 is selected only as push-pull output mode
or alternative function.
Figure 10-15. Port 4 Pull-up Control Register (P4PUR)
10-9
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
PORT 5
Port 5 High-Byte Control Register (P5CONH)
34H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
P5.7/SEG39 P5.6/SEG38 P5.5/SEG37
.1
.0
LSB
P5.4/SEG36
P5CONH bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Push-pull output mode
N-Channel open-drain output mode
Alternative function (SEG39, SEG38, SEG37, and SEG36)
Figure 10-16. Port 5 High-Byte Control Register (P5CONH)
Port 5 Low-Byte Control Register (P5CONL)
35H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
P5.3/SEG35 P5.2/SEG34 P5.1/SEG33
.1
.0
LSB
P5.0/SEG32
P5CONH bit-pair pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Push-pull output mode
N-Channel open-drain output mode
Alternative function (SEG35, SEG34, SEG33, and SEG32)
Figure 10-17. Port 5 Low-Byte Control Register (P5CONL)
10-10
S3CK11F/FK11F (Preliminary Spec)
I/O PORT
Port 5 Pull-up Control Register (P5PUR)
36H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
P5.7/SEG39
.0
LSB
P5.0/SEG32
P5.6/SEG38
P5.1/SEG33
P5.5/SEG37
P5.4/SEG36
P5.2/SEG34
P3.3/SEG35
P5 pull-up resistor settings:
0
1
NOTE:
Disable pull-up resistor
Enable pull-up resistor
The corresponding pull-up resistor is disabled automatically
when a pin of port 5 is selected only as push-pull output mode
or alternative function.
Figure 10-18. Port 5 Pull-up Control Register (P5PUR)
10-11
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
PORT 6
Port 6 Control Register (P6CON)
37H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
Not used
.2
.1
.0
LSB
P6.3/SEG27 - P6.0/SEG24
P6.7/SEG31 - P6.4/SEG28
P6CON nibble pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Schmitt trigger input mode; Pull-up resistor enable
Push-pull output mode
Alternative function (SEG31- SEG28, SEG27 - SEG24)
Figure 10-19. Port 6 Control Register (P6CON)
PORT 7
Port 7 Control Register (P7CON)
38H, R/W, Reset: 00H
MSB
.7
.6
.5
Not used
.4
.3
.2
.1
.0
LSB
P7.3/SEG19 - P7.0/SEG16
P7.7/SEG23 - P7.4/SEG20
P7CON nibble pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Schmitt trigger input mode; Pull-up resistor enable
Push-pull output mode
Alternative function (SEG23- SEG20, SEG19 - SEG16)
Figure 10-20. Port 7 Control Register (P7CON)
10-12
S3CK11F/FK11F (Preliminary Spec)
I/O PORT
PORT 8
Port 8 Control Register (P8CON)
39H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
Not used
.2
.1
.0
LSB
P8.3/SEG11 - P8.0/SEG8
P8.7/SEG15 - P8.4/SEG12
P8CON nibble pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Schmitt trigger input mode; Pull-up resistor enable
Push-pull output mode
Alternative function (SEG15 - SEG12, SEG11 - SEG8)
Figure 10-21. Port 8 Control Register (P8CON)
PORT 9
Port 9 Control Register (P9CON)
3AH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
Not used
.1
.0
LSB
P9.3/SEG3 - P9.0/SEG0
P9.7/SEG7 - P9.4/SEG4
P9CON nibble pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Schmitt trigger input mode; Pull-up resistor enable
Push-pull output mode
Alternative function (SEG7 - SEG4, SEG3 - SEG0)
Figure 10-22. Port 9 Control Register (P9CON)
10-13
I/O PORT
S3CK11F/FK11F (Preliminary Spec)
PORT 10
Port 10 Control Register (P10CON)
3BH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
Not used
.2
.1
.0
LSB
P10.3/COM11 - P10.0/COM8
P10.7/COM15 - P10.4/COM12
P10CON nibble pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Schmitt trigger input mode; Pull-up resistor enable
Push-pull output mode
Alternative function (COM15 - COM12, COM11 - COM8)
Figure 10-23. Port 10 Control Register (P10CON)
PORT 11
Port 11 Control Register (P11CON)
3CH, R/W, Reset: 00H
MSB
.7
.6
.5
Not used
.4
.3
.2
.1
.0
LSB
P11.3/COM3 - P11.0/COM0
P11.7/COM7 - P11.4/COM4
P11CON nibble pin configuration settings:
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Schmitt trigger input mode; Pull-up resistor enable
Push-pull output mode
Alternative function (COM7 - COM4, COM3 - COM0)
Figure 10-24. Port 11 Control Register (P11CON)
10-14
S3CK11F/FK11F (Preliminary Spec)
11
BASIC TIMER/WATCHDOG TIMER
BASIC TIMER/WATCHDOG TIMER
OVERVIEW
WDTCON controls basic timer clock selection and watchdog timer clear bit.
Basic timer is used in two different ways:
•
As a clock source to watchdog timer to provide an automatic reset mechanism in the event of a system
malfunction (When watchdog function is enabled in ROM code option)
•
To signal the end of the required oscillation stabilization interval after a reset or stop mode release.
The reset value of basic timer clock selection bits is decided by the ROM code option. (see the section on ROM
code option for details). After reset, programmer can select the basic timer input clock using WDTCON.
When watchdog function is enabled by the ROM code option, programmer must set WDTCON.0 periodically
within every 2048 × basic timer input clock time to prevent system reset.
Watchdog Timer Control Register (WDTCON)
0DH, R/W, Reset: X0H
MSB
.7
Not used
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Basic timer counter clock selection bits:
Watchdog timer clear bit:
000 = fxx/2
0 = don't care
001 = fxx/4
1 = clear watchdog timer counter
010 = fxx/16
011 = fxx/32
Basic timer counter clear bit:
100 = fxx/128
0 = don't care
101 = fxx/256
1 = clear basic timer counter
110 = fxx/1024
111 = fxx/2048
NOTE:
Under the reset operation, basic timer input clock source is effected
by RCOD_OPT.14-.12. After reset, it can be selected basic timer clock
source by writing appropriate value to WDTCON.6-.4.
Figure 11-1. Watchdog Timer Control Register (WDTCON)
11-1
BASIC TIMER/WATCHDOG TIMER
S3CK11F/FK11F (Preliminary Spec)
BLOCK DIAGRAM
Data Bus
RCOD_OPT .14, .13, .12
RESET
MUX
WDTCON.6, .5, .4
Reset or Stop
fxx/2048
Data Bus
fxx/1024
fxx/256
Clear
fxx/128
fxx/32
MUX
fb
8-Bit Basic Timer
Counter (Read Only)
fxx/16
BT OVF
Bit 5
BT INT
(NOTE)
fxx/4
fxx/2
OVF (System Reset)
3-Bit Watchdog
Timer Counter
RCOD_OPT.11
Clear
WDTCON.0
NOTE:
Reset
STOP
IDLE
CPU start signal (Bit 5 = 1/fb x 32) (Power down release)
Figure 11-2. Basic Timer & Watchdog Timer Functional Block Diagram
11-2
IRQ0.5
S3CK11F/FK11F (Preliminary Spec)
12
WATCH TIMER
WATCH TIMER
OVERVIEW
The source of watch timer is fx/128 (main osc.) or fxt (sub osc.). The interval of watch timer interrupt can be
selected by WTCON.3-2.
Table 12-1. Watch Timer Control Register (WTCON): 8-Bit R/W
Bit Name
Values
WTCON.7 - .6
WTCON.5-.4
WTCON.3 - .2
WTCON.1
WTCON.0
–
Function
Not used.
0
0
0.5 kHz buzzer (BUZ) signal output
0
1
1 kHz buzzer (BUZ) signal output
1
0
2 kHz buzzer (BUZ) signal output
1
1
4 kHz buzzer (BUZ) signal output
0
0
Set watch timer interrupt to 1 sec.
0
1
Set watch timer interrupt to 0.5 sec.
1
0
Set watch timer interrupt to 0.25 sec.
1
1
Set watch timer interrupt to 3.91 msec.
0
Select fx/128 as the watch timer clock.
1
Select fxt (sub osc) as the watch timer clock.
0
Disable watch timer: clear frequency dividing circuits.
1
Enable watch timer.
Address
50H
NOTES:
1. The main clock frequency (fx) is assumed to be 4.19 MHz.
2. The watch timer clock frequency (fw) is assumed to be 32.768 kHz.
12-1
WATCH TIMER
S3CK11F/FK11F (Preliminary Spec)
WATCH TIMER CIRCUIT DIAGRAM
WTCON .4-.5
fw/26 (0.5 kHz)
fw/25 (1 kHz)
fw/24 (2 kHz)
Buzzer Output
MUX
fw/23 (4 kHz)
fw/27
fxt
fx/128
Clock
Selector
fw
Frequency
Dividing
Circuit
fw/213
fw/214
Overflow
Selector
Circuit
fw/215 (1Hz)
fLCD = 4096 Hz
WTCON .1
WTCON .0
WTCON .2-.3
fx = Main clock (4.19 MHz)
fxt = Sub clock (32.768 kHz)
fw = Watch timer clock
Figure 12-1. Watch Timer Circuit Diagram
12-2
WT INT
IRQ1.0
S3CK11F/FK11F (Preliminary Spec)
13
8-BIT TIMER 0
8-BIT TIMER 0
OVERVIEW
The 8-bit timer 0 is an 8-bit general-purpose timer/counter. Timer 0 has three operating modes, one of which you
select using the appropriate T0CON setting:
— Interval timer mode (Toggle output at T0OUT pin)
— Capture input mode with a rising or falling edge trigger at the T0CAP pin
— PWM mode (T0PWM)
Timer 0 has the following functional components:
— Clock frequency divider (fxx divided by 4096, 256, 16 or 1) with multiplexer
— External clock input pin (T0CLK)
— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
— I/O pins for capture input (T0CAP), or PWM or match output (T0PWM, T0OUT)
— Timer 0 overflow interrupt (IRQ0.1) and match/capture interrupt (IRQ0.0) generation
— Timer 0 control register, T0CON (42H, read/write)
13-1
8-BIT TIMER 0
S3CK11F/FK11F (Preliminary Spec)
FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0.0, IRQ0.1)
The timer 0 module can generate two interrupts, the timer 0 overflow interrupt (T0OVF), and the timer 0
match/capture interrupt (T0INT). T0OVF is interrupt level IRQ0.1. T0INT belongs to interrupt level IRQ0.0.
Interval Timer Function
In interval timer mode, a match signal is generated and T0OUT is toggled when the counter value is identical to
the value written to the T0 reference data register, T0DATA. The match signal generates a timer 0 match
interrupt (T0INT) and clears the counter.
If, for example, you write the value 10H to T0DATA and 03H to T0CON, the counter will increment until it
reaches 10H. At this point, the T0 interrupt request is generated, the counter value is reset, and counting
resumes.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter
but can generate a match interrupt. The counter runs continuously, overflowing at FFH, and then repeat the
incrementing from 00H. Whenever an overflow is occurred, an overflow (OVF) interrupt can be generated.
Although you can use the match or the overflow interrupt in PWM mode, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data
value is less than or equal to (≤) the counter value and then pulse is held to High level for as long as the data
value is greater than (>) the counter value. One pulse width is equal to tCLK .
Capture Mode
In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter
value into the T0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source, the signal edge at the T0CAP pin. You select the capture input by
setting the value of the timer 0 capture input selection bit in the port 1 control register, P1CON(24H). When
P1CON.5-.3 is 000, the T0CAP input or normal input is selected .When P1CON.5-.3 is set to 010, normal output
is selected.
Both kinds of timer 0 interrupts can be used in capture mode, the timer 0 overflow interrupt is generated
whenever a counter overflow occurs, the timer 0 match/capture interrupt is generated whenever the counter
value is loaded into the T0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,
you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin.
13-2
S3CK11F/FK11F (Preliminary Spec)
8-BIT TIMER 0
TIMER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
T0CON is located at address 42H, and is read/written addressable.
A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, and selects an input clock
frequency of fxx/4096. To disable the counter operation, please set T0CON.0 to 0B. You can clear the timer 0
counter at any time during normal operation by writing a "1" to T0CON.1.
Timer 0 Control Register (T0CON)
42H, R/W, Reset: 00H
MSB
.7
.6
.5
Timer 0 input clock selection bits:
000 = fxx/4096
001 = fxx/256
010 = fxx/16
011 = fxx/1
1xx = External clock (at T0CLK pin)
other values = Not available
.4
Not used
.3
.2
.1
.0
LSB
Timer 0 counter enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter(when write)
Timer 0 operating mode selection bits:
00 = Interval mode
01 = Capture mode (capture on rising edge, counter running, OVF can occur)
10 = Capture mode (capture on falling edge, counter running, OVF can occur)
11 = PWM mode (OVF & match interrupt can occur)
Figure 13-1. Timer 0 Control Register (T0CON)
13-3
8-BIT TIMER 0
S3CK11F/FK11F (Preliminary Spec)
BLOCK DIAGRAM
Overflow INT
IRQ0.1
T0CON.7-.5
T0CON.0
Data Bus
T0CON.1
1/4096
Clear
1/256
1/16
T0CLK
1/1
P1.0
T0CAP
P1.1
MUX
8-bit Up-Counter
(T0CNT, Read only)
R
Match
M
U
X
8-bit Comparator
M
U
X
T0OUT/T0PWM
Timer 0 Buffer Register
P1.1
T0CON.3-.2
Match signal
T0CLR
T0OVF
T0CON.3-.2
Timer 0 Data Register
(T0DATA, Read/write)
Data Bus
Figure 13-2. Timer 0 Functional Block Diagram
13-4
Match or capture INT
IRQ0.0
S3CK11F/FK11F (Preliminary Spec)
8-BIT TIMER 0
Timer 0 Counter Register (T0CNT)
40H, R, Reset Value: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
.0
LSB
Timer 0 Data Register (T0DATA)
41H, R/W, Reset Value: FFH
MSB
.7
.6
.5
.4
.3
.2
.1
Figure 13-3. Timer 0 Counter and Data Registers (T0CNT, T0DATA)
13-5
8-BIT TIMER 0
S3CK11F/FK11F (Preliminary Spec)
NOTES
13-6
S3CK11F/FK11F (Preliminary Spec)
16-BIT TIMER 1 (8-BIT TIMER A & B)
16-BIT TIMER 1 (8-BIT TIMER A & B)
S3CK11F/FK11F (Preliminary Spec)
TIMER 1/B CONTROL REGISTER (TBCON)
49H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.0
LSB
Timer 1/B operation enable bit:
0 = Disable counting operation
1 = Enable counting operation
Not used
Timer B input clock selection bits:
00 = fxx/4096
01 = fxx/512
10 = fxx/64
11 = fxx/8
.1
Timer 1/B counter clear bit:
0 = No effect
1 = Clear the timer B (when write)
Timer 1/B mode selection bits:
0 = 8-bit operation mode
1 = 16-bit operation mode
Always logic "0"
NOTE: At 16-bit operation mode, 16-bit counter clock input is selected by TACON .6 - .4
Figure 14-2. Timer 1/B Control Register (TBCON)
14-2
S3CK11F/FK11F (Preliminary Spec)
16-BIT TIMER (8-BIT TIMER A & B)
Data Bus
TACON .1
TBCON .1
8
Timer A Data Register
(Read/Write)
MUX
TBCON .2
TBCON .2
TBCON .0
TACON .0
TACON 6, 5, 4
Timer A Buffer Register
fxx/4096
fxx/64
fxx/8
fxx/1
Interval
Output Gen.
8-Bit Comparator
fxx/512
M
U
X
TAOUT
TAINT
TACNT (8-Bit
Up-Counter, Read Only)
IRQ0.2
T1CLK
TBCON .2
TBCON 5, 4
8-Bit Comparator
fxx/4096
fxx/512
fxx/64
M
U
X
1
MUX
TBCNT (8-Bit
Up-Counter, Read Olny)
0
Interval
Output Gen.
fxx/8
Timer B Buffer Register
TBCON .2
TBCON .0
Timer B Data Register
(Read/Write)
TBOUT
IRQ0.3
TBINT
T1INT
TBCON .1
8
Data Bus
Figure 14-3. Timer A, 1/B Function Block Diagram
14-3
16-BIT TIMER 1 (8-BIT TIMER A & B)
S3CK11F/FK11F (Preliminary Spec)
NOTES
14-4
S3CK11F/FK11F (Preliminary Spec)
15
8-BIT TIMER 2
8-BIT TIMER 2
OVERVIEW
The 8-bit timer 2 is an 8-bit general-purpose timer. Timer 2 has the interval timer mode by using the appropriate
T2CON setting.
Timer 2 has the following functional components:
— Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer
— 8-bit counter (T2CNT), 8-bit comparator, and 8-bit reference data register (T2DATA)
— Timer 2 interrupt (IRQ0.4) generation
— Timer 2 control register, T2CON (4CH, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer 2 module can generate an interrupt, the timer 2 match interrupt (T2INT). T2INT belongs to interrupt
level IRQ0.4.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to
the T2 reference data registers, T2DATA. The match signal generates a timer 2 match interrupt (T2INT) and
clears the counter.
If, for example, you write the value 10H to T2DATA and 03H to T2CON, the counter will increment until it
reaches 10H. At this point, the T2 interrupt request is generated, the counter value is reset, and counting
resumes.
15-1
8-BIT TIMER 2
S3CK11F/FK11F (Preliminary Spec)
TIMER 2 CONTROL REGISTER (T2CON)
You use the timer 2 control register, T2CON, to
— Enable the timer 2 operating (interval timer)
— Select the timer 2 input clock frequency
— Clear the timer 2 counter, T2CNT
T2CON is located, at address 4CH, and is read/written addressable.
A reset clears T2CON to "00H". This sets timer 2 to disable interval timer mode, selects the fxx/256. You can
clear the timer 2 counter at any time during normal operation by writing a "1" to T2CON.1.
Timer 2 Control Register
4CH, R/W, RESET; 00H
MSB
.7
.6
.5
Timer 2 input clock selection bits:
00 = fxx/256
01 = fxx/64
10 = fxx/8
11 = fxx
NOTE:
.4
.3
Not used
.2
.1
.0
LSB
Timer 2 count enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 2 counter clear bit:
0 = No affect
1 = Clear the timer 2 counter (when write)
For normal operation T2CON.0 bit must be set 1.
Figure 15-1. Timer 2 Control Register (T2CON)
15-2
S3CK11F/FK11F (Preliminary Spec)
8-BIT TIMER 2
BLOCK DIAGRAM
T2CON .7-.6
Data Bus
T2CON.0
1/256
T2CON.1
LSB
Clear
1/64
1/8
MSB
T2CNT
(8-bit up-Counter)
MUX
R
Match
1/1
T2INT
8-bit Comparator
LSB
MSB
IRQ0.4
T2OUT
T2DATA
BUFFER
Match Signal
T2CLR
T2DATA
REGISTER
Data Bus
Figure 15-2. Timer 2 Functional Block Diagram
15-3
8-BIT TIMER 2
S3CK11F/FK11F (Preliminary Spec)
Timer 2 Counter Register (T2CNT)
4AH, R, Reset Value: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Figure 15-3. Timer 2 Counter Register (T2CNT)
Timer 2 Data Register (T2DATA)
4BH, R/W, Reset Value: FFH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
Figure 15-4. Timer 2 Data Register (T2DATA)
15-4
LSB
S3CK11F/FK11F (Preliminary Spec)
16
SERIAL I/O INTERFACE
SERIAL I/O INTERFACE
OVERVIEW
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
PROGRAMMING PROCEDURE
To program the SIO modules, follow these basic steps:
1. Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P2CONL and P2FUNC
registers, if necessary.
2. Load an 8-bit value to the SIOCON register to properly configure the serial I/O module. In this operation,
SIOCON.2 must be set to "1" to enable the data shifter.
3. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift
operation starts.
16-1
SERIAL I/O INTERFACE
S3CK11F/FK11F (Preliminary Spec)
SIO CONTROL REGISTER (SIOCON)
Serial I/O Module Control Register (SIOCON)
4DH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
SIO shift clock select bit:
0 = Internal clock (P.S clock)
1 = External clock (SCK)
SIO shift operation enable bit:
0 = Disable shifter and clock
1 = Enable shfter and clock
Data direction control bit:
0 = MSB-first
1 = LSB-first
SIO mode selction bit:
0 = Rececive-only mode
1 = Transmit/receive mode
SIO counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting
Shift clock edge selction bit:
0 = Tx at falling edge, Rx at rising edge
1 = Tx at rising edge, Rx at falling edge
Figure 16-1. Serial I/O Module Control Registers (SIOCON)
SIO PRE-SCALER REGISTER (SIOPS)
The value stored in the SIO pre-scaler registers, SIOPS, lets you determine the SIO clock rate (baud rate) as
follows:
Baud rate = Input clock( fxx/4)/(Pre-scaler value + 1), or, SCK input clock
where fxx is a selected clock.
SIO Pre-scaler Register (SIOPS)
4EH,R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
Baud rate = (fxx/4)/(SIOPS + 1)
Figure 16-2. SIO Pre-scaler Register (SIOPS)
16-2
LSB
S3CK11F/FK11F (Preliminary Spec)
SERIAL I/O INTERFACE
BLOCK DIAGRAM
CLK
SIOCON.7
(Shift Clock
Source Select)
IRQ0.7
(SIO INT)
3-Bit Counter
Clear
SIOCON.3
SIOCON.4
(Edge Select)
SIOCON.2
(Shift Enable)
SCK
SIOPS
fxx/2
8-Bit P.S
MUX
1/2
SIOCON.5
(Mode Select)
CLK 8-Bit SIO Shift Buffer
(SIODATA)
8
SO
SIOCON.6
(LSB/MSB First
Mode Select)
SI
Data Bus
Figure 16-3. SIO Function Block Diagram
16-3
SERIAL I/O INTERFACE
S3CK11F/FK11F (Preliminary Spec)
SERIAL I/O TIMING DIAGRAM
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQ0.7
Set SIOCON.3
Figure 16-4. Serial I/O Timing in Transmit/Receive Mode(Tx at falling, SIOCON.4 = 0)
SCK
SI
D17
D16
D15
D14
D13
D12
D11
D10
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQ0.7
Set SIOCON.3
Figure 16-5. Serial I/O Timing in Transmit/Receive Mode(Tx at rising, SIOCON.4 = 1)
16-4
S3CK11F/FK11F (Preliminary Spec)
17
LOW VOLTAGE RESET
LOW VOLTAGE RESET
OVERVIEW
The low voltage reset block is useful for an system reset under the specific voltage of system. The components
of LVR block are:
— LVREN pin
— Reference voltage generator
— Voltage divider
— Comparator
— Glitch filter
LVREN PIN
A LVREN pin is used to enable or disable LVR function.
The LVR function is disabled when the LVREN pin is connected to VSS and is enabled when the LVREN pin is
connected to VDD.
BLOCK DIAGRAM
Start Up
Reference
Voltage
Generator
Comparator
Glitch Filter
RESET
Voltage
Divider
Figure 17-1. Low Voltage Reset Block Diagram
17-1
LOW VOLTAGE RESET
S3CK11F/FK11F (Preliminary Spec)
NOTES
17-2
S3CK11F/FK11F (Preliminary Spec)
18
LCD CONTROLLER/DRIVER
LCD CONTROLLER/DRIVER
OVERVIEW
The S3CK11F microcontroller can directly drive an up-to-1024-dot (64 segments × 16 commons) LCD panel. Its
LCD block has the following components:
— LCD controller/driver
— Display RAM for storing display data
— 64 segment output pins (SEG0–SEG63)
— 16 common output pins (COM0–COM15)
— Internal resistors circuit for LCD bias
To use the LCD controller/driver, the watch timer must be enabled by setting WTCON.0 to "1" because fLCD for
LCD controller/driver clock source is supplied by the watch timer.
When a sub clock is selected as the watch timer clock source and watch timer is enabled, the LCD display can
be enabled even during stop and idle modes.
The LCD clock source speed, duty, bias, LCD dividing resistors, and display on or off are determined by bit
settings in the LCD control register, LCON, at address 51H.
Data written to the LCD display RAM can be transferred to the segment signal pins automatically without
program control.
8
Data Bus
8
LCD
Controller/
Driver
8
56
8
COM0-COM7/P11.0 -P11.7
COM8-COM15/P10.0-P10.7
SEG0-SEG55/P9.0 - P3.7
SEG56-SEG63/P2.7 - P2.0
Figure 18-1. LCD Function Diagram
18-1
LCD CONTROLLER/DRIVER
S3CK11F/FK11F (Preliminary Spec)
LCD CIRCUIT DIAGRAM
SEG63/P2.0
Port
Latch
SEG/Port
Driver
SEG56/P2.7
SEG55/P3.7
Data BUS
SEG0/P9.0
LCD
Display
RAM
(480H - 4FFH)
COM/Port
Driver
COM15/P10.7
COM14/P10.6
COM0/P11.0
fLCD
Timing
Controller
LCON
Figure 18-2. LCD Circuit Diagram
18-2
LCD
Voltage
Controller
S3CK11F/FK11F (Preliminary Spec)
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA
Ram addresses 80H–FFH of page 4 is used as LCD data memory. When the bit value of a display segment is
"1", the LCD display is turned on; when the bit value is "0", the display is turned off.
Display RAM data are sent out through segment pins SEG0-SEG63 using a direct memory access (DMA)
method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD
display can be allocated to general-purpose use.
4FAH
4FCH
4FEH
4FFH
S
E
G
6
3
4FBH
S
E
G
6
2
4FDH
4F8H
b7
4F9H
COM15
4F4H
4F6H
b6
4F7H
b5
COM14
4F2H
COM13
4F5H
b4
4F3H
b3
COM12
492H
COM11
490H
b2
S
E
G
6
1
493H
b1
S
E
G
6
0
491H
COM9
COM10
S
E
G
5
9
48EH
b0
S
E
G
5
8
48CH
b7
COM8
S
E
G
5
7
48FH
COM7
S
E
G
9
48DH
b6
S
E
G
8
488H
COM6
S
E
G
7
48AH
b5
S
E
G
6
489H
COM5
S
E
G
5
48BH
b4
486H
COM4
487H
b3
484H
b2
COM3
482H
COM2
S
E
G
4
485H
b1
S
E
G
3
483H
b0
COM1
S
E
G
2
480H
COM0
S
E
G
1
481H
S
E
G
0
Figure 18-3. LCD Display Data RAM Organization
18-3
LCD CONTROLLER/DRIVER
S3CK11F/FK11F (Preliminary Spec)
LCD CONTROL REGISTER (LCON)
The LCD control register for the LCD controller/driver is called LCON. LCON is located at address 51H. It has the
following control functions:
— LCD duty selection
— LCD bias selection
— LCD clock selection
— LCD dividing resistors selection for bias
— LCD display control
The LCD control register, LCON is used to turn the LCD display on/off, to select duty and bias, to select LCD
clock, and to select dividing resistors for bias. Following a RESET, all LCON values are cleared to "0". This turns
off the LCD display, select 1/4 bias and 1/8 duty, and select normal LCD dividing resistors.
The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also
referred as the frame frequency. Since the LCD clock signal is generated by the watch timer clock (fw), the watch
timer must be enabled when the LCD display is turned on.
LCD Control Register (LCON)
51H, R/W, RESET; 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
LCD display control bit:
0 = Turn off the LCD display
1 = Turn on the LCD display
Not used
LCD bias selection bit:
0 = 1/4 bias
1 = 1/5 bias
LCD dividing resistors selection bit:
0 = Normal LCD dividing resistors
1 = Diminish LCD dividing resistors
to strengthen LCD drive
LCD duty selection bits:
00 = 1/8 duty (COM0-COM7 select)
01 = 1/12 duty (COM0-COM11 select)
10 = 1/16 duty (COM0-COM15 select)
11 = Not available
LCD clock selection bits: (When fw is 32.768kHz)
.5 .4
1/8 duty
(COM0-COM7)
1/12 duty
(COM0-COM11)
1/16 duty
(COM0-COM15)
0
0
1
1
fw/27 (256 Hz)
fw/26 (512 Hz)
fw/25 (1024 Hz)
fw/24 (2048 Hz)
fw/26 (512 Hz)
fw/25 (1024 Hz)
fw/24 (2048 Hz)
fw/23 (4096 Hz)
fw/26 (512 Hz)
fw/25 (1024 Hz)
fw/24 (2048 Hz)
fw/23 (4096 Hz)
0
1
0
1
Figure 18-4. LCD Control Register (LCON)
18-4
S3CK11F/FK11F (Preliminary Spec)
LCD CONTROLLER/DRIVER
S3CK11F
VDD
LCON.0
VLC1
R
Fixed
VLC2
R
VLC3
R
LCON.6
VLCD = VDD
VLC4
R
VLC5
R
VSS
NOTES:
1. When the LCD module is turned off, clear LCON.0 to "0" to reduce power consumption.
2. The value of resistors is selected by LCON.1.
Figure 18-5. LCD Voltage Dividing Resistors Connection
18-5
LCD CONTROLLER/DRIVER
S3CK11F/FK11F (Preliminary Spec)
COMMON (COM) SIGNALS
The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
— In 1/8 duty mode, COM0–COM7 pins are selected.
— In 1/12 duty mode, COM0–COM11 pins are selected.
— In 1/16 duty mode, COM0–COM15 pins are selected.
When 1/8 duty is selected by setting LCON.5–LCON.4 to "00", COM8–COM16 (P10.0–P10.7) can be used for
I/O ports, and when 1/12 duty is selected by setting LCON.5–LCON.4 to "01", COM12–COM15 (P10.4–P10.7)
can be used for I/O ports.
SEGMENT (SEG) SIGNALS
The 64 LCD segment signal pins are connected to corresponding display RAM locations at 80H–FFH of page 4.
Bits of the display RAM are synchronized with the common signal output pins.
When the bit value of a display RAM location is "1", a 'select' signal (Display ON) is sent to the corresponding
segment pin.
When the display bit is "0", a 'non-select' signal (Display Off) is sent to the corresponding segment pin.
18-6
S3CK11F/FK11F (Preliminary Spec)
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
LCD CONTROLLER/DRIVER
0 1 2 3
15 0 1 2 3
15
FR
VLC1
VSS
1 Frame
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
COM0
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
COM1
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
COM2
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
SEG0
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
S
E
G
4
Figure 18-6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)
18-7
LCD CONTROLLER/DRIVER
S3CK11F/FK11F (Preliminary Spec)
0 1 2 3
FR
15 0 1 2 3
15
VLC1
VSS
1 Frame
SEG1
SEG0-COM0
SEG1-COM0
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
VLC4
VLC5
0V
-VLC5
-VLC4
-VLC3
-VLC2
-VLC1
VLC1
VLC2
VLC3
VLC4
VLC5
0V
-VLC5
-VLC4
-VLC3
-VLC2
-VLC1
Figure 18-6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)
18-8
S3CK11F/FK11F (Preliminary Spec)
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
LCD CONTROLLER/DRIVER
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FR
VLC1
VSS
1 Frame
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
COM0
VLC1
VLC2
VLC3 (VLC4)
VLC5
VSS
COM1
VLC1
VLC2
VLC3 (VLC4)
VLC5
VSS
COM2
VLC1
VLC2
VLC3 (VLC4)
VLC5
VSS
SEG0
VLC1
VLC2
VLC3 (VLC4)
VLC5
VSS
SEG0-COM0
VLC1
VLC2
VLC3 (VLC4)
VLC5
0V
-VLC5
-VLC3 (-VLC4)
-VLC2
-VLC1
Figure 18-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
18-9
LCD CONTROLLER/DRIVER
S3CK11F/FK11F (Preliminary Spec)
NOTES
18-10
S3CK11F/FK11F (Preliminary Spec)
19
10-BIT A/D CONVERTER
10-BIT ANALOG-TO-DIGITAL CONVERTER
OVERVIEW
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
ADC input channel to equivalent 10-bit digital values. The analog input level must lie between the AVDD and
AVSS values. The A/D converter has the following components:
— Analog comparator with successive approximation logic
— D/A converter logic (resistor string type)
— ADC control register (ADCON)
— One analog data input pin (ADCIN)
— 10-bit A/D conversion data output registers (4 × 10 bits)
— Sample and hold circuit selectable.
DESCRIPTION OF ONE TIME CONVERSION MODE
The A/D converter is automatically disabled after conversion completion when ADCON.5 is logic "0". Set the
conversion start or enable bit (ADCON.0) in this mode, and conversion is started.
After end of conversion, the ADCON.0 is cleared to logic "0", the end of conversion bit (EOC bit, ADCON.4) is
set to logic "1", and the result data are loaded to ADDATA0 at a ram address 68H–69H of page 0. Remember to
read the contents of ADDATA0 before another conversion starts.
Otherwise, the previous result will be overwritten by the next conversion result. The ADC interrupt request
(IRQ1.3) can not be set to logic "1" in this mode, so the interrupt is not available.
DESCRIPTION OF CONTINUOUS CONVERSION MODE
The A/D converter is always enabled when ADCON.5 is logic "1". Set the conversion start or enable bit
(ADCON.0) in this mode, and conversion is started. After end of conversion for a time, the result data are loaded
to ADDATA0–3 at ram address 68H–6FH of page 0 in turn. The conversion is automatically restarted every 1/fs
(sampling frequency). If the ADDATA0–3 is full up, the ADC interrupt request (IRQ1.3) is set to logic "1".
Remember to read the contents of ADDATA0–3 before another conversion starts. Otherwise, the provious result
will be overwritten from the ADDATA0 by the next conversion result. The end of conversion bit (EOC bit,
ADCON.4) is not available in this mode.
NOTE
If the chip enters to power-down mode, STOP or IDLE in conversion process, there will be current path in
A/D converter block. So, It is necessary to cut off the current path before the instructions execution
enters power-down mode.
19-1
10-BIT A/D CONVERTER
S3CK11F/FK11F (Preliminary Spec)
CONVERSION TIMING
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected
for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion
requires 4 clocks, the conversion rate is calculated as follows:
4 clocks/bit × 10-bit + set-up time = 50 clocks, 50 clock × 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8)
Note that A/D converter needs at least 25 µs for conversion time.
A/D CONVERTER CONTROL REGISTER (ADCON)
The A/D converter control register, ADCON, is located at address 67H. It has three functions:
— ADC continuous enable bit (bit 5)
— End-of-conversion status detection (bit 4)
— ADC clock selection (bits 3 and 2)
— Sample and hold circuit selectable (bit 1)
— A/D operation start or disable (bit 0 )
A/D Converter Control Register (ADCON)
67H, R/W (EOC bit is read-only), Reset; 00H
MSB
.7
.6
.5
.4
Always logic zero
A/D continuous enable bit:
0 = Disable after one time conversion
when ADCON.0 is set to logic "1".
1 = Enable continuously when
ADCON.0 is set to logic "1".
End-of-conversion bit
0 = Not complete Conversion
1 = Complete Conversion
.3
.2
.1
.0
LSB
Start or disable bit
0 = Disable operation
1 = Start operation
ADCON selection bit:
0 = Select ADCIN
1 = Select ADCIN through sample and hold circuit
Clock Selection bits:
00 = fxx/8
01 = fxx/4
10 = fxx/2
11 = fxx/1
NOTES:
1.
When the sample and hold circuit is selected as ADC input (ADCON.1 = "1"),
the A/D converter should be used for continuous conversion mode only.
2.
The ADC input (ADCIN) voltage should be from 0.3AVDD to 0.7AVDD
if the sample and hold circuit is selected for ADC (ADCON.1 = "1")
Figure 19-1. A/D Converter Control Register (ADCON)
19-2
S3CK11F/FK11F (Preliminary Spec)
10-BIT A/D CONVERTER
Conversion Data Register ADDATA0-3
68H-6FH, Read Only
Address 01101xx0B
MSB
Address 01101xx1B
MSB
.7
.6
.5
.4
.3
.2
.9
.8
LSB
.1
.0
LSB
NOTES:
1.
The ADDATA0 address is 68H/69H, ADDATA1 6AH/6BH, . . . , ADDATA3 63H/6FH.
2.
The result value of AD converter is always loaded to the ADDATA0 when the one time
conversion mode is selected for AD converter.
3.
When the continuous conversion mode is selected for AD converter, the previous
values are shifted from ADDATA1 to ADDATA3 and the result value is loaded to
ADDATA0.
Figure 19-2. A/D Converter Data Register (ADDATA0-3)
INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC function block, the analog input voltage level is compared to the reference voltage. Remember the
analog reference voltage (AVDD) should be same voltage with VDD.
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AVDD.
19-3
10-BIT A/D CONVERTER
S3CK11F/FK11F (Preliminary Spec)
ADCON.0
ADCON.5
BLOCK DIAGRAM
ADCON.3-.2
fxx/8
fADC
fS
fxx/4
MUX
fxx/2
Sample
&
hold circuit
fxx/1
Enable/
Disable
Analog
Comparator
ADCIN
fADC
Clock
Divider
fADC/256
fS
Successive
Approximation
Logic & Register
EOC flag
ADCON.4
10-bit
ADCON.1
10-bit
D/A
Converter
ADCON.5
AVDD
AVSS
68H
(Initial Address)
Reload
one time
fsyn.
68H
68H
4 x 10 bits
Conversion
Result
Register
0 1 1 0 1 x x 0
OVF
NOTE:
2
ADCON.5
When the continous conversion mode is selected. The previous result values are shifted from
ADDATA1 to ADDATA3 and the current result value is loaded to ADDATA0.
The ADDATA3 is first result value of AD converter, ADDATA2 is second,
ADDATA1 is third, and ADDATA0 is 4th.
Figure 19-3. A/D Converter Functional Block Diagram
19-4
ADCINT
IRQ1.3
6FH
DATA BUS
ADCON.0
S3CK11F/FK11F (Preliminary Spec)
10-BIT A/D CONVERTER
VDD
Reference
Voltage Input
(AVDD = VDD)
R
AVDD
10 µF
+
-
C 103
Analog
Input Pin
VDD
ADCIN
S3CK11F
C 101
AVSS
NOTE:
The symbol "R" signifies an offset resistor with a value of from 50 to 100Ω.
Figure 19-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
19-5
10-BIT A/D CONVERTER
S3CK11F/FK11F (Preliminary Spec)
NOTES
19-6
S3CK11F/FK11F (Preliminary Spec)
20
D/A CONVERTER
D/A CONVERTER
OVERVIEW
The 10-bit D/A Converter (DAC) module uses successive approximation logic to convert 10-bit digital values to
1
equivalent analog levels between VDD (1 - 1024) and VSS.
This D/A Converter consists of R–2R array structure. The D/A Converter has the following components:
— R–2R array structure
— Digital-to-analog converter control register (DACON)
— Digital-to-analog converter data register (DADATAH/DADATAL)
— Digital-to-analog converter output pin (DAO)
FUNCTION DESCRIPTION
To initiate a digital-to-analog conversion procedure, you should set the digital-to-analog converter enable bit
(DACON.0).
The DACON register is located at the RAM address 3DH. You should write the digital value calculated to digitalto-analog converter data register (DADATAH/DADATAL).
NOTE
If the chip enters to power-down mode, STOP or IDLE, in conversion process, there will be current path
in D/A Converter block. So, It is necessary to cut off the current path before the instruction execution
enters power-down mode.
20-1
D/A CONVERTER
S3CK11F/FK11F (Preliminary Spec)
Data Bus
DACON.7-.6
.0
DADATA
.1
.3
.4
.5
DACON.0
fxx/8
LSB
fxx/4
fxx/2
.2
.7
.8
.9
.7
.8
.9
DAC INT
IRQ1.4
MSB
OVF
8-bit Up-Counter
MUX
.6
DACON.1
fxx/1
DAC Buffer
.0
.1
.2
.3
.4
.5
.6
DACON.0
2R
2R
NOTE:
2R
2R
2R
2R
2R
2R
2R
2R
2R
R
R
R
R
R
R
R
R
R
The DADATA is loaded to DAC buffer when DACON.1 is set to logic "1" or 8-bit up-counter is overflowed.
Figure 20-1. DAC Circuit Diagram
D/A Converter Control Register (DACON)
3DH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Enable/Disable control bit:
D/A Converter clock selection bits: Not used
0 = Disable D/AC
00: fxx/8
1 = Enable D/AC
01: fxx/4
10: fxx/2
Data converter's 8-bit up-counter clear bit:
11: fxx/1
0 = No effect
1 = Clear the 8-bit up-counter and DADATA
is loaded into the DAC buffer (when
write, automatically cleared to "0").
Figure 20-2. Digital to Analog Converter Control Register (DACON)
20-2
DAO
S3CK11F/FK11F (Preliminary Spec)
D/A CONVERTER
D/A CONVERTER DATA REGISTER (DADATAH/DADATAL)
The DAC DATA register, DADATAH/DADATAL is located at the RAM address, 3EH–3FH. DADATAH/DADATAL
specifies the digital data to generate analog voltage. A RESET initializes the DADATAH/DADATAL value to
"00H". The D/A converter output value, VDAO, is calculated by the following formula.
n
VDAO = VDD × 1024
(n = 0-1023, DADATAH/DADATAL value)
Table 20-1. DADATA Setting to Generate Analog Voltage
DADATAH.7 DADATAH.6 DADATAH.5 DADATAH.4 DADATAH.3 DADATAH.2 DADATAH.1 DADATAH.0 DADATAL.7 DADATAL.6
VDAO
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
VDD/21
0
1
0
0
0
0
0
0
0
0
VDD/22
0
0
1
0
0
0
0
0
0
0
VDD/23
0
0
0
1
0
0
0
0
0
0
VDD/24
0
0
0
0
1
0
0
0
0
0
VDD/25
0
0
0
0
0
1
0
0
0
0
VDD/26
0
0
0
0
0
0
1
0
0
0
VDD/27
0
0
0
0
0
0
0
1
0
0
VDD/28
0
0
0
0
0
0
0
0
1
0
VDD/29
0
0
0
0
0
0
0
0
0
1
VDD/210
NOTE: These are the values determined by setting just one-bit of DADATA.0-DADATA.9. Other values of DAO can be
obtained with superimposition.
Conversion Data Register (DADATAH/DADATAL)
3EH/3FH, R/W
MSB
.9
.8
.7
.6
.5
.4
.3
.2
LSB (DADATAH, 3EH)
MSB
.1
.0
-
-
-
-
-
-
LSB (DADATAL, 3FH)
These bits should be always "0".
Figure 20-3. D/A Converter Data Register (DADATAH/DADATAL)
20-3
D/A CONVERTER
S3CK11F/FK11F (Preliminary Spec)
NOTES
20-4
S3CK11F/FK11F (Preliminary Spec)
21
OPERATIONAL AMPLIFIER AND PGC
OPERATIONAL AMPLIFIER AND PGC
OVERVIEW
There are two OP AMPs and one programmable gain controller (PGC) in the S3CK11F/FK11F. The op amps are
used for filtering out the noise from input signals or for amplifying input signals. These amplifiers can be used for
another purpose. The PGC is used to adjust the gain of input signals.
The amplifiers and PGC consist of the following components:
— OP AMP1 amplifier (OP1P, OP1N, OP1OUT)
— OP AMP2 amplifier (OP2P, OP2N, OP2OUT)
— OP AMP control register (OPCON)
— Vref generator (VREF)
— Microphone power output (VMIC)
— Programmable gain controller, PGC (PGCIN, PGCOUT, 12dB,/-6dB/0dB/6dB/12dB Selectable)
OP AMP CONTROL REGISTER (OPCON)
OP AMP Control Register (OPCON)
66H, R/W, Reset: 00H
MSB
.7
.6
.5
Not used
Microphone power control bit:
0 = Low level output (VSS)
1 = High level output (VDD)
.4
.3
.2
.1
.0
LSB
OP-AMP1 amplifier control bit:
0 = Disable operation
1 = Enable operation
OP-AMP2 amplifier control bit:
0 = Disable operation
1 = Enable operation
PGC gain selection bits:
000 = -12dB
Programmable gain controller control bit:
001 = -6dB
0 = Disable operation
010 = 0dB
1 = Enable operation
011 = 6dB
100 = 12dB
other values = not available
Figure 21-1. OP AMP Control Register (OPCON)
21-1
S3CK11F/FK11F (Preliminary Spec)
OPCON.0
OPCON.1
OPCON.2
AVSS
AVDD
OPERATIONAL AMPLIFIER AND PGC
Reference
Voltage
) should be same voltage with V
DD
PGCOUT
The analog power (AV
OP2P
OP2N
VREF
NOTE:
P.G.C.
(-12, -6, 0,
6, 12dB)
OP-AMP2
OP1OUT
VMIC
OP1P
OP1N
OP-AMP1
PGCIN
MIC
Power
Controller
OP2OUT
Analog
Power
.
DD
Figure 21-2. OP AMP and PGC Block Diagram
62k
330K
82
104 3.3k
OP1N
Signal
OP1OUT 103
47k
62k
OP1P
OP-AMP1
100uF
200k
82
OP2N
OP2P
OP2OUT 104
OP-AMP2
PGCOUT
PGCIN
102
PGC
104
Figure 21-3. Application Circuit for OP-AMP and PGC
21-2
103
471
104
ADCIN
200k
VREF
S3CK11F/FK11F (Preliminary Spec)
22
PWM MODULES
PWM MODULES
OVERVIEW
The S3CK11F/FK11F microcontroller can directly drive a speaker and it has two 8-bit PWMs, PWM0 and
PWM1. The PWM0 and PWM1 have the following components :
— Clock frequency dividers (fxx divider by 8, 4, 2 or 1)
— 8-bit counters (PWM0CNT, PWM1CNT), 8-bit comparators, and data registers (PWM0DATA, PWM1DATA)
— 2-bit up-counter overflow interrupt generations
— Selectors for 5-, 6-, 7- or 8-bit PWM
— 2-bit up-counters, 2-bit comparators, and 2-bit extend data registers for extension
— 2-bit up-counters for repeat frame
— Sign control register bit
— Volume control register bits for volume control
22-1
PWM MODULES
S3CK11F/FK11F (Preliminary Spec)
FUNCTION DESCRIPTION
PWM control register (PWMCON)
The PWM control register, located at address 58H, controls PWM0/PWM1 operation, clears PWM0/PWM1
counters and extend buffers, and selects PWM0/PWM1 output. This register is read/write addressable.
A reset clears PWMCON to "00H". This sets PWM0/PWM1 to disable counting operation, and to output low level
(VSS). You can clear PWM0/PWM1 counters and extend buffers at any time during normal operation by writing a
"1" to PWMCON.0 and PWMCON.2, respectively.
PWM Control Register (PWMCON)
58H, R/W, Reset: 00H
MSB
.7
PWM modules sign contro bit:
0 = Disable sign bit
1 = Enable sign bit
.6
.5
.4
.3
.2
.1
.0
LSB
PWM0 counter clear bit:
0 = No effect
1 = Clear the PWM0's counter and extend counter
(when write, automatically cleared to "0")
Not used
PWM1 control bit:
0 = Disable PWM1's operation and
output low level (V SS) to PWM1 pin
1 = Enable PWM1's operation and
output
PWM0 control bit:
0 = Disable PWM0's operation and
output low level (V SS) to PWM0 pin
1 = Enable PWM0's operation and output
PWM1 counter clear bit:
0 = No effect
1 = Clear the PWM1's counter and extend counter
(when write, automatically cleared to "0")
Figure 22-1. PWM Control Register (PWMCON)
22-2
S3CK11F/FK11F (Preliminary Spec)
PWM MODULES
PWM0 Mode Register (PWM0MOD)
The PWM0 mode register, located at address 5AH, selects PWM0 clock, PWM0 mode (5-. 6-, 7- or 8-bit
PWM0), the number of repeat frame, and speaker volume.
This register is read/write addressable.
A reset clears PWM0MOD to "00H". This sets PWM0, to select 8-bit PWM0 mode, to select 4 times repeat
frame, to select fxx/8 and to select 1 step volume.
PWM0 Mode Register (PWM0MOD)
5AH, R/W, Reset: 00H
MSB
.7
.6
.5
PWM output high voltage (V
POH) volume control bits:
00 = 1 step volume
01 = 2 step volume
10 = 3 step volume
11 = 4 step volume (the highest volume)
.4
.3
.2
.1
.0
LSB
PWM0 Data repeat selection bit:
00 = 4 times repeat for one data
01 = 3 times repeat for one data
10 = 2 times repeat for one data
11 = 1 times repeat for one data
PWM0 mode selection bit:
00 = 8-bit PWM0 mode
PWM0 clock selection bit:01 = 7-bit PWM0 mode
10 = 6-bit PWM0 mode
00 = fxx/8
11 = 5-bit PWM0 mode
01 = fxx/4
10 = fxx/2
11 = fxx/1
Figure 22-2. PWM0 Mode Register (PWM0MOD)
22-3
PWM MODULES
S3CK11F/FK11F (Preliminary Spec)
PWM0DATA
Register
Sign Bit
Reload
Reload
Sign Bit
Buffer
PWM0DATA
Buffer
LSB
PWMMOD.7
MSB
PWM0
note(1)
8-Bit Comparator
note(2)
note(3)
PWM0MOD.5-.4
PWMCON.1
Reload
fxx/8
PWMCON.1
fxx/4
fxx/2
fxx/1
PWM0's
Extend 2-Bits
Extend Buffer
MUX
LSB
MSB
PWM0CNT
R
(8-bit Up-Counter)
note(4)
Clear
2-Bit Comparator
2-Bit Up-Counter
Selector
8th bit OVF
7th bit OVF
6th bit OVF
5th bit OVF
Clear
2-Bit Up-Counter OVF
PWM0 INT
IRQ1.1
Reload
PWMCON.0
PWM0MOD.3-.2
PWM0MOD.1-.0
NOTES:
1. If PWM0CNT < PWM0DATA, High level. If PWM0CNT> PWM0DATA, Low level.
2. If PWM0CNT = PWM0DATA, High level.
3. Output buffer size is controlled by PWM0MOD.7-.6 and PWM1MOD.7 - .6.
4. If 2-bit Up-Counter < Extend Buffer, High level. If 2-bit Up-Counter > Extend Buffer, Low level.
5. When PWM0 is used as 5/6/7-bit PWM, the data of PWM0DATA register should be written from
MSB and 3/2/1 LSB of PWM0DATA is cleared to "0" respectively.
For example, the data, XXX10110B, should be loaded to PWM0DATA with "10110 000B" when the
PWM0 is set to 5-bit PWM.
Figure 22-3. PWM0 Block Diagram
22-4
S3CK11F/FK11F (Preliminary Spec)
PWM MODULES
PWM1 Mode Register (PWM1MOD)
The PWM1 mode register, located at address 5BH, selects PWM1 clock, PWM1 mode (5-, 6-, 7- or 8-bit
PWM1), the number of repeat frame, and speaker volume.
This register is read/write addressable.
A reset clears PWM1MOD to "00H". This sets PWM1 to select 8-bit PWM1 mode, to select 4 times repeat frame,
to select fxx/8, and to select 1 step volume.
PWM1 Mode Register (PWM1MOD)
5BH, R/W, Reset: 00H
MSB
.7
.6
.5
.4
PWM output low voltage (VPOL) volume control bits:
00 = 1 step volume
01 = 2 step volume
10 = 3 step volume
11 = 4 step volume (the highest volume)
PWM1 clock selection bit:
00 = fxx/8
01 = fxx/4
10 = fxx/2
11 = fxx/1
.3
.2
.1
.0
LSB
PWM1 Data repeat selection bit:
00 = 4 times repeat for one data
01 = 3 times repeat for one data
10 = 2 times repeat for one data
11 = 1 times repeat for one data
PWM1 mode selection bit:
00 = 8-bit PWM1 mode
01 = 7-bit PWM1 mode
10 = 6-bit PWM1 mode
11 = 5-bit PWM1 mode
Figure 22-4. PWM1 Mode Register (PWM1MOD)
22-5
PWM MODULES
S3CK11F/FK11F (Preliminary Spec)
PWM1DATA
Register
Sign Bit
Reload
Reload
Sign Bit
Buffer
PWM1DATA
Buffer
LSB
PWMMOD.7
MSB
PWM1
note (1)
8-Bit Comparator
note (2)
note (3)
PWMCON.4
PWM1MOD.5-.4
Reload
fxx/8
PWMCON.3
fxx/4
fxx/2 MUX
fxx/1
PWM1's
Extend 2-Bits
Extend Buffer
LSB
MSB
PWM1CNT
R
(8-bit Up-Counter)
note (4)
Clear
2-Bit Comparator
2-Bit Up-Counter
Selector
8th bit OVF
7th bit OVF
6th bit OVF
5th bit OVF
2-Bit Up-Counter
Clear
OVF
PWM1 INT
IRQ1.2
Reload
PWMCON.2
PWM1MOD.3-.2
PWM1MOD.1-.0
NOTES:
1. If PWM1CNT < PWM1DATA, High level. If PWM1CNT
> PWM1DATA, Low level.
2. If PWM1CNT = PWM1DATA, High level.
3. Output buffer size is controlled by PWM1MOD.7-.6 and PWM0MOD.7-.6.
4. If 2-bit Up-Counter < Extend Buffer, High level. If 2-bit Up-Counter
> Extend Buffer, Low level.
5. When PWM1 is used as 5/6/7-bit PWM, the data of PWM1DATA register should be written from
MSB and 3/2/1 LSB of PWM1DATA is cleared to "0" respectively.
For example, the data, XXX 10110 B, should be loaded to PWM1DATA with " 10110 000 B" when the
PWM1 is set to 5-bit PWM.
Figure 22-5. PWM1 Block Diagram
22-6
S3CK11F/FK11F (Preliminary Spec)
PWM MODULES
PWM Modules Extend Register (EXDREG)
The extend register, located at address 59H, controls extend frame and sign bit out. This register is read/write
addressable.
A reset clears EXDREG to "00H". This sets PWM0/PWM1 to be not extend.
PWM Modules Extend Register (EXDREG)
59H, R/W, Reset: 00H
MSB
.7
.6
Sign bit (when PWMCON.7="1"):
0 = PWM1 output is low level and PWM0 is
output according to PWM0DATA
1 = PWM0 output is low level and PWM1 is
output according to PWM1DATA.
.5
.4
.3
.2
.1
.0
LSB
Not used
PWM0 extend bits:
00 = Not extend
01 = Extend at first frame
10 = Extend at first and second frame
11 = Extend at first, second and third frame
PWM1 extend bits:
00 = Not extend
01 = Extend at first frame
10 = Extend at first and second frame
11 = Extend at first, second and third frame
Figure 22-6. PWM Modules Extend Register (EXDREG)
22-7
PWM MODULES
S3CK11F/FK11F (Preliminary Spec)
NOTES
22-8
S3CK11F/FK11F (Preliminary Spec)
23
MULTIPLICATION
MULTIPLICATION
OVERVIEW
The multiplier of the S3CK11F/FK11F is a 8-bit by 8-bit multiplication, performed in two cycles, and selected for
signed by signed or unsigned by unsigned multiplication by MULCON.0.
This multiplier consists of the following components:
— Multiplier input registers (MXINP, MYINP)
— Multiplication result register (MRH, MRL)
— 8 × 8 multiplier (signed by signed or unsigned by unsigned)
MULTIPLIER CONTROL REGISTER (MULCON)
Multiplier Control Register (MULCON)
56H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB (DADATAH)
Not used
Multiplication Selection bit:
0 = Signed by signed multiplication
1 = Unsigned by unsigned multiplication
Figure 23-1. Multiplier Control Register (MULCON)
23-1
MULTIPLICATION
S3CK11F/FK11F (Preliminary Spec)
Data Bus
Data Bus
Multiplication Result (High Byte)
Multiplier X input register
MXINP (8-bit)
Multiplier Y input register
MYINP (8-bit)
MRH (8-bit)
8x8
Multiply
Multiplication Result (Low Byte)
MRL (8-bit)
MULCON.0
Figure 23-2. Multiplier Functional Block Diagram
F PROGRAMMING TIP — Using the Multiplier
LD
LD
LD
LD
LD
LD
NOP
NOP
LD
LD
23-2
R0, #01H
MULCON, R0
R0, #32H
R1, #0CEH
MXINP, R0
MYINP, R1
; Multiply automatically after loading MXINP, MYINP
R2, MRL
R3, MRL
; The multiplication is finished after 2 cycles
; MRH/MRL = 28H/3CH
S3CK11F/FK11F (Preliminary Spec)
24
INTERNAL DATA MEMORY (DATA ROM)
INTERNAL DATA MEMORY (DATA ROM)
OVERVIEW
The S3CK11F has 96-kwords (192-kbytes) "Data ROM" with 32-kwords (64-kbytes) "Program ROM", and the
data ROM is for the purpose of data storage. The Data ROM can be not read the "LDC instruction" but read by a
special method. Of course, it can be read the data of program memory by the "LDC instruction".
The address of the Data ROM is 08000H–1FFFFH in the structure of ROM, but the Data ROM's address is
00000H–17FFFH in the structure of "Internal Data ROM Block". In other words, the address is 08000H–1FFFFH
when data are written in the Data ROM by a ROM writer (Including SPWII and SPWII+) and is 00000H–17FFFH
when data are read from the Data ROM by the "Internal Data ROM Block".
The internal data ROM block consists of the following compondents:
— Internal data ROM control register (IDRCON)
— Internal data ROM address registers (IDRAR0 - IDRAR2)
— Internal data ROM buffer address register (IDRBUFAR)
— Internal data ROM pre-scaler register (IDRPS)
INTERNAL DATA ROM CONTROL REGISTER (IDRCON)
Internal Data ROM Control Register (IDRCON)
60H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Internal Data ROM clock selection bits:
Not used
00 = fxx/8
Internal data ROM control bit:
01 = fxx/4
0 = Disable operation
10 = fxx/2
Load data number selection bits:
1 = Enable operation
11 = fxx/1
000 = To load 16 bytes to buffer
(Automatically cleared to "0" after the
001 = To load 14 bytes to buffer
IDR INT is requested)
010 = To load 12 bytes to buffer
011 = To load 10 bytes to buffer
100 = To load 8 bytes to buffer
101 = To load 6 bytes to buffer
110 = To load 4 bytes to buffer
111 = To load 2 bytes to buffer
Figure 24-1. Internal Data ROM Control Register (IDRCON)
24-1
INTERNAL DATA MEMORY (DATA ROM)
S3CK11F/FK11F (Preliminary Spec)
Internal Data ROM Address Register (IDRAR0 -IDRAR2)
61H-63H, R/W, Reset: 00H
MSB
"0"
"0"
"0"
"0"
"0"
"0"
"0"
A16
LSB (IDRAR0, 61H)
These bits should be always "0"
MSB
A15
A14
A13
A12
A11
A10
A9
A8
LSB (IDRAR1, 62H)
MSB
A7
A6
A5
A4
A3
A2
A1
A0
LSB (IDRAR2, 63H)
NOTE:
When the IDRAR0-2 are changed software, any values should be written from
IDRAR2 to IDRAR0 by turn.
For example, the 53H should be written to IDRAR2 at first, the 17H should be written
to IDRAR1 at second, and the 00H should be written to IDRAR0 at third when
001753H is written to IDRAR0-2.
Internal Data ROM Buffer Address (IDRBUFAR)
64H, R/W, Reset: 7EH
MSB
"0"
"1"
"1"
"1"
A3
A2
A1
These bits value should be kept.
"0"
LSB
This bit should be always "0"
These bits are automatically
incremented by 1 after 1-word is
loaded to Internal Data ROM
buffer from Internal Data ROM.
NOTE:
The IDRBUFAR is set to logic "70H" when the IDRCON.0 is set to logic "1"
(IDRCON.0 = 1).
Internal Data ROM Pre-scaler Register (IDRPS)
65H, R/W, Reset: 00H
MSB
"0"
"0"
"0"
"0"
"0"
.2
.1
.0
LSB
These bits should be always "0"
The read frequency = Input clock (fxx/8, fxx/4, fxx/2, or fxx/1)
2 x (IDRPS + 1)
(The read frequency should be between 0.4MHz and 1MHz)
Figure 24-2. Internal Data ROM Related Registers
24-2
S3CK11F/FK11F (Preliminary Spec)
INTERNAL DATA MEMORY (DATA ROM)
17FFFH
IDRCON.7-.6
IDRAR.0-.2
96k x 16 Bits
Data ROM
fxx/8
00000H
fxx/4
fxx/2
fxx/1
MUX
NOTE1
1
IDRCON.0
LSB
MSB
3-bit
Pre-scaler
OVF IDR INT
3-bit up-counter
IRQ4.6
NOTE2
2
Reload
2
Reload
7FH
IDRCON.5-.3
IDRPS
IDRCON.0
70H
16 x 8 Bits
Internal
Data ROM
Buffer
IDRCON.0
NOTE3
IDRBUFAR
DATA BUS
NOTES:
1. IDRCON.0 is automatically cleared to "0' after the IDR INT is requested.
2. The frequency of 3-bit pre-scaler output should be between 0.8MHz and 2MHz.
3. IDRBUFAR is automatically incremented by "2" from "0" after 1-word is loaded to buffer when internal
Data ROM block is enabled.
4. After IDR INT is generated, the 16 x 8 bits buffer should be read before the block is restarted by IDRCON.0.
5. The IDRBUFAR is set to logic "70H" when the IDRCON.0 is set to logic "1".
Figure 24-3. Internal Data ROM Block Diagram
24-3
INTERNAL DATA MEMORY (DATA ROM)
S3CK11F/FK11F (Preliminary Spec)
NOTES
24-4
S3CK11F/FK11F (Preliminary Spec)
25
ELECTRICAL DATA
ELECTRICAL DATA
OVERWIEW
Table 25-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
VDD
–
–0.3 to + 4.6
V
Input voltage
VI
–
–0.3 to VDD + 0.3
V
Output voltage
VO
–
–0.3 to VDD + 0.3
V
Output current high
I OH
One I/O pin active
–18
All I/O pins active
–60
One I/O pin active
+ 30
Total pin current for port
+ 100
Supply voltage
I OL
Output current low
Unit
mA
mA
TA
–
–25 to + 85
°C
TSTG
–
–65 to + 150
°C
Operating temperature
Storage temperature
Rating
Table 25-2. D.C. Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Symbol
Operating voltage
VDD
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Conditions
Min
Typ
Max
Unit
fx = 8 MHz
3.0
–
3.6
V
fx = 6 MHz
2.0
–
3.6
–
VDD
V
–
0.2VDD
V
VIH1
All input pins except VIH2
0.8VDD
VIH2
XIN, XTIN
VDD–0.1
VIL1
All input pins except VIL2
VIL2
XIN, XTIN
VOH1
VDD = 3.0 V to 3.6 V;
IOH = –1mA, Ports 0–11
VDD–1.0
–
–
VOH2
VDD = 2.7 V to 3.6 V;
IOH = –2mA, VMIC
VDD–0.4
–
–
VOL
VDD = 3.0 V to 3.6 V;
IOL = 15 mA, all output pins
–
–
1.0
–
0.1
V
V
25-1
ELECTRICAL DATA
S3CK11F/FK11F (Preliminary Spec)
Table 25-2. D.C. Electrical Characteristics (Continued)
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Symbol
Input high leakage
current
ILIH1
Min
Typ
Max
Unit
VIN = VDD
All input pins except ILIH2
–
–
3
uA
ILIH2
VIN = VDD ; XIN, XTIN
–
–
20
ILIL1
VIN = 0 V
All input pins except ILIL2
–
–
–3
ILIL2
VIN = 0 V; XIN, XTIN, RESET
Output high
leakage current
ILOH
VOUT = VDD
All I/O pins and output pins
–
–
3
Output low
leakage current
ILOL
VOUT = 0 V
All I/O pins and output pins
–
–
–3
Pull-up Resistor
RL1
VIN = 0 V ; VDD = 3 V;
Ta = +25 °C, Ports 0–11
40
70
100
RL2
VIN = 0 V, VDD = 3 V; RESET
220
360
500
Ta = + 25 °C
LCON.1 = "0"
38
54
70
LCON.1 = "1"
20
26
32
Input low leakage
current
LCD Voltage
RLCD1
Dividing Resistor
RLCD2
Conditions
–20
VLCD-COMi
Voltage Drop
(i = 0–15)
VDC
– 15 uA per common pin
–
–
120
VLCD-SEGx
Voltage Drop
(x = 0–63)
VDS
– 15 uA per common pin
–
–
120
Middle Output
Voltage (1)
VLC2
VDD = 2.4 V to 3.6 V, 1/5 bias
LCD clock = 0 Hz,
0.8VDD–
0.2
0.8VDD
0.8VDD+
0.2
VLC3
VLC1 = VDD
0.6VDD–
0.2
0.6VDD
0.6VDD+
0.2
VLC4
0.4VDD–
0.2
0.4VDD
0.4VDD+
0.2
VLC5
0.2VDD–
0.2
0.2VDD
0.2VDD+
0.2
NOTE: It is middle output voltage when LCD controlller/driver is 1/16 duty and 1/5 bias.
25-2
kΩ
kΩ
mV
V
S3CK11F/FK11F (Preliminary Spec)
ELECTRICAL DATA
Table 25-2. D.C. Electrical Characteristics (Concluded)
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Supply current (1)
Symbol
IDD1 (2)
IDD1
(2)
(IDLE)
Conditions
Min
Typ
Max
Unit
mA
VDD = 3.3 V ± 0.3V
8 MHz
–
4.5
9.0
Crystal oscillator
6 MHz
–
3.5
7.0
VDD = 3.3 V ± 0.3V
8 MHz
–
1.0
2.0
Crystal oscillator
6 MHz
–
0.8
1.6
mA
(3)
VDD = 3.3 V ± 0.3V
32 kHz crystal oscillator
–
20
40
uA
IDD1 (3)
(IDLE)
VDD = 3.3 V ± 0.3V
32 kHz crystal oscillator
–
5.0
10
uA
–
0.1
1.2
uA
IDD1
IDD5
Stop mode
VDD = 3.3 V± 0.3V
OSCCON.2
=1
NOTES:
1, Supply current does not include current drawn through internal pull-up resistors, PWM , ADC, LVR, or external output
current loads.
2. IDD1 and IDD2 include power consumption through sub clock oscillator.
3. IDD3 and IDD4 are current when main clock oscillation stop.
4.
Every value in this table is measured when bits 2-0 of the power control register (PCON.2-.0) is set to 111B.
25-3
ELECTRICAL DATA
S3CK11F/FK11F (Preliminary Spec)
Table 25-3. A.C. Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Symbol
Interrupt input high,
low width
tINTH,
tINTL
tRSL
RESET input
low width
Conditions
Min
Typ
Max
Unit
P0.0–P0.7
VDD = 3.3 V
–
200
–
ns
VDD = 3.3 V
10
–
–
µs
tINTL
tINTH
0.8 VDD
0.2 VDD
Figure 25-1. Input Timing for External Interrupts (Port 0)
tRSL
RESET
0.2 VDD
Figure 25-2. Input Timing for RESET
25-4
S3CK11F/FK11F (Preliminary Spec)
ELECTRICAL DATA
Table 25-4. Input/Output Capacitance
(TA = –25 °C to + 85 °C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; unmeasured pins are
returned to VSS.
–
–
10
pF
Input capacitance
COUT
Output capacitance
CIO
I/O capacitance
Table 25-5. Data Retention Supply Voltage in Stop Mode
(TA = –25 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
VDDDR
–
2.0
–
3.6
V
Data retention
supply current
IDDDR
–
–
2
uA
VDDDR = 2.0 V
RESET
Occur
~
~
Stop Mode
Oscillation
Stabilization Time
Normal
Operating Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instruction
RESET
0.2VDD
NOTE:
tWAIT
tWAIT is same as 2048 x 32 x 1/fxx when RCOD-OPT .14-.12 = "111b".
That is, tWAIT is decided by RCOD-OPT .14-.12 when system reset is generated.
Figure 25-3. Stop Mode Release Timing When Initiated by a RESET
25-5
ELECTRICAL DATA
S3CK11F/FK11F (Preliminary Spec)
OSC Start
up time
Oscillation
Stabilization Time
~
~
Normal
Operating
Mode
Stop Mode
Data Retention
~
~
VDD
VDDDR
Execution of
STOP Instruction
INT
0.2 VDD
tWAIT
NOTE:
tWAIT is decided by WDTCON register setting. When bit 6, 5, 4 of WDTCON is "110"b, tWAIT is
1024 x 32 x 1/fxx.
Figure 25-4. Stop Mode Release Timing Initiated by Interrupts
25-6
S3CK11F/FK11F (Preliminary Spec)
ELECTRICAL DATA
Table 25-6. Analog Block Electrical Characteristics
(TA = – 25 °C to 85 °C, VDD = 2.7 V to 3.6 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ADC Resolution
–
–
–
10
–
bit
ADC Total accuracy
–
–
–
±3
LSB
–
±2
AVDD = 3.072 V
AVSS = 0 V, fxx = 8 MHz
Integral Linearity Error
ILE
Differential linearity error
DLE
–
±2
Offset Error of Top
EOT
±1
±3
Offset Error of Bottom
EOB
± 0.5
±2
ADC Conversion time(1)
TCON
10-bit resolution
50 x fxx/4, fxx = 8 MHz
25
–
–
us
ADC Input Voltage
VIADC
ADCON.1 = "0"
AVSS
–
AVDD
V
ADCON.1 = "1"
0.3AVDD
–
0.7AVDD
RAN
–
2
–
–
MΩ
Analog supply voltage
AVDD
–
VDD-0.1
VDD
VDD+0.1
V
Analog reference
voltage
VREF
AVDD/2
-0.2
AVDD/2
AVDD/2
+0.2
Analog ground
AVSS
–
VSS
–
VSS+0.3
OP-Amps and PGC
input voltage range
VIOP
fin = 1 kHz with COUT (OPAmps/PGC out to AVSS)
0.5VREF
–
1.5VREF
Total harmonic distortion
THD
fin = 100 Hz to 10kHz
–
–
2
%
Analog input current
IIAN
AVDD = VDD = 3.3 V
–
–
10
uA
Analog block current (2)
IAN
AVDD = VDD = 3.3 V
–
1.0
2.0
mA
100
500
nA
Analog input impedance
AVDD = VDD = 3.3 V
When power down mode
NOTES:
1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends..
2. IAN is an operating current during analog block active.
Table 25-7. D/A Converter Electrical Characteristics
(TA = – 25 °C to 85 °C, VDD = 2.7 V to 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
VDD = 3.072V
Min
Typ
Max
Unit
–
–
10
bits
Resolution
–
Absolute accuracy
–
-3
–
3
LSB
Differential linearity error
DLE
-1
–
1
LSB
Setup time
tSU
–
–
5
µs
Output resistance
RO
4
7
10
kΩ
25-7
ELECTRICAL DATA
S3CK11F/FK11F (Preliminary Spec)
Table 25-8. Synchronous SIO Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK Cycle time
TCYC
–
250
–
–
ns
Serial Clock High Width
TSCKH
–
75
–
–
Serial Clock Low Width
TSCKL
–
75
–
–
Serial Output data delay time
TOD
–
–
–
65
Serial Input data setup time
TID
–
50
–
–
Serial Input data Hold time
TIH
–
125
–
–
tCYC
tSCKL
tSCKH
SCK
0.8 VDD
0.2 VDD
tID
tIH
0.8 VDD
SI
Input Data
0.2 VDD
tOD
SO
Output Data
Figure 25-5. Serial Data Transfer Timing
25-8
S3CK11F/FK11F (Preliminary Spec)
ELECTRICAL DATA
Table 25-9. Main Oscillator Frequency (fOSC1)
(TA = – 25 °C to + 85 °C VDD = 2.0 V to 3.6 V)
Oscillator
Crystal/Ceramic
Clock Circuit
XIN
External clock
RC
XIN
XIN
VDD = 2.0 V – 3.6 V
XOUT
C1
Test Condition
Min
Typ
Max
Unit
0.4
–
6.0
MHz
C2
XOUT
VDD = 3.0 V – 3.6 V
8.0
VDD = 2.0 V – 3.6 V
6.0
VDD = 3.0 V – 3.6 V
8.0
VDD = 3.3 V
XOUT
0.4
–
4
MHz
MHz
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. The RC/X-TAL pin should be connected to VSS for a ceramic/crystal/external clock, and the pin should be connected to
VDD for RC osc.
Table 25-10. Main Oscillator Clock Stabilization Time (TST1)
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Oscillator
Min
Typ
Max
Unit
VDD = 3.0 V to 3.6 V
–
–
10
ms
VDD = 2.0 V to 3.6 V
–
–
30
ms
Ceramic
VDD = 2.0 V to 3.6 V
–
–
4
ms
External clock
XIN input high and low level width (tXH, tXL)
62.5ns
–
125µs
–
Crystal
Test Condition
NOTE: Oscillation stabilization time (TST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal.
25-9
ELECTRICAL DATA
S3CK11F/FK11F (Preliminary Spec)
1/fosc1
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 25-6. Clock Timing Measurement at XIN
Table 25-11. Sub Oscillator Frequency (fOSC2)
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Oscillator
Crystal
Clock Circuit
Test Condition
Min
Typ
Max
Unit
XTIN XTOUT
–
32
32.768
35
kHz
–
32
–
100
kHz
C1
External clock
C2
XTIN XTOUT
NOTE: Oscillation frequency and Xtin input frequency data are for oscillator characteristics only.
1/fosc2
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 25-7. Clock Timing Measurement at XTIN
25-10
S3CK11F/FK11F (Preliminary Spec)
ELECTRICAL DATA
Table 25-12. Sub Oscillator (Crystal) Start up Time (tST2)
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Oscillator
Normal drive
External clock
Test Condition
Min
Typ
Max
Unit
VDD = 3.0 V to 3.6 V
–
1
2
sec
VDD = 2.0 V to 3.6 V
–
–
5
XTIN input high and low level width (tXTH, tXTL)
5
–
15
µs
NOTE: Oscillator stabilization time (tST2) is the time required for the oscillator to it's normal oscillation when stop mode is
released by interrupts.
Table 25-13. Low Voltage Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Symbol
LVR voltage
VLVR
LVR operating current
ILVR
Condition
LVREN = VDD
Min
Typ
Max
Unit
1.9
2.1
2.3
V
–
10
25
µA
NOTE: The S3CK11F may be fallen into malfunction when the VDD is under 2.0[V] before reset is generated by LVR.
Table 25-14. PWM0/PWM1 Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 3.6 V)
Parameter
Symbol
PWM supply voltage
Min
Typ
Max
Unit
PVDD
VDD-0.3
–
VDD+0.3
V
PWM ground
PVSS
VSS
–
VSS+0.3
PWM output high
voltage
VPOH1
PVDD = 3.0 V
IPOH1 = -32mA, 4 step volume
PVDD0.5
–
–
VPOH2
PVDD = 3.0 V
IPOH2 = -25mA, 3 step volume
PVDD0.5
–
–
VPOH3
PVDD = 3.0 V
IPOH3 = -16mA, 2 step volume
PVDD0.5
–
–
VPOH4
PVDD = 3.0 V
IPOH4 = -9mA, 1 step volume
PVDD0.5
–
–
VPOL1
PVDD = 3.0 V
IPOL1 = +32mA, 4 step volume
–
–
0.5
VPOL2
PVDD = 3.0 V
IPOL2 = +25mA, 3 step volume
–
–
0.5
VPOL3
PVDD = 3.0 V
IPOL3 = +16mA, 2 step volume
–
–
0.5
VPOL4
PVDD = 3.0 V
IPOL4 = +9mA, 1 step volume
–
–
0.5
PWM output low
voltage
Condition
25-11
ELECTRICAL DATA
S3CK11F/FK11F (Preliminary Spec)
CPU CLOCK
8 MHz
6 MHz
0.4 MHz
2.0V
3.0V
Figure 25-8. Operating Voltage Range
25-12
3.6V
S3CK11F/FK11F (Preliminary Spec)
26
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The S3CK11F/FK11F is available in pellet only. The 160-QFP-2828B package is for ES sample only.
31.20 + 0.25
0-7
28.00
0.15
+ 0.08
- 0.04
28.00
160-QFP-2828B
0.73 - 1.03
31.20 + 0.25
0.10 MAX
#160
#1
0.65
0.30+ 0.08
M 0.12
(1.325)
0.25MIN
3.40 + 0.25
4.07 MAX
Figure 26-1. 160-Pin QFP Package Dimensions (160-QFP-2828B)
26-1
MECHANICAL DATA
S3CK11F/FK11F (Preliminary Spec)
NOTES
26-2
S3CK11F/FK11F (Preliminary Spec)
27
S3FK11F FLASH MCU
S3FK11F FLASH MCU
OVERVIEW
The S3FK11F single-chip CMOS microcontroller is the FLASH ROM version of the S3CK11F microcontroller. It
has an on-chip FLASH ROM instead of masked ROM. The FLASH ROM is accessed by serial data formats.
The S3FK11F is fully compatible with S3CK11F, both in function and in electrical characteristics. Because of its
simple programming requirements, the S3FK11F is ideal for use as an evaluation for the S3CK11F.
27-1
S3CK11F/FK11F (Preliminary Spec)
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
S3CK11F(S3FK11F)
160-QFP-2828B
NC
COM11/P10.3
COM10/P10.2
COM9/P10.1
COM8/P10.0
COM7/P11.7
COM6/P11.6
COM5/P11.5
COM4/P11.4
COM3/P11.3
COM2/P11.2
COM1/P11.1
COM0/P11.0
PVDD
PWM0
PVSS
PWM1
SDAT/P1.0/T0CLK
SCLK/P1.1/T0OUT/T0PWM/T0CAP
VDD/VDD
VSS/VSS
XOUT
XIN
Vpp/TEST
XTIN
XT OUT
RESET/RESET
RESET
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3
P0.4/INT4
P0.5/INT5
P0.6/INT6
P0.7/INT7
LVREN
RC/X-TAL
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
SEG18/P7.2
SEG17/P7.1
SEG16/P7.0
SEG15/P8.7
SEG14/P8.6
SEG13/P8.5
SEG12/P8.4
SEG11/P8.3
SEG10/P8.2
SEG9/P8.1
SEG8/P8.0
SEG7/P9.7
SEG6/P9.6
SEG5/P9.5
SEG4/P9.4
SEG3/P9.3
SEG2/P9.2
SEG1/P9.1
SEG0/P9.0
COM15/P10.7
COM14/P10.6
COM13/P10.5
COM12/P10.4
NC
NC
NC
NC
NC
NC
NC
NC
NC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
SEG19/P7.3
SEG20/P7.4
SEG21/P7.5
SEG22/P7.6
SEG23/P7.7
SEG24/P6.0
SEG25/P6.1
SEG26/P6.2
SEG27/P6.3
SEG28/P6.4
SEG29/P6.5
SEG30/P6.6
SEG31/P6.7
SEG32/P5.0
SEG33/P5.1
SEG34/P5.2
SEG35/P5.3
SEG36/P5.4
SEG37/P5.5
SEG38/P5.6
SEG39/P5.7
SEG40/P4.0
SEG41/P4.1
SEG42/P4.2
SEG43/P4.3
SEG44/P4.4
SEG45/P4.5
SEG46/P4.6
SEG47/P4.7
SEG48/P3.0
SEG49/P3.1
SEG50/P3.2
SEG51/P3.3
SEG52/P3.4
SEG53/P3.5
NC
NC
S3FK11F FLASH MCU
NOTE:
The package of S3CK11F is only for Engineer sample.
Figure 27-1. S3FK11F Pin Assignments (160-QFP-2828B)
27-2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG54/P3.6
SEG55/P3.7/BUZ
SEG56/P2.7/TBOUT
SEG57/P2.6/TAOUT
SEG58/P2.5/T1CLK
SEG59/P2.4/T2OUT
SEG60/P2.3/SCK
SEG61/P2.2/SI
SEG62/P2.1/SO
SEG63/P2.0/DAO
AVSS
ADCIN
PGCOUT
PGCIN
OP2P
OP2N
OP2OUT
OP1OUT
OP1N
OP1P
VREF
VMIC
AVDD
NC
NC
NC
NC
NC
NC
NC
NC
S3CK11F/FK11F (Preliminary Spec)
S3FK11F FLASH MCU
Table 27-1. Descriptions of Pins Used to Read/Write the FLASH ROM
During Programming
Pin Name
Pin No.
I/O
Function
SDAT (P1.0)
18
I/O
Serial data pin. Output port when reading and input port when
writing. Can be assigned as a Input/push-pull output port.
SCLK (P1.1)
19
I/O
Serial clock pin. Input only pin.
VPP (TEST)
24
I
Power supply pin for FLASH ROM cell writing (indicates that
FLASH enters into the writing mode). When 12.5 V is applied,
FLASH is in writing mode and when 3 V is applied, FLASH is in
reading mode. When FLASH is operating, hold GND.
RESET
(RESET)
27
I
Chip initialization
VDD/VSS
(VDD/VSS)
20/21
I
Logic power supply pin. VDD should be tied to
+3 V during programming.
NOTE: Maximum number of writing/erasing for S3FK11F is 100 times.
27-3
S3FK11F FLASH MCU
S3CK11F/FK11F (Preliminary Spec)
NOTES
27-4
S3CK11F/FK11F (Preliminary Spec)
28
DEVELOPMENT TOOLS
DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with windows95/98/NT as its operating system can be used. One type of
debugging tool including hardware and software is provided: the effective cost and powerful in-circuit emulator,
InvisibleMDS, for CalmRISC8. Samsung also offers support software that includes debugger, Compiler,
Assembler, and a program for setting options.
CALMSHINE: IDE (INTEGRATED DEVELOPMENT ENVIRONMENT)
CalmRISC8 Samsung Host Interface for In-circuit Emulator, CalmSHINE, is a multi window based debugger for
CalmRISC8. CalmSHINE provides pull-down, pop-up and tool-bar menus, mouse support, function/hot keys,
syntax highlight, tool-tip, drag-and-drop and context-sensitive hyper-linked help. It has an advanced, multiplewindowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted,
added or removed, docked or undocked completely.
INVISIBLE MDS: IN-CIRCUIT EMULATOR
The evaluation chip of CalmRISC8 has a basic debugging utility block. Using this block, evaluation chip directly
interfaces with host through only communication wire. So, InvisibleMDS offers simple and powerful debugging
environment.
CALMRISC8 C-COMPILER: CALM8CC
The CalmRISC8 Compiler offers the standard features of the C language, plus many extensions for MCU
applications, such as interrupt handling in C and data placement controls, designed to take fully advantage of
CalmRISC8 facilities. It conforms to the ANSI specification. It supports standard library of functions applicable to
MCU systems. The standard library also conforms to the ANSI standard. It generates highly size-optimized code
for CalmRISC8 by fully utilizing CalmRISC8 architecture. It is available in a Windows version integrated with the
CalmSHINE.
CALMRISC8 RELOCATABLE ASSEMBLER: CALM8ASM
The CalmRISC8 Assembler is a relocatable assembler for Samsung's CalmRISC8 MCU and its MAC816 and
MAC2424 coprocessors. It translates a source file containing assembly language statements into a relocatable
machine object code file in Samsung format. It runs on WINDOWS95 compatible operating systems. It supports
macros and conditional assembly. It produces the relocatable object code only, so the user should link object
files. Object files can be linked with other object files and loaded into memory.
CALMRISC8 LINKER: CALM8LINK
The CalmRISC8 Linker combines Samsung object format files and library files and generates absolute, machinecode executable hex programs or binary files for CalmRISC8 MCU and its MAC816 and MAC2424 coprocessors.
It generates the map file, which shows the physical addresses to which each section and symbol is bounded, start
addresses of each section and symbol, and size of them. It runs on WINDOWS95 compatible operating systems.
28-1
DEVELOPMENT TOOLS
S3CK11F/FK11F (Preliminary Spec)
EMULATION PROBE BOARD CONFIGURATION
ON
CON2
78R33
CON1
JTAG
U11
S1
C4
OFF
U19
5V/500mA
6R4016
PWSEL
JP1
6R1016
74LV245
74LV245
74LV245
74LV245
74LV245
74LV245
74LV245
POWER
VDD
2
61
62
9
10
69
70
19
20
79
80
29
30
89
90
39
40
99
100
49
50
109
110
59
60
119
120
USER
Vpp
U18
U7
BKREGX
EVMAT
EEVMAT0
64
JP2
1
OFF
74LV245
OFF
1
65
256
Y1
S3EK110X
EEVMAT1
EEVMAT2
EEVMAT3
128
EEXT_BK0
193
EEXT_BK2
192
EP-K11F
74LV32
EEXT_BK1
74LV02
74LV125
129
EEXT_BK3
JP6
X-TAL
EXT_BK
OSC1
VDD
RUN
D2
D3
VDD
SW1
U14
JP3
C2
74HC08
VSS
C1
RESET
OSCCLK
Figure 28-1. Emulation Probe Board Configuration
Invisible MDS Connector = 10-pin/normal Pitch (2.54mm) = JTAG
28-2
Pin No.
Pin Name
Pin No.
Pin Name
1
VDD
6
PTD0_TxD
2
PNTRST_NINIT
7
GND
3
PTCK_MCLK
8
UCLK
4
PTMS
9
JTAGSEL
5
PTDI_RxD
10
–
S3CK11F/FK11F (Preliminary Spec)
DEVELOPMENT TOOLS
EXTERNAL EVENT INPUT HEADERS
These input headers are used to add the break condition to the core status externally when the break using
CalmBreaker occurs in the evaluation chip.
EXT_BK
EVACHIP_EXTBK[0]
EXT_BK0
EVACHIP_EXTBK[1]
EXT_BK1
EVACHIP_EXTBK[2]
EXT_BK2
EVACHIP_EXTBK[3]
EXT_BK3
EVENT MATCH OUTPUT HEADERS
Four event match signals and one combination event signal are occurred by the CalmBreaker in the evaluation
chip. These signals are transmitted through the evaluation chip.
EVMAT
EVACHIP_EXTBK[0]
EVACHIP_EXTBK[1]
EVACHIP_EXTBK[2]
EVACHIP_EXTBK[3]
EVMAT0
EVMAT1
EVMAT2
EVMAT3
EXTERNAL BREAK INPUT HEADERS (U7)
This input pin is used to break during the evaluation chip run.
BKREQX
EVACHIP_BKREQX
28-3
DEVELOPMENT TOOLS
28-4
S3CK11F/FK11F (Preliminary Spec)
S3CK11F/FK11F (Preliminary Spec)
DEVELOPMENT TOOLS
POWER SELECTION
U18 State
Description
Same Power Source from Target System
POWER
SELECT
OFF
VDD
User
Power
Target
System
CPU
VSS
DC
Jack
Power
VSS
MDS
DC
Jack
Power
Same Power Source from DC Jack
POWER
SELECT
OFF
VDD
User
Power
Target
System
CPU
VSS
EP-K11F
USER
_VDD
POWER
_VDD
MDS
EP-K11F
USER
_VDD
POWER
_VDD
VSS
CLOCK SELECTION
JP3 State
CLKSEL
X-TAL
XTALI
Description
OSC[Y1] is used to clock source for Evaluation chip
MXOUT
XTALO
MXIN
MXOUT
OSC
OFF
XMIN
OSC CLK
CPU
EP-K11F
OSCCLK
X-TAL[JP6] is used to clock source for Evaluation chip
CLKSEL
X-TAL
XTALI
XTALO
MXIN
MXOUT
OSC
OFF
XTALI
OSCCLK
XTALO
JP6
MXOUT
XMIN
CPU
EP-K11F
28-5
DEVELOPMENT TOOLS
S3CK11F/FK11F (Preliminary Spec)
USE CLOCK SETTING FOR EXTERNAL CLOCK MODE
Proper crystal and capacitors for main clock should be inserted into pin socket on the IE Board as follows;
XIN
C
JP3
XOUT
C
X-Tal
SUB CLOCK SETTING
For sub-clock mode a crystal, 32.768 kHz and capacitors should be inserted into pin socket on the IE Board as
follows;
C
XTIN
Y1
R
X-Tal
NOTE: The value of resistor is 0 kΩ.
28-6
XTOUT
C
S3CK11F/FK11F (Preliminary Spec)
DEVELOPMENT TOOLS
JP1, JP2 PIN ASSIGNMENT
JP1, 2 are the signals of IE-K11F and their pin assignment is the same as the pin of S3CK11F.
JP1
Function
JP1
Function
JP2
Function
JP2
Function
1
P10.3
2
P10.2
61
P3.5
62
P3.4
3
P10.1
4
P10.0
63
P3.3
64
P3.2
5
P11.7
6
P11.6
65
P3.1
66
P3.0
7
P11.5
8
P11.4
67
P4.7
68
P4.6
9
P11.3
10
P11.2
69
P4.5
70
P4.4
11
P11.1
12
P11.0
71
P4.3
72
P4.2
13
PVDD
14
PWM0
73
P4.1
74
P4.0
15
PVSS
16
PWM1
75
P5.7
76
P5.6
17
P1.0
18
P1.1
77
P5.5
78
P5.4
19
VDD
20
VSS
79
P5.3
80
P5.2
21
NC
22
NC
81
P5.1
82
P5.0
23
TEST
24
NC
83
P6.7
84
P6.6
25
NC
26
RESET
85
P6.5
86
P6.4
27
P0.0
28
P.1
87
P6.3
88
P6.2
29
P0.2
30
P0.3
89
P6.1
90
P6.0
31
P0.4
32
P0.5
91
P7.7
92
P7.6
33
P0.6
34
P0.7
93
P7.5
94
P7.4
35
LVREN
36
RC/X-TAL
95
P7.3
96
P7.2
37
AVDD
38
VMIC
97
P7.1
98
P7.0
39
VREF
40
OP1P
99
P8.7
100
P8.6
41
OP1N
42
OP1OUT
101
P8.5
102
P8.4
43
OP2OUT
44
OP2N
103
P8.3
104
P8.2
45
OP2P
46
PGCIN
105
P8.1
106
P8.0
47
PGCOUT
48
ADCIN
107
P9.7
108
P9.6
49
AVSS
50
P2.0
109
P9.5
110
P9.4
51
P2.1
52
P2.2
111
P9.3
112
P9.2
53
P2.3
54
P2.4
113
P9.1
114
P9.0
55
P2.5
56
P2.6
115
P10.7
116
P10.6
57
P2.7
58
P3.7
117
P10.5
118
P10.4
59
P3.6
60
NC
119
NC
120
NC
28-7