VNH5019A-E
Automotive fully integrated
H-bridge motor driver
Features
Type
VNH5019A-E
RDS(on)
Iout
Vccmax
18 mΩ typ
(per leg)
30 A
41 V
■
ECOPACK®: lead free and RoHS compliant
■
Automotive Grade: compliance with AEC
guidelines
■
Output current: 30 A
■
3 V CMOS compatible inputs
■
Undervoltage and overvoltage shutdown
■
High-side and low-side thermal shutdown
■
Cross-conduction protection
■
Current limitation
■
Very low standby power consumption
■
PWM operation up to 20 khz
■
Protection against:
– Loss of ground and loss of VCC
■
Current sense output proportional to motor
current
■
Charge pump output for reverse polarity
protection
■
Output protected against short to ground and
short to VCC
Description
The VHN5019A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side drivers and two low-side
switches. The high-side driver switch is designed
using STMicroelectronics’ well known and proven
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
September 2013
MultiPowerSO-30™
Power MOSFET with an intelligent
signal/protection circuit.
The three dice are assembled in
MultiPowerSO-30 package on electrically isolated
lead-frames. This package, specifically designed
for the harsh automotive environment offers
improved thermal performance thanks to exposed
die pads. The input signals INA and INB can
directly interface to the microcontroller to select
the motor direction and the brake condition.
The DIAGA/ENA or DIAGB/ENB, when connected
to an external pull-up resistor, enable one leg of
the bridge. They also provide a feedback digital
diagnostic signal. The CS pin allows to monitor
the motor current by delivering a current
proportional to its value when CS_DIS pin is
driven low or left open. The PWM, up to 20 KHz,
lets us to control the speed of the motor in all
possible conditions. In all cases, a low-level state
on the PWM pin turns-off both the LSA and LSB
switches. When PWM rises to a high-level, LSA or
LSB turn-on again depending on the input pin
state.
Output current limitation and thermal shutdown
protects the concerned high-side in short to
ground condition.
The short to battery condition is revealed by the
overload detector or by thermal shutdown that
latches off the relevant low-side.
Active VCC pin voltage clamp protects the device
against low energy spikes in all configurations for
the motor.
CP pin provides the necessary gate drive for an
external n-channel PowerMOS used for reverse
polarity protection.
Doc ID 15701 Rev 9
1/37
www.st.com
1
Contents
VNH5019A-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4
Waveforms and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1
4
MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2
Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2
MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3
MultiPowerSO-30 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4
MultiPowerSO-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/37
Doc ID 15701 Rev 9
VNH5019A-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current sense (8 V < VCC < 21 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 27
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 15701 Rev 9
3/37
List of figures
VNH5019A-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
4/37
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection
(option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection
(option B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 21
Waveforms in full bridge operation (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Waveforms in full bridge operation (part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Definition of delay response time of sense current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 26
Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 28
MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 28
Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 29
MultiPowerSO-30 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Doc ID 15701 Rev 9
VNH5019A-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
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Doc ID 15701 Rev 9
5/37
Block diagram and pin description
Figure 2.
VNH5019A-E
Configuration diagram (top view)
1
OUTA
N.C.
VCC
INA
ENA/DIAGA
CS_DIS
PWM
30
OUTA
Heat Slug2
GNDA
OUTA
N.C.
VCC
VCC
Heat Slug1
CS
ENB/DIAGB
INB
N.C.
OUTB
CP
VBAT
OUTB
Heat Slug3
VCC
N.C.
OUTB
Table 1.
15
16
GNDB
GNDB
GNDB
N.C.
OUTB
Suggested connections for unused and not connected pins
Connection / pin
Current sense
N.C.
OUTx
INPUTx, PWM
DIAGx/ENx
CS_DIS
Floating
Not allowed
X
X
X
To ground
Through 1 kΩ resistor
X
Not allowed
Through 10 kΩ
resistor
Table 2.
Pin definitions and functions
Pin
Symbol
Function
1, 25, 30
OUTA,
Heat Slug2
Source of high-side switch A / drain of low-side switch A, power
connection to the motor
2,14,17, 22,
24,29
N.C.
3, 13, 23
VCC,
Heat Slug1
12
VBAT
Battery connection and connection to the source of the external
PowerMOS used for the reverse battery protection
ENA/DIAGA
Status of high-side and low-side switches A; open drain output.
This pin must be connected to an external pull-up resistor. When
externally pulled low, it disables half-bridge A. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 13: Truth table in fault conditions
(detected on OUTA))
5
6/37
OUTA
N.C.
GNDA
GNDA
Not connected
Drain of high-side switches and connection to the drain of the
external PowerMOS used for the reverse battery protection
Doc ID 15701 Rev 9
VNH5019A-E
Block diagram and pin description
Table 2.
Pin definitions and functions (continued)
Pin
Symbol
6
CS_DIS
4
INA
7
PWM
Function
Active high CMOS compatible pin to disable the current sense
pin
Clockwise input. CMOS compatible
PWM input. CMOS compatible.
CS
Output of current sense. This output delivers a current
proportional to the motor current, if CS_DIS is low or left open.
The information can be read back as an analog voltage across
an external resistor.
9
ENB/DIAGB
Status of high-side and low-side switches B; Open drain output.
This pin must be connected to an external pull up resistor. When
externally pulled low, it disables half-bridge B. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 13: Truth table in fault conditions
(detected on OUTA).
10
INB
Counter clockwise input. CMOS compatible
11
CP
Connection to the gate of the external MOS used for the reverse
battery protection
15, 16, 21
OUTB,
Heat Slug3
Source of high-side switch B / drain of low-side switch B, power
connection to the motor
26, 27, 28
GNDA
Source of low-side switch A and power ground(1)
18, 19, 20
GNDB
Source of low-side switch B and power ground(1)
8
1. GNDA and GNDB must be externally connected together
)
Table 3.
Block descriptions(1)
Name
Description
Logic control
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the Table 12.
Overvoltage + undervoltage
Shut down the device outside the range [4.5 V to 24 V] for the
battery voltage.
High-side, low-side and clamp
voltage
Protect the high-side and the low-side switches from the
high-voltage on the battery line in all configuration for the motor.
High-side and low-side driver
Drive the gate of the concerned switch to allow a proper RDS(on)
for the leg of the bridge.
Linear current limiter
Limits the motor current, by reducing the high-side switch
gate-source voltage when short-circuit to ground occurs.
High-side and low-side
overtemperature protection
In case of short-circuit with the increase of the junction’s
temperature, it shuts down the concerned driver to prevent its
degradation and to protect the die.
Low-side overload detector
Detects when low-side current exceeds shutdown current and
latches off the concerned low-side.
Doc ID 15701 Rev 9
7/37
Block diagram and pin description
Table 3.
VNH5019A-E
Block descriptions(1) (continued)
Name
Description
Charge pump
Provides the voltage necessary to drive the gate of the external
PowerMOS used for the reverse polarity protection
Fault detection
Signalizes an abnormal condition of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Power limitation
Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
1. See Figure 1
8/37
Doc ID 15701 Rev 9
VNH5019A-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
ICP
IBAT
IS
VCP
IINA
IINB
VINA
IENA
VINB
IENB
CP
INA
VBAT
VCC
IOUTA
OUTA
INB
OUTB
CS
DIAGA/ENA
CS_DIS
DIAGB/ENB
VENA
VBAT
VCC
VENB
PWM
IOUTB
VOUTA
ISENSE
VOUTB
ICSD
GNDA GNDB
VCSD
VSENSE
Ipw
GND
Vpw
2.1
IGND
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
program and other relevant quality document.
Table 4.
Absolute maximum rating
Symbol
Parameter
Value
Unit
VBAT
Maximum battery voltage(1)
-16
+41
V
V
VCC
Maximum bridge supply voltage
+ 41
V
Imax
Maximum output current (continuous)
30
A
IR
Reverse output current (continuous)
-30
A
IIN
Input current (INA and INB pins)
+/- 10
mA
IEN
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
+/- 10
mA
Ipw
PWM input current
+/- 10
mA
ICP
CP output current
+/- 10
mA
CS_DIS input current
+/- 10
mA
ICS_DIS
Doc ID 15701 Rev 9
9/37
Electrical specifications
Table 4.
VNH5019A-E
Absolute maximum rating (continued)
Symbol
Parameter
Value
Unit
VCC - 41
+VCC
V
V
2
kV
Case operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
VCS
Current sense maximum voltage
VESD
Electrostatic discharge (human body model: R = 1.5 kΩ,
C = 100 pF)
Tc
TSTG
1. This applies with the n-channel MOSFET used for the reverse battery protection. Otherwise VBAT has to be
shorted to VCC.
2.2
Thermal data
Table 5.
Symbol
Rthj-case
Rthj-amb
10/37
Thermal data
Parameter
Max. value
Unit
Thermal resistance junction-case HSD
1.7
°C/W
Thermal resistance junction-case LSD
3.2
°C/W
See Figure 18
°C/W
Thermal resistance junction-ambient
Doc ID 15701 Rev 9
VNH5019A-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8 V < VCC < 21 V, -40 °C < Tj < 150 °C, unless
otherwise specified.
Table 6.
Power section
Symbol
Parameter
VCC
Operating bridge supply
voltage
IS
Test conditions
Min.
5.5
OFF-state with all fault cleared and ENx = 0 V
(standby):
INA = INB = PWM = 0; Tj = 25 °C; VCC = 13 V
INA = INB = PWM = 0
OFF-state (no standby):
INA = INB = PWM = 0; ENx = 5 V
Supply current
10
ON-state:
INA or INB = 5 V, no PWM
INA or INB = 5 V, PWM = 20 kHz
RONHS
Static high-side
resistance
IOUT = 15 A; Tj = 25 °C
RONLS
Static low-side
resistance
IOUT = 15 A; Tj = 25 °C
IL(off)
High-side OFF-state
output current (per
channel)
Max.
Unit
24
V
15
60
µA
µA
6
mA
8
8
mA
mA
12.0
mΩ
26.5
6.0
mΩ
IOUT = 15 A; Tj = - 40 °C to 150 °C
High-side
free-wheeling diode
forward voltage
Symbol
4
IOUT = 15 A; Tj = - 40 °C to 150 °C
Vf
Table 7.
Typ.
11.5
If = 15 A,
Tj = 150 °C
0.6
0.8
Tj = 25 °C; VOUTX = ENX = 0 V; VCC = 13 V
3
Tj = 125 °C; VOUTX = ENX = 0 V; VCC = 13 V
5
V
µA
Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS)
Parameter
Test conditions
VIL
Low-level input
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin)
VIH
High-level input
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin)
IINL
Low-level input current VIN = 0.9 V
IINH
High-level input
current
VIN = 2.1 V
VIHYST
Input hysteresis
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin)
Doc ID 15701 Rev 9
Min.
Typ.
Max.
Unit
0.9
V
2.1
V
1
µA
10
0.15
µA
V
11/37
Electrical specifications
Table 7.
Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) (continued)
Symbol
VICL
VDIAG
Parameter
Test conditions
Input clamp voltage
Enable low-level
output voltage
Table 8.
Symbol
f
Min.
Typ.
Max.
IIN = 1 mA
5.5
6.3
7.5
IIN = -1 mA
-1.0
-0.7
-0.3
Unit
V
Fault operation (DIAGX/ENX pin
acts as an output pin); IEN = 1 mA
0.4
V
Max
Unit
20
kHz
Switching (VCC = 13 V, RLOAD = 0.87 Ω, Tj = 25 °C)
Parameter
Test conditions
PWM frequency
Min
Typ
0
td(on)
HSD rise time
Input rise time < 1µs
(see Figure 9)
250
µs
td(off)
HSD fall time
Input rise time < 1µs
(see Figure 9)
250
µs
tr
LSD rise time
(see Figure 8)
1
2
µs
tf
LSD fall time
(see Figure 8)
1
2
µs
tDEL
Delay time during change of
operating mode
(see Figure 7)
400
1600
µs
trr
High-side free wheeling
diode reverse recovery time
(see Figure 10)
110
ns
Dynamic cross-conduction
current
IOUT = 15 A
(see Figure 10)
2
A
IRM
Table 9.
Symbol
VUSD
VUSDhyst
200
Protection and diagnostic
Parameter
Test conditions
Min
Typ
Max
Unit
VCC undervoltage
shutdown
4.5
5.5
V
VCC undervoltage
shutdown hysteresis
0.5
V
VOV
VCC overvoltage shutdown
24
27
30
V
ILIM_H
High-side current limitation
30
50
70
A
ISD_LS
Low-side shutdown current
70
115
160
A
VCLPHS(1)
High-side clamp voltage
(VCC to OUTA = 0 or
OUTB = 0)
IOUT = 15 A
43
48
54
V
VCLPLS(1)
Low-side clamp voltage
(OUTA = VCC or
OUTB = VCC to GND)
IOUT = 15 A
27
30
33
V
Thermal shutdown
temperature
VIN = 2.1 V
150
175
200
°C
TTSD(2)
12/37
VNH5019A-E
Doc ID 15701 Rev 9
VNH5019A-E
Electrical specifications
Table 9.
Protection and diagnostic (continued)
Symbol
TTSD_LS
TTR(3)
THYST(3)
Parameter
Test conditions
Low-side thermal
shutdown temperature
VIN = 0 V
Thermal reset temperature
Min
Typ
Max
Unit
150
175
200
°C
135
Thermal hysteresis
7
°C
15
°C
1. The device is able to pass the ESD and ISO pulse requirements as specified in the Table 15.
2. TTSD is the minimum threshold temperature between HS and LS
3. Valid for both HSD and LSD
Table 10.
Symbol
Current sense (8 V < VCC < 21 V)
Test conditions
Min
Typ
Max
IOUT/ISENSE
IOUT = 3 A, VSENSE = 0.5 V,
Tj = - 40 °C to 150°C
4670
7110
10110
Analog current sense ratio
drift
IOUT = 3 A; VSENSE = 0.5 V,
Tj = -40 °C to 150 °C
-19
IOUT/ISENSE
IOUT = 8 A, VSENSE = 1.3V,
Tj = - 40 °C to 150°C
6060
Analog current sense ratio
drift
IOUT = 8 A; VSENSE = 1.3V,
Tj = -40 °C to 150 °C
-14
IOUT/ISENSE
IOUT = 15 A, VSENSE = 2.4 V,
Tj = - 40 °C to 150°C
6070
Analog current sense ratio
drift
IOUT = 15 A; VSENSE = 2.4 V,
Tj = -40 °C to 150 °C
-12
IOUT/ISENSE
IOUT = 25 A, VSENSE = 4 V,
Tj = - 40 °C to 150°C
6000
dK3/K3
Analog current sense ratio
drift
IOUT =25 A; VSENSE = 4 V,
Tj = -40 °C to 150 °C
-12
VSENSE
Max analog sense output
voltage
IOUT = 15 A, RSENSE = 1.1 kΩ
5
IOUT = 0 A, VSENSE = 0 V, VCSD = 5 V,
VIN = 0 V,
Tj = - 40 to 150°C
0
IOUT = 0 A, VSENSE = 0 V, VCSD = 0 V,
VIN = 5 V,
Tj = - 40 to 150°C
0
K0
dK0/K0
K1
dK1/K1
K2
dK2/K2
K3
ISENSEO
Parameter
Analog sense leakage current
Unit
19
7030
%
8330
14
6990
%
7810
12
6940
%
7650
12
%
V
5
µA
100
tDSENSEH
Delay response time from
falling edge of CS_DIS pin
VIN = 5 V, VSENSE < 4 V, IOUT = 8 A,
ISENSE = 90% of ISENSEmax
(see fig Figure 13)
50
µs
tDSENSEL
Delay response time from
rising edge of CS_DIS pin
VIN = 5 V, VSENSE < 4 V, IOUT = 8 A,
ISENSE = 10% of ISENSEmax
(see fig Figure 13)
20
µs
Doc ID 15701 Rev 9
13/37
Electrical specifications
2.4
VNH5019A-E
Table 11.
Charge pump
Symbol
Parameter
Test conditions
Min
ENX = 5 V
Typ
VCC + 5
VCP
Charge pump output
voltage
IBAT
Charge pump standby
ENA = ENB = 0 V
current
ENX = 5 V, VCC = 4.5 V
Max
Unit
VCC + 10
V
10.5
200
nA
Waveforms and truth table
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled-high
PWM pin usage: in all cases, a “0” on the PWM pin turns-off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn-on again depending on the input pin state.
Table 12.
14/37
Truth table in normal operating conditions
INA
INB
DIAGA/ENA DIAGB/ENB
OUTA
OUTB
CS (VCSD = 0 V)
1
1
1
1
0
0
0
1
H
H
High imp.
1
1
H
L
ISENSE = IOUT/K
Clockwise (CW)
1
1
1
L
H
ISENSE = IOUT/K
Counterclockwise
(CCW)
0
1
1
L
L
High imp.
Doc ID 15701 Rev 9
Operating mode
Brake to VCC
Brake to GND
VNH5019A-E
Figure 4.
Electrical specifications
Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option A)
VBAT
Reg 5V
+5V
G
D
S
+ 5V
3.3K
VBAT
1K
CP
3.3K
VCC
DIAGB/ENB
1K
DIAG A/ENA
1K
HSA
HSB
PWM
μC
OUT A
1K
OUT B
LSA
10K
33nF
INB
INA
1K
LSB
CS
C
M
1.5K
GNDB
GNDA
Note:
The external N-channel Power MOSFET used for the reverse battery protection should have the following characteristics:
- BVdss > 20 V (for a reverse battery of -16 V);
- RDS(on) < 1/3 of H-bridge total RDS(on)
- Standard Logic Gate Driving
Doc ID 15701 Rev 9
15/37
Electrical specifications
Figure 5.
VNH5019A-E
Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option B)
VCC
Reg 5V
+5V
+ 5V
VCC
3.3K
VBAT
CP
3.3K
DIAGB/ENB
1K
1K
DIAGA/ENA
1K
HSA
HSB
PWM
μC
OUTA
1K
OUTB
INA
INB
LSA
10K
33nF
1K
LSB
CS
C
M
1.5K
GNDB
GNDA
S
100K
G
D
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply line at PWM
operation. Stored energy of the motor inductance may flyback into the blocking capacitor, if the bridge driver goes into 3-state. This causes a
hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500 µF per 10 A load current is recommended.
Table 13.
INA
Truth table in fault conditions (detected on OUTA)
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
CS (VCSD=0V)
H
L
High
impedance
H
IOUTB/K
L
High
impedance
1
1
0
1
1
0
OPEN
0
0
X
X
0
Fault Information
Note:
OPEN
Protection Action
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
16/37
Doc ID 15701 Rev 9
VNH5019A-E
Electrical specifications
The fault conditions are:
●
overtemperature on one or both high-sides (for example, if a short to ground occurs as
it could be the case described in line 1 and 2 in the Table 14);
●
Short to battery condition on the output (saturation detection on the low-side
Power MOSFET).
Possible origins of fault conditions may be:
●
OUTA is shorted to ground. It follows that, high-side A is in overtemperature state.
●
OUTA is shorted to VCC. It follow that, low-side Power MOSFET is in saturation state.
When a fault condition is detected, the user can know which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the
respective output (OUTX) again, the input signal must rise from low-level to high-level.
Figure 6.
Behavior in fault condition (how a fault can be cleared)
Note:
In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA=0 or INB if ENB=0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL.
If the Diag/En pins are already low, PWM=0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
Doc ID 15701 Rev 9
17/37
Electrical specifications
Table 14.
VNH5019A-E
Electrical transient requirements (part 1)
ISO T/R
Test level
7637/1
Test Pulse
I
II
III
IV
Delay and impedance
1
-25 V
-50 V
-75 V
-100 V
2 ms, 10 Ω
2
+25 V
+50 V
+75 V
+100 V
0.2 ms, 10 Ω
3a
-25 V
-50 V
-100 V
-150 V
0.1 μs, 50 Ω
3b
+25 V
+50 V
+75 V
+100 V
0.1 μs, 50 Ω
4
-4 V
-5 V
-6 V
-7 V
100 ms, 0.01 Ω
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
400 ms, 2 Ω
Table 15.
Electrical transient requirements (part 2)
ISO T/R
Test levels
7637/1
Test Pulse
I
II
III
IV
1
C
C
C
C
2
C
C
C
C
3a
C
C
C
C
3b
C
C
C
C
4
C
C
C
C
5
C
E
E
E
Table 16.
Electrical transient requirements (part 3)
Class
18/37
Contents
C
All functions of the device are performed as designed after exposure to
disturbance.
E
One or more functions of the device are not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.
Doc ID 15701 Rev 9
VNH5019A-E
2.5
Electrical specifications
Reverse battery protection
Against reverse battery condition the charge pump feature allows to use an external
N-channel MOSFET connected as shown in the typical application circuit (see Figure 4).
As alternative option, a N-channel MOSFET connected to GND pin can be used (see typical
application circuit in figure Figure 5).
With this configuration we recommend to short VBAT pin to VCC.
The device sustains no more than -30 A in reverse battery conditions because of the two
body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5019A-E is pulled-down to the VCC line (approximately -1.5 V). Series resistor must be
inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum
target reverse current through microcontroller I/Os, series resistor is:
V IOs – V CC
R = -------------------------------I Rmax
Figure 7.
Definition of the delay times measurement
VINA,
t
VINB
t
PWM
t
ILOAD
tDEL
tDEL
t
Doc ID 15701 Rev 9
19/37
Electrical specifications
Figure 8.
VNH5019A-E
Definition of the low-side switching times
PWM
t
VOUTA, B
90%
tf
Figure 9.
80%
20%
10%
tr
t
Definition of the high-side switching times
VINA,
td(off)
td(on)
t
VOUTA
90%
10%
t
20/37
Doc ID 15701 Rev 9
VNH5019A-E
Electrical specifications
Figure 10. Definition of dynamic cross conduction current during a PWM operation
INA=1, INB=0
PWM
t
IMOTOR
t
VOUTB
t
ICC
IRM
t
trr
Doc ID 15701 Rev 9
21/37
Electrical specifications
VNH5019A-E
Figure 11. Waveforms in full bridge operation (part 1)
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA ->OUTB
CS (*)
tDEL
CS_DIS
tDEL
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS
CS_DIS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA
INB
ILIM
IOUTA->OUTB
Tj =TTSD
TTSD_HSA
TTR_HSA
Tj < TTSD
TjHSA
Tj > TTR
DIAGA/ENA
DIAGB/ENB
CS
CS_DIS
current
limitation
normal operation
22/37
power limitation
OUTA shorted to ground
Doc ID 15701 Rev 9
normal operation
VNH5019A-E
Electrical specifications
Figure 12. Waveforms in full bridge operation (part 2)
OUTA shorted to VCC (resistive short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
ISD_LS
ILSA
TTSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA softly shorted to VCC
normal operation
undervoltage shutdown
OUTA shorted to VCC (pure short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
ISD_LS
ILSA
TTSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA hardly shorted to VCC
Doc ID 15701 Rev 9
normal operation
undervoltage shutdown
23/37
Electrical specifications
VNH5019A-E
Figure 13. Definition of delay response time of sense current
INPUT
CS_DIS
LOAD CURRENT
CURRENT SENSE
tDSENSEH
tDSENSEL
The VNH5019A-E can be used as a high power half-bridge driver achieving an
on- resistance per leg of 9.5 mΩ. The figure below shows the suggested configuration:
Figure 14. Half-bridge configuration
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
VCC
CP
CP VCC
VBAT
VBAT
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
CS_DIS
CS_DIS
OUTA
OUTB
GNDA
M
GNDA
GNDB
OUTB
OUTA
GNDB
The VNH5019A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high-impedance. The figure below shows the suggested
configuration:
24/37
Doc ID 15701 Rev 9
VNH5019A-E
Electrical specifications
Figure 15. Multi-motors configuration
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
CS_DIS
CP
CP
OUTA
OUTB
GNDA
VCC
VBAT
VBAT
M2
M1
OUTB
OUTA
GNDA
GNDB
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
CS_DIS
GNDB
M3
Doc ID 15701 Rev 9
25/37
Package and PCB thermal data
VNH5019A-E
3
Package and PCB thermal data
3.1
MultiPowerSO-30 thermal data
Figure 16. MultiPowerSO-30™ PC board
Note:
Layout condition of Rth and Zth measurements (PCB FR4 area= 58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 mm, Copper areas:
from minimum pad lay-out to 16 cm2).
Figure 17. Chipset configuration
CHIP 1
RthA
RthAB
RthAC
CHIP 2
RthBC
CHIP 3
RthC
RthB
Figure 18. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
50
RthA
RthB = RthC
RthAB = RthAC
RthBC
45
40
35
30
25
°C/W
20
15
10
5
0
0
26/37
2
4
6
8
10
12
cm 2 of Cu Area (refer to PCB layout)
Doc ID 15701 Rev 9
14
16
18
VNH5019A-E
Package and PCB thermal data
3.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
Table 17.
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode
Chip 1
Chip 2 Chip 3
Tjchip1
Tjchip2
Tjchip3
Pdchip1 • RthAB + Pdchip3 •
RthBC + Tamb
Pdchip1 • RthAC + Pdchip3 •
RthC + Tamb
ON
OFF
ON
Pdchip1 • RthA + Pdchip3 •
RthAC + Tamb
ON
ON
OFF
Pdchip1 • RthA + Pdchip2 • Pdchip1 • RthAB + Pdchip2 • RthB
RthAB + Tamb
+ Tamb
ON
OFF
OFF
ON
ON
ON
3.1.2
Pdchip1 • RthA+ Tamb
Pdchip1 • RthAB + Tamb
Pdchip1 • RthAC + Pdchip2 •
RthBC + Tamb
Pdchip1 • RthAC + Tamb
Pdchip1 • RthA + (Pdchip2 +
Pdchip2 • RthB + Pdchip1 •
Pdchip1 • RthAB + Pdchip2 •
Pdchip3) • RthAB + Tamb RthAB + Pdchip3 • RthBC + Tamb RthBC + Pdchip3 • RthC + Tamb
Thermal calculation in transient mode
Ths= Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA= PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zhsls + Tamb
TlsB= PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zhsls + Tamb
Figure 19. Chipset configuration
CHIP 1
Zls
Zhsls
Zhsls
CHIP 2
Zlsls
Zls
CHIP 3
Zls
Equation 1: pulse calculation formula
Z THδ = R TH ⋅ δ + ZTHtp ( 1 – δ )
where δ = t p ⁄ T
Doc ID 15701 Rev 9
27/37
Package and PCB thermal data
Figure 20.
VNH5019A-E
MultiPowerSO-30 HSD thermal impedance junction ambient single pulse
ZTH -HSD @ cu area
100
°C/W
10
HSD-16 cm^2 Cu
HSD-8 cm^2 Cu
HSD-4 cm^2 Cu
HSD-footprint
HsLsD-16 cm^2 Cu
HsLsD-8 cm^2 Cu
HsLsD-4 cm^2 Cu
HsLsD-footprint
1
0.1
0.001
0.01
0.1
time (sec) 1
10
100
1000
Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse
ZTH -LSD @ cu area
100
10
LSD-16 cm^2 Cu
LSD-8 cm^2 Cu
LSD-4 cm^2 Cu
LSD-footprint
LsLsD-16 cm^2 Cu
LsLsD-8 cm^2 Cu
LsLsD-4 cm^2 Cu
LsLsD-footprint
°C/W
Z ls
Z lsls
1
0.1
0.001
28/37
0.01
0.1
time (sec)
1
Doc ID 15701 Rev 9
10
100
1000
VNH5019A-E
Package and PCB thermal data
Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30
Table 18.
Thermal parameters(1)
Area/island (cm2)
Footprint
R1 = R7 (°C/W)
0.1
R2 = R8 (°C/W)
0.3
R3 = R10 = R16 (°C/W)
0.5
4
8
16
R4 (°C/W)
6
R5 (°C/W)
30
24
24
24
R6 (°C/W)
56
52
42
32
R9 = R15 (°C/W)
0.05
R11 = R17 (°C/W)
0.7
R12 = R18 (°C/W)
10
R13 = R19 (°C/W)
36
26
26
26
R14 = R20 (°C/W)
56
42
36
28
R21 = R22 (°C/W)
35
25
25
25
160
150
150
150
R23 (°C/W)
C1 = C7 = C9 = C15 (W.s/°C)
0.005
C2 = C8 (W.s/°C)
0.01
C3 (W.s/°C)
0.03
C4 (W.s/°C)
0.4
C5 (W.s/°C)
1.5
2
2
2
3
4
5
6
C6 (W.s/°C)
C10 = C16 (W.s/°C)
0.015
C11 = C17 (W.s/°C)
0.05
C12 = C18 (W.s/°C)
0.3
C13 = C19 (W.s/°C)
1.2
2
2
2
C14 = C20 (W.s/°C)
2.5
3
4
5
C21 = C22 = C23 (W.s/°C)
0.01
0.008
0.008
0.008
1. The blank space means that the value is the same as the previous one.
Doc ID 15701 Rev 9
29/37
Package and packing information
VNH5019A-E
4
Package and packing information
4.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.2
MultiPowerSO-30 mechanical data
Figure 23. MultiPowerSO-30 package dimensions
S
A3
0.35
A2
N
L
BOTTOM VIEW
F1
h x 45°
B
F1
e
A
F2
E
E1
F2
30
1
C
D
30/37
Doc ID 15701 Rev 9
F3
VNH5019A-E
Package and packing information
Table 19.
MultiPowerSO-30 mechanical data
Data book mm
Symbol
Min.
Typ.
A
Max.
2.35
A2
1.85
2.25
A3
0
0.1
B
0.42
0.58
C
0.23
0.32
D
17.1
E
18.85
E1
15.9
e
17.2
17.3
19.15
16
16.1
1
F1
5.55
6.05
F2
4.6
5.1
F3
9.6
10.1
L
0.8
1.15
N
S
10°
0°
Doc ID 15701 Rev 9
7°
31/37
Package and packing information
4.3
VNH5019A-E
MultiPowerSO-30 suggested land pattern
Figure 24. MultiPowerSO-30 suggested pad layout
32/37
Doc ID 15701 Rev 9
VNH5019A-E
4.4
Package and packing information
MultiPowerSO-30 packing information
The devices can be packed in tube or tape and reel shipments (see Table 20: Device
summary for packaging quantities).
Figure 25. MultiPowerSO-30 tube shipment (no suffix)
Dimension
A
C
B
mm
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.13)
29
435
532
3.82
23.6
0.8
Figure 26. MultiPowerSO-30 tape and reel shipment (suffix “TR”)
Reel dimensions
SO-28 tube shipment (no suffix)
Dimension
mm
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
D (min)
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
32
100
38.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Description
Dimension
mm
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
32
4
24
1.5
2
14.2
2.2
2
End
Start
Top
cover
tape
No components
Components
No components
500 mm min
500 mm min
Empty components pockets
User direction of feed
Doc ID 15701 Rev 9
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Order codes
5
VNH5019A-E
Order codes
Table 20.
Device summary
Order codes
Package
MultiPowerSO-30
34/37
Tube
Tape and reel
VNH5019A-E
VNH5019TR-E
Doc ID 15701 Rev 9
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6
Revision history
Revision history
Table 21.
Document revision history
Date
Revision
22-Jan-2008
1
Initial release.
2
Uploaded corporate template by using V3 version
Added Table 5: Thermal data
Section 2.1: Absolute maximum ratings
– Added text
Table 6: Power section
– IS: added max value for INA = INB = PWM = 0; Tj = 25 °C;
VCC=13V in Test conditions, deleted INA = INB = PWM = 0
– Vf: changed Test conditions, changed typ/max value
– IRM: deleted and copied in Table 8: Switching (VCC = 13 V,
RLOAD = 0.87 W, Tj = 25 °C) whole row
Table 8: Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C)
– tDEL: changed min/typ/max value
– Copied IRM row by Table 6: Power section
Updated Table 10: Current sense (8 V < VCC < 21 V)
Table 11: Charge pump
– VCP: changed min/max value for ENX = 5 V, changed typ
value for ENX = 5 V, VCC = 4.5 V
Updated Figure 11: Waveforms in full bridge operation (part 1)
Updated Figure 12: Waveforms in full bridge operation (part 2)
Added Chapter 4
3
Updated following tables:
– Table 6: Power section
– Table 9: Protection and diagnostic
– Table 10: Current sense (8 V < VCC < 21 V)
Added Figure 6: Behavior in fault condition (how a fault can be
cleared)
Added Chapter 3: Package and PCB thermal data
06-Apr-2010
4
Updated Table 5: Thermal data.
Table 6: Power section:
– IS: updated test condition and max value
Updated table notes on Table 9: Protection and diagnostic.
Table 10: Current sense (8 V < VCC < 21 V):
– dK0/k0, dK1/k1, dK3/k3: updated minimum end maximum
values.
19-Apr-2010
5
Updated Table 10: Current sense (8 V < VCC < 21 V).
25-May-2010
6
Updated Features list.
Updated Table 6: Power section.
02-Sep-2010
7
Updated Table 5: Thermal data.
04-Nov-2009
16-Dec-2009
Changes
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Revision history
VNH5019A-E
Table 21.
Document revision history (continued)
Date
36/37
Revision
Changes
22-Dec-2011
8
Updated Figure 1: Block diagram
Added Table 1: Suggested connections for unused and not
connected pins
Updated Table 3: Block descriptions
Table 8: Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C):
– TTSD, TTR, THYST: added note
– TTSD_LS: added row
Updated Table 13: Truth table in fault conditions (detected on
OUTA)
Updated Figure 11: Waveforms in full bridge operation (part 1)
and Figure 12: Waveforms in full bridge operation (part 2)
19-Sep-2013
9
Updated Disclaimer.
Doc ID 15701 Rev 9
VNH5019A-E
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