ESDALC6V1-5T6 Low capacitance Transil™ arrays for ESD protection Features ■ 5 unidirectional Transil diodes ■ Breakdown voltage VBR = 6.1 V min. ■ Low diode capacitance: 7 pF typ. ■ Low leakage current < 100 nA ■ Very small PCB area: 1.0 mm² ■ 350 µm pitch micro-package ■ Lead-free and RoHS package Micro DFN package 1.0 x 1.0-6L Complies with the following standards ■ IEC 61000-4-2: – 15 kV (air discharge) – 8 kV (contact discharge) ■ MIL STD 883G- Method 3015-7: class3B: – >8 kV (human body model) Figure 1. Functional diagram (top view) Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as: ■ Cellular phone handsets and accessories ■ Computers ■ Printers ■ Communication systems ■ Video equipment ■ Set top boxes Description The ESDALC6V1-5T6 is monolithic arrays designed to protect up to 5 lines against ESD transients. The device is ideal for applications where both reduced print circuit board space and high ESD protection level are required. TM: Transil is a trademark of STMicroelectronics March 2011 Doc ID 16741 Rev 2 1/11 www.st.com 11 Characteristics 1 ESDALC6V1-5T6 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter VPP ESD IEC 61000-4-2, air discharge ESD IEC 61000-4-2, contact discharge PPP Peak pulse power dissipation (8/20 µs)(1) Ipp Repetitive peak pulse current typical value (8/20 µs) Tj Junction temperature Tstg Unit 15 8 kV 25 W 2 A 125 °C -55 + 150 °C 260 °C Tj initial = Tamb Storage temperature range TL Value Maximum lead temperature for soldering during 10 s 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) I IF Symbol VBR = IRM = VRM = Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage VF VCL VBR VRM V IRM Slope: 1/Rd Table 2. Electrical characteristics (values, Tamb = 25 °C) Symbol 2/11 Test conditions VBR IR = 1 mA IRM VRM = 3 V C IPP Min. Typ. 6.1 VR = 3 V DC, Fosc = 1 MHz, Vosc = 30 mV rms Doc ID 16741 Rev 2 7 Max. Unit 7.2 V 100 nA 9 pF ESDALC6V1-5T6 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tjinitial]/PPP[Tjinitial = 25 °C] 1.1 Peak pulse power versus exponential pulse duration PPP(W) 1000 Tjinitial = 25 °C 1.0 0.9 0.8 100 0.7 0.6 0.5 0.4 10 0.3 0.2 0.1 Tj(°C) 0.0 0 25 Figure 5. 10.0 50 75 100 125 1 150 Clamping voltage versus peak pulse current (typical values, exponential waveform) tp (µs) 1 10 Figure 6. IPP(A) 100 1000 Forward voltage drop versus peak forward current (typical values) IFM(A) 10.00 Wave 8/20 µs T= 25 °C 1.00 0.10 1.0 0.01 VCL (V) 0.1 5 Figure 7. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 7 8 9 10 11 12 13 Junction capacitance versus reverse voltage applied (typical values) 0.00 0.00 Figure 8. C (pF) 100 F = 1 MHz VOSC = 30 mVRMS TJ = 25 °C VFM(V) 0.50 1.00 1.50 2.00 2.50 3.00 Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj = 25 °C] VR = 3 V 10 IO/GND IO/IO V 0 1 2 3 4 Tj (°C) 1 5 25 Doc ID 16741 Rev 2 50 75 100 125 3/11 Ordering information scheme Figure 9. 0.00 ESDALC6V1-5T6 S21 attenuation measurement results of each channel Figure 10. Analog crosstalk measurements between channels dB 0.00 dB -20.00 -5.00 -40.00 -10.00 -60.00 -15.00 -80.00 -20.00 -100.00 -25.00 -120.00 F/Hz -30.00 100.0K 1.0M 10.0M 100.0M Figure 11. ESD response to IEC 61000-4-2 (+15 kV air discharge) on each channel F/Hz -140.00 100.0K 1.0G 1.0M 10.0M 100.0M 1.0G Figure 12. ESD response to IEC 61000-4-2 (-15 kV air discharge) on each channel 10 V/Div 5 V/Div C2 C2 100 ns/Div 2 100 ns/Div Ordering information scheme Figure 13. Ordering information scheme ESDA LC ESD array Low capacitance Breakdown voltage 6V1 = 6.1 Volts min Package 5 = 5 lines T = Micro DFN, pitch 0.35 mm 6 = 6 pads 4/11 Doc ID 16741 Rev 2 6V1 5T6 ESDALC6V1-5T6 3 Package information Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. Micro DFN 1.0 x 1.0-6L dimensions Dimensions Ref. Typ. Max. Min. Typ. Max. A 0.31 - 0.40 0.012 - 0.016 A1 0.00 0.02 0.05 0.00 b 0.10 0.15 0.20 0.004 0.006 0.008 D 0.95 1.00 1.05 0.037 0.039 0.041 E 0.95 1.00 1.05 0.037 0.039 0.041 L1 0.22 0.32 0.42 0.009 0.012 0.016 e - 0.35 - b PIN#1 ID 0.0008 0.002 0.06 L1 E 0.56 L=0.36 ±0.10 Index area (D/2xE/2) Index area (D/2xE/2) Inches Min. e D Millimeters BOTTOM VIEW A A1 TOP VIEW SEATING PLANE SIDE VIEW - 0.014 - Figure 14. Footprint dimensions (in mm) Figure 15. Marking 0.150 0.175 1.280 0.520 0.175 0.520 Pin 1 0.560 0.240 K 0.375 0.200 0.900 Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 16741 Rev 2 5/11 Package information ESDALC6V1-5T6 Figure 16. Tape and reel specifications 2.0 ± 0.05 4.0 ± 0.1 Ø 1.50 + 0.10 / -0.00 1.75 ± 0.1 Dot identifying Pin 1 location 3.5 ± 0.05 1.13 ± 0.05 8.0 ± 0.3 0.23 ± 0.02 K K 1.13 ± 0.05 K 2.0 ± 0.05 0.53± 0.05 All dimensions in mm 6/11 User direction of unreeling Doc ID 16741 Rev 2 ESDALC6V1-5T6 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 17. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio is 100%. Figure 18. Recommended stencil window position µm 520 T=100 µm and opening ratio is 100% 0.175 0.150 0.175 0.520 1.280 0.240 0.560 0.520 150 µm 0.375 0.200 µm 550 µm 520 0.900 Footprint Stencil window Footprint 175 µm 175 µm Doc ID 16741 Rev 2 7/11 Recommendation on PCB assembly 4.2 4.3 4.4 8/11 ESDALC6V1-5T6 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 16741 Rev 2 ESDALC6V1-5T6 4.5 Recommendation on PCB assembly Reflow profile Figure 19. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 16741 Rev 2 9/11 Ordering information 5 ESDALC6V1-5T6 Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC6V1-5T6 K(1) DFN1.0 x1.0-6L 1.78 mg 3000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 6 Revision history Table 5. 10/11 Document revision history Date Revision Changes 05-Nov-2009 1 Initial release. 03-Mar-2011 2 Added Figure 15 and following note. Added footnote toTable 4. Doc ID 16741 Rev 2 ESDALC6V1-5T6 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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