L5983 1.5 A step-down switching regulator Datasheet - production data Industrial: chargers, PLD, PLA, FPGA Networking: XDSL, modems, DC-DC modules Computer: optical storage, hard disk drive, printers, audio/graphic cards VFQFPN8 3 x 3 mm LED driving Features Description 1.5 A DC output current The L5983 is a step-down switching regulator with a 2.0 A (min.) current limited embedded Power MOSFET, so it is able to deliver an output current in excess of 1.5 A DC to the load. 2.9 V to 18 V input voltage Output voltage adjustable from 0.6 V 250 kHz switching frequency, programmable up to 1 MHz Internal soft-start and inhibit Low dropout operation: 100% duty cycle Voltage feedforward Zero load current operation Overcurrent and thermal protection VFQFPN8 3 x 3 mm package Applications The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from 0.6 V to VIN. Having a minimum input voltage of 2.9 V, the device is suitable also for a 3.3 V bus. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The VFQFPN package with an exposed pad allows reducing the RthJA down to approximately 60 °C/W. Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors Figure 1. Application circuit May 2014 This is information on a product in full production. DocID13005 Rev 8 1/41 www.st.com Contents L5983 Contents 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 6 2/41 4.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DocID13005 Rev 8 L5983 Contents 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID13005 Rev 8 3/41 41 Pin settings L5983 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) OUT VCC SYNCH GND INH FSW COMP 1.2 FB Pin description Table 1. Pin description 4/41 No. Type 1 OUT Description Regulator output 2 SYNCH Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period with respect to the power turn-on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift. Connecting together the SYNCH pin of two devices, the one with the higher frequency works as a master and the other as a slave; so the turnon of the two power switches has a phase shift of half a period. 3 INH A logical signal (active high) disables the device. With INH higher than 1.9 V the device is OFF and with INH lower than 0.6 V the device is ON. 4 COMP 5 FB Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from the Vout to the FB pin. 6 FSW The switching frequency can be increased connecting an external resistor from the FSW pin and ground. If this pin is left floating the device works at its free running frequency of 250 kHz. 7 GND Ground 8 VCC Unregulated DC input voltage Error amplifier output to be used for loop frequency compensation DocID13005 Rev 8 L5983 Maximum ratings 2 Maximum ratings 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VCC Input voltage OUT Output DC voltage Value Unit 20 -0.3 to VCC FSW, COMP, SYNCH Analog pin -0.3 to 4 INH Inhibit pin -0.3 to VCC FB Feedback voltage -0.3 to 1.5 PTOT 2.2 Parameter Power dissipation at TA < 60 °C V 1.5 W TJ Junction temperature range -40 to 150 °C Tstg Storage temperature range -55 to 150 °C Thermal data Table 3. Thermal data Symbol Parameter Value Unit RthJA Maximum thermal resistance VFQFPN junction ambient(1) 60 °C/W 1. Package mounted on demonstration board. DocID13005 Rev 8 5/41 41 Electrical characteristics 3 L5983 Electrical characteristics TJ = 25 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Operating input voltage range (1) Turn-on VCC threshold (1) VCCHYS VCC UVLO hysteresis (1) RDS(on) MOSFET on resistance VCC VCCON ILIM 2.9 Max. 18 2.9 0.175 V 0.3 140 170 140 220 2.0 2.3 2.6 225 250 275 (1) Maximum limiting current Typ. m A Oscillator FSW Switching frequency VFSW FSW pin voltage D FADJ (1) 275 1.254 Duty cycle Adjustable switching frequency 220 0 RFSW = 33 k kHz V 100 1000 % kHz Dynamic characteristics VFB Feedback voltage 2.9 V < VCC < 18 V(1) 0.593 0.6 0.607 V 2.4 mA 30 A DC characteristics IQ IQST-BY Quiescent current Duty cycle = 0, VFB = 0.8 V Total standby quiescent current 20 Inhibit INH threshold voltage INH current Device ON level Device OFF level 0.6 1.9 INH = 0 7.5 10 8.2 9.1 V A Soft-start TSS Soft-start duration FSW pin floating 7.4 FSW = 1 MHz, RFSW = 33 k 2 ms Error amplifier 6/41 VCH High level output voltage VFB < 0.6 V VCL Low level output voltage VFB > 0.6 V IFB Bias source current VFB = 0 V to 0.8 V DocID13005 Rev 8 3 0.1 1 V A L5983 Electrical characteristics Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. IO SOURCE Source COMP pin IO SINK GV Typ. Max. VFB = 0.5 V, VCOMP = 1 V 20 mA Sink COMP pin VFB = 0.7 V, VCOMP = 1 V 25 mA Open loop voltage gain (2) 100 dB Synchronization function High input voltage 2 3.3 Low input voltage 1 Slave sink current VSYNCH = 2.9 V Master output amplitude ISOURCE = 4.5 mA Output pulse width SYNCH floating Input pulse width 0.7 0.9 2.0 V mA V 110 70 ns Protection IFBDISC TSHDN(2) FB disconnection source current 1 Thermal shutdown 150 Hysteresis 30 A °C 1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation. 2. Guaranteed by design. DocID13005 Rev 8 7/41 41 Functional description 4 L5983 Functional description The L5983 device is based on a “voltage mode”, constant frequency control. The output voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and OFF time of the power switch. The main internal blocks are shown in the block diagram in Figure 3. They are: A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The voltage and frequency feedforward are implemented. The soft-start circuitry to limit inrush current during the startup phase The voltage mode error amplifier The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch The high-side driver for embedded P-channel Power MOSFET switch The peak current limit sensing block, to handle overload and short-circuit conditions A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference. A voltage monitor circuitry (UVLO) that checks the input and internal voltages. A thermal shutdown block, to prevent thermal runaway. Figure 3. Block diagram 8/41 DocID13005 Rev 8 L5983 4.1 Functional description Oscillator and synchronization Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor externally connected to the FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as shown in Figure 6 by the external resistor connected to ground. To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feedforward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 5.a). The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feedforward is implemented (Figure 5.b) in order to keep the PWM gain constant versus the switching frequency (see Section 5.4 on page 18 for PWM gain expression). The synchronization signal is generated on the SYNCH pin. This signal has a phase shift of 180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pins together. When SYNCH pins are connected, the device with a higher oscillator frequency works as a master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet: “4 A continuous (more than 5 A pulsed) step-down switching regulator with synchronous rectification”). Figure 4. Oscillator circuit block diagram Clock FSW Clock Generator Synchronization SYNCH Ramp Generator Sawtooth The device can be synchronized to work at a higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain (Figure 5.c). This change has to be taken into account when the loop stability is studied. To minimize the change of the PWM gain, the free running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render the truncation of sawtooth negligible, due to the external synchronization. DocID13005 Rev 8 9/41 41 Functional description L5983 Figure 5. Sawtooth: voltage and frequency feedforward; external synchronization Figure 6. Oscillator frequency vs. FSW pin resistor 10/41 DocID13005 Rev 8 L5983 4.2 Functional description Soft-start The soft-start is essential to assure a correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monotonically. The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error amplifier. So the output voltage slew rate is: Equation 1 R1 SR OUT = SR VREF 1 + -------- R2 where SRVREF is the slew rate of the non-inverting input, while R1 and R2 is the resistor divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 7. Soft-start scheme Soft-start time results: Equation 2 32 64 SS TIME = ----------------Fsw For example, with a switching frequency of 250 kHz the SSTIME is 8 ms. DocID13005 Rev 8 11/41 41 Functional description 4.3 L5983 Error amplifier and compensation The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are the following: Table 5. Uncompensated error amplifier characteristics Error amplifier Value Low frequency gain 100 dB GBWP 4.5 MHz Slew rate 7 V/s Output voltage swing 0 to 3.3 V Maximum source/sink current 25 mA/40 mA In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see Section 5.4 on page 18 for details of the compensation network selection). However, the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin. 12/41 DocID13005 Rev 8 L5983 4.4 Functional description Overcurrent protection The L5983 device implements the overcurrent protection sensing current flowing through the Power MOSFET. Due to the noise created by the switching activity of the Power MOSFET, the current sensing is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 200 ns. When the overcurrent is detected, two different behaviors are possible depending on the operating condition. 1. Output voltage in regulation. When the overcurrent is sensed, the Power MOSFET is switched off and the internal reference (VREF), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal reference begins ramping (see Figure 8.a). 2. Soft-start phase. If the overcurrent limit is reached, the Power MOSFET is turned off implementing the pulse by pulse overcurrent protection. During the soft-start phase, under the overcurrent condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the Power MOSFET is turned off and it skips one pulse. If, at the next switching on at the end of the “masking time”, the current is still higher than the threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the “masking time” the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit. At the end of the soft-start phase the output voltage is in regulation and if the overcurrent persists, the behavior explained above takes place (see Figure 8.b). So the overcurrent protection can be summarized as a “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase. If the output is shorted to ground when the output voltage is in regulation, the overcurrent is triggered and the device starts cycling with a period of 2048 clock cycles between the “hiccup” (Power MOSFET off and no current to the load) and “constant current” with very short ON time and with reduced switching frequency (up to one eighth of normal switching frequency). See Figure 32 on page 33 for short-circuit behavior. DocID13005 Rev 8 13/41 41 Functional description L5983 Figure 8. Overcurrent protection strategy 4.5 Inhibit function The inhibit feature allows the device to be put into standby mode. With the INH pin higher than 1.9 V, the device is disabled and the power consumption is reduced to less than 30 A. With the INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 4.6 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, therefore ensuring an accurate and fast temperature detection. 14/41 DocID13005 Rev 8 L5983 Application information 5 Application information 5.1 Input capacitor selection The capacitor connected to the input must be able to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 3 2 2 2D D I RMS = I O D – --------------- + ------2 where IO is the maximum DC output current, D is the duty cycle, is the efficiency. Considering this function has a maximum at D = 0.5 and it is equal to IO/2. In a specific application the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 4 V OUT + V F D MAX = ------------------------------------V INMIN – V SW and Equation 5 V OUT + V F D MIN = -------------------------------------V INMAX – V SW where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. In Table 6 some multi-layer ceramic capacitors suitable for this device are reported. Table 6. Input capacitors Manufacturer MURATA TDK Series Cap value (F) Rated voltage (V) GRM31 10 25 GRM55 10 25 C3225 10 25 DocID13005 Rev 8 15/41 41 Application information 5.2 L5983 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. The inductance value can be calculated by the following equation: Equation 6 V IN – V OUT V OUT I L = ------------------------------ T ON = -------------- T OFF L L where TON is the conduction time of the internal high-side switch and TOFF is the conduction time of the external diode [in CCM, FSW = 1 / (TON + TOFF)]. The maximum current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle (see Section 5.1 to calculate minimum duty). So fixing IL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated as: Equation 7 V OUT + V F 1 – D MIN L MIN = ---------------------------- ----------------------I MAX F SW where FSW is the switching frequency, 1 / (TON + TOFF). For example, for VOUT = 3.3 V, VIN = 12 V, IO = 1.5 A and FSW = 250 kHz, the minimum inductance value to have IL = 30% of IO is about 21H. The peak current through the inductor is given by: Equation 8 I L I L PK = I O + -------2 So if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table 7 some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (H) Saturation current (A) Wurth PD 3.3 to 6.8 2.75 to 4.2 MSS1038 15 to 18 3.2 to 3.6 MSS7341 3.3 to 6.2 2.5 to 3.5 CD1 15 to 22 2.9 to 3.6 UP2.8B 4.7 to 10 2.7 to 3.9 HM76-3 15 to 33 2.5 to 3.7 CDRH8D28 4.7 to 10 2.5 to 3.4 CDRH8D28/HP 15 to 22 2.5 to 2.8 Coilcraft Coiltronics BI SUMIDA 16/41 DocID13005 Rev 8 L5983 5.3 Application information Output capacitor selection The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 9 I MAX V OUT = ESR I MAX + ------------------------------------8 C OUT f SW Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Section 5.4, how to consider its effect in the system stability is illustrated. For example, with VOUT = 3.3 V, VIN = 12 V, IL = 0.5 A (resulting from the inductor value), in order to have a VOUT = 0.01·VOUT, if the multi-layer ceramic capacitor is adopted, 10 F is needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So in case of 100 F with ESR = 40 m, the resistive component of the drop dominates and the voltage ripple is 20 mV. The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application, the output capacitor and system bandwidth must be chosen in order to sustain the load transient. In Table 8 some capacitor series are listed. Table 8. Output capacitors Manufacturer Series Cap value (F) Rated voltage (V) ESR (m) GRM32 22 to 100 6.3 to 25 <5 GRM31 10 to 47 6.3 to 25 <5 ECJ 10 to 22 6.3 <5 EEFCD 10 to 68 6.3 15 to 55 SANYO TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 <5 MURATA PANASONIC DocID13005 Rev 8 17/41 41 Application information 5.4 L5983 Compensation network The compensation network has to assure stability and good dynamic performance. The loop of the L5983 device is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So, by selecting the compensation network the E/A is considered as ideal, that is, its bandwidth is much larger than that of the system. The transfer functions of the PWM modulator and the output LC filter are studied (see Figure 9). The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the OUT pin, results: Equation 10 V IN G PW0 = --------Vs where VS is the sawtooth amplitude. As seen in Section 4.1 on page 9, the voltage feedforward generates a sawtooth amplitude directly proportional to the input voltage, that is: Equation 11 V S = K V IN In this way the PWM modulator gain results constant and equal to: Equation 12 V IN 1 G PW0 = --------- = ---- = 9 Vs K The synchronization of the device with an external clock provided trough the SYNCH pin can modify the PWM modulator gain (see Section 4.1 to understand how this gain changes and how to keep it constant in spite of the external synchronization). The transfer function on the LC filter is given by: Equation 13 s 1 + -------------------------2 f zESR G LC s = ------------------------------------------------------------------------2s s 1 + ---------------------------- + ------------------- 2 Q f LC 2 f LC where: Equation 14 1 f LC = ------------------------------------------------------------------------ ESR 2 L C OUT 1 + --------------R OUT 18/41 DocID13005 Rev 8 1 f zESR = -------------------------------------------2 ESR C OUT L5983 Application information Equation 15 R OUT L C OUT R OUT + ESR Q = ------------------------------------------------------------------------------------------ , L + C OUT R OUT E SR V OUT R OUT = -------------I OUT As seen in Section 4.3 on page 12, two different kinds of network can compensate the loop. In the two following paragraphs the guidelines to select the type II and type III compensation network are illustrated. Figure 9. Error amplifier, PWM modulator and LC output filter VCC VS VREF FB PWM E/A L OUT COMP ESR GPW0 5.4.1 GLC COUT Type III compensation network The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, therefore increasing phase margin; then to place one pole in the origin to minimize the DC error on regulated output voltage; finally to place other poles far from the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 * ESR * COUT < 1 /BW), the type III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low ESR (< 1 m), with very high frequency zero, so a type III network is adopted to compensate the loop. In Figure 10 the type III compensation network is shown. This network introduces two zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as: Equation 16 1 f Z1 = ------------------------------------------------ 2 C 3 R 1 + R 3 1 f Z2 = -----------------------------2 R 4 C 4 Equation 17 f P0 = 0 1 f P1 = ------------------------------ 2 R 3 C 3 DocID13005 Rev 8 1 f P2 = -------------------------------------------C4 C5 2 R 4 -------------------C4 + C5 19/41 41 Application information L5983 Figure 10. Type III compensation network In Figure 11 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)] and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)] is given. Figure 11. Open loop gain: module Bode diagram The guidelines for positioning the poles and the zeros and for calculating the component values can be summarized as follows: 1. Choose a value for R1, usually between 1 k and 5 k. 2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means: Equation 18 BW K R 4 = ------------------ R 1 f LC where K is the feedforward constant and 1 / K is equal to 9. 20/41 DocID13005 Rev 8 L5983 Application information 3. Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC): Equation 19 1 C 4 = -------------------------- R 4 f LC 4. Calculate C5 by placing the second pole at four times the system bandwidth (BW): Equation 20 C4 C 5 = -------------------------------------------------------------2 R 4 C 4 4 BW – 1 5. Set the first pole also at four times the system bandwidth and also the second zero at the output filter double pole: Equation 21 R1 R 3 = --------------------------- 4 BW ----------------- – 1 f LC 1 C 3 = ----------------------------------------2 R 3 4 BW The suggested maximum system bandwidth is equal to the switching frequency divided by 3.5 (FSW / 3.5), but lower than 100 kHz if the FSW is set higher than 500 kHz. For example, with VOUT = 3.3 V, VIN = 12 V, IO = 1.5 A, L = 22 H, COUT = 22 F, ESR < 1 m, the type III compensation network is: R 1 = 4.99k R 2 = 1.1k R 3 = 120 R 4 = 4.99k DocID13005 Rev 8 C 3 = 4.7nF C 4 = 10nF C 5 = 68pF 21/41 41 Application information L5983 In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about 77 kHz and the phase margin is 47°. Figure 12. Open loop gain Bode diagram with ceramic output capacitor 22/41 DocID13005 Rev 8 L5983 5.4.2 Application information Type II compensation network If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2* ESR * COUT > 1 / BW), this zero helps stabilize the loop. Electrolytic capacitors show not negligible ESR (> 30 m), so with this kind of the output capacitor the type II network combined with the zero of the ESR allows the loop to be stabilized. In Figure 13 the type II network is shown. Figure 13. Type II compensation network The singularities of the network are: Equation 22 1 f Z1 = ------------------------------ 2 R 4 C 4 f P0 = 0 DocID13005 Rev 8 1 f P1 = -------------------------------------------C4 C5 2 R 4 -------------------C4 + C5 23/41 41 Application information L5983 In Figure 14 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)] and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] is given. Figure 14. Open loop gain: module Bode diagram The guidelines for positioning the poles and the zeros and for calculating the component values can be summarized as follows: 1. Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. 2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means: Equation 23 f ESR 2 BW V S R 4 = ------------ ------------ --------- R 1 f LC f ESR V IN where fESR is the ESR zero: Equation 24 1 f ESR = -------------------------------------------2 ESR C OUT and VS is the sawtooth amplitude. The voltage feedforward keeps the ratio VS/VIN constant. 3. Calculate C4 by placing the zero one decade below the output filter double pole: Equation 25 10 C 4 = ------------------------------2 R 4 f LC 24/41 DocID13005 Rev 8 L5983 Application information 4. Then calculate C3 in order to place the second pole at four times the system bandwidth (BW): Equation 26 C4 C 5 = -------------------------------------------------------------2 R 4 C 4 4 BW – 1 For example, with VOUT = 3.3 V, VIN = 12 V, IO = 1.5 A, L = 22 H, COUT = 330 F, ESR = 50 m the type II compensation network is: R 1 = 1.1k R 2 = 249 R 4 = 10k DocID13005 Rev 8 C 4 = 6.8nF C 5 = 68pF 25/41 41 Application information L5983 In Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about 30 kHz and the phase margin is 45°. Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor 26/41 DocID13005 Rev 8 L5983 5.5 Application information Thermal considerations The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) Conduction losses due to the not negligible RDS(on) of the power switch; these are equal to: Equation 27 2 P ON = R DS on I OUT D where D is the duty cycle of the application and the maximum RDS(on) is 220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increase compared with the ideal case. b) Switching losses due to Power MOSFET turn-on and -off; these can be calculated as: Equation 28 T RISE + T FALL P SW = V IN I OUT ------------------------------------------- Fsw = V IN I OUT T SW F SW 2 where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn-on and turn-off phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 50 ns. c) Quiescent current losses, calculated as: Equation 29 P Q = V IN I Q where IQ is the quiescent current. (IQ = 2.4 mA). The junction temperature TJ can be calculated as: Equation 30 T J = T A + Rth JA P TOT where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA, measured on the demonstration board described in Section 5.6: Layout considerations, is about 60 °/W. DocID13005 Rev 8 27/41 41 Application information L5983 Figure 16. Switching losses 5.6 Layout considerations The PC board layout of the switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. In a step-down converter the input loop (including the input capacitor, the Power MOSFET and the freewheeling diode) is the most critical one. This is due to the fact that the high value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as short as possible. To filter the high frequency noise, a small capacitor can be added as close as possible to the input voltage pin of the device. The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interferences can be minimized placing the routing of the feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion. 28/41 DocID13005 Rev 8 L5983 Application information In Figure 17 a layout example is shown. Figure 17. Layout example DocID13005 Rev 8 29/41 41 Application information 5.7 L5983 Application circuit In Figure 18 the demonstration board application circuit is shown. Figure 18. Demonstration board application circuit VIN=3.3V to 18V VCC INH GND C1 C6 10uF 68nF 8 1 3 2 L5985 L5983 L1 6.8uH OUT D1 SYNCH STPS2L25U 7 FSW 22uF 5 4 C4 10nF COMP R3 330 R4 2.49K R5 100K C2 R1 4.99K FB 6 Vout=3.3V C3 2.2nF R2 1.1K C5 220pF Table 9. Component list 30/41 Reference Part number Description Manufacturer C1 GRM31CR61E106KA12 10 F, 25 V MURATA C2 GRM31CR61C226KE15B 22 F, 16 V MURATA C3 2.2 nF, 50 V C4 10 nF, 50 V C5 220 pF, 50 V C6 68 nF, 25 V R1 4.99 k, 1%, 0.1 W 0603 R2 1.1 k, 1%, 0.1 W 0603 R3 330 , 1%, 0.1 W 0603 R4 2.99 k, 1%, 0.1 W 0603 R5 100 k, 1%, 0.1 W 0603 L1 7447779006 6.8 H, 30%, 2.91 A Coilcraft D1 STPS2L25V 2 A, 25 V STMicroelectronics DocID13005 Rev 8 L5983 Application information Figure 19. PCB layout (component side) Figure 20. PCB layout (bottom side) Figure 21. PCB layout (front side) DocID13005 Rev 8 31/41 41 Application information L5983 Figure 22. Junction temperature vs. output current - VCC = 5 V Figure 23. Junction temperature vs. output current - VCC = 12 V Figure 24. Junction temperature vs. output current - VCC = 18 V Figure 25. Efficiency vs. output current - VCC = 12 V 95 Vo=5V Efficiency [%] 90 Vo=3.3V 85 Vo=2.5V 80 VCC=12V, FSW =250kHz 75 70 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Io [A] Figure 26. Efficiency vs. output current - VCC = 5 V 94 Figure 27. Efficiency vs. output current - VCC = 3.3 V 95 92 Vo=3.3V E ffic ie nc y [% ] E ffic ie nc y [% ] 88 Vo=2.5V 84 80 Vo=1.8V 80 Vo=1.2V 75 VCC=5V, FSW=250kHz 78 Vo=1.8V 85 86 82 Vo=2.5V 90 90 VCC=3.3V, FSW=250kHz 70 76 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 32/41 0.2 0.4 0.6 0.8 Io [A] Io [A] DocID13005 Rev 8 1 1.2 1.4 1.6 1.8 L5983 Application information Figure 28. Load regulation 0.4 0.4 0.35 0.35 0.25 V CC=12V 0.2 V CC=18V 0.15 0.1 0.3 V FB /V FB [% ] V CC=5V 0.3 VFB/VFB [%] Figure 29. Line regulation 0.25 0.2 0.15 0.1 Io=1A 0.05 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -0.05 2 4 6 8 10 12 14 16 18 VCC [V] IO [A] Figure 30. Load transient: from 300 mA to 1.3 A Figure 31. Soft-start VOUT AC coupled 100mV/div VOUT 0.5V/div COUT=47uF L=6.8uH FSW=500kHz IL 0.5A/div IL 0.5A/div VFB 200mV/div Timescale 100us/div Load slew rate = 2.5A/us Time base = 1 ms/div Figure 32. Short-circuit behavior OUT 10V/div IL 500mA/div VOUT 1V/div OUTPUT SHORTED Time base 5ms/div DocID13005 Rev 8 33/41 41 Application ideas L5983 6 Application ideas 6.1 Positive buck-boost The L5983 device can implement the step-up/down converter with a positive output voltage. Figure 33 shows the schematic: one Power MOSFET and one Schottky diode are added to the standard buck topology to provide 12 V output voltage with input voltage from 2.9 V to 18 V. Figure 33. Positive buck-boost regulator The relationship between input and output voltage is: Equation 31 D V OUT = V IN ------------1–D so the duty cycle is: Equation 32 V OUT D = -----------------------------V OUT + V IN The output voltage is not limited by the maximum operating voltage of the device (18 V), because the output voltage is sensed only through the resistor divider. The external Power MOSFET maximum drain to source voltage, must be higher than output voltage; the maximum gate to source voltage must be higher than the input voltage (in Figure 33, if VIN is higher than 16 V, the gate must be protected through a Zener diode and a resistor). The current flowing through the internal Power MOSFET is transferred to the load only during the OFF time, so according to the maximum DC switch current (1.5 A), the maximum output current for the buck-boost topology can be calculated from the following equation. Equation 33 I OUT I SW = ------------- 1.5 A 1–D where ISW is the average current in the embedded Power MOSFET in the ON time. 34/41 DocID13005 Rev 8 L5983 Application ideas To chose the right value of the inductor and to manage transient output current, which for a short time can exceed the maximum output current calculated by Equation 33, the peak current in the Power MOSFET must also be calculated. The peak current, shown in Equation 34, must be lower than the minimum current limit (2.0 A). Equation 34 I OUT r I SW,PK = ------------- 1 + --- 2.0A 1–D 2 V OUT 2 r = ------------------------------------ 1 – D I OUT L F SW where r is defined as the ratio between the inductor current ripple and the inductor DC current. Therefore, in the buck-boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value). In Figure 34 the maximum output current for the above configuration is depicted varying the input voltage from 2.9 V to 18 V. The dashed line considers a more accurate estimation of the duty cycles given by Equation 35, where power losses across diodes, the external Power MOSFET, and the internal Power MOSFET are taken into account. Figure 34. Maximum output current according to max DC switch current (1.5 A): VO = 12 V Equation 35 V OUT + 2 V D D = -------------------------------------------------------------------------------------------V IN – V SW – V SWE + V OUT + 2 V D where VD is the voltage drop across the diodes, and VSW and VSWE across the internal and external Power MOSFET. DocID13005 Rev 8 35/41 41 Application ideas 6.2 L5983 Inverting buck-boost The L5983 device can implement the step-up/down converter with a negative output voltage. Figure 33 shows the schematic to regulate -5 V: no further external components are added to the standard buck topology. The relationship between input and output voltage is: Equation 36 D V OUT = – V IN ------------1–D so the duty cycle is: Equation 37 V OUT D = -----------------------------V OUT – V IN As in the positive one, in the inverting buck-boost the current flowing through the Power MOSFET is transferred to the load only during the OFF time. So according to the maximum DC switch current (1.5 A), the maximum output current can be calculated from Equation 33, where the duty cycle is given by Equation 37. Figure 35. Inverting buck-boost regulator The GND pin of the device is connected to the output voltage so, given the output voltage, the input voltage range is limited by the maximum voltage, the device can withstand across VCC and GND (18 V). Therefore, if the output is -5 V, the input voltage can range from 2.9 V to 13 V. As in the positive buck-boost, the maximum output current according to application conditions is shown in Figure 36. The dashed line considers a more accurate estimation of the duty cycles given by Equation 38, where power losses across diodes and the internal Power MOSFET are taken into account: 36/41 DocID13005 Rev 8 L5983 Application ideas Equation 38 V OUT – V D D = ----------------------------------------------------------------– V IN – V SW + V OUT – V D Figure 36. Maximum output current according to max DC switch current (1.5 A): VO=-5 V DocID13005 Rev 8 37/41 41 Package information 7 L5983 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST registered trademark. Figure 37. VFQFPN8 (3 x 3 x 1.08 mm) package outline 38/41 DocID13005 Rev 8 L5983 Package information Table 10. VFQFPN8 (3 x 3 x 1.08 mm) package mechanical data Dimensions Symbol mm inch Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A2 0.70 0.0276 A3 0.20 0.0079 A b 0.18 0.23 0.30 0.0071 0.0091 0.0118 D 2.95 3.00 3.05 0.1161 0.1181 0.1200 D2 2.23 2.38 2.48 0.0878 0.0937 0.0976 E 2.95 3.00 3.05 0.1161 0.1181 0.1200 E2 1.65 1.70 1.75 0.0649 0.0669 0.0689 e L ddd 0.50 0.35 0.40 0.0197 0.45 0.08 DocID13005 Rev 8 0.0137 0.0157 0.0177 0.0031 39/41 41 Order codes 8 L5983 Order codes Table 11. Order codes 9 Order codes Package Packaging L5983TR VFQFPN8 (3 x 3 x 1.08 mm) Tape and reel Revision history Table 12. Document revision history Date Revision 21-Dec-2006 1 Initial release 16-Oct-2007 2 Document status promoted from preliminary data to datasheet 27-May-2008 3 Updated: Cover page, Figure 2 on page 4, Figure 8 on page 14, Figure 5 on page 10, Figure 17 on page 29, Figure 18 on page 30, Table 8 on page 17, Table 10 on page 39 Added: Table 3 on page 5 16-Sep-2008 4 Updated: Table 4 on page 6 and Figure 18 on page 30 28-Jan-2009 5 Updated: Equation 18 15-Jun-2009 6 Updated Table 4 on page 6 and Figure 6 on page 10 29-Nov-2010 7 Added: Section 6 on page 34 Updated: Figure 19, Figure 20 and Figure 21 on page 31 8 Numbered Equation 22 on page 23. Added VCC values to titles from Figure 22 on page 32 to Figure 27 on page 32. Updated Section 7: Package information on page 38 (updated titles, reversed order of Figure 37 and Table 10, minor modifications). Updated Table 11: Order codes (removed the L5983 order code related to the VFQFPN8 in tube, updated “Packaging” of the L5983TR order code). Updated cross-references throughout document. Minor modifications throughout document. 12-May-2014 40/41 Changes DocID13005 Rev 8 L5983 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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