STFI24NM60N N-channel 600 V, 0.168 Ω typ., 17 A MDmesh™ II Power MOSFET in a I²PAKFP package Datasheet − production data Features Order codes VDS @Tjmax RDS(on) max. ID STFI24NM60N 650 V 0.19 Ω 17 A • Fully insulated and low profile package with increased creepage path from pin to heatsink plate 1 2 • 100% avalanche tested 3 • Low input capacitance and gate charge I2PAKFP (TO-281) • Low gate input resistance Figure 1. Internal schematic diagram ' Applications • Switching applications Description This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. * 6 $0Y Table 1. Device summary Order code Marking Packages Packaging STFI24NM60N 24NM60N I2PAKFP (TO-281) Tube July 2014 This is information on a product in full production. DocID022440 Rev 3 1/12 www.st.com Contents STFI24NM60N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 .............................................. 8 DocID022440 Rev 3 STFI24NM60N 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Value Unit Gate- source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 17(1) A ID Drain current (continuous) at TC = 100 °C 11(1) A IDM (2) Drain current (pulsed) 68(1) A PTOT Total dissipation at TC = 25 °C 30 W Peak diode recovery voltage slope 15 V/ns 2500 V -55 to 150 °C VGS dv/dt(3) Parameter VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; TC=25 °C) TJ Tstg Operating junction temperature Storage temperature 1. Limited by maximum junction temperature. 2. Pulse width limited by safe operating area. 3. ISD ≤ 17 A, di/dt ≤ 400 A/µs, peak VDS ≤ V(BR)DSS, VDD = 80% V(BR)DSS Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max. 4.17 °C/W Rthj-amb Thermal resistance junction-ambient max. 62.5 °C/W Value Unit Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or notrepetitive (pulse width limited by TJ max) 6 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 300 mJ DocID022440 Rev 3 3/12 12 Electrical characteristics 2 STFI24NM60N Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current VGS = 0, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0, VDS = 600 V 1 µA VGS = 0, VDS = 600 V, TC=125 °C 100 µA VDS = 0, VGS = ± 25 V ±100 nA 3 4 V 0.168 0.19 Ω Min. Typ. Max. Unit - 1330 - pF - 80 - pF 3.2 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on- resistance 2 VGS = 10 V, ID = 8 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 - 182 - pF Rg Gate input resistance f=1 MHz open drain - 5 - Ω Qg Total gate charge - 44 - nC Qgs Gate-source charge - 7 - nC Qgd Gate-drain charge VDD = 480 V, ID = 17 A, VGS = 10 V (see Figure 15) - 24 - nC VDS = 50 V, f = 1 MHz, VGS = 0 - 1. Co(eff). is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS. 4/12 DocID022440 Rev 3 STFI24NM60N Electrical characteristics Table 7. Switching times Symbol td(on) tr(v) td(off) tf(i) Parameter Test conditions Turn-on delay time VDD = 300 V, ID = 8.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14) Voltage rise time Turn-off-delay time Fall time Min. Typ. Max Unit - 11.5 - ns - 16.5 - ns - 73 - ns - 37 - ns Table 8. Source drain diode Symbol ISD ISDM (1) VSD (2) Parameter Test conditions Min. Typ. Max Unit Source-drain current - 17 A Source-drain current (pulsed) - 68 A 1.6 V Forward on voltage ISD = 17 A, VGS = 0 - trr Reverse recovery time - 340 ns Qrr Reverse recovery charge - 4.6 µC IRRM Reverse recovery current ISD = 17 A, di/dt = 100 A/µs VDD= 60 V (see Figure 16) - 27 A ISD = 17 A, di/dt = 100 A/µs VDD= 60 V TJ = 150 °C (see Figure 16) - 404 ns - 5.7 µC - 28 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID022440 Rev 3 5/12 12 Electrical characteristics 2.1 STFI24NM60N Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM07975v1 D S( on ) O Li per m at ite io d ni by n m this ax a R rea is ID (A) 10 1 10µs 100µs 1ms 10ms Tj=150°C Tc=25°C 0.1 Sinlge pulse 0.01 0.1 10 1 100 VDS(V) Figure 4. Output characteristics Figure 5. Transfer characteristics AM07977v1 ID (A) 40 AM07978v1 ID (A) VGS = 10 V 40 VDS= 20 V VGS = 7 V 30 30 VGS = 6 V 20 20 10 10 VGS = 5 V 0 0 5 10 15 20 Figure 6. Gate charge vs gate-source voltage AM07979v1 VDS VGS (V) 12 VDD=480V (V) ID= 17A 500 VDS 10 0 0 25 VDS(V) 400 2 4 6 8 10 VGS(V) Figure 7. Static drain-source on-resistance AM08534v1 RDS(on) (Ω) 0.176 0.174 VGS=10V 0.172 0.170 8 300 6 0.168 0.166 200 0.164 4 100 2 0.160 0 0 6/12 0.162 10 20 30 40 50 0 Qg(nC) 0.158 0 DocID022440 Rev 3 5 10 15 ID(A) STFI24NM60N Electrical characteristics Figure 8. Capacitance variations C (pF) Figure 9. Output capacitance stored energy AM08535v1 Eoss (µJ) 9.0 Ciss 8.0 1000 AM08536v1 7.0 6.0 100 5.0 Coss 4.0 3.0 10 2.0 Crss 1 0.1 1 100 10 1.0 0 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature AM08537v1 VGS(th) (norm) 0 300 200 100 400 500 VDS(V) 600 Figure 11. Normalized on-resistance vs temperature AM08538v1 RDS(on) (norm) ID= 8 A 1.10 2.0 ID = 250 µA 1.00 1.5 0.90 1.0 0.80 0.70 -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Normalized V(BR)DSS vs temperature AM09028v1 V(BR)DSS (norm) ID=1mA 1.10 0.5 -50 -25 0 25 50 TJ(°C) Figure 13. Source-drain diode forward characteristics AM10328v1 VSD (V) 1.4 1.08 75 100 TJ=-50°C 1.2 1.06 TJ=25°C 1.0 1.04 TJ=150°C 0.8 1.02 1.00 0.6 0.98 0.4 0.96 0.94 0.92 -50 -25 0.2 0 0 25 50 75 100 TJ(°C) DocID022440 Rev 3 0 2 4 6 8 10 12 14 16 ISD(A) 7/12 12 Test circuits 3 STFI24NM60N Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/12 0 DocID022440 Rev 3 10% AM01473v1 STFI24NM60N 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID022440 Rev 3 9/12 12 Package mechanical data STFI24NM60N Figure 20. I2PAKFP (TO-281) drawing UHY$ Table 9. I2PAKFP (TO-281) mechanical data mm Dim. Min. Typ. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 10/12 Max. 1.20 G 4.95 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 1.25 L6 7.30 7.50 - DocID022440 Rev 3 5.20 STFI24NM60N 5 Revision history Revision history Table 10. Document revision history Date Revision Changes 07-Nov-2011 1 First release. 20-Mar-2012 2 – Document status promoted from preliminary data to production data. – Package name has been updated. – Minor text changes. 24-Jul-2014 3 – Modified: the entire typical values in Table 6 – Minor text changes DocID022440 Rev 3 11/12 12 STFI24NM60N IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 12/12 DocID022440 Rev 3