Datasheet

3.3V CMOS TCXO Stratum 3
HTFL & HTVL
Specifications
Product
Parameters
HTFL


±1.0ppm


Frequency stability:
±4.6ppm
(inclusive of calibration tolerance
temperature, voltage, load, 20years
ageing, shock & vibration)


Temperature range:
0 to +70°C
-40 to +85°C




Storage temperature range:
-55 to +125°C


±0.5ppm
±1.0ppm
other






+3.3V (±5%)


Supply current (6.4~52.0MHz):
10mA max


Driving ability:
15pF CMOS


Logic levels: ‘0’ level = 10%VDD max
‘1’ level = 90%VDD min




Output current:
‘0’ level = 4.0mA
‘1’ level = -4.0mA




Waveform symmetry:
45:55 max at 50%VDD


Rise / fall time:
8ns max


Frequency adjustment:
None
±10ppm min, +1.65V ±1.35V
>100kΩ input impedance
±5% linearity

Frequency range:
6.40 ~ 56.0MHz
Calibration tolerance:
Temperature stability:
Supply voltage (VDD):
Features





3.3V Stratum 3 compliant (VC)TCXO
CMOS output
Suitable as SONET/SDH timing source
Enable / disable function:
None
Tristate (control via pin 1)
(VIH=70%VDD min, VIL=30%VDD max)
Excellent frequency stability
Low jitter
3ps max


Phase jitter RMS:
1.0ps max, 12kHz~fo/2
3.0ps max, 10Hz~fo/2








Enable / Disable Function (HTFL)
Open
‘1’ level
‘0’ level
Enabled
Enabled
High Impedance








-50dBc/Hz typ @ 1Hz
-80dBc/Hz typ @ 10Hz
-110dBc/Hz typ @ 100Hz
-135dBc/Hz typ @ 1kHz
-150dBc/Hz typ @ 10kHz
-150dBc/Hz typ @ 100kHz
Output (pin 8)









Phase noise:
Input (pin 1)
HTVL
Period jitter RMS:
TDEV:
1.0ns max over 1 sec
2.0ns max over 4 sec
 Standard.  Optional - Please specify required code(s) when ordering
Ordering Information
Product name + option codes + frequency
eg: HTFL/5F 19.440MHz ±1.0ppm, 0+70°C, TCXO no VC
HTVL/6E 44.7360MHz ±0.5ppm, -40+85°C, TCXO with VC
Option code X (eg HTVL/X) denotes a custom spec.
Tel: +44 1460 256 100
18 Oct 2010
Fax: +44 1460 256 101
E-mail: sales@golledge.com
Web: www.golledge.com
Option
Codes
5
6
E
F
specify