AT91SAM9263-EK Evaluation Board Rev. B ................................................................................................................... User Guide 6341D–ATARM–30-Sep-09 Table of Contents Section 1 Overview .................................................................................................................... 1-1 1.1 Scope................................................................................................................................. 1-1 1.2 How to Identify the Kit BOM Revision ................................................................................ 1-1 1.3 How to Identify the PCB Revision ...................................................................................... 1-2 1.4 How to Identify the SAM9263 Silicon Revision .................................................................. 1-2 1.5 NAND Flash Access Issue................................................................................................. 1-3 1.6 Deliverables ....................................................................................................................... 1-3 1.7 AT91SAM9263-EK Evaluation Board Rev. B .................................................................... 1-4 Section 2 Setting Up the AT91SAM9263-EK Board Rev. B....................................................... 2-1 2.1 Electrostatic Warning ......................................................................................................... 2-1 2.2 Requirements..................................................................................................................... 2-1 2.3 Layout ................................................................................................................................ 2-1 2.4 Powering Up the Board...................................................................................................... 2-4 2.5 Backup Power Supply........................................................................................................ 2-4 2.6 Getting Started................................................................................................................... 2-4 2.7 AT91SAM9263-EK Block Diagram .................................................................................... 2-5 Section 3 Board Description....................................................................................................... 3-1 3.1 AT91SAM9263 Microcontroller .......................................................................................... 3-1 3.2 AT91SAM9263 Block Diagram .......................................................................................... 3-4 3.3 Memory .............................................................................................................................. 3-5 3.4 Clock Circuitry.................................................................................................................... 3-5 3.5 Reset Circuitry ................................................................................................................... 3-5 3.6 Shutdown Controller .......................................................................................................... 3-5 3.7 Power Supply Circuitry....................................................................................................... 3-5 3.8 Remote Communication .................................................................................................... 3-5 3.9 Audio Stereo Interface ....................................................................................................... 3-6 3.10 User Interface .................................................................................................................... 3-6 3.11 Debug Interface ................................................................................................................. 3-6 3.12 Expansion Slot ................................................................................................................... 3-6 3.13 PIO Usage ......................................................................................................................... 3-7 Section 4 AT91SAM9263-EK Evaluation Board Rev. B User Guide i 6341D–ATARM–30-Sep-09 Table of Contents (Continued) Configuration .............................................................................................................. 4-1 4.1 Configuration Jumpers and Straps .................................................................................... 4-1 Section 5 Schematics................................................................................................................. 5-1 5.1 Schematics ........................................................................................................................ 5-1 Section 6 Warning ...................................................................................................................... 6-1 6.1 BMS Signal Sampling ........................................................................................................ 6-1 Section 7 Revision History ......................................................................................................... 7-1 7.1 ii 6341D–ATARM–30-Sep-09 Revision History ................................................................................................................. 7-1 AT91SAM9263-EK Evaluation Board Rev. B User Guide Section 1 Overview 1.1 Scope The AT91SAM9263-EK evaluation kit enables the evaluation of and code development for applications running on an AT91SAM9263. This guide focuses on the AT91SAM9263-EK board Rev. B as an evaluation platform. 1.2 How to Identify the Kit BOM Revision Table 1-1. AT91SAM9263-EK History NAND Flash Device Mounted on Board AT91SAM9623 Silicon Revision Boot from DataFlash® Card Boot from on-board NAND Flash A MN21B = Samsung® K9F2G08U0M-PCB0 A yes no B B MN21B = Samsung K9F2G08U0M-PCB0 A yes no 007 B B MN21B = Micron® MT29F2G08AACWP B yes yes 008..on C B MN21B = Micron MT29F2G08AACWP B yes yes Kit BOM Revision Schematics Revision PCB Revision 001..003 A 004..006 The BOM (bill of material) revision level is tagged on the kit box as shown below in Figure 1-1. AT91SAM9263-EK Evaluation Board Rev. B User Guide 1-1 6341D–ATARM–30-Sep-09 Overview Figure 1-1. 1.3 AT91SAM9263-E Kit BOM How to Identify the PCB Revision The PCB revision can be clearly identified by looking at the board copper marking on the bottom side. The last character of the series indicates the revision. Thus, If the series of characters ends with the letter “B” (e.g. 63PC0608021B), your board is Rev. B. For technical information on Revision A boards, refer to the corresponding User Guide, Atmel literature number 6279, available on the Atmel web site. 1.4 How to Identify the SAM9263 Silicon Revision The AT91SAM9263 MRL B (Marketing Revision Level B) parts are identified with a letter “B” on top of the package as shown below: Figure 1-2. AT91SAM92639263 MRL B 1-2 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Overview 1.5 NAND Flash Access Issue On the AT91SAM9263-EK with Kit BOM revision 007, the user can experience access errors when reading or writing the NAND Flash device (MN21B). This problem is due to disturbances on the chip select line. It can be fixed by the following: replacing the resistor R139 (0 Ohms) by a 2.2 µH inductor replacing the resistor R33 (470 K Ohms) by a 100 pF capacitor This fix has been implemented on the AT91SAM9263-EK with Kit BOM revisions 008 and onward. Alternatively, tying the NAND Flash chip select line to the ground fixes the problem. This can be achieved simply by connecting pin 2 of J29 together with pin 30 of J23. However, this simpler solution prevents some Flash modes from being operational because the accesses are then controlled only through NANDOE and NANDWE. But, this does at least allow to boot WinCE and Linux on the board from the NAND Flash. 1.6 Deliverables The AT91SAM9263-EK package contains the following items: an AT91SAM9263-EK board Rev. B one A/B-type USB cable one serial RS232 cable one RJ45 crossed Ethernet cable one CD-ROM that allows the user to begin evaluating the AT91 ARM® Thumb® 32-bit microcontroller quickly. AT91SAM9263-EK Evaluation Board Rev. B User Guide 1-3 6341D–ATARM–30-Sep-09 Overview 1.7 AT91SAM9263-EK Evaluation Board Rev. B The board is equipped with an AT91SAM9263 (324-ball LFBGA package) together with the following: 64 Mbytes of SDRAM memory 4 Mbytes of PSRAM memory on EBI1 256 Mbytes of NAND Flash memory One NOR Flash memory (footprint only) One 1.8” Hard disk connectors One TWI serial memory One USB device port interface Two USB Host port interfaces One RS232 serial communication port One DBGU serial communication port One serial CAN 2.0B communication port One JTAG/ICE debug interface One Ethernet 100-base TX with three status LEDs One AC97 Audio DAC One 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight One ISI connector (camera interface) One Power LED and two general-purpose LEDs Two user input push buttons One Wakeup input push button One reset push button One DataFlash®/SD/SDIO/MMC card slot One SD/SDIO/MMC card slot One Lithium Coin Cell Battery Retainer for 12 mm cell size 1-4 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Section 2 Setting Up the AT91SAM9263-EK Board Rev. B 2.1 Electrostatic Warning The AT91SAM9263-EK evaluation board Rev. B is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 2.2 Requirements In order to set up the AT91SAM9263-EK evaluation board Rev. B, the following items are needed: 2.3 the AT91SAM9263-EK evaluation board Rev. B itself AC/DC power adapter (12V at 1A), 2.1 mm by 5.5 mm Layout See Figures 2-1 and 2-2. AT91SAM9263-EK Evaluation Board Rev. B User Guide 2-1 6341D–ATARM–30-Sep-09 Setting Up the AT91SAM9263-EK Board Rev. B Figure 2-1. AT91SAM9263-EK Layout - Top View 2-2 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Setting Up the AT91SAM9263-EK Board Rev. B Figure 2-2. AT91SAM9263-EK Layout - Bottom View AT91SAM9263-EK Evaluation Board Rev. B User Guide 2-3 6341D–ATARM–30-Sep-09 Setting Up the AT91SAM9263-EK Board Rev. B 2.4 Powering Up the Board The AT91SAM9263-EK requires 12V DC. DC power is supplied to the board via the 2.1 mm by 5.5 mm socket J1. Coaxial plug center positive standard. 2.5 Backup Power Supply The user has the possibility to plug a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. 2.6 Getting Started The AT91SAM9263-EK evaluation board Rev. B is delivered with a CD-ROM that allows the user to begin evaluation of the AT91 ARM Thumb 32-bit microcontroller quickly. Please refer to the AT91 web site, http://www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the AT91SAM9263-EK. 2-4 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Setting Up the AT91SAM9263-EK Board Rev. B 2.7 AT91SAM9263-EK Block Diagram Figure 2-3. AT91SAM9263-EK Block Diagram AT91SAM9263-EK Evaluation Board Rev. B User Guide 2-5 6341D–ATARM–30-Sep-09 Section 3 Board Description 3.1 AT91SAM9263 Microcontroller Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 200 MIPS at 180 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support – Mid-level Implementation Embedded Trace Macrocell™ Bus Matrix – Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth – Boot Mode Select Option, Remap Command Embedded Memories – One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed – One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor Bus Matrix Speed – One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed Dual External Bus Interface (EBI0 and EBI1) – EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® – EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash DMA Controller (DMAC) – Acts as one Bus Matrix Master – Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control Twenty Peripheral DMA Controller Channels (PDC) LCD Controller – Supports Passive or Active Displays – Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers 2D Graphics Accelerator – Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-1 6341D–ATARM–30-Sep-09 Board Description USB 2.0 Full Speed (12 Mbits per second) Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM Ethernet MAC 10/100 Base-T – Media Independent Interface or Reduced Media Independent Interface – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Double Real-time Timer Reset Controller (RSTC) – Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Two Real-time Timers (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE) – 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output 3-2 6341D–ATARM–30-Sep-09 One Part 2.0A and Part 2.0B-compliant CAN Controller AT91SAM9263-EK Evaluation Board Rev. B User Guide Board Description – 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two Multimedia Card Interface (MCI) – SDCard/SDIO and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC – Two SDCard Slots Support on eAch Controller Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) – 6-channel Single AC97 Analog Front End Interface, Slot Assigner Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – Synchronous Communications at Up to 90Mbits/sec One Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) One Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel® EEPROMs Supported IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os) – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os) Available in a 324-ball BGA Green Package AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-3 6341D–ATARM–30-Sep-09 3-4 NRST VDDCORE SHDN WKUP XIN32 XOUT32 VDDBU TWI USART0 USART1 USART2 MCI0 MCI1 PIOE PIOD PIOC PIOB PIOA PDC RSTC SHDWC RTT1 RTT0 DTCM I D ETM PWMC TC0 TC1 TC2 FIFO AC97C PDC 20-channel Peripheral DMA FIFO PDC SSC0 SSC1 APB DMA Transc. MCI0_, MCI_1 SPI0_, SPI1_ DMA DMA USB OHCI Transc. Transc. H D HD PA M H A D HDPB M B Image Sensor Interface 2D Graphics Controller DMA FIFO USB Device Port DMA 10/100 Ethernet MAC 2-channel 9-layer Bus Matrix DMA LUT LCD Controller TC TS LK TPYN C TPS0 K -T P BM 0-T S2 S PK1 5 LC LCDD 0 L DV -LC C S LCDH YN DD S L DD YNC 23 C O LCDD TCC DCEN K ET C ETXCK ECXEN-ER R - X ER S- ETX CK E ERXE CO ER ERE R L FC ET X0- -ER K E X X EM 0-E RX DV 3 EMDC TX 3 EF DIO 10 0 Peripheral Bridge DCache 16K bytes PDC SPI0 SPI1 ROM 128 Kbytes SRAM 16 Kbytes CAN Fast SRAM 80 Kbytes ITCM MMU Bus Interface ICache 16K bytes ARM926EJ-S Processor TCM Interface In-Circuit Emulator JTAG Boundary Scan NT TDRS T TDI TMO TC S K PDC POR POR OSC PIT PMC 20GPREG OSC XIN XOUT VDDCORE PLLB PLLRCB WDT PLLA DBGU DRXD DTXD PCK0-PCK3 PLLRCA AIC FIQ IRQ0-IRQ1 PDC System Controller TST SLAVE L RT JT CK AG SE 6341D–ATARM–30-Sep-09 DB 0 -D DA C B3 0 D DAB CD 3 A CK TW CT TW D C RTS0- K C SC S0- TS R 2 RD K0- TS X S 2 TX 0- CK2 R D 0- DX TX 2 D2 C A CA NT NR X NP X NPCS 3 NPCS 2 N CS P C 1 SP S0 M CK O M SI PW IS O M 0PW TC M L 3 TI K0O T T A C I O 0- LK B0 TIO 2 -T A2 AC IOB AC97C 2 AC 97 K F AC97RS 9 X TK 7TX T 0-T F TD 0-TK1 RD 0-T F1 DM D R 0-R 1 AR Q R F0- D1 0_ K R 0 F D M -RK1 AR 1 Q 3 DD DD P M EBI0 ECC Controller Static Memory Controller SDRAM Controller NAND Flash EBI1 ECC Controller Static Memory Controller SDRAM Controller CompactFlash NAND Flash D0-D15 A0/NBS0 A1/NWR2 A2-A15/A18-A20 A16/BA0 A17/BA1 NCS0 NRD NWR0/NWE NWR1/NBS1 SDCK A21/NANDALE A22/NANDCLE NWAIT NWR3/NBS3 NCS1/SDCS NCS2/NANDCS D16-D31 SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE EBI1_ EBI0_ D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 NCS3/NANDCS A25/CFRNW CFCE1-CFCE2 D16-D31 NCS2 Figure 3-1. I 3.2 SI I _ D0 SI_ P IS -IS CK I_ I IS _HS D1 I_ Y 1 V N I S S Y NC I_ C M CK MASTER Board Description AT91SAM9263 Block Diagram AT91SAM9263 Block Diagram AT91SAM9263-EK Evaluation Board Rev. B User Guide Board Description 3.3 3.4 3.5 3.6 3.7 3.8 Memory 16 Kbytes of Internal data cache 16 Kbytes of Internal instruction cache 128 Kbytes of Internal ROM 80 Kbytes of Internal single-cycle access high-speed SRAM 16 Kbytes of Internal single-cycle access high-speed SRAM 8 Mbytes of Atmel NOR Flash (not populated) 64 Mbytes of SDRAM memory 4 Mbytes of PSRAM (EBI1) 256 Mbytes of NAND Flash memory Atmel TWI serial EEPROM Clock Circuitry 16.36766 MHz standard crystal for the embedded oscillator 32.768 kHz standard crystal for the slow clock oscillator Reset Circuitry Internal reset controller with bi-directional reset pin External reset pushbutton Shutdown Controller Programmable shutdown and Wake-Up Wake-up push button Power Supply Circuitry For dynamic power consumption, the AT91SAM9263 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm. On-board 1.2V high efficiency step-down Charge Pump regulator with shutdown control On-board 3.3V switching regulator with shutdown control On-board 5V switching regulator with shutdown control Remote Communication One RS232 serial communication port One serial CAN 2.0B communication port via 3-position printed circuit terminal block One USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP) Two USB Host ports V2.0 Full-speed Compliant, 12 Mbits per second (UHP) One RMII Ethernet 100-base TX with three status LEDs AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-5 6341D–ATARM–30-Sep-09 Board Description 3.9 3.10 3.11 3.12 Audio Stereo Interface One AC'97 2.3 compliant Codec (20-bit PCM DAC) One 32-ohm Stereo Headset line-out One stereo line input One stereo electret microphone input One mono 8-ohm amplified speaker User Interface Two user input push buttons Two user green LEDs One yellow power LED (can be also software controlled) One 3.5" ¼ VGA display LCD with Touch Panel and white LED backlight One ISI connector (camera interface) Debug Interface 20-pin JTAG/ICE interface connector One Serial interface (DBGU COM Port) via RS-232 DB9 male socket Expansion Slot One DataFlash/SD/SDIO/MMC card slot One SD/SDIO/MMC card slot All unused I/Os of the AT91SAM9263 are routed to peripheral extension connectors (J24 and J25). This allows the developer to add external hardware components or boards. 3-6 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Board Description 3.13 PIO Usage Table 3-1. PIO Controller A I/O Line Peripheral A Peripheral B Peripheral Usage PA0 MCI0_DA0 SPI0_MISO SD/MMC/DATAFLASH SOCKET (J9) & TOUCH SCEEN CONTROLLER MCI0_DA0 or SPI0_MISO VDDIOP0 PA1 MCI0_CDA SPI0_MOSI SD/MMC/DATAFLASH SOCKET (J9) & TOUCH SCEEN CONTROLLER MCI0_CDA or SPI0_MOSI VDDIOP0 SPI0_SPCK SD/MMC/DATAFLASH SOCKET (J9) & TOUCH SCEEN CONTROLLER SPI0_SPCK VDDIOP0 PA2 Powered by PA3 MCI0_DA1 SPI0_NPCS1 SD/MMC/DATAFLASH SOCKET (J9) VDDIOP0 PA4 MCI0_DA2 SPI0_NPCS2 SD/MMC/DATAFLASH SOCKET (J9) VDDIOP0 PA5 MCI0_DA3 SPI0_NPCS0 SD/MMC/DATAFLASH SOCKET (J9) VDDIOP0 PA6 MCI1_CK PCK2 SD/MMC SOCKET (J10) MCI1_CK VDDIOP0 PA7 MCI1_CDA SD/MMC SOCKET (J10) MCI1_CDA VDDIOP0 PA8 MCI1_DA0 SD/MMC SOCKET (J10) MCI1_DA0 VDDIOP0 PA9 MCI1_DA1 SD/MMC SOCKET (J10) MCI1_DA1 VDDIOP0 PA10 MCI1_DA2 SD/MMC SOCKET (J10) MCI1_DA2 VDDIOP0 PA11 MCI1_DA3 SD/MMC SOCKET (J10) MCI1_DA3 VDDIOP0 PA12 MCI0_CK SD/MMC/DATAFLASH SOCKET (J9) MCI0_CK VDDIOP0 PA13 CANTX PCK0 CAN BUS INTERFACE (J17) CANTX VDDIOP0 PA14 CANRX IRQ0 CAN BUS INTERFACE (J17) CANRX VDDIOP0 PA15 TCLK2 IRQ1 TOUCH SCREEN CONTROLLER (MN19) IRQ1 VDDIOP0 PA16 MCI0_CDB EBI1_D16 IMAGE SENSORS CONNECTORS (J23) PA16 as CTRL1 VDDIOM1 PA17 MCI0_DB0 EBI1_D17 IMAGE SENSORS CONNECTORS (J23) PA17 as CTRL2 VDDIOM1 PA18 MCI0_DB1 EBI1_D18 CAN INTERFACE (RXEN) PA18 as RXEN VDDIOM1 PA19 MCI0_DB2 EBI1_D19 CAN INTERFACE (RS) PA19 as RS VDDIOM1 PA20 MCI0_DB3 EBI1_D20 USB HOST B POWER MONITOR (MN17) PA20 as FLGB VDDIOM1 PA21 MCI1_CDB EBI1_D21 USB HOST B POWER CONTROL (MN17) PA21 as ENB VDDIOM1 PA22 MCI1_DB0 EBI1_D22 NAND FLASH (MN12B) PA22 as RDY/BSY VDDIOM1 PA23 MCI1_DB1 EBI1_D23 USB HOST B POWER MONITOR (MN17) PA23 as FLGA VDDIOM1 PA24 MCI1_DB2 EBI1_D24 USB HOST B POWER CONTROL (MN17) PA24 as ENA VDDIOM1 PA25 MCI1_DB3 EBI1_D25 USB DEVICE INTERFACE PA25 as USB_CNX VDDIOM1 PA26 TXD0 EBI1_D26 RS232 COM PORT (J15) TXD0 VDDIOM1 PA27 RXD0 EBI1_D27 RS232 COM PORT (J15) RXD0 VDDIOM1 PA28 RTS0 EBI1_D28 RS232 COM PORT (J15) RTS0 VDDIOM1 PA29 CTS0 EBI1_D29 RS232 COM PORT (J15) CTS0 VDDIOM1 PA30 SCK0 EBI1_D30 LCD PANEL (Power Control In) PA30 as PCI VDDIOM1 PA31 DMARQ0 EBI_D31 TOUCH SCREEN CONTROLLER (MN19) PA31 as BUSY VDDIOM1 AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-7 6341D–ATARM–30-Sep-09 Board Description Table 3-2. PIO Controller B I/O Line Peripheral A Peripheral B Peripheral Usage Powered by PB0 AC97FS TF0 AC97 CODEC (MN12) AC97FS VDDIOP0 PB1 AC97CK TK0 AC97 CODEC (MN12) AC97CK VDDIOP0 PB2 AC97TX TD0 AC97 CODEC (MN12) AC97TX VDDIOP0 PB3 AC97RX RD0 AC97 CODEC (MN12) AC97RX VDDIOP0 PB4 TWD RK0 TWI EEPROM (MN11) TWD / SDA VDDIOP0 PB5 TWCK RF0 TWI EEPROM (MN11) TWCK / SCL VDDIOP0 PB6 TF1 DMARQ1 PB7 TK1 PWM0 POWER LED CONTROL (DS3) PB7 or PWM0 VDDIOP0 PB8 TD1 PWM1 USER'S LED1 CONTROL (DS1) PB8 or PWM1 VDDIOP0 PB9 RD1 LCDCC LCD PANEL (backlight control) LCDCC VDDIOP0 PB10 RK1 PCK1 AC97 CODEC (MN12) Optional clock source PCK1 VDDIOP0 PB11 RF1 SPI0_NPCS3 TOUCH SCREEN CONTROLLER (MN19) SPI0_NPCS3 VDDIOP0 PB12 SPI1_MISO VDDIOP0 PB13 SPI1_MOSI VDDIOP0 PB14 SPI1_SPCK VDDIOP0 PB15 SPI1_NPCS0 VDDIOP0 PB16 SPI1_NPCS1 PCK1 VDDIOP0 PB17 SPI1_NPCS2 TIOA2 VDDIOP0 PB18 SPI1_NPCS3 TIOB2 VDDIOP0 VDDIOP0 PB19 VDDIOP0 PB20 VDDIOP0 PB21 VDDIOP0 PB22 VDDIOP0 PB23 VDDIOP0 PB24 DMARQ3 VDDIOP0 PB25 VDDIOP0 PB26 VDDIOP0 PB27 PWM2 VDDIOP0 PB28 TCLK0 VDDIOP0 PB29 PWM3 VDDIOP0 PB30 VDDIOP0 PB31 VDDIOP0 3-8 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Board Description Table 3-3. PIO Controller C I/O Line Peripheral A Peripheral B Peripheral Usage Powered by PC0 LCDVSYNC PC1 LCDHSYNC LCD PANEL LCDHSYNC VDDIOP0 PC2 LCDDOTCK LCD PANEL LCDDOTCK VDDIOP0 PC3 LCDDEN PWM1 LCD PANEL LCDDEN VDDIOP0 PC4 LCDD0 LCDD3 USER'S PUSH BUTTON (BP2) PC4 as RIGHT CLICK VDDIOP0 PC5 LCDD1 LCDD4 USER'S PUSH BUTTON (BP1) PC5 as LEFT CLICK VDDIOP0 PC6 LCDD2 LCDD5 LCD PANEL LCDD2 RED VDDIOP0 PC7 LCDD3 LCDD6 LCD PANEL LCDD3 RED VDDIOP0 PC8 LCDD4 LCDD7 LCD PANEL LCDD4 RED VDDIOP0 PC9 LCDD5 LCDD10 LCD PANEL LCDD5 RED VDDIOP0 PC10 LCDD6 LCDD11 LCD PANEL LCDD6 RED VDDIOP0 PC11 LCDD7 LCDD12 LCD PANEL LCDD7 RED VDDIOP0 PC12 LCDD8 LCDD13 LCD PANEL LCDD13 GREEN VDDIOP0 PC13 LCDD9 LCDD14 PC14 LCDD10 LCDD15 LCD PANEL LCDD10 GREEN VDDIOP0 PC15 LCDD11 LCDD19 LCD PANEL LCDD11 GREEN VDDIOP0 PC16 LCDD12 LCDD20 LCD PANEL LCDD12 GREEN VDDIOP0 PC17 LCDD13 LCDD21 LCD PANEL LCDD21 BLUE VDDIOP0 PC18 LCDD14 LCDD22 LCD PANEL LCDD14 GREEN VDDIOP0 PC19 LCDD15 LCDD23 LCD PANEL LCDD15 GREEN VDDIOP0 PC20 LCDD16 ETX2 VDDIOP0 PC21 LCDD17 ETX3 VDDIOP0 PC22 LCDD18 ERX2 LCD PANEL LCDD18 BLUE VDDIOP0 PC23 LCDD19 ERX3 LCD PANEL LCDD19 BLUE VDDIOP0 PC24 LCDD20 ETXER LCD PANEL LCDD20 BLUE VDDIOP0 PC25 LCDD21 ERXDV ETHERNET RMII (MN18) ERXDV PC26 LCDD22 ECOL LCD PANEL LCDD22 BLUE VDDIOP0 PC27 LCDD23 ERXCK LCD PANEL LCDD23 BLUE VDDIOP0 PC28 PWM0 TCLK1 PC29 PCK0 PWM2 PC30 PC31 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 USER'S LED2 CONTROL (DS2) PC29 or PWM2 VDDIOP0 DRXD SERIAL DEBUG PORT (J14) DRXD VDDIOP0 DTXD SERIAL DEBUG PORT (J14) DTXD VDDIOP0 AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-9 6341D–ATARM–30-Sep-09 Board Description Table 3-4. PIO Controller D I/O Line Peripheral A Peripheral B PD0 TXD1 SPI0_NPCS2 VDDIOP0 PD1 RXD1 SPI0_NPCS3 VDDIOP0 PD2 TXD2 SPI1_NPCS2 HDD CONNECTORS (J8) PD2 as IRQ VDDIOP0 PD3 RXD2 SPI1_NPCS3 HDD CONNECTORS (J8) PD3 as IOREADY VDDIOP0 PD4 FIQ DMARQ2 VDDIOP0 PD5 EBI0_NWAIT RTS2 VDDIOM0 PD6 EBI0_NCS4/CFCS0 CTS2 VDDIOM0 PD7 EBI0_NCS5/CFCS1 RTS1 VDDIOM0 PD8 EBI0_CFCE1 CTS1 HDD CONNECTORS (J8) EBI0_CFCE1 VDDIOM0 PD9 EBI0_CFCE2 SCK2 HDD CONNECTORS (J8) EBI0_CFCE2 VDDIOM0 PD10 Peripheral Usage Powered by SCK1 VDDIOM0 PD11 EBI0_NCS2 TSYNC VDDIOM0 PD12 EBI0_A23 TCLK VDDIOM0 PD13 EBI0_A24 TPS0 VDDIOM0 PD14 EBI0_A25_CFRNW TPS1 VDDIOM0 PD15 EBI0_NCS3/NANDCS TPS2 NAND FLASH (MN12B) EBI0_NCS3/NANDCS VDDIOM0 PD16 EBI0_D16 TPK0 EBI0 SDRAM DATA BUS D16 VDDIOM0 PD17 EBI0_D17 TPK1 EBI0 SDRAM DATA BUS D17 VDDIOM0 PD18 EBI0_D18 TPK2 EBI0 SDRAM DATA BUS D18 VDDIOM0 PD19 EBI0_D19 TPK3 EBI0 SDRAM DATA BUS D19 VDDIOM0 PD20 EBI0_D20 TPK4 EBI0 SDRAM DATA BUS D20 VDDIOM0 PD21 EBI0_D21 TPK5 EBI0 SDRAM DATA BUS D21 VDDIOM0 PD22 EBI0_D22 TPK6 EBI0 SDRAM DATA BUS D22 VDDIOM0 PD23 EBI0_D23 TPK7 EBI0 SDRAM DATA BUS D23 VDDIOM0 PD24 EBI0_D24 TPK8 EBI0 SDRAM DATA BUS D24 VDDIOM0 PD25 EBI0_D25 TPK9 EBI0 SDRAM DATA BUS D25 VDDIOM0 PD26 EBI0_D26 TPK10 EBI0 SDRAM DATA BUS D26 VDDIOM0 PD27 EBI0_D27 TPK11 EBI0 SDRAM DATA BUS D27 VDDIOM0 PD28 EBI0_D28 TPK12 EBI0 SDRAM DATA BUS D28 VDDIOM0 PD29 EBI0_D29 TPK13 EBI0 SDRAM DATA BUS D29 VDDIOM0 PD30 EBI0_D30 TPK14 EBI0 SDRAM DATA BUS D30 VDDIOM0 PD31 EBI0_D31 TPK15 EBI0 SDRAM DATA BUS D31 VDDIOM0 3-10 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Board Description Table 3-5. PIO Controller E I/O Line Peripheral A Peripheral B PE0 ISI_D0 IMAGE SENSORS CONNECTORS (J23) ISI_D0 VDDIOP1 PE1 ISI_D1 IMAGE SENSORS CONNECTORS (J23) ISI_D1 VDDIOP1 PE2 ISI_D2 IMAGE SENSORS CONNECTORS (J23) ISI_D2 VDDIOP1 PE3 ISI_D3 IMAGE SENSORS CONNECTORS (J23) ISI_D3 VDDIOP1 PE4 ISI_D4 IMAGE SENSORS CONNECTORS (J23) ISI_D4 VDDIOP1 PE5 ISI_D5 IMAGE SENSORS CONNECTORS (J23) ISI_D5 VDDIOP1 PE6 ISI_D6 IMAGE SENSORS CONNECTORS (J23) ISI_D6 VDDIOP1 PE7 ISI_D7 IMAGE SENSORS CONNECTORS (J23) ISI_D7 VDDIOP1 PE8 ISI_PCK TIOA1 IMAGE SENSORS CONNECTORS (J23) ISI_PCK VDDIOP1 PE9 ISI_HSYNC TIOB1 IMAGE SENSORS CONNECTORS (J23) ISI_HSYNC VDDIOP1 PE10 ISI_VSYNC PWM3 IMAGE SENSORS CONNECTORS (J23) ISI_VSYNC VDDIOP1 PE11 ISI_MCK PCK3 IMAGE SENSORS CONNECTORS (J23) ISI_MCK VDDIOP1 PE12 ISI_D8 IMAGE SENSORS CONNECTORS (J23) ISI_D8 VDDIOP1 PE13 ISI_D9 IMAGE SENSORS CONNECTORS (J23) ISI_D9 VDDIOP1 PE14 ISI_D10 IMAGE SENSORS CONNECTORS (J23) ISI_D10 VDDIOP1 PE15 ISI_D11 IMAGE SENSORS CONNECTORS (J23) ISI_D11 VDDIOP1 SD/MMC/DATAFLASH SOCKET (J9) PE16 as CD (Card Detect) VDDIOP1 PE16 Peripheral Usage Powered by PE17 VDDIOP1 PE18 TIOA0 SD/MMC SOCKET (J10) PE18 as CD (Card Detect) VDDIOP1 PE19 TIOB0 PE20 EBI1_NWAIT SD/MMC/DATAFLASH SOCKET (J9) PE20 as CKSEL (Clock Select) VDDIOM1 ETHERNET RMII (MN18) ETXCK VDDIOM1 VDDIOP1 PE21 ETXCK EBI1_NANDWE PE22 ECRS EBI1_NCS2/NANDCS PE23 ETX0 EB1_NANDOE ETHERNET RMII (MN18) ETX0 VDDIOM1 PE24 ETX1 EBI1_NWR3/NBS3 ETHERNET RMII (MN18) ETX1 VDDIOM1 PE25 ERX0 EBI1_NCS1/SDCS ETHERNET RMII (MN18) ERX0 VDDIOM1 PE26 ERX1 ERX1 VDDIOM1 PE27 ERXER EBI1_SDCKE ETHERNET RMII (MN18) ERXER VDDIOM1 PE28 ETXEN EBI1_RAS ETHERNET RMII (MN18) ETXEN VDDIOM1 PE29 EMDC EBI1_CAS ETHERNET RMII (MN18) EMDC VDDIOM1 PE30 EMDIO EBI1_SDWE ETHERNET RMII (MN18) EMDIO VDDIOM1 PE31 EF100 EBI1_SDA10 ETHERNET RMII (MN18) PE31 as IRQ VDDIOM1 AT91SAM9263-EK Evaluation Board Rev. B User Guide VDDIOM1 3-11 6341D–ATARM–30-Sep-09 Section 4 Configuration 4.1 Configuration Jumpers and Straps Table 4-1. Configuration Jumpers and Straps Designation Default Setting Feature J2 Closed Forces power on. To use the software shutdown control, J2 must be opened and the battery backup inserted in its socket. J4-1 Closed VDDBU jumper (1) J4-2 Closed VDDCORE jumper (1) J5-1 Closed VDDOSC jumper (1) J5-2 Closed VDDIOP0 jumper(1) J5-3 Closed VDDIOP1 jumper(1) J5-4 Closed VDDIOM0 jumper (1) J5.5 Closed VDDIOM1 jumper (1) Opened Enables Boot on the internal ROM. Close to boot from NCS0. Closed Enables Boot on the NCS0 J5-7 Opened NTRST Ground J16 Closed Enables 120 ohms CAN bus resistance termination J21 Closed Enables Ethernet Auto MDIX control J29 Closed NAND FLash chip select S1 Opened Selects ICE or JTAG mode. (closed) S2 Opened Disables NAND FLASH write protect S3 Opened Disables 5V power supply on J24, J25 expansion connectors R17 IN Enables the ICE NTRST input R18 IN Enables the ICE NRST input R13 IN R15 IN Enables the use of the Y1 crystal. If an external clock has to be used, R13 and R15 must be unsoldered and R16/J16 fitted. R30 IN Enables the use of the MN7 SDRAM device. Needs to be removed when ETM is used.(2) R45 IN Enables the use of the SERIAL EEPROM SCL (PB5) R46 IN Enables the use of the SERIAL EEPROM SDA (PB4) R75 IN Enables the use of the DBGU TXD signal (PC31) J5-6 AT91SAM9263-EK Evaluation Board Rev. B User Guide 4-1 6341D–ATARM–30-Sep-09 Configuration Table 4-1. Configuration Jumpers and Straps (Continued) Designation Default Setting R79 IN Enables the use of the DBGU RXD signal (PC30) R84 IN Enables the use of the USB CNX detection (PA25) R76 IN Enables the use of the RS232 COM PORT TXD signal (PA26) R78 IN Enables the use of the RS232 COM PORT RTS signal (PA28) R80 IN Enables the use of the RS232 COM PORT RXD signal (PA27) R82 IN Enables the use of the RS232 COM PORT CTS signal (PA29) R87 IN Enables the use of the CAN BUS driver RS control signal (PA26) R89 IN Enables the use of the CAN BUS driver CANTXRT RTS signal (PA28) R91 IN Enables the use of the RS232 COM PORT RXD signal (PA27) R93 IN Enables the use of the RS232 COM PORT CTS signal (PA29) R112 IN Enables the use of interrupt ETHERNET PHY (PE31) R126 IN Enables the use of TOUCH SCEEN CONTROLLER (PB11_SPI0_NPCS3) R127 IN Enables the use of TOUCH SCEEN CONTROLLER BUSY signal (PA31) R128 IN Enables the use of TOUCH SCEEN CONTROLLER PENIRQ (PA15_IRQ1) TP67 N.A GND Test point TP68 N.A GND Test point TP69 N.A GND Test point TP70 N.A GND Test point TP71 N.A 0 to 3.3V analog user's input TP72 N.A 0 to 3.3V analog user's input TP73 N.A AGND of TP71 TP74 N.A AGND of TP72 Note: Feature 1. These jumpers are provided for power consumption measurement use. By default, they are closed. To use this feature, the user has to open the strap and insert an ammeter. 2. AT91SAM9263 ETM signals [TPK0 - TPK15] are multiplexed with EBI0 signals [EBI0_D16 - EBI0_D31]. AT91SAM9263-EK EBI0 signals [EBI0_D16 - EBI0_D31] are connected to an SDRAM device (part MN7). Having this SDRAM device enabled adds capacitance to the data line [EBI0_D16 - EBI0_D31], which leads to ETM data corruption. You need to remove the resistor R30 to release the EBI0_NCS1_SDCS signal and put the SDRAM IOs [EBI0_D16 - EBI0_D31] in High-Z. Having these signals in High-Z removes the added capacitance; the ETM signals are no longer corrupted. 4-2 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Section 5 Schematics 5.1 Schematics This section contains the following schematics: AT91SAM9263-EK Diagram Power Supply AT91SAM9263 EBI0 Memory EBI1 Memory Serial Memory Audio AC97 Serial Interfaces Ethernet LCD and ISI Expansion AT91SAM9263-EK Evaluation Board Rev. B User Guide 5-1 6341D–ATARM–30-Sep-09 RS232 COM0 TXD RXD RTS CTS DEVICE USBCNX DDM DDP HOST A HDMA HDPA ENA FLGA HOST B HDMB HDPB ENB FLGB CANRS CANRXEN CAN USB DBGU DTXD DRXD CANRX CANTX RMII ETHERNET - SHEET 9 10/100 FAST ETHERNET TX_CLK TXD1 TXD0 TX_EN RXD1 RXD0 RX_DV RX_ER MDC MDIO MDINTR NRST LCD INTERFACE R[0..5] G[0..5] B[0..5] 3.5" QVGA HSYNC DCLK DTMG VCTRL PCI MOSI MISO TOUCH SCREEN SPCK CONTROLLER NPCS CAMERA INTERFACE IRQ BUSY ISI_D[0..11] ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK ISI PC4 PC5 VDDISI VDDISI RAS CAS SDA10 SDWE SDCS EBI0_SDCK EBI0_SDCKE SDCK SDCKE EBI0_A0 EBI0_NBS1 EBI0_A1 EBI0_NBS3 DTXD DRXD TXD0 RXD0 RTS0 CTS0 EBI0_NANDOE EBI0_NANDWE PD15 PA22 EBI0_NCS0 EBI0_NWE/NWR0/CFWE EBI0_NRD/CFOE HDMB HDPB PA21 PA20 NCS NWE NRD NRSTFLASH PA19 PA18 NRST CANRX CANTX EBI0_NBS1/NW1/CFIOR EBI0_NBS3/NW3/CFIOW RESETEBI0_CFCE1 EBI0_CFCE2 EBI0_NBS1 EBI0_NBS3 EBI1_D[0..15] EBI1_A[0..21] EXPANSION CONNECTORS - SHEET 10 PA[0..31] PA[0..31] PB[0..31] PB[0..31] EMDC EMDIO PE31 PC[0..31] PC[0..31] PD[0..31] PD[0..31] NRST PE[0..31] PE[0..31] PA[0..31] INTRQ IORDY D[0..15] EBI1_A[1..21] VDDISI SDA SCL CTRL2 CTRL1 A[1..21] EBI1_NCS0 EBI1_NWE/NWR0/CFWE EBI1_NRD/CFOE PB[0..31] PC[0..31] NCS NWR NOE EBI1_A0 PD[0..31] EBI1_NBS1/NW1/CFIOR PE[0..31] EBI1_SDCK LB UB MCI & TWI - SHEET 6 MCI0_CD MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_CDA LCDHSYNC LCDDOTCK LCDDEN MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_CDA MCI0_CK SPI0_SPCK PE20 PIO USAGE SPI0_MISO PA0 SPI0_MOSI PA1 ISI_D[0..11] ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK VDDISI TWD TWCK PA17 PA16 A PB[0..31] PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 MCI0_DA0 MCI0_CDA SPI0_SPCK MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI1_CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI0_CK CANTX CANRX IRQ1 (CTRL1) (CTRL2) (CANRXEN) (CANRS) (FLGB) (ENB) (RDYBSY) (FLGA) (ENA) (USBCNX) TXD0 RXD0 RTS0 CTS0 (PCI) (BUSY) PC[0..31] PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 AC97FS AC97CK AC97TX AC97RX TWD TWCK PWM0 PWM1 LCDCC PCK1 SPI0_NPCS3 PD[0..31] PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PE[0..31] PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 LCDHSYNC LCDDOTCK LCDDEN (RIGHTCLIC) (LEFTCLIC) LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD13 LCDD10 LCDD11 LCDD12 LCDD21 LCDD14 LCDD15 LCDD18 LCDD19 LCDD20 ERXDV LCDD22 LCDD23 PWM2 DRXD DTXD (INTRQ) (IORDY) EBI0_CFCE1 EBI0_CFCE2 (NANDCS) PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC ISI_MCK ISI_D8 ISI_D9 ISI_D10 ISI_D11 (MCI0_CD) (MCI1_CD) CARD READER MCI0_CK SPI0_SPCK CKSEL PE18 PA[0..31] C EBI1 MEMORY - SHEET 5 EBI1_D[0..15] EBI1_A[0..21] LCDD[2..7] LCDD[10..15] LCDD[18..23] IRQ1 PA31 CS0CS1DIORDIOW- PD2 PD3 ETX1 ETX0 ETXEN SPI0_MOSI SPI0_MISO SPI0_SPCK SPI0_NPCS3 NRSTFLASH NRST ETXCK LCDCC PA30 CLE ALE NANDOE NANDWE NANDCS RDYBSY HDMA HDPA PA24 PA23 D BA0 BA1 EBI0_A22 EBI0_A21 DDM DDP ERX1 ERX0 ERXDV ERXER NBS0 NBS1 NBS2 NBS3 EBI0_A16 EBI0_A17 PA25 SDRAM PWM2 EBI0 A[0..22] PE16 LCD & ISI - SHEET 10 B D[0..31] EBI0_A[0..22] EBI0_RAS EBI0_CAS EBI0_SDA10 EBI0_SDWE EBI0_NCS1/SDCS PWM1 D SERIAL INTERFACES - SHEET 8 EBI0_D[0..31] NORFLASH NANFLASH EBI0_A[0..22] 1.8" HDD USERLED2 RIGHTCLIC LEFTCLIC EBI0_D[0..31] 1 EBI0 MEMORY - SHEET 4 EBI1 USERLED1 SHDN PWM0 NRSTFLASH 2 PSRAM SHDN POWERLED NRSTFLASH C 3 MCI1_CD MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CDA MCI1_CK CARD READER MCI1_CK TWCK TWD SCL SDA AC97FS AC97CK AC97TX AC97RX MMC SD/SDIO DATAFLASH USER'S 12VDC INTERFACE 4 B MMC SD/SDIO 5 AT91SAM9263 - SHEET 3 SERIAL EEPROM 6 AUDIO AC97 - SHEET 7 PCK1 OUT 7 POWER SUPPLY - PAGE 2 SYNC BITCLK SDATA_OUT SDATA_IN AUDIO EXT_CLK NRST RST# MIC IN 8 (CKSEL) ETXCK A ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO (MDINTR) C B A INIT EDIT REV MODIF. AT91SAM9263-EK SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET C DIAGRAM This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 1 11 8 7 6 5 4 3 2 1 D D C1 180NF 1 Q1 BSH103 NC NC NC 2 LT1765-5 14 2.1 MM SOCKET 7 3 10 15 SHDN SW SW 6 5 FB 12 L1 2.2µH C3 10µF CR3 STPS2L30A VC R141 200K 5V 13 11 SYNC 3 C2 2.2µF VIN VIN 1 8 17 9 16 3 4 BOOST MN1 1 2 GND GND GND GND GND CR2 STPS2L30A J1 CR1 BAT20J C4 2.2NF 2 R3 100K C7 180NF C5 1µF CR4 BAT20J 8 C Q3 BSH103 R4 3 10K 2 C1M 5 C9 10µF CR5 STPS2L30A VC GND GND GND GND GND L2 2.2µH 12 FB 13 1 Q2 BSH103 NC NC NC 6 5 SW SW LT1765-3.3 14 7 3 10 15 SHDN SYNC 11 VIN VIN 1 8 17 9 16 3 4 BOOST MN3 C8 2.2µF 3V3 C6 1µF 6 3 4 C1P C2M VIN C2P VOUT 7 C 1V2 C10 R1 22µF 100K C11 10PF TPS60500 C12 2.2µF 1 C13 2.2NF EN GND MN2 FB 10 PG 2 R2 200K 9 2 J2 1 SHDN FORCE POWER ON 2 C14 15PF R140 0R NRSTFLASH B B USER INTERFACE 3V3 3V3 R5 120R DS2 POWER LED 220R R7 220R ADHESIVE FEET USERLED2 USERLED1 RIGHT CLICK 3 1 0R POWERLED Z1 Z2 11.1 11.1 Z3 Z4 Z5 11.1 11.1 11.1 GND TEST POINT TP67 TP68 TP69 LEFT CLICK BP1 A LEFTCLIC 2 C B A INIT EDIT REV MODIF. AT91SAM9263-EK POWER SUPPLY SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 7 6 5 4 3 2 VER. DATE REV. SHEET C This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 TP70 RIGHTCLIC BP2 R9 Q4 IRLML2402 GREEN R6 R8 470K DS3 YELLOW A DS1 GREEN 1 2 11 PE[0..31] EBI0_NBS0/A0 EBI0_NBS2/NWR2/A1 EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 EBI0_A9 EBI0_A10 EBI0_A11 EBI0_A12 EBI0_A13 EBI0_A14 EBI0_A15 EBI0_BA0/A16 EBI0_BA1/A17 EBI0_A18 EBI0_A19 EBI0_A20 EBI0_A21 EBI0_A22 EBI0_RAS EBI0_CAS EBI0_SDWE EBI0_SDA10 EBI0_SDCKE EBI0_SDCK B4 B3 C4 E8 A2 C5 EBI0_RAS EBI0_CAS EBI0_SDWE EBI0_SDA10 EBI0_SDCKE EBI0_SDCK EBI0_NCS0 EBI0_NCS1/SDCS F6 A4 EBI0_NCS0 EBI0_NCS1/SDCS EBI0_NRD/CFOE EBI0_NWE/NWR0/CFWE EBI0_NBS1/NW1/CFIOR EBI0_NBS3/NW3/CFIOW E6 A3 E5 B5 EBI0_NRD/CFOE EBI0_NWE/NWR0/CFWE EBI0_NBS1/NWR1/CFIOR EBI0_NBS3/NWR3/CFIOW EBI0_NANDOE EBI0_NANDWE B2 C3 EBI0_NANDOE EBI0_NANDWE This Inductor is intentionally mounted in place of R139 1 2 3 4 8 7 6 5 1 2.2µH 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 RR3 0R R139 RR4 0R RR5 0R R21 RR6 0R RR7 0R PE0/ISI_D0 PE1/ISI_D1 PE2/ISI_D2 PE3/ISI_D3 PE4/ISI_D4 PE5/ISI_D5 PE6/ISI_D6 PE7/ISI_D7 PE8/ISI_PCK/TIOA1 PE9/ISI_HSYNC/TIOB1 PE10/ISI_VSYNC/PWM3 PE11/ISI_MCK/PCK3 PE12/ISI_D8 PE13/ISI_D9 PE14/ISI_D10 PE15/ISI_D11 PE16 PE17 PE18/TIOA0 PE19/TIOB0 PE20/EBI1_NWAIT PE21/E_TXCK/EBI1_NANDWE PE22/E_CRS/EBI1_NCS2/NANDCS PE23/E_TX0/EBI1_NANDOE PE24/E_TX1/EBI1_NWR3/NBS3/CFIOW PE25/E_RX0/EBI1_NCS1/SDCS PE26/E_RX1 PE27/E_RXER/EBI1_SDCKE PE28/E_TXEN/EBI1_RAS PE29/E_MDC/EBI1_CAS PE30/E_MDIO/EBI1_SDWE PE31/EF100/EBI1_SDA10 3V3 C22 4.7NF HDPA HDMA E18 F18 HDPA HDMA DDP DDM A18 B18 DDP DDM R11 1,96K 1% P18 PLLRCB R12 1.5K U18 PLLRCA C26 1NF ICE INTERFACE 3V3 2 4 6 8 10 12 14 16 18 20 J7 RR1 100K 3V3 SMB MALE 3V3 1 3 5 7 9 11 13 15 17 19 R17 R18 0R C36 15PF 0R VDDBU J5-7 BP3 13 BP4 R20 100K EBI1_SDCK P10 EBI1_NCS0 EBI1_NRD/CFOE EBI1_NWE/NWR0/CFWE EBI1_NBS1/NWR1/CFIOR U10 P11 V10 EBI1_NRD/CFOE EBI1_NWE/NWR0/CFWE EBI1_NBS1/NW1/CFIOR R18 XOUT T18 XIN M8 L12 C15 100NF J4-2 V1 H10 A16 C17 C18 C19 100NF 100NF 100NF VDDPLLB VDDPLLA VDDOSC GNDPLLB GNDPLLA V18 U17 T1 T17 N14 C20 C21 C23 L11 C17 A17 L8 L10 K12 K10 H8 C27 C29 C30 100NF 100NF 100NF C32 100NF C34 C35 C37 C38 100NF 100NF 100NF 100NF 9 JTAGSEL NTRST TDI TMS TCK RTCK TDO NRST VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 T2 M13 M10 L9 4 1V2 2 3V3 C39 C40 C41 C42 4 3V3 6 3V3 7 5 3V 1K R10 B 8 3V3 10 3V3 VDDISI J5-5 100NF 100NF 100NF 100NF A C B A INIT EDIT REV MODIF. SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 4 3 2 VER. DATE REV. SHEET C AT91SAM9263 WAKE UP 6 Z7 + J5-4 AT91SAM9263-EK 8 CR1225 3 J5-3 SHDN NRST NRST C16 100NF J5-2 7 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 CR6 MMBD1704A J3 100NF 100NF 100NF 3 VDDIOP1 XIN32 J28 J5-1 5 P1 P5 U16 P17 N17 R17 U15 N18 V15 2 MN5 R1100D121C VDDIOP0 VDDIOP0 VDDIOP0 XOUT32 VDDBU J4-1 1 1 R1 R138 10K 3V3 VDDCORE VDDCORE VDDCORE Y2 32.768 kHz VDDBU S1 NTRST TDI TMS TCK RTCK TDO NRST 14 R19 1K Y1 16.36766MHz R15 0R J6 NOT POPULATED C31 22PF 1 2 3 C33 4 5 R16 15PF NOT POPULATED R15 EBI1_NCS0 3 HDPB HDMB R13 0R C160 100NF EBI1_SDCK VDDBU GNDBU C18 D18 C28 22PF R137 0R D C TST HDPB HDMB C24 470 pF C25 10NF TCLK MN4H R2 MN4E K3 K4 L6 L7 L2 L5 K1 L4 M7 L3 L1 M4 M6 M5 M2 M3 N6 N5 M1 N3 P6 V13 U13 T13 V14 T14 R14 U14 P16 T15 R16 T16 10K 3V3 R136 10K TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 NTRST TDI TMS TCK RTCK TDO NRST 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 2 PD[0..31] 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 1 BOOT MODE SELECT Opened = Internal ROM BOOT Closed = NCS0 EBI1_A0 EBI1_A1 EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A9 EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15 EBI1_A16 EBI1_A17 EBI1_A18 EBI1_A19 EBI1_A20 EBI1_A21 NOT USED TPS0 TPS1 TPS2 TSYNC TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 2 4.7K U6 V5 R6 V6 P8 U7 N7 T7 P7 V7 U8 N8 T8 R8 R7 V8 U9 R9 T9 P9 V9 M9 N9 ETM TRACE PORT VDD R135 12 EBI1_NBS0/A0 EBI1_NWR2/A1 EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A9 EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15 EBI1_BA0/A16 EBI1_BA1/A17 EBI1_A18 EBI1_A19 EBI1_A20 EBI1_A21 EBI1_A22 EBI1_A[0..21] 1 J5-6 11 EBI0_A0 EBI0_A1 EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 EBI0_A9 EBI0_A10 EBI0_A11 EBI0_A12 EBI0_A13 EBI0_A14 EBI0_A15 EBI0_A16 EBI0_A17 EBI0_A18 EBI0_A19 EBI0_A20 EBI0_A21 EBI0_A22 EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8 EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15 OUT EBI0_A[0..22] R134 4.7K T10 R10 N10 U11 P12 V11 N11 T11 R11 N12 P13 V12 R12 U12 T12 R13 G1 G2 G3 G4 G5 E9 A9 D9 C9 B9 A8 F9 B8 C8 D8 A7 A6 F8 C7 E7 B7 F7 D6 D7 A5 D5 C6 B6 PB3 EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8 EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15 GND PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 EBI0_D0 EBI0_D1 EBI0_D2 EBI0_D3 EBI0_D4 EBI0_D5 EBI0_D6 EBI0_D7 EBI0_D8 EBI0_D9 EBI0_D10 EBI0_D11 EBI0_D12 EBI0_D13 EBI0_D14 EBI0_D15 1 3 B10 D10 C10 F10 A10 G5 G3 F1 G6 H4 G7 H5 G2 H2 H6 H3 H7 G1 J5 J4 J8 J7 J3 J6 H1 K8 J2 K5 K2 K7 J1 K6 C2 D4 A1 D2 B1 E3 C1 E2 E4 F3 D1 F4 F5 F2 G4 E1 P2 P4 A PD0/TXD1/SPI0_NPCS2 PD1/RXD1/SPI0_NPCS3 PD2/TXD2/SPI1_NPCS2 PD3/RXD2/SPI1_NPCS3 PD4/FIQ/DMARQ2 PD5/EBI0_NWAIT/RTS2 PD6/EBI0_NCS4/CFCS0/CTS2 PD7/EBI0_NCS5/CFCS1/RTS1 PD8/EBI0_CFCE1/CTS1 PD9/EBI0_CFCE2/SCK2 PD10/SCK1 PD11/EBI0_NCS2/TSYNC PD12/EBI0_A23/TCLK PD13/EBI0_A24/TPS0 PD14/EBI0_A25_CFRNW/TPS1 PD15/EBI0_NCS3/NANDCS/TPS2 PD16/EBI0_D16/TPK0 PD17/EBI0_D17/TPK1 PD18/EBI0_D18/TPK2 PD19/EBI0_D19/TPK3 PD20/EBI0_D20/TPK4 PD21/EBI0_D21/TPK5 PD22/EBI0_D22/TPK6 PD23/EBI0_D23/TPK7 PD24/EBI0_D24/TPK8 PD25/EBI0_D25/TPK9 PD26/EBI0_D26/TPK10 PD27/EBI0_D27/TPK11 PD28/EBI0_D28/TPK12 PD29/EBI0_D29/TPK13 PD30/EBI0_D30/TPK14 PD31/EBI0_D31/TPK15 MN4D EBI0_D0 EBI0_D1 EBI0_D2 EBI0_D3 EBI0_D4 EBI0_D5 EBI0_D6 EBI0_D7 EBI0_D8 EBI0_D9 EBI0_D10 EBI0_D11 EBI0_D12 EBI0_D13 EBI0_D14 EBI0_D15 4 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 PC0/LCDVSYNC PC1/LCDHSYNC PC2/LCDDOTCK PC3/LCDDEN/PWM1 PC4/LCDD0/LCDD3 PC5/LCDD1/LCDD4 PC6/LCDD2/LCDD5 PC7/LCDD3/LCDD6 PC8/LCDD4/LCDD7 PC9/LCDD5/LCDD10 PC10/LCDD6/LCDD11 PC11/LCDD7/LCDD12 PC12/LCDD8/LCDD13 PC13/LCDD9/LCDD14 PC14/LCDD10/LCDD15 PC15/LCDD11/LCDD19 PC16/LCDD12/LCDD20 PC17/LCDD13/LCDD21 PC18/LCDD14/LCDD22 PC19/LCDD15/LCDD23 PC20/LCDD16/E_TX2 PC21/LCDD17/E_TX3 PC22/LCDD18/E_RX2 PC23/LCDD19/E_RX3 PC24/LCDD20/E_TXER PC25/LCDD21/E_RXDV PC26/LCDD22/E_COL PC27/LCDD23/E_RXCK PC28/PWM0/TCLK1 PC29/PCK0/PWM2 PC30/DRXD PC31/DTXD EBI0_D16 EBI0_D17 EBI0_D18 EBI0_D19 EBI0_D20 EBI0_D21 EBI0_D22 EBI0_D23 EBI0_D24 EBI0_D25 EBI0_D26 EBI0_D27 EBI0_D28 EBI0_D29 EBI0_D30 EBI0_D31 1 B MN4C PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 5 6 7 8 C PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 2 EBI1_D[0..15] MN4G GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E16 D17 D16 C15 E14 B16 D13 B15 C14 B14 D15 E13 A15 F13 C13 E12 D14 B13 F12 A14 D12 B12 E11 C12 A13 D11 A12 F11 B11 C11 A11 E10 K17 K16 K18 K13 L14 J15 J16 J17 J18 J13 J14 J12 H18 H15 H17 H14 B17 H13 G18 H12 G14 G13 G17 G15 H16 F15 F14 F17 G16 F16 E15 E17 3 MN4F V16 V17 C16 G8 G10 G11 G12 H9 H11 J9 J10 J11 K9 K11 M11 M12 N13 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PC[0..31] PB0/AC97FS/TF0 PB1/AC97CK/TK0 PB2/AC97TX/TD0 BMS_PB3/AC97RX/RD0 PB4/TWD/RK0 PB5/TWCK/RF0 PB6/TF1/DMARQ1 PB7/TK1/PWM0 PB8/TD1/PWM1 PB9/RD1/LCDCC PB10/RK1/PCK1 PB11/RF1/SPI0_NPCS3 PB12/SPI1_MISO PB13/SPI1_MOSI PB14/SPI1_SPCK PB15/SPI1_NPCS0 PB16/SPI1_NPCS1/PCK1 PB17/SPI1_NPCS2/TIOA2 PB18/SPI1_NPCS3/TIOB2 PB19 PB20 PB21 PB22 PB23 PB24/DMARQ3 PB25 PB26 PB27/PWM2 PB28/TCLK0 PB29/PWM3 PB30 PB31 PA0/MCI0_DA0/SPI0_MISO PA1/MCI0_CDA/SPI0_MOSI PA2/SPI0_SPCK PA3/MCI0_DA1/SPI0_NPCS1 PA4/MCI0_DA2/SPI0_NPCS2 PA5/MCI0_DA3/SPI0_NPCS0 PA6/MCI1_CK/PCK2 PA7/MCI1_CDA PA8/MCI1_DA0 PA9/MCI1_DA1 PA10/MCI1_DA2 PA11/MCI1_DA3 PA12/MCI0_CK PA13/CANTX/PCK0 PA14/CANRX/IRQ0 PA15/TCLK2/IRQ1 PA16/MCI0_CDB/EBI1_D16 PA17/MCI0_DB0/EBI1_D17 PA18/MCI0_DB1/EBI1_D18 PA19/MCI0_DB2/EBI1_D19 PA20/MCI0_DB3/EBI1_D20 PA21/MCI1_CDB/EBI1_D21 PA22/MCI1_DB0/EBI1_D22 PA23/MCI1_DB1/EBI1_D23 PA24/MCI1_DB2/EBI1_D24 PA25/MCI1_DB3/EBI1_D25 PA26/TXD0/EBI1_D26 PA27/RXD0/EBI1_D27 PA28/RTS0/EBI1_D28 PA29/CTS0/EBI1_D29 PA30/SCK0/EBI1_D30 PA31/DMARQ0/EBI1_D31 4 EBI0_D[0..31] NC NC NC NC NC N16 N15 P15 P14 M15 M17 M14 M16 M18 L15 L17 L18 L16 L13 K14 K15 P3 U1 R3 T3 U2 T4 V2 U3 U4 R4 T5 V3 U5 V4 R5 T6 5 PB[0..31] 4 3 2 1 D PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 6 MN4B SHDN WKUP 7 MN4A D3 G9 N1 N2 N4 8 PA[0..31] 1 3 11 8 7 6 5 4 3 2 1 SDRAM A[0..22] NORFLASH D[0..31] MN6 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D A13 SDA10 SDA10 BA0 BA1 BA0 BA1 20 21 A14 36 40 SDCKE SDCK SDCKE 37 SDCK 38 15 39 NBS0 NBS1 C R26 SDCS CAS RAS CAS RAS 3V3 R25 470K 23 24 25 26 29 30 31 32 33 34 22 35 17 18 SDWE SDWE 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SDA10 A13 BA0 BA1 3V3 A14 C43 C45 C47 C49 C51 C53 C55 100NF 100NF 100NF 100NF 100NF 100NF 100NF 28 41 54 6 12 46 52 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE 37 SDCK 38 15 39 NBS2 NBS3 CAS RAS 3V3 256 Mbits 0R MN7 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDWE 17 18 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 1 14 27 3 9 43 49 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 3V3 P15 R22 0R A20 R23 NOT POPULATED C44 C46 C48 C50 C52 C54 C56 100NF 100NF 100NF 100NF 100NF 100NF 100NF P9 R24 0R MN8 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A22 P15 A21 3V3 R144 P9 4.7K A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 12 11 14 13 26 28 RESET WE N.C VPP CE OE I/00 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 VCCQ 47 VCC 37 GND GND 46 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D AT49BV642D 3V3 C57 100NF NRSTFLASH NWE 28 41 54 6 12 46 52 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 3V3 NRD 256 Mbits R27 470K R30 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 C58 100NF NOT POPULATED 0R R28 NCS 0R C R29 470K 3V3 3V3 NANDFLASH R33 10K IDE CONNECTOR J8 DUAL FOOTPRINT CLE ALE NANDOE NANDWE NANDCS J29 RDYBSY 3V3 R31 R32 0R 0R R34 R35 0R 1K R37 470K B S2 MN21A CLE ALE RE WE CE 16 17 8 18 9 CLE ALE RE WE CE RB 7 R/B WP 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C !"#$!%&$'"(#) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 26 28 30 32 40 42 44 46 27 29 31 33 41 43 45 47 N.C PRE N.C 39 38 36 VCC VCC 37 12 VSS VSS VSS 48 25 13 NOT POPULATED D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C60 100NF C59 100NF MN21B CLE ALE RE WE CE 16 17 8 18 9 CLE ALE RE WE CE RB 7 R/B WP 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C !"#$!%&$'"(#) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.C 48 47 46 45 40 39 38 35 34 33 28 27 VCC VCC 37 12 VSS VSS 36 13 LT1 D0 D1 D2 D3 D4 D5 D6 D7 RESET- 3V3 R38 A C E 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 D7 D6 D5 D4 D3 D2 D1 D0 10K DIOWDIORIORDY INTRQ 3V3 A1 A0 CS03V3 B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 D8 D9 D10 D11 D12 D13 D14 D15 B R39 10K A2 CS13V3 C62 10µF 10V LT2 IDE ATA-6 3V3 C61 100NF A A C B A INIT EDIT REV MODIF. AT91SAM9263-EK EBI0 MEMORY SCALE PP 10-JUI-08 JPG 15-MAR-07 JPG 10-OCT-06 DES. DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET C This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 4 11 8 7 6 5 4 3 2 1 D D PSRAM D[0..15] A[1..21] MN9 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 C A3 A4 A5 B3 B4 C3 C4 D4 H2 H3 H4 H5 G3 G4 F3 F4 E4 D3 H1 G2 H6 E3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 NC A6 B5 G5 A2 E2 E1 W G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 B6 C5 C6 D5 E5 F5 F6 G6 B1 C1 C2 D2 E2 F2 F1 G1 VCC E1 D1 VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C 3V3 C63 100NF R40 10K NCS NWR NOE 3V3 A1 B2 LB UB LB UB 3V3 R142 R143 NOT POPULATED 5 D6 VCC E6 VSS M69AW048B 0R C64 100NF C161 1µF 4 VOUT N.C VIN 1 VEN 3 GND 2 MN21 LP5951MF-1.8 B C162 1µF B A A C B A INIT EDIT REV MODIF. AT91SAM9263-EK EBI1 MEMORY SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET C This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 5 11 8 7 6 5 4 3 2 1 CKSEL MN10 MCI0_CK D SPI0_SPCK 1 IN1 2 GND 3 IN0 IN2 6 VCC 5 3V3 Y 4 C65 100NF SN74LVC1G97 D R41 10K 4 3 2 1 RR8 68K 5 6 7 8 3V3 MCI0_CD C66 100NF MCI0_DA1 MCI0_DA0 3V3 MCI0_CDA MCI0_DA3 MCI0_DA2 J9 FPS009 12 11 10 8 7 6 5 4 3 2 1 9 SD CARD / MMC CARD DATAFLASH CARD INTERFACE C C R42 10K 4 3 2 1 RR9 68K 5 6 7 8 3V3 MCI1_CD C67 100NF MCI1_DA1 MCI1_DA0 3V3 MCI1_CK B MCI1_CDA MCI1_DA3 MCI1_DA2 J10 FPS009 12 11 10 8 7 6 5 4 3 2 1 9 B SD CARD / MMC CARD INTERFACE 3V3 R43 2,2K SCL SDA R45 0R R46 0R R44 2,2K MN11 3V3 C68 100NF A 6 5 SCL SDA 8 VCC 4 GND A0 A1 NC 1 2 3 WP 7 A SERIAL EEPROM C B A INIT EDIT REV MODIF. AT91SAM9263-EK MCI & TWI SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET C This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 6 11 8 7 6 5 4 3 2 3.5 PHONEJACK STEREO J11 3 5 + C69 100µF 6V3 RB CODEC ID CLK FREQ OUT OUT IN IN OUT IN OUT IN PRIMARY SECONDARY PRIMARY PRIMARY 24.576 MHz 12.288 MHz 48.000 MHz 14.318 MHz Local XTAL Ext. BITCLK Ext. BITCLK (Into XTAL-IN) Ext. BITCLK (Into XTAL-IN) RA AVDD_AC97 R49 1K C81 100NF Y3 24.576MHz C80 C82 100NF 22PF SDATA_OUT BITCLK R54 47R SDATA_IN R55 47R 1 2 3 4 5 6 7 8 9 10 11 12 C 3V3 MN20 1 A 2 B 3 GND DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET NC VCC 5 C 4 AD1981B R56 2,2K SN74LVC1G66 C76 1µF R52 22K C78 36 35 34 33 32 31 30 29 28 27 26 25 VREFOUT C84 100NF C85 C86 C87 C88 270 pF 270 pF 270 pF 270 pF C89 100NF C90 C91 100NF 1µF 2 Bypass C93 C94 R66 0R 8 SR800SMT 1 Shutdown Bias SSM2211 1µF R57 GND 7 4.7K 1µF R59 100NF C98 L5 742792093 L6 742792093 3.5 PHONEJACK STEREO J12 3 5 4.7K R61 4.7K C95 470 pF C96 470 pF 1 4 B R62 100R 100NF LINE-IN 2 AGND_AC97 AVDD_AC97 C103 47 uF 6V3 Vo2 C C92 100NF R60 4.7K 4.7µH 220mA Av=1 VDD/2 SPK1 5 AGND_AC97 C97 C101 10µF 10V Vo1 3 +IN OPTIONAL VOICE FILTER COMPONENTS C102 100NF 4 VDD 4 -IN AGND_AC97 B L8 10µF 6 C83 100NF MN13 AVDD_AC97 AGND_AC97 5V 1 R53 22K R58 2,2K Need only to isolate PB3/BMS during the reset sequence C72 470 pF AGND_AC97 AVDD_AC97 LINE_OUT_R LINE_OUT_L AVDD4 AVSS4 AFILT4 AFILT3 AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1 HEADPHONE LINE-OUT 2 C71 470 pF 13 14 15 16 17 18 19 20 21 22 23 24 SYNC RST# R48 1K 48 47 46 45 44 43 42 41 40 39 38 37 MN12 C79 10µF 10V AGND_AC97 SPDIF EAPD ID1 ID0 AVSS3 AVDD3 NC HP_OUT_R AVSS2 HP_OUT_L AVDD2 MONO_OUT 22PF 3V3 PHONE_IN AUX_L AUX_R JS1 JS0 CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R C77 742792093 D C75 10µF 10V C73 100NF R50 1K R51 NOT POPULATED R47 1K C74 100NF (see table) RB EXT_CLK L4 AGND_AC97 D C70 100µF 6V3 RA 742792093 + CLOCK SELECTION - PIN STRAPING TABLE L3 1 L7 742792093 L9 742792093 3.5 PHONEJACK STEREO J13 3 5 R63 100R C99 10NF C100 10NF R64 3,9K R65 3,9K C104 470 pF MONO / STEREO MICROPHONE INPUT 2 C105 470 pF 1 AGND_AC97 AGND_AC97 R67 0R AVDD_AC97 OPTIONAL MIC BIASING FROM VREFOUT VREFOUT 4 C106 470 pF R68 NOT POPULATED R69 470R AGND_AC97 R71 470R A A R70 NOT POPULATED TO BIAS FROM VREFOUT CHANGE R64 and R65 to 3k 5% DO NOT INSTALL R71, R69, C107, C108 C107 10µF 10V C108 10µF 10V C B A INIT EDIT REV MODIF. VREFOUT MUST BE PROGRAMMED TO 3.7V AGND_AC97 USING VREFH BIT (REG 76h) AT91SAM9263-EK AUDIO AC97 SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET C This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 7 11 7 6 3V3 C117 100NF GND 1 C1C2+ 3 4 6 V- C2- 5 14 3V3 C111 100NF C115 100NF R73 100K R72 100K 0R R75 DTXD TXD 0R R77 10 T RTS 0R 12 R R79 DRXD RXD 0R R81 8 J14 9 R CTS R76 C116 100NF R74 100K 0R R78 0R R80 0R R82 0R 3V3 C R84 0R VCC 16 GND 15 C1C2+ V+ 2 5 C2- V- 6 CANRS C119 33PF CANTX USB DEVICE INTERFACE 1 2 27R 4 3 27R R92 5 CANRXEN DDM R94 CANRX DDP C121 15PF 5V MN17 C125 100NF C127 33 uF 16V J19 1 6 2 7 3 8 4 9 5 C118 100NF 14 T 7 T 12 R 13 9 R 8 D J15 C122 15PF R87 0R R89 0R R91 0R R93 0R C CAN BUS MN16 8 Rs 1 D J17 CANH 7 1 J16 2 CANL 6 R90 120R 5 EN 3 4 R 2 GND R95 10K VCC 3 SN65HVD234 C123 100NF C126 33 uF 16V MALE RIGHT ANGLE C114 100NF R86 10K NOT POPULATED B RS232 COM PORT C113 100NF 3V3 USBCNX R85 22K 3V3 J18 C1+ 3 4 10 1 ADM3202ARNZ * R88 1,5K 1 11 ADM3202ARNZ 15K R83 6 C112 100NF 3V3 11 T 7 10 11 C1+ 2 V+ 13 C120 100NF 2 10 C110 100NF 1 6 2 7 3 8 4 9 5 D 3 MN14 VCC 15 MALE RIGHT ANGLE 4 MN15 16 C109 100NF SERIAL DEBUG PORT 5 11 8 3V3 C124 10µF 10V USB HOST INTERFACE 8 OUTA ENA 1 ENA 7 IN FLGA 2 FLGA 6 GNG FLGB 3 FLGB 5 OUTB ENB 4 ENB B SP2526A-2 CCUSBA-32002-30X B1 B2 B3 B4 A1 A2 A3 A4 4 3 C128 100NF NOT POPULATED C130 47pF 2 1 C131 47pF R98 15K 39R R96 39R R97 HDMA HDPA R99 15K C129 100NF NOT POPULATED A C132 47pF C133 47pF R102 15K 39R R100 39R R101 HDMB HDPB A R103 15K C B A INIT EDIT REV MODIF. AT91SAM9263-EK SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 7 6 5 4 3 2 DATE REV. SHEET C SERIAL INTERFACES 8 VER. 1 8 11 8 7 6 D 5 4 3 2 1 D 3V3 R104 1 OE 10K VDD 4 C134 100NF 50 MHz 2 VSS OUT 3 Y4 C135 100NF R105 0R TXD1 TXD0 TX_EN C RXD1 RXD0 RX_DV R145 10K R146 10K R147 R148 10K 10K RX_ER 3V3 MDC MDIO MDINTR 3V3 R149 R112 R113 R114 R110 10K 1.5K 0R 10K 10K REF_CLK/XT2 17 18 19 20 21 22 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE 26 27 28 29 RXD3/PHYAD3 RXD2/PHYAD2 RXD1/PHYAD1 RXD0/PHYAD0 34 37 RX_CLK/10BTSER RX_DV/TESTMODE 16 38 TX_ER/TXD4 RX_ER/RXD4/RPTR 36 35 COL/RMII CRS/PHYAD4 24 25 32 MDC MDIO MDINTR 39 DISMDIX 3V3 J21 C143 100NF 41 DVDD C144 100NF 30 DVDD C145 100NF 23 DVDD 15 33 44 DGND DGND DGND 10 PWRDWN 40 RESET B R118 0R NRST XT1 43 TX+ 7 R107 49R9 1% R108 49R9 1% J20 1 TD+ 16 42 15 TX_CLK GND_ETH MN18 0R TX+ 1 2 TD- TX- 2 3 RD+ RX+ 3 RX- 6 4 CT TX- 8 C AVDDT RX+ 3 5 CT RX- 6 RD- 4 AVDDR 1 AVDDR 2 C136 100NF C138 100NF AVDDT DM9161AEP C139 10µF 10V AVDDT 9 C141 100NF AGND AGND AGND 5 6 46 GND_ETH BGRESG 47 BGRES LEDMODE LED0/OP0 LED1/OP1 LED2/OP2 CABLESTS/LINKSTS 48 31 11 12 13 14 N.C 45 AVDDT L10 742792093 C140 10µF 10V R109 49R9 1% R111 49R9 1% C137 100NF 75 75 GND_ETH 1nF 4 7 8 J00-0061NL GND_ETH RR2 10K 75 8 3V3 R115 6,80K 1% 75 7 NC 5 C142 100NF RJ45 ETHERNET CONNECTOR 8 7 6 5 R106 1 2 3 4 SG-8002JC-50.0000M-PCB 3V3 1K DS4 DS5 YELLOW GREEN DS6 GREEN 1K 1K R116 FULL DUPLEX R117 SPEED 100 R119 LINK&ACT B 3V3 C146 10µF 10V R120 0R R121 0R GND_ETH A A C B A INIT EDIT REV MODIF. AT91SAM9263-EK SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET C RMII ETHERNET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 9 11 8 7 6 5 4 3V3 C149 100NF J23 VDDISI CTRL1 SCL ISI_D1 ISI_D3 ISI_D5 ISI_D7 ISI_D9 ISI_D11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 ISI_D0 ISI_D2 ISI_D4 ISI_D6 ISI_D8 ISI_D10 C148 100NF D 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Z17 TX09D71VM1CCA 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R123 10K 1 54132-4097 C147 10V 10µF C150 100NF C 2 1/4 VGA TFT LCD DISPLAY IMAGE SENSOR CONNECTOR D 3 CTRL2 SDA ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK ISI_D[0..11] J22 R122 B0 B1 B2 LCDD18 LCDD19 LCDD20 B3 B4 B5 LCDD21 LCDD22 LCDD23 G0 G1 G2 LCDD10 LCDD11 LCDD12 G3 G4 G5 LCDD13 LCDD14 LCDD15 R0 R1 R2 LCDD2 LCDD3 LCDD4 R3 R4 R5 LCDD5 LCDD6 LCDD7 10K X_RIGHT Y_LOW X_LEFT Y_UP VCTRL PCI B[0..5] G[0..5] C R[0..5] DTMG HSYNC DCLK 3V3 C151 100NF C152 10µF 10V 3V3 TOUCH SCREEN CONTROLLER B X_LEFT Y_UP X_RIGHT Y_LOW 2 3 4 5 R130 100K R131 100K TP71 7 8 16 14 12 15 R126 0R SPCK MOSI MISO NPCS BUSY PENIRQ 13 11 R127 R128 0R 0R BUSY IRQ IN3 IN4 ADS7843E TP74 47R DCLK DIN DOUT CS XP YP XM YM VREF VCC VCC GND TP73 B R125 MN19 TP72 AGND R124 100K 9 1 10 C154 100NF 6 R129 0R L11 4.7µH 220mA R132 NOT POPULATED C155 100NF C156 100NF 3V3 C153 10µF R133 0R TWO USER'S ANALOG INPUTS Full-Scale Input Span 0 to VREF A A C B A INIT EDIT REV MODIF. AT91SAM9263-EK SCALE PP JPG JPG DES. 10-JUI-08 15-MAR-07 10-OCT-06 DATE 1/1 LCD & ISI This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 VER. DATE REV. SHEET C 1011 8 7 6 5 4 3 PA[0..31] PC[0..31] PB[0..31] PD[0..31] D 2 1 D PE[0..31] J24 MCI1_CDA MCI1_DA1 MCI1_DA3 TWCK/RF0 PA7 PA9 PA11 PB5 SPI1_MOSI SPI1_NPCS0 SPI1_NPCS2/TIOA2 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PA6 PA8 PA10 PB4 PB6 PB12 PB14 PB16 PB18 PB20 PB22 PB24 PB26 PB28 PB30 MCI1_CK/PCK2 MCI1_DA0 MCI1_DA2 TWD/RK0 TF1/DMARQ1 SPI1_MISO SPI1_SPCK SPI1_NPCS1/PCK1 SPI1_NPCS3/TIOB2 RXD1/SPI0_NPCS3 RXD2/SPI1_NPCS3 EBI0_NWAIT/RTS2 EBI0_NCS5/CFCS1/RTS1 EBI0_CFCE2/SCK2 EBI0_NCS2/TSYNC EBI0_A24/TPS0 PD1 PD3 PD5 PD7 PD9 PD11 PD13 TIOB0 PE17 PE19 LCDD17/ETX3 PC13 PC21 3V3 3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PD0 PD2 PD4 PD6 PD8 PD10 PD12 PD14 PE16 PE18 PE22 TXD1/SPI0_NPCS2 TXD2/SPI1_NPCS2 FIQ/DMARQ2 EBI0_NCS4/CFCS0/CTS2 EBI0_CFCE1/CTS1 SCK1 EBI0_A23/TCLK EBI0_A25_CFRNW/TPS1 TIOA0 ECRS/EBI1_NCS2/NANDCS PC0 LCDVSYNC PC28 PWM0/TCLK1 PC20 LCDD16/ETX2 3V3 S3 5V C C USER'S GRID AERA 3V3 5V + $ , B B 3V3 5V + $ , A A C B A INIT EDIT REV MODIF. AT91SAM9263-EK SCALE PP 10-JUI-08 JPG 15-MAR-07 JPG 10-OCT-06 DES. DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 7 6 5 4 3 2 DATE REV. SHEET C EXPANSION CONNECTORS 8 VER. 1 11 11 Section 6 Warning 6.1 BMS Signal Sampling The following behavior and its consequences are related to an AT91SAM9263 device issue described in the Errata section of the AT91SAM9263 datasheet (“BMS: BMS does not have correct state”). The text below is a reminder of this issue and a Workaround proposal at the board level. Description The BMS signal, which is multiplexed with the PB3/AC97RX PIO needs to be sampled at a High Level for the AT91SAM9263 microcontroller to boot out of the internal ROM. At power up, the on-board AC97 device negates its “SDATA_IN” output pin and due to this fact, the BMS_PB3/AC97RX pin needs to be isolated during the reset phase. The MN20 gate, controlled by the NRST signal, achieves this, but with the default ERSTL value in the reset controller (refer to the RSTC section in the AT91SAM9263 datasheet for more details), when the VDDBU power supply is applied for more than 1.2 seconds before the VDDCORE power supply, the AT91SAM9263 microcontroller samples the BMS signal one Slow Clock (SLCK) cycle after the NRST signal rising (See Figure 6-1). As a result, the BMS signal is sampled at a Low Level and the AT91SAM9263 boots out of the external EBI device connected to NCS0. AT91SAM9263-EK Evaluation Board Rev. B User Guide 6-1 6341D–ATARM–30-Sep-09 Warning Figure 6-1. BMS Signal Sampling SLCK Any Freq. MCK Backup Supply (VDDBU) POR output Startup Time backup_nreset Processor Startup = 3 cycles processor_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles BMS_PB3/AC97RX BMS signal sampling Workaround: At the first VDDBU power up or if this power supply has been shut down (J4-1 opened (VDDBU/VDDBACKUP Jumper) or the CR1225 battery cell (J3) removed or changed), the following power-up sequence has to be applied in order to boot out of the internal ROM: 1. Close J2 to force power on 2. Open J5 (Boot Mode Select Jumper) 3. Power on the board 4. Remove and replace J4-1 (VDDBU/VDDBACKUP Jumper) 6-2 6341D–ATARM–30-Sep-09 AT91SAM9263-EK Evaluation Board Rev. B User Guide Section 7 Revision History 7.1 Revision History In the following table the most recent version of the document appears first. Table 7-1. Document 6341D 6341C 6341B 6341A Change Request Ref. Comments PE17 and PE19 information removed from ‘Peripheral Usage’ column in Table 3-5, “PIO Controller E,” on page 3-11 6694 Section 1.5 ”NAND Flash Access Issue” on page 1-3 edited 6024 Row R30 and note (2) added to Table 4-1 on page 4-1 6057 Section 1.2, ” How to Identify the Kit BOM Revision”, added to this user guide. Section 1.3, ” How to Identify the PCB Revision”, updated. Section 1.4, ” How to Identify the SAM9263 Silicon Revision”, added to this user guide Section 1.5, ” NAND Flash Access Issue”, added to this user guide. 5626 Section 5.1, ” Schematics”, updated with rev C schematics. (“Audio AC97” schematic updated) 5626 5082 Table 4-1, “Configuration Jumpers and Straps,” on page 4-1, added J5-7 and J29 5391 First issue. AT91SAM9263-EK Evaluation Board Rev. B User Guide 7-1 6341D–ATARM–30-Sep-09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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