AVR535: Migration from ATtiny26 to ATtiny261A

AVR535: Migration from ATtiny26 to
ATtiny261A/461A/861A
Features
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General Porting Considerations
Memories
System Clock and Clock Options
System Control and Reset
Registers
Interrupts
Timer/Counters
USI – Universal Serial Interface
Analogue-to-Digital Converter
I/O Ports
Memory Programming
Electrical Characteristics
8-bit
Microcontrollers
Application Note
1 Introduction
This application note is a guide to assist users of ATtiny26 in converting existing
designs to ATtiny261A. The document will also assist ATtiny26 users to migrate to
the ATtiny461A and ATtiny861A devices, which are members of the same family
as the ATtiny261A, offering larger memories.
In addition to the differences described in this document, the electrical
characteristics of the devices are different. Some of these differences are outlined
in this document and some are not. Please check the latest data sheets for detailed
information.
Improvements or added features in ATtiny261A that are not in conflict with those in
ATtiny26 are not listed in this document.
Note: This application note serves as a guide to ease migration. For complete
device details, always refer to the most recent version of the
ATtiny261A/461A/861A data sheet.
Rev. 8273-AVR-12/09
2 General Porting Considerations
Between the devices described in this application note, some registers and register
bits have changed name but note that they preserve the same functionality. They are
all listed later in this document.
To make the porting process as easy as possible, always refer to registers and bit
positions using their defined names. Avoid using absolute addresses and values. In
most cases, the register and bit names are unchanged from device to device. When
you are porting a design, it is more convenient to include the correct definition file for
the new device, rather than manually changing all your addresses and bit values. It is
also considered good programming practice to use named references instead of
absolute values. Some examples are shown below.
PORTB |= (1<<PORTB3);
DDRB &= ~(1<<PORTB3);
// Set pin 3 on port B high
// Set pin 3 on port B as input
// Configure USI
USICR = (1<<USISIE)|(0<<USIOIE)|(1<<USIWM1)|(0<<USIWM0)|
(1<<USICS1)|(0<<USICS0)|(0<<USICLK)|(0<<USITC);
To avoid conflicts with added features and register functionality, never access
registers that are marked as reserved. Reserved bits should always be written to zero
if accessed. This ensures forward compatibility, and added features will stay in their
default states when unused.
3 Memories
ATtiny26 and ATtiny261A have the same amount of volatile and non-volatile memory.
ATtiny461A and ATtiny861A have more SRAM, Flash and EEPROM than ATtiny26.
Applications that rely on the size of memory may therefore misbehave when memory
size is increased. For example, this may be the case with wrap-around indexing of
EEPROM.
3.1 Stack
The ATtiny26 stack pointer is implemented as an 8-bit register in the I/O space. In
ATtiny261A the stack pointer is also realized as one 8-bit register, but in ATtiny461A
and ATtiny861A the amount of data memory exceeds the 8-bit address range and the
stack pointer has been realized as two 8-bit registers. See table below.
Table 3-1. Device Stack Pointers.
Device
Low Stack Pointer
ATtiny26
SP
ATtiny261A
ATtiny461A
ATtiny861A
SPL
High Stack Pointer
N/a
SPH
See ATtiny261A/461A/861A data sheet for information on how to access stack
pointer registers.
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3.2 EEPROM
EEPROM write access times depend on the frequency of the internal RC oscillator. In
ATtiny261A/461A/861A the access times are shorter than in ATtiny26.
ATtiny261A is part of a pin and functionally compatible subfamily of tinyAVR®, where
the size of EEPROM ranges from 128 to 512 bytes. This means more than eight data
bits are required for memory addressing and, therefore, the EEPROM address
register has been expanded from one 8-bit register (EEAR in ATtiny26) to two
(EEARL and EEARH in ATtiny261A, ATtiny461A and ATtiny861A). Since the initial
values of the registers are undefined it is important to always write both registers
even when accessing only the bottom section of the EEPROM.
4 System Clock and Clock Options
ATtiny261A/461A/861A has a more advanced clock system than ATtiny26. In
ATtiny261A/461A/861A there is a system clock prescaler and three internal clock
sources.
4.1 Clock Sources
Clock source options are set differently in ATtiny261A/461A/861A. See table below
how to set the ATtiny26 settings on the ATtiny261A/461A/861A.
Table 4-1. Clock Source Settings of the ATtiny26 on the ATtiny261A/461A/861A.
ATtiny26
ATtiny261A/461A/861A
Clocking Option
PLLCK
CKSEL[3:0]
CKSEL[3:0]
CLKPS[3…0]
PLL
0
0001
0001
0000
0000
External Clock
1
0000
Internal RC Oscillator, 1 MHz
1
0001
Internal RC Oscillator, 2 MHz
1
0010
Internal RC Oscillator, 4 MHz
1
0011
Internal RC Oscillator, 8 MHz
1
0100
Internal 128 kHz Oscillator
Not available
External RC Oscillator, 0.1…0.9 MHz
1
0101
External RC Oscillator, 0.9…3.0 MHz
1
0110
External RC Oscillator, 3.0…8.0 MHz
1
0111
External RC Oscillator, 8.0…12.0 MHz
1
1000
External Low-Frequency Oscillator, 32.768 kHz
1
1001
01xx
0000
1
1010
0000
1
1011
1000
1001
1
1100
0000
1
1101
1010
1011
1
1110
0000
1
1111
1100, 1101
1110, 1111
External Resonator Oscillator, 0.4…0.9 MHz
External Crystal/Resonator Oscillator, 0.9…3.0 MHz
External Crystal/Resonator Oscillator, 3.0…16.0 MHz
0000
0011
0010
0010
0001
0000
0011
0000
Not available, use internal RC
oscillator instead
0000
0000
0000
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4.2 High Frequency PLL Clock
When using the internal PLL as a clock source, ATtiny261A/461A/861A applies a
longer start-up delay than ATtiny26 after a power-on reset and power-down wakeup.
This is to ensure stable and glitch-free operation.
5 System Control and Reset
ATtiny261A/461A/861A has more fuse bits than ATtiny26. In addition, some fuse bits
have a different functionality.
5.1 Brown-Out Detection (BOD)
Both ATtiny26 and ATtiny261A/461A/861A have programmable Brown-Out Detection
levels. The programming method and levels are not entirely the same. See table
below.
Table 5-1. Brown-Out Detection (BOD) Characteristics.
ATtiny26
ATtiny261A/461A/861A
BODEN
BODLEVEL
VBOT
BODLEVEL[2…0]
VBOT
1
X
Disabled
111
Disabled
0
4.0 V
100
4.3 V
1
2.7 V
101
2.7 V
110
1.8
0
Not available.
5.2 Start-up Times & Brown-out Detection
Due to electrical differences between ATtiny26 and ATtiny261A/461A/861A there may
be minor dissimilarities in start-up times. Please see device data sheets for more
detailed information.
5.3 Power-On Reset
The table below summarizes the differences between the reset circuitry of ATtiny26
and that of ATtiny261A/461A/861A. Please see device data sheets for more detailed
information.
Table 5-2. Changes in Power-On Reset
ATtiny26
Symbol
Min
ATtiny261A/461A/861A
Unit
Typ
Max
Min
Typ
Max
VPOR
1.4
2.3
1.1
1.4
1.6
V
VPOA
1.3
2.3
0.6
1.3
1.6
V
SRon
0.01
V/ms
5.4 Watchdog Timer
The ATtiny261A/461A/861A includes an enhanced Watchdog Timer (WDT),
compared to the watchdog timer used in ATtiny26. At 5V operating voltage the WDT
will behave similar on ATtiny26 and ATtiny261A/461A/861A. At lower voltages the
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watchdog timeout interval may differ. Please see data sheet for characteristic data on
watchdog oscillator frequency.
If the WDT is not used, it is still recommended to disable it initially in the application
code to clear unintentional WDT enabled events.
6 Registers
6.1 Renamed Registers
The below tables list the registers which have been renamed but still exist at the
same physical address and have maintained their functionality. It is only required to
update the register name in the application.
Table 6-1. Changes to Register Names.
Address [hex]
Name in ATtiny26
Name in ATtiny261A/461A/861A
0x06
ADCSR
ADCSRA
0x08
ACSR
ACSRA
0x1E
EEAR
EEARL
0x1F
-
EEARH
0x32
TCNT0
TCNT0L
0x33
TCCR0
TCCR0B
0x3D
SP
SPL
6.2 Renamed Bits
The below table lists the bits that have been renamed, but still exist in the same
register and in the same register location.
Table 6-2. Changes to Bit Names.
ATtiny26
ATtiny261A/461A/861A
Bit Name
Register
Address
Bit Name
ADFR
ADCSR
0x06
ADATE
USISIF
USISR
0x0E
USICIF
EEMWE
EECR
0x1C
EEMPE
EEWE
EECR
0x1C
EEPE
6.3 Removed Bits
The below table lists register bits, which have been removed and have no close
replacements.
Table 6-3. ATtiny26 Removed Register Bits and Functions.
Register Name
Register Bit
Function
TCCR1B
CTC1
Resets Timer/Counter1
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6.4 New Registers and Bits
The new registers and bits for ATtiny261A/461A/861A can be seen in the following
table. See the data sheet for the full description.
Table 6-4. ATtiny261A new bits and registers.
Address
Register
Name
Bit
Bit Name
Function
0x3B (0x5B)
GIMSK
7
INT1
External Interrupt Request 1 Enable
0x3A (0x5A)
GIFR
7
INTF1
External Interrupt Flag 1
7
OCIE1D
Timer/Counter1 Output Compare Interrupt Enable
4
OCIE0A
Timer/Counter0 Output Compare Match A Interrupt Enable
3
OCIE0B
Timer/Counter Output Compare Match B Interrupt Enable
0
TICIE0
Timer/Counter0, Input Capture Interrupt Enable
7
OCF1D
Output Compare Flag 1D
4
OCF0A
Output Compare Flag 0 A
3
OCF0B
Output Compare Flag 0 B
0
ICF0
Timer/Counter0, Input Capture Flag
4
CTPB
Clear Temporary Page Buffer
3
RFLB
Read Fuse and Lock Bits
2
PGWRT
Page Write
1
PGERS
Page Erase
0
SPMEN
Store Program Memory Enable
3
PRTIM1
Power Reduction Timer/Counter1
2
PRTIM0
Power Reduction Timer/Counter0
1
PRUSI
Power Reduction USI
0
PRADC
Power Reduction ADC
7
BODS
BOD Sleep
2
BODSE
BOD Sleep Enable
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
6
TIMSK
TIFR
SPMCSR
PRR
0x34 (0x54)
MCUSR
0x33 (0x53)
TCCR0B
4
TSM
Timer/Counter Synchronization Mode
0x2F (0x4F)
TCCR1B
5, 4
DTPS11, DTPS10
Dead Time Prescaler Bits
0x2A (0x4A)
OCR1D
7:0
Timer/Counter1 Output
Compare Register D
Timer/Counter1 Output Compare Register D
0x29 (0x49)
PLLCSR
7
LSM
PLL Low Speed Mode
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0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
CLKPR
TCCR1C
TCCR1D
0x25 (0x45)
TC1H
0x24 (0x44)
DT1
7
CLKPCE
Clock Prescaler Change Enable
3:0
CLKPS3: CLKPS0
Clock Prescaler Select Bits 3 - 0
7,6
COM1A1S, COM1A0S
Comparator A Output Mode, Shadow Bits 1 and 0
5,4
COM1B1S, COM1B0S
Comparator B Output Mode, Shadow Bits 1 and 0
3,2
COM1D1 , COM1D0
Comparator D Output Mode, Bits 1 and 0
1
FOC1D
Force Output Compare Match 1D
0
PWM1D
Pulse Width Modulator D Enable
7
FPIE1
Fault Protection Interrupt Enable
6
FPEN1
Fault Protection Mode Enable
5
FPNC1
Fault Protection Noise Canceler
4
FPES1
Fault Protection Edge Select
3
FPAC1
Fault Protection Analog Comparator Enable
2
FPF1
Fault Protection Interrupt Flag
1, 0
WGM11, WGM10
Waveform Generation Mode Bits
1, 0
TC19 , TC18
Two MSB bits of the 10-bit accesses
7:4
DT1H3: DT1H0
Dead Time Value for OC1x Output
3:0
DT1L3: DT1L0
Dead Time Value for inverted OC1x Output
0x23 (0x43)
PCMSK0
7:0
PCINT7:0
Pin Change Enable Mask 7:0
0x22 (0x42)
PCMSK1
7:0
PCINT15:8
Pin Change Enable Mask 15:8
7
WDIF
Watchdog Timeout Interrupt Flag
0x21 (0x41)
WDTCR
6
WDIE
Watchdog Timeout Interrupt Enable
5
WDP3
Watchdog Timer Prescaler 3
0x20 (0x40)
DWDR
7:0
DWDR[7:0]
debugWire Data Register
0x1F (0x3F)
EEARH
0
EEAR8
EEPROM Address
0x1C (0x3C)
EECR
5,4
EEPM1, EEPM0
EEPROM Programming Mode Bits
7
TCW0
Timer/Counter0 Width
6
ICEN0
Input Capture Mode Enable
5
ICNC0
Input Capture Noise Canceler
4
ICES0
Input Capture Edge Select
3
ACIC0
Analog Comparator Input Capture Enable
0
CTC0
Waveform Generation Mode
0x15 (0x35)
TCCR0A
0x14 (0x34)
TCNT0H
7:0
Timer/Counter0 Counter
Register High Byte
Timer/Counter0 Counter Register High Byte
0x13 (0x33)
OCR0A
7:0
Timer/Counter0 Output
Compare Register A
Timer/Counter0 Output Compare Register A
0x12 (0x32)
OCR0B
7:0
Timer/Counter0 Output
Compare Register B
Timer/Counter0 Output Compare Register B
0x11 (0x31)
USIPP
0
USIPOS
USI Pin Position
7
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0x10 (0x30)
USIBR
7:0
USI Buffer Register
USI Buffer Register
0x0C (0x2C)
GPIOR2
7:0
General Purpose I/O
Register 2
General Purpose I/O Register 2
0x0B (0x2B)
GPIOR1
7:0
General Purpose I/O
Register 1
General Purpose I/O Register 1
0x0A (0x2A)
GPIOR0
7:0
General Purpose I/O
Register 0
General Purpose I/O Register 0
7
HSEL
Analog Comparator Hysteresis Select
6
HLEV
Analog Comparator Hysteresis Level
2:0
ACM2:0
Analog Comparator Multiplexer
7
BIN
ADC Bipolar Input Mode
6
GSEL
Gain Select
4
REFS2
Reference Selection Bit
3
MUX5
Analog Channel and Gain Selection Bit 5
2:0
ADTS2 :0
ADC Auto Trigger Source
7:4
ADC10D: ADC7D
Digital Input Disable
7:4
ADC6D:ADC3D
Digital Input Disable
3
AREFD
AREF Digital Input Disable
2:0
ADC2D:ADC0D
Digital Input Disable
5:0
OC1OE5:0
Output Compare Override Enable Bits
0x09 (0x29)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
ACSRB
ADCSRB
DIDR1
DIDR0
TCCR1E
7 Interrupts
7.1 Interrupt Vectors
ATtiny261A/461A/861A has more interrupt vectors than ATtiny26, but all ATtiny26
vectors exist in identical locations on ATtiny261A/461A/861A. Programs can still use
the end of ATtiny26 interrupt vector table as a starting address on
ATtiny261A/461A/861A, provided that ATtiny261A/461A/861A specific interrupts are
not enabled. Additional interrupt vectors can be seen at the table below.
New interrupt vectors
Vector Program Source
Address
13
0x000C
WDT
14
0x000D
INT1
15
0x000E
TIMER0_COMPA
16
0x000F
TIMER0_COMPB
17
0x0010
TIMER0_CAPT
18
0x0011
TIMER1_COMPD
19
0x0012
FAULT_PROTECTION
8
Interrupt Definition
Watchdog Time-out
External Interrupt Request 1
Timer/Counter0 Compare Match A
Timer/Counter0 Compare Match B
Timer/Counter1 Capture Event
Timer/Counter1 Compare Match D
Timer/Counter1 Fault Protection
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7.2 Pin Change Interrupt
Pin change interrupts are automatically disabled on ATtiny26 if an alternative function
has been enabled for the given pin. In ATtiny261A/461A/861A this is not the case,
where alternative pin functions and pin change interrupts may be concurrently
enabled for the same pin. Pin change interrupts for a given pin in
ATtiny261A/461A/861A are masked and unmasked using Pin Change Mask Register
A (PCMSKA) and Pin Change Mask Register B (PCMSKB).
7.2.1 Source Pins and Masking
ATtiny261A/461A/861A extends pin change interrupts to cover all I/O pins, while
ATtiny26 only includes pins PA3, PA6…7 and PB0…7. Also, ATtiny261A/461A/861A
allows individual masking of pin change interrupt sources via registers PCMSK0 and
PCMSK1 (a feature not found in ATtiny26) but the default setting is to enable only
those sources that are common for both ATtiny26 and ATtiny261A/461A/861A.
8 Timer/Counters
8.1 Timer/Counter1
In ATtiny261A/461A/861A the synchronization registers are not bypassed as in
ATtiny26. This means a synchronization delay of 1.5 clock cycles is present in both
asynchronous and synchronous modes.
8.1.1 Bit CTC1 of Register TCCR1B
Bit CTC1 of register TCCR1B has been replaced by PWM1X on
ATtiny261A/461A/861A. Please note that these bits have a different functionality and
that this must be considered during migration.
8.1.2 Register OCR1C
Register OCR1C is now always the TOP value for the timer/counter and the register
is always reset (cleared to zero) after reaching the TOP value.
The lowest allowed TOP value is 3. If register OCR1C is loaded with a value lower
than 3 it will be forced to the value 3. Also note that after a reset the OCR1C register
is loaded with the timer/counter MAX value, which means that the default TOP value
is 0x3FF.
8.1.3 PWM Mode
When writing to register OCR1C on ATtiny261A/461A/861A the data is buffered and
the register updated only when OCR1C has reached the TOP value. In ATtiny26
writing to OCR1C is immediate.
9 USI – Universal Serial Interface
The ATtiny261A/461A/861A uses an enhanced version of the Universal Serial
Interface, as compared to the ATtiny26.
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9.1 Clock Sources
The USI clock can be selected from three different sources, two of which are common
for ATtiny26 and ATtiny261A/461A/861A. The third clock source option (USICS[2:0] =
01X) in ATtiny26 is Timer/Counter0 Overflow, but in ATtiny261A/461A/861A it has
been replaced by Timer/Counter0 Compare Match. Similar functionality can be
achieved but it may be necessary to update any parts of firmware that refer to
Timer/Counter0 overflow flags and interrupts.
10 Analogue-to-Digital Converter
The Analogue-to-Digital Converter (ADC) has been enhanced and in
ATtiny261A/461A/861A includes more features. ATtiny261A/461A/861A is a 1.8V
device and the default internal voltage reference is therefore set to 1.1V.
10.1 Voltage Reference Selection
Voltage reference source is selected using bits REFS2…0, located in registers
ADMUX (ADC Multiplexer Selection) and ADCSRB (ADC Control and Status Register
B). ATtiny26 only includes bits REFS1…0. The table below shows how to update
reference selection bits to maintain functionality.
Table 10-1. Voltage Reference setting of the ATtiny26 on ATtiny261A/461A/861A.
ATtiny26
ATtiny261A/461A/861A
REFS1…0
REFS2…0
00
000
AVCC
01
001
AREF (internal reference turned off)
10
110
Internal 2.56V reference (AREF
disconnected)
11
111
Internal 2.56V reference (AREF connected)
Not available
010
Internal 1.1V voltage reference
Voltage Reference
11 I/O Ports
Test limits for port drive strength are lower on ATtiny261A/461A/861A. This means
ATtiny261A/461A/861A ports are rated for a lower current than ATtiny26. Port driver
characteristics are outlined in the table below.
Table 11-1. Port Drive Characteristics.
Pin Rating [mA]
Sum Rating [mA]
ATtiny26
ATtiny261A/461A/861A
ATtiny26
ATtiny261A/461A/861A
VCC = 5V
20 mA
10 mA
VCC = 3V
10 mA
5 mA
400 mA
60 mA
Condition
12 Memory Programming
Some modifications regarding the programming of fuse and calibration bytes must be
taken into account. Also, the functionality of the calibration byte has been changed.
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12.1 Fuse Bits
The number of fuse bits has been increased and fuse bits are scattered over three
bytes in ATtiny261A/461A/861A. Read and write algorithms must be updated for
proper fuse programming.
The functionality of the following fuse bits has changed:
• The BODLEVEL fuse bit of ATtiny26 has been expanded to three fuse bits
(BODLEVEL2…0) on ATtiny261A/461A/861A.
• The BODEN fuse bit functionality of ATtiny26 has been integrated into
BODLEVEL2…0 fuse bits of ATtiny261A/461A/861A.
• The PLLCK and CKOPT fuse bit functionality of ATtiny26 has been integrated into
CKSEL3…0 fuse bits of ATtiny261A/461A/861A.
• Clock prescaler functionality of CKSEL fuses has been removed, since
ATtiny261A/461A/861A has a software configurable clock prescaler.
12.2 Signature Bytes
Signature bytes reside in a separate address space and can only be read external to
the device. Therefore, this notion only applies to programmers, et al, and not to the
actual program being migrated.
Signature bytes have been updated as illustrated in the table below.
Table 12-1. Summary of Signature Bytes.
Byte
ATtiny26
ATtiny261A
ATtiny461A
ATtiny861A
$000
$1E
$1E
$1E
$1E
$001
$91
$91
$92
$93
$002
$09
$0C
$08
$0D
12.3 Calibration Byte
ATtiny26 has four calibration bytes for the 1MHz, 2MHz, 4MHz and 8MHz operation
of the internal RC oscillator. ATtiny261A/461A/861A only has one calibration byte for
the internal RC oscillator.
13 Electrical Characteristics
ATtiny261A/461A/861A is manufactured using a different process than ATtiny26 and
electrical characteristics will therefore differ between these devices. For detailed
information, refer to the most recent version of the device data sheets.
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