AT73C240 Power-On and Power-Off Sequences 1. Scope This document decribes the sequences to apply to the AT73C240 product in order to operate the Power-On and Power-Off modes. The AT73C240 is a fully integrated, low-cost, combined stereo audio DAC and audio power amplifier circuit. The stereo DAC section is a complete high performance, stereo, audio digital-to-analog converter. It comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. Master clock is 256 or 384 times the input data rate, allowing choice of input data rate up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC section is followed by a volume and mute control and can be simultaneously played back directly through a stereo 32 Ohm headset pair of drivers. The stereo 32 Ohm headset pair of drivers also includes a mixer of a LINEL and LINER pair of stereo inputs. Power Management and Analog Companions (PMAAC) Application Note The Audio Power Amplifier is a differential amplifier designed in CMOS technology. It is capable of driving an 8 Ohm Loudspeaker at maximum power of 440mW. The volume, mute, power down, de-emphasis controls and audio formats are digitally programmable via a serial bus and the digital audio data are provided through a multiformat I2S interface. 2. Operating Conditions Table 2-1. Operating Condition Table For AT73C240 Product Parameter/Function Pads Min Max Unit Storage Temperature -- -55 150 °C Operating Temperature -- -40 85 °C Audio Power Input Voltage VBAT 3.0 5.5 V Digital Input Voltage VDIG 2.4 3.3 V Analog Input Voltage AVDD, AVDDHS 2.7 3.3 V 3. Glossary DAC -- Digital to Analog Converter SPI -- Serial Peripheral Interface TWI -- Two Wire Interface I²S -- Integrated Interchip Sound Interface 6466A–PMAAC–04-Jun-09 4. AT73C240 Block Diagram -36 to +12dB / 3dB step AT73C240 GNDB VREF PAINN VBAT CBP HPP Audio PA HPN AT73C240 Block Diagram PAINP Figure 4-1. VDIG AVDD Voltage Reference AVDDHS SPI_DOUT LINER PGA SPI_DIN / TWD Status Registers INGND -36 to +12dB / 3dB step SPI SPI_CLK / TWCK LINEL SPI_CSB / TW_ADD PGA -46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step MCLK -6 to +6dB / 3dB step 32 driver + DAC Volume Control + Volume Control RSTB Digital Filter VCM -6 to +6dB / 3dB step HSR 32 driver + DAC Volume Control + Volume Control Digital Filter Serial Audio I/F HSL SMODE SDIN LRFS BCLK GNDA -46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step MONOP MONO + GNDD MONON 2 Application Note 6466A–PMAAC–04-Jun-09 Application Note 5. Hardware Setup 5.1 Application Block Diagram In this Application Note we describe Power-On and Power-Off sequences in the case of the use of the following application diagram. Figure 5-1. AT73C240 Application Block Diagram PAINN AT73C240 22u 3.6 V VBAT Battery (Li-Ion or 3 x NiMh or NiCd) 100n 2.8V from LDO VDIG C17 100n C16 CBP 2.8V from LDO AVDD C7 HPP 8 Ohm Loudspeaker C18 100n Audio PA HPN AVDDHS C19 10µF C15 PAINP C9 470n MONOP REF VREF 10u 470n C11 MONON VCM C12 R C8 stereo line input 10u LINER L SPI_DOUT C3 470n SPI_DIN/TWD LINEL (e.g. FM Radio) SPI / TWI SPI_CLK/TWCK 470n DIG SPI_CSB/TW_ADD SMODE RSTB MCLK C6 32 HSR 32 Ohm 100u Headset or Line Out C5 HSL 32 100u Audio DAC Reset active low SDIN LRFS I2S BCLK 10u INGND C10 GNDA 5.2 GNDD Setup To perform any tests and measurements, it is necessary to have the following setup: VDIG = AVDDHS = AVDD = 2.8V VBAT = 3.6V SPI/TWI and I²S Interfaces connected The examples explained after are defined with the following DAC setup OVRSEL = 1 Write Bit [4] at ”1” @ 0x09 Address [DAC_CSFC Register] NBITS = 10 Write Bits [1:0] at ”10” @ 0x0A Address [DAC_MISC Register] DEEMPEN = 1 Write Bit [2] at ”1” @ 0x0A Address [DAC_MISC Register] DITHEN = 1 Write Bit [3] at ”1” @ 0x0A Address [DAC_MISC Register] DINTSEL = 00 Write Bits [4:5] at ”00” @ 0x0A Address [DAC_MISC Register] SPARE = 1 Write Bit [2] at ”1” @ 0x0B Address [Private Register] 3 6466A–PMAAC–04-Jun-09 6. Power-On and Power-Off Sequences 6.1 Playback Mode The Playback Mode corresponds to a data transfer from the i²S interface to the headset connector. Below is a diagram that shows the data path. Figure 6-1. AT73C240 Playback Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 6.1.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Power-On Sequence HEADSET ON - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - ONLNOR & ONLNOL = 1 Write Bits [2:3] = ”11” @ 0x00 address - ONMSTR & PRCHG = 1 Write Bits [1:0] = ”11” @ 0x0C address Wait 500ms I²S ON - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - RESFILZ & RSTZ = 1 Write Bits [1:0] = ”11” @ 0x10 address - PRCHG = 0 Write Bit [1] = ”0” @ 0x0C address Wait 1ms INCREASE GAIN 4 - ONDACL & ONDACR = 1 Write Bits [4:5] = ”11” @ 0x00 address - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LMPG & RMPG = xxx Write these bits to obtain desired output gain value Application Note 6466A–PMAAC–04-Jun-09 Application Note 6.1.2 Power-Off Sequence DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = ”00” @ 0x00 address - RESFILZ = 0 Write Bit [1] = ”0” @ 0x10 address - RSTZ = 1 Write Bit [0] = ”1” @ 0x10 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms - ONLNOR & ONLNOL = 0 Write Bits [2:3] = ”00” @ 0x00 address 5 6466A–PMAAC–04-Jun-09 6.2 Playback Amplified Mode The Playback Amplified mode corresponds to a data transfer from the i²S interface to the power amplifier output connector. Below is a diagram that shows the data path. Figure 6-2. AT73C240 Playback Amplified Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 6.2.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Power-On Sequence SET GAIN AT THE MINIMUM - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address MASTER ON - ONMSTR & PRCHG = 1 Write Bits [1:0] = ”11” @ 0x0C address Wait 500ms I²S ON - RESFILZ & RSTZ = 1 Write Bits [1:0] = ”11” @ 0x10 address - PRCHG = 0 Write Bit [1] = ”0” @ 0x0C address Wait 1ms PA ON - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAPRECH = 1 Write Bit [4] = ”1” @ 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = ”0” @ 0x11 address - APAON = 1 Write Bit [5] = ”1” @ 0x11 address Wait 10ms 6 - APAGAIN = xxdB Write these bits to obtain desired output gain value - LMPG & RMPG = xxdB Write these bits to obtain desired output gain value Application Note 6466A–PMAAC–04-Jun-09 Application Note 6.2.2 Power-Off Sequence DECREASE GAIN - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address PA OFF - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 0 Write Bit [6] = ”0” @ 0x00 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = ”00” @ 0x00 address - RESFILZ = 0 Write Bit [1] = ”0” @ 0x10 address - RSTZ = 1 Write Bit [0] = ”1” @ 0x10 address MASTER OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms 7 6466A–PMAAC–04-Jun-09 6.3 Playback + Playback Amplified Mode This mode corresponds to a data transfer from the i²S interface to the headset and to the power amplifier output connectors. Below is a diagram that shows the data path. Figure 6-3. AT73C240 Playback + Playback Amplified Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 6.3.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Power-On Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = ”11” @ 0x00 address - ONMSTR & PRCHG = 1 Write Bits [1:0] = ”11” @ 0x0C address Wait 500ms I²S ON - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - RESFILZ & RSTZ = 1 Write Bits [1:0] = ”11” @ 0x10 address - PRCHG = 0 Write Bit [1] = ”0” @ 0x0C address Wait 1ms - ONDACL & ONDACR = 1 Write Bits [4:5] = ”11” @ 0x00 address PA ON - APAPRECH = 1 Write Bit [4] = ”1” @ 0x11 address Wait 50ms 8 - APAPRECH = 0 Write Bit [4] = ”0” @ 0x11 address - APAON = 1 Write Bit [5] = ”1” @ 0x11 address Application Note 6466A–PMAAC–04-Jun-09 Application Note Wait 10ms 6.3.2 - APAGAIN = xxdB Write these bits to obtain desired output gain value - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LMPG & RMPG = xxx Write these bits to obtain desired output gain value Power-Off Sequence DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address PA OFF - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 0 Write Bit [6] = ”0” @ 0x00 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = ”00” @ 0x00 address - RESFILZ = 0 Write Bit [1] = ”0” @ 0x10 address - RSTZ = 1 Write Bit [0] = ”1” @ 0x10 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms - ONLNOR & ONLNOL = 0 Write Bits [2:3] = ”00” @ 0x00 address 9 6466A–PMAAC–04-Jun-09 6.4 Bypass Mode This mode corresponds to a data transfer from the line-in input connectors to the headset connector. Below is a diagram that shows the data path. Figure 6-4. AT73C240 Bypass Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 6.4.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Power-On Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = ”11” @ 0x00 address - ONMSTR = 1 Write Bit [0] = ”1” @ 0x0C address Wait 500ms LINE_IN ON 6.4.2 - ONLNIR & ONLNIL = 1 Write Bits [1:0] = ”11” @ 0x00 address - RLIG & LLIG= xxdB Write these bits to obtain desired output gain value - ROLC & LOLC = xxdB Write these bits to obtain desired output gain value Power-Off Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = ”00” @ 0x00 address HEADSET OFF - ONMSTR = 0 10 Write Bit [0] = ”0” @ 0x0C address Application Note 6466A–PMAAC–04-Jun-09 Application Note Wait 500ms - ONLNOR & ONLNOL = 0 Write Bits [2:3] = ”00” @ 0x00 address 11 6466A–PMAAC–04-Jun-09 6.5 Bypass Amplified Mode This mode corresponds to a data transfer from the line-in input connectors to the power amplifier output connector. Below is a diagram that shows the explained path. Figure 6-5. AT73C240 Bypass Amplified Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 6.5.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Power-On Sequence SET GAIN AT MINIMUM - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address MASTER ON - ONMSTR = 1 Write Bits [0] = ”1” @ 0x0C address Wait 500ms LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = ”11” @ 0x00 address PA ON - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address - APAPRECH = 1 Write Bit [4] = ”1” @ 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = ”0” @ 0x11 address - APAON = 1 Write Bit [5] = ”1” @ 0x11 address Wait 10ms 12 Application Note 6466A–PMAAC–04-Jun-09 Application Note 6.5.2 - APAGAIN = xxdB Write these bits to obtain desired output gain value - RLIG & LLIG= xxdB Write these bits to obtain desired output gain value Power-Off Sequence SET GAIN AT MINIMUM - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address PA OFF - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 0 Write Bit [6] = ”0” @ 0x00 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = ”00” @ 0x00 address MASTER OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms 13 6466A–PMAAC–04-Jun-09 6.6 Bypass + Bypass Amplified Mode This mode corresponds to a data transfer from the line-in input connectors to the headset and to the power amplifier output connectors. Below is a diagram that shows the data path. Figure 6-6. AT73C240 Bypass + Bypass Amplified Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 6.6.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Power-On Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = ”11” @ 0x00 address - ONMSTR = 1 Write Bit [0] = ”1” @ 0x0C address Wait 500ms LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = ”11” @ 0x00 address PA ON - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address - APAPRECH = 1 Write Bit [4] = ”1” @ 0x11 address Wait 50ms 14 - APAPRECH = 0 Write Bit [4] = ”0” @ 0x11 address - APAON = 1 Write Bit [5] = ”1” @ 0x11 address Application Note 6466A–PMAAC–04-Jun-09 Application Note Wait 10ms 6.6.2 - APAGAIN = xxdB Write these bits to obtain desired output gain value - RLIG & LLIG= xxdB Write these bits to obtain desired output gain value - ROLC & LOLC = xxdB Write these bits to obtain desired output gain value Power-Off Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address PA OFF - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 0 Write Bit [6] = ”0” @ 0x00 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = ”00” @ 0x00 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms - ONLNOR & ONLNOL = 0 Write Bits [2:3] = ”00” @ 0x00 address 15 6466A–PMAAC–04-Jun-09 7. Switching Modes Sequences 7.1 Playback Mode to Playback Amplified Mode This section shows how to switch from the Playback Mode to Playback Amplified Mode. Below is a diagram that shows the switching modes. Figure 7-1. AT73C240 Playback Mode to Playback Amplified Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 7.1.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Switch Sequence AT73C240 is already starts in Playback Mode as defined in Section 6.1. DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = ”00” @ 0x00 address - RESFILZ = 0 Write Bit [1] = ”0” @ 0x10 address - RSTZ = 1 Write Bit [0] = ”1” @ 0x10 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms - ONLNOR & ONLNOL = 0 Write Bits [2:3] = ”00” @ 0x00 address MASTER ON - ONMSTR & PRCHG = 1 Write Bits [1:0] = ”11” @ 0x0C address Wait 500ms 16 Application Note 6466A–PMAAC–04-Jun-09 Application Note I²S ON - RESFILZ & RSTZ = 1 Write Bits [1:0] = ”11” @ 0x10 address - PRCHG = 0 Write Bit [1] = ”0” @ 0x0C address Wait 1ms - ONDACL & ONDACR = 1 Write Bits [4:5] = ”11” @ 0x00 address PA ON - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAPRECH = 1 Write Bit [4] = ”1” @ 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = ”0” @ 0x11 address - APAON = 1 Write Bit [5] = ”1” @ 0x11 address Wait 10ms - APAGAIN = xxdB Write these bits to obtain desired output gain value - LMPG = xxdB Write these bits to obtain desired output gain value - RMPG = xxdB Write these bits to obtain desired output gain value 17 6466A–PMAAC–04-Jun-09 7.2 Playback Amplified Mode to Playback Mode This section shows how to switch from the Playback Amplified Mode to Playback Mode. Below is a diagram that shows the switching modes. Figure 7-2. AT73C240 Playback Amplified Mode to Playback Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 7.2.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Switch Sequence AT73C240 is already starts in Playback Amplified Mode as defined in Section 6.2. DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x1F @ 0x04 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address PA OFF - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 0 Write Bit [6] = ”0” @ 0x00 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = ”00” @ 0x00 address - RESFILZ = 0 Write Bit [1] = ”0” @ 0x10 address - RSTZ = 1 Write Bit [0] = ”1” @ 0x10 address MASTER OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = ”11” @ 0x00 address - ONMSTR & PRCHG = 1 Write Bits [1:0] = ”11” @ 0x0C address Wait 500ms 18 Application Note 6466A–PMAAC–04-Jun-09 Application Note I²S ON - RESFILZ & RSTZ = 1 Write Bits [1:0] = ”11” @ 0x10 address - PRCHG = 0 Write Bit [1] = ”0” @ 0x0C address Wait 1ms - ONDACL & ONDACR = 1 Write Bits [4:5] = ”11” @ 0x00 address INCREASE GAIN - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LMPG & RMPG = xxx Write these bits to obtain desired output gain value 19 6466A–PMAAC–04-Jun-09 7.3 Bypass Mode to Bypass Amplified Mode This section shows how to switch from the Bypass Mode to Bypass Amplified Mode. Below is a diagram that shows the switching modes. Figure 7-3. AT73C240 Bypass Mode to Bypass Amplified Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 7.3.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Switch Sequence AT73C240 is already starts in Bypass Mode as defined in Section 6.4. SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = ”00” @ 0x00 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms - ONLNOR & ONLNOL = 0 Write Bits [2:3] = ”00” @ 0x00 address MASTER ON - ONMSTR = 1 Write Bits [0] = ”1” @ 0x0C address Wait 500ms LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = ”11” @ 0x00 address PA ON 20 Application Note 6466A–PMAAC–04-Jun-09 Application Note - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAPRECH = 1 Write Bit [4] = ”1” @ 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = ”0” @ 0x11 address - APAON = 1 Write Bit [5] = ”1” @ 0x11 address Wait 10ms - APAGAIN = xxdB Write these bits to obtain desired output gain value - RLIG & LLIG= xxdB Write these bits to obtain desired output gain value 21 6466A–PMAAC–04-Jun-09 7.4 Bypass Amplified Mode to Bypass Mode This section shows how to switch from the Bypass Amplified Mode to Bypass Mode. Below is a diagram that shows the switching modes. Figure 7-4. AT73C240 Bypass Amplified Mode to Bypass Mode Diagram AT73C240 SPI / TWI I2S Interface Stereo Line Input 7.4.1 Stereo Headset Output DAC Mono Output Power Amplifier Output Switch Sequence AT73C240 is already starts in Bypass Amplified Mode as defined in Section 6.5. SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at ”0” @ 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x10 @ 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x10 @ 0x02 address - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 1 Write Bit [6] = ”1” @ 0x00 address - APAGAIN = -22dB Write Bits [3:0] = ”1111” @ 0x11 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = ”00” @ 0x00 address PA OFF - APAON = 0 Write Bit [5] = ”0” @ 0x11 address - ONPADRV = 0 Write Bit [6] = ”0” @ 0x00 address MASTER OFF - ONMSTR = 0 Write Bit [0] = ”0” @ 0x0C address Wait 500ms HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = ”11” @ 0x00 address - ONMSTR = 1 Write Bit [0] = ”1” @ 0x0C address Wait 500ms 22 Application Note 6466A–PMAAC–04-Jun-09 Application Note LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = ”11” @ 0x00 address INCREASE GAIN - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LLIG = xxdB Write these bits to obtain desired output gain value - RLIG = xxdB Write these bits to obtain desired output gain value 23 6466A–PMAAC–04-Jun-09 8. Revision History Doc. Rev Date Comments 6466A 04-JUn-09 Creation 24 Change Request Ref. Application Note 6466A–PMAAC–04-Jun-09 Application Note 25 6466A–PMAAC–04-Jun-09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM www.atmel.com/Iproducts/ASIC Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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