ATmega48PB/88PB/168PB

Atmel AVR 8-bit Microcontroller with 4/8/16KBytes
In-System Programmable Flash
ATmega48PB/88PB/168PB
PRELIMINARY DATASHEET
Features
 High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
 Advanced RISC Architecture
̶
131 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
̶ Fully Static Operation
̶ Up to 20 MIPS Throughput at 20MHz
̶ On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
̶ 4/8/16KBytes of In-System Self-Programmable Flash program memory
̶ 256/512/512Bytes EEPROM
̶ 512/1K/1KBytes Internal SRAM
̶ Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
̶ Data retention: 20 years at 85C/100 years at 25C
̶ Optional Boot Code Section with Independent Lock Bits
 In-System Programming by On-chip Boot Program
 True Read-While-Write Operation
̶ Programming Lock for Software Security
Atmel® QTouch® library support
̶ Capacitive touch buttons, sliders and wheels
̶ QTouch and QMatrix acquisition
̶ Up to 64 sense channels
Peripheral Features
̶ Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
̶ 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
̶ Real Time Counter with Separate Oscillator
̶ Six PWM Channels
̶ 8-channel 10-bit ADC with Temperature Measurement
̶ Programmable Serial USART with Start of Frame Detection
̶ Master/Slave SPI Serial Interface
̶ Byte-oriented 2-wire Serial Interface (Phillips I2C compatible)
̶ Programmable Watchdog Timer with Separate On-chip Oscillator
̶ On-chip Analog Comparator
̶ Interrupt and Wake-up on Pin Change
 256-channel capacitive touch and proximity sensing
Special Microcontroller Features
̶ Power-on Reset and Programmable Brown-out Detection
̶ Internal Calibrated Oscillator
̶ External and Internal Interrupt Sources
̶ Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
̶ Unique Device ID
I/O and Packages
̶ 27 Programmable I/O Lines
̶ 32-lead TQFP and 32-pad VFQFN
Operating Voltage: 1.8 - 5.5V
Temperature Range: -40C to 105C
Speed Grade: 0 - [email protected] - 5.5V, 0 - [email protected] - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25C
̶ Active Mode: 0.35mA
̶ Power-down Mode: 0.4µA
̶ Power-save Mode: <1.0µA (Including 32kHz RTC)
̶









Atmel-42176D–AVR-ATmega48PB-88PB-168PB–04/2015
1.
Configuration Summary
ATmega48PB
ATmega88PB
ATmega168PB
Pin count
32
32
32
Flash (KB)
4
8
16
SRAM (Bytes)
512
1024
1024
EEPROM (Bytes)
256
512
512
Max I/O pins
27
SPI
2
2
TWI (I C)
1
USART
1
ADC
10-bit 15ksps
ADC channels
8
AC
1
8-bit Timer/Counters
2
16-bit Timer/Counters
1
PWM channels
6
OCD “printf()”
No
Clock failure detector
No
Operating voltage
Max operating frequency
Temperature range
1.8V - 5.5V
20MHz
-40°C to +105°C
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Pin Configurations
Figure 2-1.
Pinout ATmega48PB/88PB/168PB
32 TQFP Top View
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
32 VFQFN Top View
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
(ACO) PE0
VCC
GND
PE1
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
PE3 (ADC7)
GND
AREF
PE2 (ADC6)
AVCC
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
2.1
Pin Descriptions
2.1.1
VCC
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
PE3 (ADC7)
GND
AREF
PE2 (ADC6)
AVCC
PB5 (SCK/PCINT5)
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
(ACO) PE0
VCC
GND
PE1
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
NOTE: Bottom pad should be soldered to ground.
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
2.
Digital supply voltage.
2.1.2
GND
Ground.
2.1.3
Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and
input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for the
Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 79 and ”System
Clock and Clock Options” on page 26.
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2.1.4
Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
2.1.5
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6
differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the
minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a Reset.
The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 82.
2.1.6
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 84.
2.1.7
Port E(PE3:0)
Port E is an 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that
are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
The various special features of Port E are elaborated in ”Alternate Functions of Port E” on page 86.
2.1.8
AVCC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and PE3:2. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that
PC6:4 use digital supply voltage, VCC.
2.1.9
AREF
AREF is the analog reference pin for the A/D Converter.
2.1.10 ADC7:6 (TQFP and VFQFN Package Only)
In the TQFP and VFQFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered
from the analog supply and serve as 10-bit ADC channels.
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3.
Overview
The ATmega48PB/88PB/168PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega48PB/88PB/168PB achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus
processing speed.
Block Diagram
Block Diagram
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
VCC
GND
Figure 3-1.
Power
Supervision
POR / BOD &
RESET
debugWIRE
Flash
SRAM
PROGRAM
LOGIC
CPU
EEPROM
AVCC
AREF
GND
DATABUS
3.1
8bit T/C 0
16bit T/C 1
A/D Conv.
8bit T/C 2
Analog
Comp.
Internal
Bandgap
6
TWI
USART 0
SPI
PORT E
PORT D (8)
PORT B (8)
PORT C (7)
PE[0..3]
2
RESET
XTAL[1..2]
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega48PB/88PB/168PB provides the following features: 4/8/16Kbytes of In-System Programmable Flash
with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1Kbytes SRAM, 23 general purpose I/O
lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and
external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface (I2C), an SPI serial port,
a 6-channel 10-bit ADC (8 channels in TQFP and VFQFN packages), a programmable Watchdog Timer with
internal Oscillator, and six software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning.
The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until
the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the
user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the
CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.
This allows very fast start-up combined with low power consumption.
Atmel® offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into
AVR® microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous
detection of key events. The easy-to-use QTouch Composer allows you to explore, develop and debug your own
touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use
any interface to download the application program in the Application Flash memory. Software in the Boot Flash
section will continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the
Atmel ATmega48PB/88PB/168PB is a powerful microcontroller that provides a highly flexible and cost effective
solution to many embedded control applications.
The ATmega48PB/88PB/168PB AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation
kits.
3.2
Comparison Between Processors
The ATmega48PB/88PB/168PB differ only in memory sizes, boot loader support, and interrupt vector sizes. Table
3-1 summarizes the different memory and interrupt vector sizes for the devices.
Table 3-1.
Memory Size Summary
Device
Flash
EEPROM
RAM
Interrupt Vector Size
ATmega48PB
4KBytes
256Bytes
512Bytes
1 instruction word/vector
ATmega88PB
8KBytes
512Bytes
1KBytes
1 instruction word/vector
ATmega168PB
16KBytes
512Bytes
1KBytes
2 instruction words/vector
ATmega88PB/168PB support a real Read-While-Write Self-Programming mechanism. There is a separate Boot
Loader Section, and the SPM instruction can only execute from there. In ATmega48PB there is no Read-WhileWrite support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash
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4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
5.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
6.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
7.
Capacitive Touch Sensing
7.1
QTouch Library
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR® microcontrollers. The library supports both QTouch (self-capacitance) and QMatrix (mutual-capacitance)
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then
calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/tools/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch
Library User Guide - also available for download from Atmel website.
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8.
AVR CPU Core
8.1
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure
correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
Figure 8-1.
Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two
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operands are output from the Register File, the operation is executed, and the result is stored back in the Register
File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before
subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the
Register File, 0x20 - 0x5F. In addition, the ATmega48PB/88PB/168PB has Extended I/O space from 0x60 - 0xFF
in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
8.3
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
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8.3.1
SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
0x3F (0x5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the
interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be
set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the
operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can
be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic.
See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set
Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
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8.4
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the Register File:

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input
Figure 8-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 8-2.
AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of them are
single cycle instructions.
As shown in Figure 8-2, each register is also assigned a data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to
index any register in the file.
8.4.1
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 8-3.
Figure 8-3.
The X-, Y-, and Z-registers
15
X-register
XH
7
XL
0
7
R27 (0x1B)
15
Y-register
R26 (0x1A)
YH
7
YL
0
R29 (0x1D)
0
0
7
0
0
R28 (0x1C)
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Z-register
15
ZH
7
0
ZL
7
0
0
R31 (0x1F)
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic
increment, and automatic decrement (see the instruction set reference for details).
8.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory
locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data
SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease
the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be
set to point above start of the SRAM, see Table 9-3 on page 18.
See Table 8-1 for Stack Pointer details.
Table 8-1.
Stack Pointer instructions
Instruction
Stack pointer
Description
PUSH
Decremented by 1
Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2
Return address is pushed onto the stack with a subroutine call or interrupt
POP
Incremented by 1
Data is popped from the stack
RET
RETI
Incremented by 2
Return address is popped from the stack with return from subroutine or return from
interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
8.5.1
SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit
15
14
13
12
11
10
9
8
0x3E (0x5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D (0x5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
Read/Write
Initial Value
8.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
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Figure 8-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 8-4.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 8-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 8-5.
Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
8.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits
BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory
Programming” on page 283 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in ”Interrupts” on page 55. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash
section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 55 for more
information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 267.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user
software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the
current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is
executed.
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There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by
writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not
necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt
will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in
r16, SREG
; store SREG
value
cli
; disable interrupts during timed
sequence
sbi
EECR, EEMPE
; start
EEPROM write
sbi
EECR, EEPE
out
SREG, r16
; restore
SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;
SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
/* store
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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any
pending interrupts, as shown in this example.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
8.7.1
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
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9.
AVR Memories
9.1
Overview
This section describes the different memories in the ATmega48PB/88PB/168PB. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega48PB/88PB/168PB features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
9.2
In-System Reprogrammable Flash Program Memory
The ATmega48PB/88PB/168PB contains 4/8/16Kbytes On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 2/4/8/16K x 16. For
software security, the Flash Program memory space is divided into two sections, Boot Loader Section and
Application Program Section in ATmega88PB and ATmega168PB. See SPMEN description in section ”SPMCSR –
Store Program Memory Control and Status Register” on page 281 for more details.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega48PB/88PB/168PB
Program Counter (PC) is 11/12/13/14 bits wide, thus addressing the 2/4/8/16K program memory locations. The
operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in
”Self-Programming the Flash, ATmega48PB” on page 259 and ”Boot Loader Support – Read-While-Write SelfProgramming” on page 267. ”Memory Programming” on page 283 contains a detailed description on Flash
Programming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program
Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Timing” on page 12.
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Figure 9-1.
Program Memory Map ATmega48PB
Program Memory
0x0000
Application Flash Section
0x7FF
Figure 9-2.
Program Memory Map ATmega88PB and ATmega168PB ,
Program Memory
0x0000
Application Flash Section
Boot Flash Section
0x0FFF/0x1FFF/0x3FFF
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9.3
SRAM Data Memory
Figure 9-3 shows how the ATmega48PB/88PB/168PB SRAM Memory is organized.
The ATmega48PB/88PB/168PB is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from
0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 768/1280/1280/2303 data memory locations address both the Register File, the I/O memory, Extended
I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the
standard I/O memory, then 160 locations of Extended I/O memory, and the next 512/1024/1024/2048 locations
address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect,
Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the
indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the
512/1024/1024/2048 bytes of internal data SRAM in the ATmega48PB/88PB/168PB are all accessible through all
these addressing modes. The Register File is described in ”General Purpose Register File” on page 11.
Figure 9-3.
Data Memory Map
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
Internal SRAM
(512/1024/1024/2048 x 8)
0x02FF/0x04FF/0x4FF/0x08FF
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9.3.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clkCPU cycles as described in Figure 9-4.
Figure 9-4.
On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Compute Address
Address valid
Write
Data
WR
Read
Data
RD
Memory Access Instruction
9.4
Next Instruction
EEPROM Data Memory
The ATmega48PB/88PB/168PB contains 256/512/512bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following,
specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
”Memory Programming” on page 283 contains a detailed description on EEPROM Programming in SPI or Parallel
Programming mode.
9.4.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 9-2 on page 23. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on
power-up/down. This causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See ”Preventing EEPROM Corruption” on page 20 for details on how to
avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the
description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When
the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
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9.4.2
Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU
and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and
the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute
instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the
needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write
operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
9.5
I/O Memory
The I/O space definition of the ATmega48PB/88PB/168PB is shown in ”Register Summary” on page 362.
All ATmega48PB/88PB/168PB I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed
by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working
registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using
the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and
SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these addresses. The ATmega48PB/88PB/168PB is a complex
microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such
Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
9.5.1
General Purpose I/O Registers
The ATmega48PB/88PB/168PB contains three General Purpose I/O Registers. These registers can be used for
storing any information, and they are particularly useful for storing global variables and Status Flags. General
Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS,
and SBIC instructions.
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9.6
Register Description
9.6.1
EEARH and EEARL – The EEPROM Address Register
Bit
15
14
13
12
11
10
9
8
0x22 (0x42)
–
–
–
–
–
–
EEAR9(1)
EEAR8(1)
EEARH
0x21 (0x41)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7
6
5
4
3
2
1
0
Read/Write
Initial Value
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
• Bits [15:10] – Reserved
These bits are reserved bits in the ATmega48PB/88PB/168PB and will always read as zero.
• Bits 9:0 – EEAR[9:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 256/512/512/1Kbytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255/511/511/1023. The initial
value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
Note:
9.6.2
1.
EEAR9 and EEAR8 are unused bits in ATmega48PB and must always be written to zero.
EEDR – The EEPROM Data Register
Bit
7
0x20 (0x40)
MSB
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
LSB
EEDR
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the
address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from
the EEPROM at the address given by EEAR.
9.6.3
EECR – The EEPROM Control Register
Bit
7
6
5
4
3
2
1
0
0x1F (0x3F)
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
0
0
X
0
EECR
• Bits 7:6 – Reserved
These bits are reserved bits in the ATmega48PB/88PB/168PB and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing
EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to
split the Erase and Write operations in two different operations. The Programming times for the different modes are
shown in Table 9-1 on page 22. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn
bits will be reset to 0b00 unless the EEPROM is busy programming.
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Table 9-1.
EEPROM Mode Bits
EEPM1
EEPM0
Programming Time
Operation
0
0
3.4ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8ms
Erase Only
1
0
1.8ms
Write Only
1
1
–
Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero
disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared. The
interrupt will not be generated during EEPROM write or SPM.
• Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set,
setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero,
setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to
zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Write Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly
set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to
one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure
should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the
Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software
contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the
CPU, step 2 can be omitted. See ”Boot Loader Support – Read-While-Write Self-Programming” on page 267
for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write
Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the
EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to
have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before
the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in
the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read
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access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the
CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither
possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 9-2 lists the typical programming time for
EEPROM access from the CPU.
Table 9-2.
EEPROM Programming Time
Symbol
EEPROM write (from CPU)
Number of Calibrated RC Oscillator Cycles
Typ. Programming Time
26,368
3.3ms
The following code examples show one assembly and one C function for writing to the EEPROM. The examples
assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during
execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If
such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
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Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic
EECR,EEPE
rjmp
EEPROM_write
; Set up address (r18:r17) in address register
out
EEARH, r18
out
EEARL, r17
; Write data (r16) to Data Register
out
EEDR,r16
; Write logical one to EEMPE
sbi
EECR,EEMPE
; Start eeprom write by setting EEPE
sbi
EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that
interrupts are controlled so that no interrupts will occur during execution of these functions.
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Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic
EECR,EEPE
rjmp
EEPROM_read
; Set up address (r18:r17) in address register
out
EEARH, r18
out
EEARL, r17
; Start eeprom read by writing EERE
sbi
EECR,EERE
; Read data from Data Register
in
r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
9.6.4
9.6.5
9.6.6
GPIOR2 – General Purpose I/O Register 2
Bit
7
0x2B (0x4B)
MSB
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
4
3
2
1
LSB
GPIOR2
GPIOR1 – General Purpose I/O Register 1
Bit
7
0x2A (0x4A)
MSB
6
5
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
4
3
2
1
LSB
GPIOR1
GPIOR0 – General Purpose I/O Register 0
Bit
7
0x1E (0x3E)
MSB
6
5
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
LSB
GPIOR0
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10.
System Clock and Clock Options
10.1
Clock Systems and their Distribution
Figure 10-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted
by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 37. The clock
systems are detailed below.
Figure 10-1.
Clock Distribution
Asynchronous
Timer/Counter
General I/O
Modules
ADC
CPU Core
RAM
Flash and
EEPROM
clkADC
clkI/O
AVR Clock
Control Unit
clkASY
clkFLASH
System Clock
Prescaler
Source clock
Clock
Multiplexer
Timer/Counter
Oscillator
External Clock
clkCPU
Crystal
Oscillator
Reset Logic
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
10.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such
modules are the General Purpose Register File, the Status Register and the data memory holding the Stack
Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
10.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is
also used by the External Interrupt module, but note that start condition detection in the USI module is carried out
asynchronously when clkI/O is halted, TWI address recognition in all sleep modes.
Note:
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the
Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT
and CKSEL Fuses as described in ”System Clock and Clock Options” on page 26.
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10.1.3 Flash Clock – clkFLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the
CPU clock.
10.1.4 Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external
clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a realtime counter even when the device is in sleep mode.
10.1.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce
noise generated by digital circuitry. This gives more accurate ADC conversion results.
10.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from
the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 10-1.
Device Clocking Options Select(1)
Device Clocking Option
CKSEL3...0
Low Power Crystal Oscillator
1111 - 1000
Full Swing Crystal Oscillator
0111 - 0110
Low Frequency Crystal Oscillator
0101 - 0100
Internal 128kHz RC Oscillator
0011
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0001
Note:
1.
For all fuses “1” means unprogrammed while “0” means programmed.
10.2.1 Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in
1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT =
"10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting using
any available programming interface.
10.2.2 Clock Startup Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it
can be considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is
released by all other reset sources. ”System Control and Reset” on page 45 describes the start conditions for the
internal reset. The delay (tTOUT) is timed from the Watchdog Oscillator and the number of cycles in the delay is set
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by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 10-2. The frequency of the
Watchdog Oscillator is voltage dependent as shown in ”Register Summary” on page 362.
Table 10-2.
Number of Watchdog Oscillator Cycles
Typ. Time-out (VCC = 5.0V)
Typ. Time-out (VCC = 3.0V)
Number of Cycles
0ms
0ms
0
4.1ms
4.3ms
512
65ms
69ms
8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not
monitor the actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not
possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient
VCC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without
utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An
internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of
clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up
time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low
frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts
up from reset. When starting up from Power-save or Power-down mode, VCC is assumed to be at a sufficient level
and only the start-up time is included.
10.3
Low Power Crystal Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use
as an On-chip Oscillator, as shown in Figure 10-2. Either a quartz crystal or a ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the
lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise
in noisy environments. In these cases, refer to the ”Full Swing Crystal Oscillator” on page 29.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends
on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the
environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 10-3. For
ceramic resonators, the capacitor values given by the manufacturer should be used.
Figure 10-2.
Crystal Oscillator Connections
C2
C1
XTAL2 (TOSC2)
XTAL1 (TOSC1)
GND
The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The
operating mode is selected by the fuses CKSEL3...1 as shown in Table 10-3.
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Table 10-3.
Notes:
Low Power Crystal Oscillator Operating Modes(3)
Frequency Range
[MHz]
Recommended Range for
Capacitors C1 and C2 [pF]
CKSEL3...1(1)
0.4 - 0.9
–
100(2)
0.9 - 3.0
12 - 22
101
3.0 - 8.0
12 - 22
110
8.0 - 16.0
12 - 22
111
1.
2.
3.
This is the recommended CKSEL settings for the difference frequency ranges.
This option should not be used with crystals, only with ceramic resonators.
If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be
programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock
meets the frequency specification of the device.
The CKSEL0 Fuse together with the SUT1...0 Fuses select the start-up times as shown in Table 10-4.
Table 10-4.
Start-up Times for the Low Power Crystal Oscillator Clock Selection
Oscillator Source / Power Conditions
Additional Delay from
Reset
(VCC = 5.0V)
CKSEL0
SUT1...0
(1)
0
00
0
01
Ceramic resonator, fast rising power
258 CK
19CK + 4.1ms
Ceramic resonator, slowly rising power
258 CK
19CK + 65ms(1)
Ceramic resonator, BOD enabled
Ceramic resonator, fast rising power
1K CK
1K CK
19CK
(2)
0
10
(2)
0
11
(2)
1
00
19CK + 4.1ms
Ceramic resonator, slowly rising power
1K CK
Crystal Oscillator, BOD enabled
16K CK
19CK
1
01
Crystal Oscillator, fast rising power
16K CK
19CK + 4.1ms
1
10
Crystal Oscillator, slowly rising power
16K CK
19CK + 65ms
1
11
Notes:
1.
2.
10.4
Start-up Time from
Power-down and Powersave
19CK + 65ms
These options should only be used when not operating close to the maximum frequency of the device, and only if
frequency stability at start-up is not important for the application. These options are not suitable for crystals.
These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They
can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency
stability at start-up is not important for the application.
Full Swing Crystal Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use
as an On-chip Oscillator, as shown in Figure 10-2 on page 28. Either a quartz crystal or a ceramic resonator may
be used.
This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving
other clock inputs and in noisy environments. The current consumption is higher than the ”Low Power Crystal
Oscillator” on page 28. Note that the Full Swing Crystal Oscillator will only operate for VCC = 2.7 - 5.5V.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends
on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the
environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 10-6 on page
30. For ceramic resonators, the capacitor values given by the manufacturer should be used.
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The operating mode is selected by the fuses CKSEL3...1 as shown in Table 10-5.
Table 10-5.
Full Swing Crystal Oscillator operating modes
Frequency Range(1) [MHz]
Recommended Range for Capacitors C1 and C2 [pF]
0.4 - 20
Notes:
1.
Figure 10-3.
CKSEL3...1
12 - 22
011
If the crystal frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be
programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock
meets the frequency specification of the device.
Crystal Oscillator Connections
C2
XTAL2 (TOSC2)
C1
XTAL1 (TOSC1)
GND
Table 10-6.
Start-up Times for the Full Swing Crystal Oscillator Clock Selection
Oscillator Source / Power Conditions
Ceramic resonator, fast rising power
Start-up Time from
Power-down and
Power-save
258 CK
Ceramic resonator, slowly rising power
258 CK
Ceramic resonator, BOD enabled
1K CK
Ceramic resonator, fast rising power
1K CK
Additional Delay from
Reset
(VCC = 5.0V)
CKSEL0
SUT1...0
(1)
0
00
(1)
0
01
19CK + 4.1ms
19CK + 65ms
19CK(2)
0
10
(2)
0
11
(2)
1
00
19CK + 4.1ms
Ceramic resonator, slowly rising power
1K CK
Crystal Oscillator, BOD enabled
16K CK
19CK
1
01
Crystal Oscillator, fast rising power
16K CK
19CK + 4.1ms
1
10
Crystal Oscillator, slowly rising power
16K CK
19CK + 65ms
1
11
Notes:
1.
2.
19CK + 65ms
These options should only be used when not operating close to the maximum frequency of the device, and only if
frequency stability at start-up is not important for the application. These options are not suitable for crystals.
These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They
can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency
stability at start-up is not important for the application.
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10.5
Low Frequency Crystal Oscillator
The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals,
load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values
are specified by the crystal vendor. ATmega48PB/88PB/168PB oscillator is optimized for very low power
consumption, and thus when selecting crystals, see Table 10-7 for maximum ESR recommendations on 6.5pF,
9.0pF and 12.5pF crystals
Table 10-7.
Note:
Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL [pF]
Max. ESR [k](1)
6.5
75
9.0
65
12.5
30
1. Maximum ESR is typical value based on characterization
The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 10-8 at each TOSC pin.
Table 10-8.
Capacitance for Low-frequency Oscillator
Device
32kHz Osc. Type
Cap. (Xtal1/Tosc1)
Cap. (Xtal2/Tosc2)
System Osc.
18pF
8pF
Timer Osc.
18pF
8pF
ATmega48PB/88PB/168PB
The capacitance (Ce+Ci) needed at each TOSC pin can be calculated by using:
C = 2  CL – C s
where:
•
Ce - is optional external capacitors as described in Figure 10-2 on page 28
•
Ci - is the pin capacitance in Table 10-8
•
CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor
•
CS - is the total stray capacitance for one TOSC pin.
Crystals specifying load capacitance (CL) higher than 6 pF, require external capacitors applied as described in
Figure 10-2 on page 28.
The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111”, as shown
in Table 10-10 on page 31. Start-up times are determined by the SUT Fuses as shown in Table 10-9.
Table 10-9.
Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
SUT1...0
Additional Delay from Reset (VCC = 5.0V)
Recommended Usage
00
19CK
01
19CK + 4.1ms
Slowly rising power
10
19CK + 65ms
Stable frequency at start-up
Fast rising power or BOD enabled
11
Reserved
Table 10-10.
CKSEL3...0
(1)
0100
0101
Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time from
Power-down and Power-save
Recommended Usage
1K CK
32K CK
Stable frequency at start-up
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Note:
10.6
1.
This option should only be used if frequency stability at start-up is not important for the application.
Calibrated Internal RC Oscillator
By default, the Internal RC Oscillator provides an approximate 8.0MHz clock. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. See Table 30-4 on page 305 for more details.
The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 34 for more
details.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 10-11. If
selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration
value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator.
By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on page 35, it is
possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is
shown as User calibration in Table 30-4 on page 305.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer
and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section
”Calibration Byte” on page 286.
Table 10-11.
Notes:
1.
2.
Internal Calibrated RC Oscillator Operating Modes
Frequency Range(2) [MHz]
CKSEL3...0
7.3 - 8.1
0010(1)
The device is shipped with this option selected.
If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be
programmed in order to divide the internal frequency by 8.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10-12.
Table 10-12.
Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions
Start-up Time from Power-down and
Power-save
Additional Delay from Reset
(VCC = 5.0V)
19CK
SUT1...0
(1)
BOD enabled
6 CK
00
Fast rising power
6 CK
19CK + 4.1ms
01
Slowly rising power
6 CK
19CK + 65ms(2)
10
Reserved
Note:
1.
2.
10.7
11
If the RSTDISBL fuse is programmed, this start-up time will be increased to
19CK + 4.1ms to ensure programming mode can be entered.
The device is shipped with this option selected.
128kHz Internal Oscillator
The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The frequency is nominal at
3V and 25C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in
Table 10-13.
Table 10-13.
Note:
1.
128kHz Internal Oscillator Operating Modes
Nominal Frequency(1)
CKSEL3...0
128kHz
0011
Note that the 128kHz oscillator is a very low power clock source, and is not designed for high accuracy.
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When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10-14.
Table 10-14.
Start-up Times for the 128kHz Internal Oscillator
Power Conditions
Start-up Time from Power-down and
Power-save
Additional Delay from Reset
19CK
SUT1...0
(1)
BOD enabled
6 CK
00
Fast rising power
6 CK
19CK + 4ms
01
Slowly rising power
6 CK
19CK + 64ms
10
Reserved
Note:
10.8
1.
11
If the RSTDISBL fuse is programmed, this start-up time will be increased to
19CK + 4.1ms to ensure programming mode can be entered.
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 10-4. To run the
device on an external clock, the CKSEL Fuses must be programmed to “0000” (see Table 10-15).
Table 10-15.
Figure 10-4.
Crystal Oscillator Clock Frequency
Frequency
CKSEL3...0
0 - 20MHz
0000
External Clock Drive Configuration
PB7
XTAL2
EXTERNAL
CLOCK
SIGNAL
XTAL1
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10-16 on
page 33.
Table 10-16.
Start-up Times for the External Clock Selection
Start-up Time from Power-down and
Power-save
Additional Delay from Reset
(VCC = 5.0V)
SUT1...0
BOD enabled
6 CK
19CK
00
Fast rising power
6 CK
19CK + 4.1ms
01
Slowly rising power
6 CK
19CK + 65ms
10
Power Conditions
Reserved
11
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure
stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the
changes.
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Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation. Refer to ”System Clock Prescaler” on page 34 for details.
10.9
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be
programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock
also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is
programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on
CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.
10.10 Timer/Counter Oscillator
ATmega48PB/88PB/168PB uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter
Oscillator. See ”Low Frequency Crystal Oscillator” on page 31 for details on the oscillator and crystal requirements.
ATmega48PB/88PB/168PB share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and
XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency.
Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal RC
Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one.
See ”Asynchronous Operation of Timer/Counter2” on page 148 for further description on selecting external clock
as input instead of a 32.768kHz watch crystal.
10.11 System Clock Prescaler
The ATmega48PB/88PB/168PB has a system clock prescaler, and the system clock can be divided by setting the
”CLKPR – Clock Prescale Register” on page 35. This feature can be used to decrease the system clock frequency
and the power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC,
clkCPU, and clkFLASH are divided by a factor as shown in Table 10-17 on page 36.
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the
clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency
corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter
that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's
clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the
exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the
CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In
this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period
corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the
CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
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10.12 Register Description
10.12.1 OSCCAL – Oscillator Calibration Register
Bit
7
6
5
4
3
2
1
0
(0x66)
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OSCCAL
Device Specific Calibration Value
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process
variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register
during chip reset, giving the Factory calibrated frequency as specified in Table 30-4 on page 305. The application
software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies
as specified in Table 30-4 on page 305. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected
accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM
or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6...0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest
frequency in that range, and a setting of 0x7F gives the highest frequency in the range.
10.12.2 CLKPR – Clock Prescale Register
Bit
7
6
5
4
3
2
1
0
(0x61)
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
CLKPR
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated
when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after
it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither
extend the time-out period, nor clear the CLKPCE bit.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the
master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
The division factors are given in Table 10-17 on page 36.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will
be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start
up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency
of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless
of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the
selected clock source has a higher frequency than the maximum frequency of the device at the present operating
conditions. The device is shipped with the CKDIV8 Fuse programmed.
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Table 10-17.
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0
1
0
1
32
0
1
1
0
64
0
1
1
1
128
1
0
0
0
256
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
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11.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR
provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods.
To further save power, it is possible to disable the BOD in some sleep modes. See ”BOD Disable(1)” on page 38
for more details.
11.1
Sleep Modes
Figure 10-1 on page 26 presents the different clock systems in the ATmega48PB/88PB/168PB, and their
distribution. The figure is helpful in selecting an appropriate sleep mode. Table 11-1 shows the different sleep
modes, their wake up sources BOD disable ability.(1)
Note:
1. BOD disable is available for ATmega48PB/88PB/168PB.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
clkASY
Main Clock
Source Enabled
Timer Oscillator
Enabled
INT1, INT0 and
Pin Change
TWI Address
Match
Timer2
SPM/EEPROM
Ready
ADC
WDT
USART(4)
Other I/O
X
X
X
X
X(2)
X
X
X
X
X
X
X
X
X
X
X
X(2)
X(3)
X
X(2)
X
X
X
X
X(3)
X
X
X
X
(3)
X
X
X
X
(3)
X
X
X
X
X
X(3)
X
X
X
X
Power-down
Power-save
Standby
Notes:
1.
2.
3.
4.
(2)
X
(1)
Extended
Standby
Wake-up Sources
clkADC
ADC Noise
Reduction
Oscillators
clkIO
Idle
clkFLASH
Sleep Mode
clkCPU
Active Clock Domains
X
X
X(2)
X
X(2)
X
X
X
Only recommended with external crystal or resonator selected as clock source.
If Timer/Counter2 is running in asynchronous mode.
For INT1 and INT0, only level interrupt.
Start frame detection, only.
To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must
be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise
Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.
See Table 11-2 on page 42 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up
from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
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Software
BOD Disable
Table 11-1.
11.2
BOD Disable(1)
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see Table 29-6 on page 285 and onwards,
the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to
disable the BOD by software for some of the sleep modes, see Table 11-1 on page 37. The sleep mode power
consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in
software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep,
BOD is automatically enabled again. This ensures safe operation in case the VCC level has dropped during the
sleep period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 µs to ensure that
the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see ”MCUCR – MCU
Control Register” on page 43. Writing this bit to one turns off the BOD in relevant sleep modes, while a zero in this
bit keeps BOD active. Default setting keeps BOD active, i.e. BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR – MCU Control
Register” on page 43.
11.3
Idle Mode
When the SM2...0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the
CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog,
and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing
the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control
and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a
conversion starts automatically when this mode is entered.
11.4
ADC Noise Reduction Mode
When the SM2...0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction
mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial Interface address watch,
Timer/Counter2(1), and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O,
clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete
interrupt, only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire
Serial Interface address match, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level
interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
Note:
11.5
1. Timer/Counter2 will only keep running in asynchronous mode, see ”8-bit Timer/Counter2 with PWM and Asynchronous Operation” on page 137 for details.
Power-down Mode
When the SM2...0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this
mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface address watch,
and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, an external level interrupt on
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INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated
clocks, allowing operation of asynchronous modules only.
Note:
If a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the
MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time,
the MCU will still wake up, but no interrupt will be generated. ”External Interrupts” on page 67. The start-up time is
defined by the SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 26.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ”Clock
Sources” on page 27.
11.6
Power-save Mode
When the SM2...0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow
or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the Global Interrupt Enable bit in SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If
Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If
Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the
synchronous clock is running in Power-save, this clock is only available for Timer/Counter2.
11.7
Standby Mode
When the SM2...0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is
kept running. From Standby mode, the device wakes up in six clock cycles.
11.8
Extended Standby Mode
When the SM2...0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Extended Standby mode. This mode is identical to Power-save with the exception that the
Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles.
11.9
Power Reduction Register
The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 43, provides a method to
stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen
and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will
remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a
module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power
consumption. In all other sleep modes, the clock is already stopped.
11.10 Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled
system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so
that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In
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particular, the following modules may need special consideration when trying to achieve the lowest possible power
consumption.
11.10.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering
any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
Refer to ”Analog-to-Digital Converter” on page 240 for details on ADC operation.
11.10.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is
automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will
be enabled, independent of sleep mode. Refer to ”Analog Comparator” on page 236 for details on how to configure
the Analog Comparator.
11.10.3 Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out
Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to
”Brown-out Detection” on page 47 for details on how to configure the Brown-out Detector.
11.10.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator
or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be
disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to
”Internal Voltage Reference” on page 48 for details on the start-up time.
11.10.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 49 for details on
how to configure the Watchdog Timer.
11.10.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock
(clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it
will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 76 for details on which
pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level
close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on
page 239 and ”DIDR0 – Digital Input Disable Register 0” on page 255 for details.
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11.10.7 On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source
is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the
total current consumption.
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11.11 Register Description
11.11.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bit
7
6
5
4
3
2
1
0
0x33 (0x53)
–
–
–
–
SM2
SM1
SM0
SE
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SMCR
• Bits [7:4]: Reserved
These bits are unused in the ATmega48PB/88PB/168PB, and will always be read as zero.
• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 11-2.
Table 11-2.
Note:
Sleep Mode Select
SM2
SM1
SM0
0
0
0
Idle
0
0
1
ADC Noise Reduction
0
1
0
Power-down
0
1
1
Power-save
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Standby(1)
1
1
1
External Standby(1)
1.
Sleep Mode
Standby mode is only recommended for use with external crystals or resonators.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is
executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
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11.11.2 MCUCR – MCU Control Register
Bit
7
6
5
4
3
2
1
0
0x35 (0x55)
–
BODS
BODSE
PUD
–
–
IVSEL
IVCE
Read/Write
R
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 11-1 on page 37.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable BOD
in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must
be set to one and BODSE must be set to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active
in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock
cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a
timed sequence.
11.11.3 PRR – Power Reduction Register
Bit
7
6
5
4
3
2
1
0
(0x64)
PRTWI
PRTIM2
PRTIM0
–
PRTIM1
PRSPI
PRUSART0
PRADC
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PRR
• Bit 7 – PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI
again, the TWI should be re initialized to ensure proper operation.
• Bit 6 – PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the
Timer/Counter2 is enabled, operation will continue like before the shutdown.
• Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled,
operation will continue like before the shutdown.
• Bit 4 – Reserved
This bit is reserved in ATmega48PB/88PB/168PB and will always read as zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled,
operation will continue like before the shutdown.
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• Bit 2 – PRSPI: Power Reduction Serial Peripheral Interface
If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit
shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the
SPI should be re initialized to ensure proper operation.
• Bit 1 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the
USART again, the USART should be re initialized to ensure proper operation.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog
comparator cannot use the ADC input MUX when the ADC is shut down.
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12.
System Control and Reset
12.1
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset
Vector. For ATmega168PB the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction
to the reset handling routine. For the ATmega48PB and ATmega88PB, the instruction placed at the Reset Vector
must be an RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an
interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot
section or vice versa (ATmega88PB/168PB only). The circuit diagram in Figure 12-1 on page 46 shows the reset
logic.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not
require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the
power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by
the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in ”Clock
Sources” on page 27.
12.2
Reset Sources
The ATmega48PB/88PB/168PB has four sources of reset:
•
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).
•
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum
pulse length.
•
Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog
System Reset mode is enabled.
•
Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold
(VBOT) and the Brown-out Detector is enabled.
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Figure 12-1.
Reset Logic
DATA BUS
PORF
BORF
EXTRF
WDRF
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
RSTDISBL
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL[3:0]
SUT[1:0]
12.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated whenever VCC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure
in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise.
The RESET signal is activated again, without any delay, when VCC decreases below the detection level.
Figure 12-2.
MCU Start-up, RESET Tied to VCC
VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
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Figure 12-3.
MCU Start-up, RESET Extended Externally
VCC
VPOT
RESET
TIME-OUT
VRST
tTOUT
INTERNAL
RESET
12.4
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse
width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter
starts the MCU after the Time-out period – tTOUT – has expired. The External Reset can be disabled by the
RSTDISBL fuse, see Table 29-6 on page 285.
Figure 12-4.
External Reset During Operation
CC
12.5
Brown-out Detection
ATmega48PB/88PB/168PB has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during
operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL
Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection
level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.When the BOD is enabled, and
VCC decreases to a value below the trigger level (VBOT- in Figure 12-5 on page 48), the Brown-out Reset is
immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 12-5 on page 48), the delay
counter starts the MCU after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD.
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Figure 12-5.
Brown-out Reset During Operation
VCC
VBOT-
VBOT+
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
12.6
Watchdog System Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of
this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to ”Watchdog Timer” on page 49 for
details on operation of the Watchdog Timer.
Figure 12-6.
Watchdog System Reset During Operation
CC
CK
12.7
Internal Voltage Reference
ATmega48PB/88PB/168PB features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
12.7.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. To save power, the
reference is not always turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2.
When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power
consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is
turned off before entering Power-down mode.
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12.8
Watchdog Timer
12.8.1 Features

Clocked from separate On-chip Oscillator

Three operating modes:
̶ Interrupt
̶ System Reset
̶ Interrupt and System Reset

Selectable Time-out period from 16ms to 8s

Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
12.8.2 Overview
ATmega48PB/88PB/168PB has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a
separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a
given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer
Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the
counter, an interrupt or system reset will be issued.
Watchdog Timer
128kHz
OSCILLATOR
WATCHDOG
RESET
WDE
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
Figure 12-7.
WDP0
WDP1
WDP2
WDP3
MCU RESET
WDIF
WDIE
INTERRUPT
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the
device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed
for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode,
the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway
code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt
and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical
parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode.
With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0
respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences.
The sequence for clearing WDE and changing time-out configuration is as follows:
1.
In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one
must be written to WDE regardless of the previous value of the WDE bit.
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2.
Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the
WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The
example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur
during the execution of these functions.
Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in
r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out
MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional
time-out
lds r16, WDTCSR
ori
r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi
r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional
time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note:
1.
See ”About Code Examples” on page 7.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device
will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might
lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is
not in use.
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The following code example shows one assembly and one C function for changing the time-out value of the
Watchdog Timer.
Assembly Code Example(1)
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCSR
ori
r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here ; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi
r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles ; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed sequence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5
s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Note:
1.
See ”About Code Examples” on page 7.
Note:
The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in
a time-out when switching to a shorter time-out period.
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12.9
Register Description
12.9.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
0x34 (0x54)
–
–
–
–
WDRF
BORF
EXTRF
PORF
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
MCUSR
See Bit Description
• Bit 7:4: Reserved
These bits are unused bits in the ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as
early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can
be found by examining the Reset Flags.
12.9.2 WDTCSR – Watchdog Timer Control Register
Bit
7
6
5
4
3
2
1
0
(0x60)
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
X
0
0
0
WDTCSR
• Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out
Interrupt is executed.
• Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE
is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding
interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt
and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding
interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode).
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This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System
Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service
routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is
not executed before the next time-out, a System Reset will be applied.
Table 12-1.
Watchdog Timer Configuration
WDTON(1)
WDE
WDIE
1
0
1
Mode
Action on Time-out
0
Stopped
None
0
1
Interrupt Mode
Interrupt
1
1
0
System Reset Mode
Reset
1
1
1
Interrupt and System Reset Mode
Interrupt, then go to System Reset Mode
0
x
x
System Reset Mode
Reset
Note:
1.
WDTON Fuse set to “0” means programmed and “1” means unprogrammed.
• Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the
prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE,
WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe
start-up after the failure.
• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different
prescaling values and their corresponding time-out periods are shown in Table 12-2.
Table 12-2.
Watchdog Timer Prescale Select
WDP3
WDP2
WDP1
WDP0
Number of WDT Oscillator Cycles
Typical Time-out at VCC = 5.0V
0
0
0
0
2K (2048) cycles
16ms
0
0
0
1
4K (4096) cycles
32ms
0
0
1
0
8K (8192) cycles
64ms
0
0
1
1
16K (16384) cycles
0.125s
0
1
0
0
32K (32768) cycles
0.25s
0
1
0
1
64K (65536) cycles
0.5s
0
1
1
0
128K (131072) cycles
1.0s
0
1
1
1
256K (262144) cycles
2.0s
1
0
0
0
512K (524288) cycles
4.0s
1
0
0
1
1024K (1048576) cycles
8.0s
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Table 12-2.
Watchdog Timer Prescale Select (Continued)
WDP3
WDP2
WDP1
WDP0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Number of WDT Oscillator Cycles
Typical Time-out at VCC = 5.0V
Reserved
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13.
Interrupts
This section describes the specifics of the interrupt handling as performed in ATmega48PB/88PB/168PB. For a
general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 13.
The interrupt vectors in ATmega48PB, ATmega88PB and ATmega168PB are generally the same, with the
following differences:
13.1
•
Each Interrupt Vector occupies two instruction words in ATmega168PB; and one instruction word in
ATmega48PB and ATmega88PB
•
ATmega48PB does not have a separate Boot Loader Section. In ATmega88PB and ATmega168PB the
Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the
IVSEL bit in MCUCR
Interrupt Vectors in ATmega48PB
Table 13-1.
Reset and Interrupt Vectors in ATmega48PB
Vector No.
Program Address
Source
Interrupt Definition
1
0x000
RESET
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
2
0x001
INT0
External Interrupt Request 0
3
0x002
INT1
External Interrupt Request 1
4
0x003
PCINT0
Pin Change Interrupt Request 0
5
0x004
PCINT1
Pin Change Interrupt Request 1
6
0x005
PCINT2
Pin Change Interrupt Request 2
7
0x006
WDT
Watchdog Time-out Interrupt
8
0x007
TIMER2 COMPA
Timer/Counter2 Compare Match A
9
0x008
TIMER2 COMPB
Timer/Counter2 Compare Match B
10
0x009
TIMER2 OVF
Timer/Counter2 Overflow
11
0x00A
TIMER1 CAPT
Timer/Counter1 Capture Event
12
0x00B
TIMER1 COMPA
Timer/Counter1 Compare Match A
13
0x00C
TIMER1 COMPB
Timer/Coutner1 Compare Match B
14
0x00D
TIMER1 OVF
Timer/Counter1 Overflow
15
0x00E
TIMER0 COMPA
Timer/Counter0 Compare Match A
16
0x00F
TIMER0 COMPB
Timer/Counter0 Compare Match B
17
0x010
TIMER0 OVF
Timer/Counter0 Overflow
18
0x011
SPI, STC
SPI Serial Transfer Complete
19
0x012
USART, RX
USART Rx Complete
20
0x013
USART, UDRE
USART, Data Register Empty
21
0x014
USART, TX
USART, Tx Complete
22
0x015
ADC
ADC Conversion Complete
23
0x016
EE READY
EEPROM Ready
24
0x017
ANALOG COMP
Analog Comparator
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Table 13-1.
Reset and Interrupt Vectors in ATmega48PB (Continued)
Vector No.
Program Address
Source
Interrupt Definition
25
0x018
TWI
2-wire Serial Interface (I2C)
26
0x019
SPM READY
Store Program Memory Ready
27
0x01A
USART, START
USART Start Edge Interrupt
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega48PB is:
Address
0x000
0x001
0x002
0x003
0x004
0x005
0x006
Handler
0x007
Compare A Handler
0x008
Compare B Handler
0x009
Overflow Handler
0x00A
Capture Handler
0x00B
Compare A Handler
0x00C
Compare B Handler
0x00D
Overflow Handler
0x00E
Compare A Handler
0x00F
Compare B Handler
0x010
Overflow Handler
0x011
Complete Handler
0x012
Complete Handler
0x013
Empty Handler
0x014
Complete Handler
0x015
Complete Handler
0x016
Handler
0x017
Comparator Handler
0x018
Interface Handler
Labels
CodeComments
rjmpRESET; Reset Handler
rjmpEXT_INT0; IRQ0 Handler
rjmpEXT_INT1; IRQ1 Handler
rjmpPCINT0; PCINT0 Handler
rjmpPCINT1; PCINT1 Handler
rjmpPCINT2; PCINT2 Handler
rjmpWDT; Watchdog Timer
rjmpTIM2_COMPA; Timer2
rjmpTIM2_COMPB; Timer2
rjmpTIM2_OVF; Timer2
rjmpTIM1_CAPT; Timer1
rjmpTIM1_COMPA; Timer1
rjmpTIM1_COMPB; Timer1
rjmpTIM1_OVF; Timer1
rjmpTIM0_COMPA; Timer0
rjmpTIM0_COMPB; Timer0
rjmpTIM0_OVF; Timer0
rjmpSPI_STC; SPI Transfer
rjmpUSART_RXC; USART, RX
rjmpUSART_UDRE; USART, UDR
rjmpUSART_TXC; USART, TX
rjmpADC; ADC Conversion
rjmpEE_RDY; EEPROM Ready
rjmpANA_COMP; Analog
rjmpTWI; 2-wire Serial
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0x019
Memory Ready Handler
;
0x01A
RESET:
program start
0x01B
Pointer to top of RAM
0x01C
0x01D
0x01E
0x01F
...
13.2
rjmpSPM_RDY; Store Program
ldir16, high(RAMEND); Main
out SPH,r16; Set Stack
ldi r16, low(RAMEND)
out SPL,r16
sei; Enable interrupts
<instr> xxx
... ...
...
Interrupt Vectors in ATmega88PB
Table 13-2.
Vector No.
1
Reset and Interrupt Vectors in ATmega88PB
Program
Address(2)
0x000
(1)
Source
Interrupt Definition
RESET
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
2
0x001
INT0
External Interrupt Request 0
3
0x002
INT1
External Interrupt Request 1
4
0x003
PCINT0
Pin Change Interrupt Request 0
5
0x004
PCINT1
Pin Change Interrupt Request 1
6
0x005
PCINT2
Pin Change Interrupt Request 2
7
0x006
WDT
Watchdog Time-out Interrupt
8
0x007
TIMER2 COMPA
Timer/Counter2 Compare Match A
9
0x008
TIMER2 COMPB
Timer/Counter2 Compare Match B
10
0x009
TIMER2 OVF
Timer/Counter2 Overflow
11
0x00A
TIMER1 CAPT
Timer/Counter1 Capture Event
12
0x00B
TIMER1 COMPA
Timer/Counter1 Compare Match A
13
0x00C
TIMER1 COMPB
Timer/Coutner1 Compare Match B
14
0x00D
TIMER1 OVF
Timer/Counter1 Overflow
15
0x00E
TIMER0 COMPA
Timer/Counter0 Compare Match A
16
0x00F
TIMER0 COMPB
Timer/Counter0 Compare Match B
17
0x010
TIMER0 OVF
Timer/Counter0 Overflow
18
0x011
SPI, STC
SPI Serial Transfer Complete
19
0x012
USART, RX
USART Rx Complete
20
0x013
USART, UDRE
USART, Data Register Empty
21
0x014
USART, TX
USART, Tx Complete
22
0x015
ADC
ADC Conversion Complete
23
0x016
EE READY
EEPROM Ready
24
0x017
ANALOG COMP
Analog Comparator
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Reset and Interrupt Vectors in ATmega88PB (Continued)
Table 13-2.
Vector No.
Program
Address(2)
25
Source
Interrupt Definition
0x018
TWI
2-wire Serial Interface (I2C)
26
0x019
SPM READY
Store Program Memory Ready
27
0x01A
USART, START
USART Start Edge Interrupt
Notes:
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader
Support – Read-While-Write Self-Programming” on page 267.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of
each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.
Table 13-3 on page 58 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
regular program code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa.
Table 13-3.
Reset and Interrupt Vectors Placement in ATmega88PB(1)
BOOTRST
IVSEL
1
Note:
Reset Address
Interrupt Vectors Start Address
0
0x000
0x001
1
1
0x000
Boot Reset Address + 0x001
0
0
Boot Reset Address
0x001
0
1
Boot Reset Address
Boot Reset Address + 0x001
1.
The Boot Reset Address is shown in Table 28-7 on page 279. For the BOOTRST Fuse “1” means unprogrammed
while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88PB is:
Address
0x000
0x001
0x002
0x003
0x004
0x005
0x006
Handler
0x007
Compare A Handler
0X008
Compare B Handler
0x009
Overflow Handler
0x00A
Capture Handler
0x00B
Compare A Handler
0x00C
Compare B Handler
0x00D
Overflow Handler
Labels
CodeComments
rjmpRESET; Reset Handler
rjmpEXT_INT0; IRQ0 Handler
rjmpEXT_INT1; IRQ1 Handler
rjmpPCINT0; PCINT0 Handler
rjmpPCINT1; PCINT1 Handler
rjmpPCINT2; PCINT2 Handler
rjmpWDT; Watchdog Timer
rjmpTIM2_COMPA; Timer2
rjmpTIM2_COMPB; Timer2
rjmpTIM2_OVF; Timer2
rjmpTIM1_CAPT; Timer1
rjmpTIM1_COMPA; Timer1
rjmpTIM1_COMPB; Timer1
rjmpTIM1_OVF; Timer1
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0x00E
Compare A Handler
0x00F
Compare B Handler
0x010
Overflow Handler
0x011
Complete Handler
0x012
Complete Handler
0x013
Empty Handler
0x014
Complete Handler
0x015
Complete Handler
0x016
Handler
0x017
Comparator Handler
0x018
Interface Handler
0x019
Memory Ready Handler
;
0x01A
RESET:
program start
0x01B
Pointer to top of RAM
0x01C
0x01D
0x01E
0x01F
rjmpTIM0_COMPA; Timer0
rjmpTIM0_COMPB; Timer0
rjmpTIM0_OVF; Timer0
rjmpSPI_STC; SPI Transfer
rjmpUSART_RXC; USART, RX
rjmpUSART_UDRE; USART, UDR
rjmpUSART_TXC; USART, TX
rjmpADC; ADC Conversion
rjmpEE_RDY; EEPROM Ready
rjmpANA_COMP; Analog
rjmpTWI; 2-wire Serial
rjmpSPM_RDY; Store Program
ldir16, high(RAMEND); Main
out SPH,r16; Set Stack
ldi r16, low(RAMEND)
out SPL,r16
sei; Enable interrupts
<instr> xxx
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega88PB is:
Address
0x000
program start
0x001
Pointer to top of RAM
0x002
0x003
0x004
0x005
;
.org 0xC01
0xC01
0xC02
...
0xC19
Memory Ready Handler
Labels
RESET:
CodeComments
ldir16,high(RAMEND); Main
outSPH,r16; Set Stack
ldir16,low(RAMEND)
outSPL,r16
sei; Enable interrupts
<instr> xxx
rjmpEXT_INT0; IRQ0 Handler
rjmpEXT_INT1; IRQ1 Handler
......;
rjmpSPM_RDY; Store Program
When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega88PB is:
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Address
.org 0x001
0x001
0x002
...
0x019
Memory Ready Handler
;
.org 0xC00
0xC00
program start
0xC01
Pointer to top of RAM
0xC02
0xC03
0xC04
0xC05
Labels
CodeComments
rjmpEXT_INT0; IRQ0 Handler
rjmpEXT_INT1; IRQ1 Handler
......;
rjmpSPM_RDY; Store Program
RESET:
ldir16,high(RAMEND); Main
outSPH,r16; Set Stack
ldir16,low(RAMEND)
outSPL,r16
sei; Enable interrupts
<instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses in ATmega88PB is:
Address
;
.org 0xC00
0xC00
0xC01
0xC02
...
0xC19
Memory Ready Handler
;
0xC1A
program start
0xC1B
Pointer to top of RAM
0xC1C
0xC1D
0xC1E
0xC1F
13.3
Labels
CodeComments
rjmpRESET; Reset handler
rjmpEXT_INT0; IRQ0 Handler
rjmpEXT_INT1; IRQ1 Handler
......;
rjmpSPM_RDY; Store Program
RESET:
ldir16,high(RAMEND); Main
outSPH,r16; Set Stack
ldir16,low(RAMEND)
outSPL,r16
sei; Enable interrupts
<instr> xxx
Interrupt Vectors in ATmega168PB
Table 13-4.
VectorNo.
1
Reset and Interrupt Vectors in ATmega168PB
Program
Address(2)
(1)
0x0000
Source
Interrupt Definition
RESET
External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset
2
0x0002
INT0
External Interrupt Request 0
3
0x0004
INT1
External Interrupt Request 1
4
0x0006
PCINT0
Pin Change Interrupt Request 0
5
0x0008
PCINT1
Pin Change Interrupt Request 1
6
0x000A
PCINT2
Pin Change Interrupt Request 2
7
0x000C
WDT
Watchdog Time-out Interrupt
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Reset and Interrupt Vectors in ATmega168PB (Continued)
Table 13-4.
VectorNo.
Program
Address(2)
8
Source
Interrupt Definition
0x000E
TIMER2 COMPA
Timer/Counter2 Compare Match A
9
0x0010
TIMER2 COMPB
Timer/Counter2 Compare Match B
10
0x0012
TIMER2 OVF
Timer/Counter2 Overflow
11
0x0014
TIMER1 CAPT
Timer/Counter1 Capture Event
12
0x0016
TIMER1 COMPA
Timer/Counter1 Compare Match A
13
0x0018
TIMER1 COMPB
Timer/Coutner1 Compare Match B
14
0x001A
TIMER1 OVF
Timer/Counter1 Overflow
15
0x001C
TIMER0 COMPA
Timer/Counter0 Compare Match A
16
0x001E
TIMER0 COMPB
Timer/Counter0 Compare Match B
17
0x0020
TIMER0 OVF
Timer/Counter0 Overflow
18
0x0022
SPI, STC
SPI Serial Transfer Complete
19
0x0024
USART, RX
USART Rx Complete
20
0x0026
USART, UDRE
USART, Data Register Empty
21
0x0028
USART, TX
USART, Tx Complete
22
0x002A
ADC
ADC Conversion Complete
23
0x002C
EE READY
EEPROM Ready
24
0x002E
ANALOG COMP
Analog Comparator
25
0x0030
TWI
2-wire Serial Interface (I2C)
26
0x0032
SPM READY
Store Program Memory Ready
27
0x0034
USART, START
USART Start Edge Interrupt
Notes:
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader
Support – Read-While-Write Self-Programming” on page 267.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of
each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.
Table 13-5 on page 61 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST
and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and
regular program code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa.
Table 13-5.
Reset and Interrupt Vectors Placement in ATmega168PB(1)
BOOTRST
IVSEL
1
Note:
Reset Address
Interrupt Vectors Start Address
0
0x000
0x002
1
1
0x000
Boot Reset Address + 0x0002
0
0
Boot Reset Address
0x002
0
1
Boot Reset Address
Boot Reset Address + 0x0002
1.
The Boot Reset Address is shown in Table 28-7 on page 279. For the BOOTRST Fuse “1” means unprogrammed
while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168PB is:
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Address
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
Handler
0x000E
Compare A Handler
0x0010
Compare B Handler
0x0012
Handler
0x0014
Handler
0x0016
Compare A Handler
0x0018
Compare B Handler
0x001A
Handler
0x001C
Compare A Handler
0x001E
Compare B Handler
0x0020
Handler
0x0022
Complete Handler
0x0024
Complete Handler
0x0026
Empty Handler
0x0028
Complete Handler
0x002A
Complete Handler
0x002C
Handler
0x002E
Comparator Handler
0x0030
Interface Handler
0x0032
Memory Ready Handler
;
0x0033
RESET:
program start
0x0034
Pointer to top of RAM
0x0035
0x0036
0x0037
Labels
CodeComments
jmpRESET; Reset Handler
jmpEXT_INT0; IRQ0 Handler
jmpEXT_INT1; IRQ1 Handler
jmpPCINT0; PCINT0 Handler
jmpPCINT1; PCINT1 Handler
jmpPCINT2; PCINT2 Handler
jmpWDT; Watchdog Timer
jmpTIM2_COMPA; Timer2
jmpTIM2_COMPB; Timer2
jmpTIM2_OVF; Timer2 Overflow
jmpTIM1_CAPT; Timer1 Capture
jmpTIM1_COMPA; Timer1
jmpTIM1_COMPB; Timer1
jmpTIM1_OVF; Timer1 Overflow
jmpTIM0_COMPA; Timer0
jmpTIM0_COMPB; Timer0
jmpTIM0_OVF; Timer0 Overflow
jmpSPI_STC; SPI Transfer
jmpUSART_RXC; USART, RX
jmpUSART_UDRE; USART, UDR
jmpUSART_TXC; USART, TX
jmpADC; ADC Conversion
jmpEE_RDY; EEPROM Ready
jmpANA_COMP; Analog
jmpTWI; 2-wire Serial
jmpSPM_RDY; Store Program
ldir16, high(RAMEND); Main
out SPH,r16; Set Stack
ldi r16, low(RAMEND)
out SPL,r16
sei; Enable interrupts
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0x0038
...
...
<instr> xxx
... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses in ATmega168PB is:
Address
0x0000
program start
0x0001
Pointer to top of RAM
0x0002
0x0003
0x0004
0x0005
;
.org 0x1C02
0x1C02
0x1C04
...
0x1C32
Memory Ready Handler
Labels
RESET:
CodeComments
ldir16,high(RAMEND); Main
outSPH,r16; Set Stack
ldir16,low(RAMEND)
outSPL,r16
sei; Enable interrupts
<instr> xxx
jmpEXT_INT0; IRQ0 Handler
jmpEXT_INT1; IRQ1 Handler
......;
jmpSPM_RDY; Store Program
When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in ATmega168PB is:
Address
.org 0x0002
0x0002
0x0004
...
0x0032
Memory Ready Handler
;
.org 0x1C00
0x1C00
program start
0x1C01
Pointer to top of RAM
0x1C02
0x1C03
0x1C04
0x1C05
Labels
CodeComments
jmpEXT_INT0; IRQ0 Handler
jmpEXT_INT1; IRQ1 Handler
......;
jmpSPM_RDY; Store Program
RESET:
ldir16,high(RAMEND); Main
outSPH,r16; Set Stack
ldir16,low(RAMEND)
outSPL,r16
sei; Enable interrupts
<instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses in ATmega168PB is:
Address
;
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
Labels
CodeComments
jmpRESET; Reset handler
jmpEXT_INT0; IRQ0 Handler
jmpEXT_INT1; IRQ1 Handler
......;
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0x1C32
Memory Ready Handler
;
0x1C33
program start
0x1C34
Pointer to top of RAM
0x1C35
0x1C36
0x1C37
0x1C38
jmpSPM_RDY; Store Program
RESET:
ldir16,high(RAMEND); Main
outSPH,r16; Set Stack
ldir16,low(RAMEND)
outSPL,r16
sei; Enable interrupts
<instr> xxx
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13.4
Register Description
13.4.1 Moving Interrupts Between Application and Boot Space, ATmega88PB and ATmega168PB
The MCU Control Register controls the placement of the Interrupt Vector table.
13.4.2 MCUCR – MCU Control Register
Bit
7
6
5
4
3
2
1
0
0x35 (0x55)
–
BODS
BODSE
PUD
–
–
IVSEL
IVCE
Read/Write
R
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this
bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual
address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to ”Boot Loader Support
– Read-While-Write Self-Programming” on page 267 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
1. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE
is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written,
interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot
Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to ”Boot
Loader Support – Read-While-Write Self-Programming” on page 267 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four
cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the
IVSEL description above. See Code Example below.
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Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi
r16, (1<<IVCE)
out
MCUCR, r16
; Move interrupts to Boot Flash section
ldi
r16, (1<<IVSEL)
out
MCUCR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of Interrupt Vectors */
MCUCR = (1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = (1<<IVSEL);
}
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14.
External Interrupts
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT[23:0] pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT[23:0] pins are configured as outputs. This
feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled
PCINT[23:16] pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles. The
pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK2, PCMSK1 and PCMSK0
Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT23...0 are
detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes
other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated
in the specification for the External Interrupt Control Register A – EICRA. When the INT0 or INT1 interrupts are
enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that
recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
”Clock Systems and their Distribution” on page 26. Low level interrupt on INT0 and INT1 is detected
asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than
Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note:
14.1
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the
Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT
and CKSEL Fuses as described in ”System Clock and Clock Options” on page 26.
Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 14-1.
Figure 14-1.
Timing of pin change interrupts
pin_lat
PCINT(0)
LE
clk
D
pcint_in_(0)
Q
0
pcint_syn
pcint_setflag
PCIF
pin_sync
x
PCINT(0) in PCMSK(x)
clk
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
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14.2
Register Description
14.2.1 EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
7
6
5
4
3
2
1
0
(0x69)
–
–
–
–
ISC11
ISC10
ISC01
ISC00
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EICRA
• Bit 7:4 – Reserved
These bits are unused bits in the ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 14-1.
The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
Table 14-1.
Interrupt 1 Sense Control
ISC11
ISC10
Description
0
0
The low level of INT1 generates an interrupt request.
0
1
Any logical change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
1
The rising edge of INT1 generates an interrupt request.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 14-2.
The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
Table 14-2.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
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14.2.2 EIMSK – External Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
0x1D (0x3D)
–
–
–
–
–
–
INT1
INT0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EIMSK
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control Register A
(EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level
sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The
corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A
(EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level
sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
14.2.3 EIFR – External Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
0x1C (0x3C)
–
–
–
–
–
–
INTF1
INTF0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EIFR
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in
SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
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14.2.4 PCICR – Pin Change Interrupt Control Register
Bit
7
6
5
4
3
2
1
0
(0x68)
–
–
–
–
–
PCIE2
PCIE1
PCIE0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCICR
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is
enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins are enabled individually
by the PCMSK2 Register.
• Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is
enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are enabled individually by
the PCMSK1 Register.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by
the PCMSK0 Register.
14.2.5 PCIFR – Pin Change Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
0x1B (0x3B)
–
–
–
–
–
PCIF2
PCIF1
PCIF0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCIFR
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in
SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[14:8] pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in
SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
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• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
14.2.6 PCMSK2 – Pin Change Mask Register 2
Bit
7
6
5
4
3
2
1
0
(0x6D)
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK2
• Bit 7:0 – PCINT[23:16]: Pin Change Enable Mask 23...16
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
14.2.7 PCMSK1 – Pin Change Mask Register 1
Bit
7
6
5
4
3
2
1
0
(0x6C)
–
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK1
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
• Bit 6:0 – PCINT[14:8]: Pin Change Enable Mask 14...8
Each PCINT[14:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[14:8]
is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[14:8] is cleared, pin change interrupt on the corresponding I/O pin is disabled.
14.2.8 PCMSK0 – Pin Change Mask Register 0
Bit
7
6
5
4
3
2
1
0
(0x6B)
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK0
• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7...0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is
set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0]
is cleared, pin change interrupt on the corresponding I/O pin is disabled.
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15.
I/O-Ports
15.1
Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or
enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays
directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O
pins have protection diodes to both VCC and Ground as indicated in Figure 15-1.
Figure 15-1.
I/O Pin Equivalent Schematic
Rpu
Logic
Pxn
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” represents the
numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or
bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here
documented generally as PORTxn. The physical I/O Registers and bit locations are listed in ”Register Description”
on page 88.
Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the
Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx
Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD
bit in MCUCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page 73. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function
interferes with the port pin is described in ”Alternate Port Functions” on page 77. Refer to the individual module
sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.
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15.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 15-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Figure 15-2.
General Digital I/O(1)
PUD
Q
D
DDxn
Q CLR
WDx
RESET
DATA BUS
RDx
1
Q
Pxn
D
0
PORTxn
Q CLR
RESET
SLEEP
RRx
SYNCHRONIZER
D
Q
L
Q
D
WRx
WPx
RPx
Q
PINxn
Q
clk I/O
PUD:
SLEEP:
clkI/O:
Note:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports.
15.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register Description” on
page 88, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and
the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch
the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The
port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
15.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
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15.2.3 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an
intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10)
must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not
notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR
Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 15-1 summarizes the control signals for the pin value.
Table 15-1.
Port Pin Configurations
DDxn
PORTxn
PUD
(in MCUCR)
I/O
Pull-up
0
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled low
0
1
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
1
X
Output
No
Output High (Source)
Comment
15.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 15-2 on page 73, the PINxn Register bit and the preceding latch constitute a synchronizer. This is
needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also
introduces a delay. Figure 15-3 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 15-3.
Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
INSTRUCTIONS
XXX
XXX
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd, max
t pd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
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When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 15-4.
The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is 1 system clock period.
Figure 15-4.
Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
0xFF
out PORTx, r16
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from
4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as
previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of
the pins.
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Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in
r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
Note:
1.
For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0,
1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong
high drivers.
15.2.5 Digital Input Enable and Sleep Modes
As shown in Figure 15-2 on page 73, the digital input signal can be clamped to ground at the input of the Schmitt
Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Powersave mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an
analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled,
SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in
”Alternate Port Functions” on page 77.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising
Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding
External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these
sleep mode produces the requested logic change.
15.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle
mode).
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The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the
pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use
an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this
may cause excessive currents if the pin is accidentally configured as an output.
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 15-5 shows how the port pin
control signals from the simplified Figure 15-2 on page 73 can be overridden by alternate functions. The overriding
signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins
in the AVR microcontroller family.
Figure 15-5.
Alternate Port Functions(1)
PUOExn
PUOVxn
1
PUD
0
DDOExn
DDOVxn
1
Q D
DDxn
0
Q CLR
WDx
PVOExn
RESET
RDx
PVOVxn
1
DATA BUS
15.3
1
Pxn
Q
0
D
0
PORTxn
PTOExn
Q CLR
DIEOExn
DIEOVxn
WPx
RESET
WRx
1
0
RRx
SLEEP
SYNCHRONIZER
D
SET
Q
RPx
Q
D
PINxn
L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
PTOExn:
Note:
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clkI/O:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports. All other signals are unique for each pin.
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Table 15-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 15-5 on page
77 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having
the alternate function.
Table 15-2.
Generic Description of Overriding Signals for Alternate Functions
Signal Name
Full Name
Description
PUOE
Pull-up Override Enable
If this signal is set, the pull-up enable is controlled by the PUOV signal. If this
signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up Override Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared,
regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
DDOE
Data Direction Override
Enable
If this signal is set, the Output Driver Enable is controlled by the DDOV signal.
If this signal is cleared, the Output driver is enabled by the DDxn Register bit.
DDOV
Data Direction Override
Value
If DDOE is set, the Output Driver is enabled/disabled when DDOV is
set/cleared, regardless of the setting of the DDxn Register bit.
PVOE
Port Value Override
Enable
If this signal is set and the Output Driver is enabled, the port value is controlled
by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the
port Value is controlled by the PORTxn Register bit.
PVOV
Port Value Override
Value
If PVOE is set, the port value is set to PVOV, regardless of the setting of the
PORTxn Register bit.
PTOE
Port Toggle Override
Enable
If PTOE is set, the PORTxn Register bit is inverted.
DIEOE
Digital Input Enable
Override Enable
If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If
this signal is cleared, the Digital Input Enable is determined by MCU state
(Normal mode, sleep mode).
DIEOV
Digital Input Enable
Override Value
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is
set/cleared, regardless of the MCU state (Normal mode, sleep mode).
DI
Digital Input
This is the Digital Input to alternate functions. In the figure, the signal is
connected to the output of the Schmitt Trigger but before the synchronizer.
Unless the Digital Input is used as a clock source, the module with the
alternate function will use its own synchronizer.
AIO
Analog Input/Output
This is the Analog Input/output to/from alternate functions. The signal is
connected directly to the pad, and can be used bi-directionally.
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to
the alternate function. Refer to the alternate function description for further details.
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15.3.1 Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 15-3.
Table 15-3.
Port Pin
Port B Pins Alternate Functions
Alternate Functions
PB7
XTAL2 (Chip Clock Oscillator pin 2)
TOSC2 (Timer Oscillator pin 2)
PCINT7 (Pin Change Interrupt 7)
PB6
XTAL1 (Chip Clock Oscillator pin 1 or External clock input)
TOSC1 (Timer Oscillator pin 1)
PCINT6 (Pin Change Interrupt 6)
PB5
SCK (SPI Bus Master clock Input)
PCINT5 (Pin Change Interrupt 5)
PB4
MISO (SPI Bus Master Input/Slave Output)
PCINT4 (Pin Change Interrupt 4)
PB3
MOSI (SPI Bus Master Output/Slave Input)
OC2A (Timer/Counter2 Output Compare Match A Output)
PCINT3 (Pin Change Interrupt 3)
PB2
SS (SPI Bus Master Slave select)
OC1B (Timer/Counter1 Output Compare Match B Output)
PCINT2 (Pin Change Interrupt 2)
PB1
OC1A (Timer/Counter1 Output Compare Match A Output)
PCINT1 (Pin Change Interrupt 1)
PB0
ICP1 (Timer/Counter1 Input Capture Input)
CLKO (Divided System Clock Output)
PCINT0 (Pin Change Interrupt 0)
The alternate pin configuration is as follows:
• XTAL2/TOSC2/PCINT7 – Port B, Bit 7
XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator.
When used as a clock pin, the pin can not be used as an I/O pin.
TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as chip clock source, and
the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) and the
EXCLK bit is cleared (zero) to enable asynchronous clocking of Timer/Counter2 using the Crystal Oscillator, pin
PB7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a
crystal Oscillator is connected to this pin, and the pin cannot be used as an I/O pin.
PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source.
If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.
• XTAL1/TOSC1/PCINT6 – Port B, Bit 6
XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When
used as a clock pin, the pin can not be used as an I/O pin.
TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip clock source, and
the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) to enable
asynchronous clocking of Timer/Counter2, pin PB6 is disconnected from the port, and becomes the input of the
inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used
as an I/O pin.
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PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.
If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.
• SCK/PCINT5 – Port B, Bit 5
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is
configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction
of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled
by the PORTB5 bit.
PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.
• MISO/PCINT4 – Port B, Bit 4
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is
configured as an input regardless of the setting of DDB4. When the SPI is enabled as a Slave, the data direction of
this pin is controlled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by
the PORTB4 bit.
PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source.
• MOSI/OC2/PCINT3 – Port B, Bit 3
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is
configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Master, the data direction
of this pin is controlled by DDB3. When the pin is forced by the SPI to be an input, the pull-up can still be controlled
by the PORTB3 bit.
OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the Timer/Counter2
Compare Match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC2
pin is also the output pin for the PWM mode timer function.
PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source.
• SS/OC1B/PCINT2 – Port B, Bit 2
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the
setting of DDB2. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master,
the data direction of this pin is controlled by DDB2. When the pin is forced by the SPI to be an input, the pull-up can
still be controlled by the PORTB2 bit.
OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the Timer/Counter1
Compare Match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The
OC1B pin is also the output pin for the PWM mode timer function.
PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source.
• OC1A/PCINT1 – Port B, Bit 1
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1
Compare Match A. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The
OC1A pin is also the output pin for the PWM mode timer function.
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.
• ICP1/CLKO/PCINT0 – Port B, Bit 0
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
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CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The divided system clock
will be output if the CKOUT Fuse is programmed, regardless of the PORTB0 and DDB0 settings. It will also be
output during reset.
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.
Table 15-4 and Table 15-5 on page 81 relate the alternate functions of Port B to the overriding signals shown in
Figure 15-5 on page 77. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is
divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 15-4.
Overriding Signals for Alternate Functions in PB7...PB4
Signal
Name
PB7/XTAL2/
TOSC2/PCINT7(1)
PB6/XTAL1/
TOSC1/PCINT6(1)
PB5/SCK/
PCINT5
PB4/MISO/
PCINT4
PUOE
INTRC • EXTCK+ AS2
INTRC + AS2
SPE • MSTR
SPE • MSTR
PUOV
0
0
PORTB5 • PUD
PORTB4 • PUD
DDOE
INTRC • EXTCK+ AS2
INTRC + AS2
SPE • MSTR
SPE • MSTR
DDOV
0
0
0
0
PVOE
0
0
SPE • MSTR
SPE • MSTR
PVOV
0
0
SCK OUTPUT
SPI SLAVE
OUTPUT
DIEOE
INTRC • EXTCK + AS2 + PCINT7 • PCIE0
INTRC + AS2 +
PCINT6 • PCIE0
PCINT5 • PCIE0
PCINT4 • PCIE0
DIEOV
(INTRC + EXTCK) • AS2
INTRC • AS2
1
1
DI
PCINT7 INPUT
PCINT6 INPUT
PCINT5 INPUT
SCK INPUT
PCINT4 INPUT
SPI MSTR INPUT
AIO
Oscillator Output
Oscillator/Clock
Input
–
–
Notes:
1.
INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses), EXTCK means that
external clock is selected (by the CKSEL fuses).
Table 15-5.
Overriding Signals for Alternate Functions in PB3...PB0
Signal
Name
PB3/MOSI/
OC2/PCINT3
PB2/SS/
OC1B/PCINT2
PB1/OC1A/
PCINT1
PB0/ICP1/
PCINT0
PUOE
SPE • MSTR
SPE • MSTR
0
0
PUOV
PORTB3 • PUD
PORTB2 • PUD
0
0
DDOE
SPE • MSTR
SPE • MSTR
0
0
DDOV
0
0
0
0
PVOE
SPE • MSTR + OC2A ENABLE
OC1B ENABLE
OC1A ENABLE
0
PVOV
SPI MSTR OUTPUT + OC2A
OC1B
OC1A
0
DIEOE
PCINT3 • PCIE0
PCINT2 • PCIE0
PCINT1 • PCIE0
PCINT0 • PCIE0
DIEOV
1
1
1
1
DI
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT
SPI SS
PCINT1 INPUT
PCINT0 INPUT
ICP1 INPUT
AIO
–
–
–
–
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15.3.2 Alternate Functions of Port C
The Port C pins with alternate functions are shown in Table 15-6.
Table 15-6.
Port Pin
Port C Pins Alternate Functions
Alternate Function
PC6
RESET (Reset pin)
PCINT14 (Pin Change Interrupt 14)
PC5
ADC5 (ADC Input Channel 5)
SCL (2-wire Serial Bus Clock Line)
PCINT13 (Pin Change Interrupt 13)
PC4
ADC4 (ADC Input Channel 4)
SDA (2-wire Serial Bus Data Input/Output Line)
PCINT12 (Pin Change Interrupt 12)
PC3
ADC3 (ADC Input Channel 3)
PCINT11 (Pin Change Interrupt 11)
PC2
ADC2 (ADC Input Channel 2)
PCINT10 (Pin Change Interrupt 10)
PC1
ADC1 (ADC Input Channel 1)
PCINT9 (Pin Change Interrupt 9)
PC0
ADC0 (ADC Input Channel 0)
PCINT8 (Pin Change Interrupt 8)
The alternate pin configuration is as follows:
• RESET/PCINT14 – Port C, Bit 6
RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part
will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is
unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin.
If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.
PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt source.
• SCL/ADC5/PCINT13 – Port C, Bit 5
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface,
pin PC5 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this
mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is
driven by an open drain driver with slew-rate limitation.
PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital power.
PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt source.
• SDA/ADC4/PCINT12 – Port C, Bit 4
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface,
pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this
mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is
driven by an open drain driver with slew-rate limitation.
PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital power.
PCINT12: Pin Change Interrupt source 12. The PC4 pin can serve as an external interrupt source.
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• ADC3/PCINT11 – Port C, Bit 3
PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog power.
PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt source.
• ADC2/PCINT10 – Port C, Bit 2
PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power.
PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt source.
• ADC1/PCINT9 – Port C, Bit 1
PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power.
PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source.
• ADC0/PCINT8 – Port C, Bit 0
PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power.
PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.
Table 15-7 and Table 15-8 on page 84 relate the alternate functions of Port C to the overriding signals shown in
Figure 15-5 on page 77.
Overriding Signals for Alternate Functions in PC6...PC4(1)
Table 15-7.
Signal
Name
PC6/RESET/PCINT14
PC5/SCL/ADC5/PCINT13
PC4/SDA/ADC4/PCINT12
PUOE
RSTDISBL
TWEN
TWEN
PUOV
1
PORTC5 • PUD
PORTC4 • PUD
DDOE
RSTDISBL
TWEN
TWEN
DDOV
0
SCL_OUT
SDA_OUT
PVOE
0
TWEN
TWEN
PVOV
0
0
0
DIEOE
RSTDISBL + PCINT14 • PCIE1
PCINT13 • PCIE1 + ADC5D
PCINT12 • PCIE1 + ADC4D
DIEOV
RSTDISBL
PCINT13 • PCIE1
PCINT12 • PCIE1
DI
PCINT14 INPUT
PCINT13 INPUT
PCINT12 INPUT
AIO
RESET INPUT
ADC5 INPUT / SCL INPUT
ADC4 INPUT / SDA INPUT
Note:
1.
When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4 and PC5. This is not
shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and
the digital logic of the TWI module.
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Table 15-8.
Overriding Signals for Alternate Functions in PC3...PC0
Signal
Name
PC3/ADC3/
PCINT11
PC2/ADC2/
PCINT10
PC1/ADC1/
PCINT9
PC0/ADC0/
PCINT8
PUOE
0
0
0
0
PUOV
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
0
0
0
PVOV
0
0
0
0
DIEOE
PCINT11 • PCIE1 +
ADC3D
PCINT10 • PCIE1 +
ADC2D
PCINT9 • PCIE1 +
ADC1D
PCINT8 • PCIE1 +
ADC0D
DIEOV
PCINT11 • PCIE1
PCINT10 • PCIE1
PCINT9 • PCIE1
PCINT8 • PCIE1
DI
PCINT11 INPUT
PCINT10 INPUT
PCINT9 INPUT
PCINT8 INPUT
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
ADC0 INPUT
15.3.3 Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 15-9.
Table 15-9.
Port Pin
Port D Pins Alternate Functions
Alternate Function
PD7
AIN1 (Analog Comparator Negative Input)
PCINT23 (Pin Change Interrupt 23)
PD6
AIN0 (Analog Comparator Positive Input)
OC0A (Timer/Counter0 Output Compare Match A Output)
PCINT22 (Pin Change Interrupt 22)
PD5
T1 (Timer/Counter 1 External Counter Input)
OC0B (Timer/Counter0 Output Compare Match B Output)
PCINT21 (Pin Change Interrupt 21)
PD4
XCK (USART External Clock Input/Output)
T0 (Timer/Counter 0 External Counter Input)
PCINT20 (Pin Change Interrupt 20)
PD3
INT1 (External Interrupt 1 Input)
OC2B (Timer/Counter2 Output Compare Match B Output)
PCINT19 (Pin Change Interrupt 19)
PD2
INT0 (External Interrupt 0 Input)
PCINT18 (Pin Change Interrupt 18)
PD1
TXD (USART Output Pin)
PCINT17 (Pin Change Interrupt 17)
PD0
RXD (USART Input Pin)
PCINT16 (Pin Change Interrupt 16)
The alternate pin configuration is as follows:
• AIN1/OC2B/PCINT23 – Port D, Bit 7
AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comparator.
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PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt source.
• AIN0/OC0A/PCINT22 – Port D, Bit 6
AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comparator.
OC0A, Output Compare Match output: The PD6 pin can serve as an external output for the Timer/Counter0
Compare Match A. The PD6 pin has to be configured as an output (DDD6 set (one)) to serve this function. The
OC0A pin is also the output pin for the PWM mode timer function.
PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt source.
• T1/OC0B/PCINT21 – Port D, Bit 5
T1, Timer/Counter1 counter source.
OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0
Compare Match B. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. The
OC0B pin is also the output pin for the PWM mode timer function.
PCINT21: Pin Change Interrupt source 21. The PD5 pin can serve as an external interrupt source.
• XCK/T0/PCINT20 – Port D, Bit 4
XCK, USART external clock.
T0, Timer/Counter0 counter source.
PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt source.
• INT1/OC2B/PCINT19 – Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.
OC2B, Output Compare Match output: The PD3 pin can serve as an external output for the Timer/Counter0
Compare Match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The
OC2B pin is also the output pin for the PWM mode timer function.
PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt source.
• INT0/PCINT18 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.
PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source.
• TXD/PCINT17 – Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is
configured as an output regardless of the value of DDD1.
PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt source.
• RXD/PCINT16 – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this pin is configured as
an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be
controlled by the PORTD0 bit.
PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source.
Table 15-10 and Table 15-11 relate the alternate functions of Port D to the overriding signals shown in Figure 15-5
on page 77.
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Table 15-10.
Overriding Signals for Alternate Functions PD7...PD4
Signal
Name
PD7/AIN1
/PCINT23
PD6/AIN0/
OC0A/PCINT22
PD5/T1/OC0B/
PCINT21
PD4/XCK/
T0/PCINT20
PUOE
0
0
0
0
PUO
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
OC0A ENABLE
OC0B ENABLE
UMSEL
PVOV
0
OC0A
OC0B
XCK OUTPUT
DIEOE
PCINT23 • PCIE2
PCINT22 • PCIE2
PCINT21 • PCIE2
PCINT20 • PCIE2
DIEOV
1
1
1
1
DI
PCINT23 INPUT
PCINT22 INPUT
PCINT21 INPUT
T1 INPUT
PCINT20 INPUT
XCK INPUT
T0 INPUT
AIO
AIN1 INPUT
AIN0 INPUT
–
–
Table 15-11.
Overriding Signals for Alternate Functions in PD3...PD0
Signal
Name
PD3/OC2B/INT1/
PCINT19
PD2/INT0/
PCINT18
PD1/TXD/
PCINT17
PD0/RXD/
PCINT16
PUOE
0
0
TXEN
RXEN
PUO
0
0
0
PORTD0 • PUD
DDOE
0
0
TXEN
RXEN
DDOV
0
0
1
0
PVOE
OC2B ENABLE
0
TXEN
0
PVOV
OC2B
0
TXD
0
DIEOE
INT1 ENABLE +
PCINT19 • PCIE2
INT0 ENABLE +
PCINT18 • PCIE1
PCINT17 • PCIE2
PCINT16 • PCIE2
DIEOV
1
1
1
1
DI
PCINT19 INPUT
INT1 INPUT
PCINT18 INPUT
INT0 INPUT
PCINT17 INPUT
PCINT16 INPUT
RXD
AIO
–
–
–
–
15.3.4 Alternate Functions of Port E
The Port E pins with alternate functions are shown in Table 15-12.
Table 15-12.
Port Pin
Port E Pins Alternate Functions
Alternate Function
PE3
ADC7 (ADC Input Channel 7)
PE2
ADC6 (ADC Input Channel 6)
PE1
NONE
PE0
ACO (AC Output Channel 0)
The alternate pin configuration is as follows:
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• ADC7 – Port E, Bit 3
PE3 can also be used as ADC input Channel 7.
• ADC6 – Port E, Bit 2
PE2 can also be used as ADC input Channel 6.
• Port E, Bit 1
No alternate function.
• ACO – Port E, Bit 0
PE0 can also be used as Analog Comparator output.
Table 15-13 on page 87 relate the alternate functions of Port E to the overriding signals shown in Figure 15-5 on
page 77.
Table 15-13.
Overriding Signals for Alternate Functions in PE3...PE0
Signal
Name
PE3/ADC7
PE2/ADC6
PE1
PE0/ACO
PUOE
0
0
0
aco_oe
PUOV
0
0
0
0
DDOE
0
0
0
aco_oe
PVOE
0
0
0
aco_oe
PVOV
0
0
0
acompout
DIEOE
ADC7D
ADC6D
0
0
DIEOV
0
0
0
0
DI
0
0
0
0
AIO
ADC7 INPUT
ADC6 INPUT
0
AC OUTPUT
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15.4
Register Description
15.4.1 MCUCR – MCU Control Register
Bit
7
6
5
4
3
2
1
0
0x35 (0x55)
–
BODS
BODSE
PUD
–
–
IVSEL
IVCE
Read/Write
R
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers
are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Configuring the Pin” on page 73 for more
details about this feature.
15.4.2 PORTB – The Port B Data Register
Bit
7
6
5
4
3
2
1
0
0x05 (0x25)
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTB
15.4.3 DDRB – The Port B Data Direction Register
Bit
7
6
5
4
3
2
1
0
0x04 (0x24)
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRB
15.4.4 PINB – The Port B Input Pins Address()
Bit
7
6
5
4
3
2
1
0
0x03 (0x23)
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PINB
15.4.5 PORTC – The Port C Data Register
Bit
7
6
5
4
3
2
1
0
0x08 (0x28)
–
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTC
15.4.6 DDRC – The Port C Data Direction Register
Bit
7
6
5
4
3
2
1
0
0x07 (0x27)
–
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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15.4.7 PINC – The Port C Input Pins Address()
Bit
7
6
5
4
3
2
1
0
0x06 (0x26)
–
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PINC
15.4.8 PORTD – The Port D Data Register
Bit
7
6
5
4
3
2
1
0
0x0B (0x2B)
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTD
15.4.9 DDRD – The Port D Data Direction Register
Bit
7
6
5
4
3
2
1
0
0x0A (0x2A)
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRD
15.4.10 PIND – The Port D Input Pins Address()
Bit
7
6
5
4
3
2
1
0
0x09 (0x29)
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PIND
15.4.11 PORTE – The Port E Data Register
Bit
7
6
5
4
3
2
1
0
0x08 (0x28)
–
–
–
–
PORTE3
PORTE2
PORTE1
PORTE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTE
15.4.12 DDRE – The Port E Data Direction Register
Bit
7
6
5
4
3
2
1
0
0x07 (0x27)
–
–
–
–
DDRE3
DDRE2
DDRE1
DDRE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRE
15.4.13 PINE – The Port E Input Pins Address()
Bit
7
6
5
4
3
2
1
0
0x06 (0x26)
–
–
–
–
PINE3
PINE2
PINE1
PINE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Note:
1.
PINE
Writing to the pin register provides toggle functionality for IO (see ”Toggling the Pin” on page 73)
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16.
8-bit Timer/Counter0 with PWM
16.1
Features
16.2

Two Independent Output Compare Units

Double Buffered Output Compare Registers

Clear Timer on Compare Match (Auto Reload)

Glitch Free, Phase Correct Pulse Width Modulator (PWM)

Variable PWM Period

Frequency Generator

Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units,
and with PWM support. It allows accurate program execution timing (event management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-1. For the actual placement of I/O pins,
refer to ”Pinout ATmega48PB/88PB/168PB” on page 3. CPU accessible I/O Registers, including I/O bits and I/O
pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ”Register Description” on
page 101.
The PRTIM0 bit in ”Minimizing Power Consumption” on page 39 must be written to zero to enable Timer/Counter0
module.
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Figure 16-1.
8-bit Timer/Counter Block Diagram
Count
TOVn
(Int.Req.)
Clear
Direction
Control Logic
clkTn
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
=0
OCnA
(Int.Req.)
Waveform
Generation
=
OCnA
OCRnA
DATA BUS
Fixed
TOP
Value
OCnB
(Int.Req.)
Waveform
Generation
=
OCnB
OCRnB
TCCRnA
TCCRnB
16.2.1 Definitions
Many register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare
Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 16-1 are also used extensively throughout the document.
Table 16-1.
BOTTOM
MAX
TOP
Definitions
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored
in the OCR0A Register. The assignment is dependent on the mode of operation.
16.2.2 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not
shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable
frequency output on the Output Compare pins (OC0A and OC0B). See ”Using the Output Compare Unit” on page
118 for details. The compare match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to
generate an Output Compare interrupt request.
16.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control
Register (TCCR0B). For details on clock sources and prescaler, see ”Timer/Counter0 and Timer/Counter1
Prescalers” on page 134.
16.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 16-2 on page 92
shows a block diagram of the counter and its surroundings.
Figure 16-2.
Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
Clock Select
count
clear
TCNTn
Control Logic
clkTn
Edge
Detector
Tn
direction
( From Prescaler )
bottom
top
Signal description (internal signals)
count
Increment or decrement TCNT0 by 1.
direction
Select between increment and decrement.
clear
Clear TCNT0 (set all bits to zero).
clkTn
Clear TCNT0 (set all bits to zero).
top
Signalize that TCNT0 has reached maximum value.
bottom
Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock
(clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the
Output Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform
generation, see ”Modes of Operation” on page 95.
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The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits.
TOV0 can be used for generating a CPU interrupt.
16.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B).
Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output
Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the
Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared
when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O
bit location. The Waveform Generator uses the match signal to generate an output according to operating mode
set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by
the Waveform Generator for handling the special cases of the extreme values in some modes of operation (”Modes
of Operation” on page 95).9
Figure 16-3 on page 93 shows a block diagram of the Output Compare unit.
Figure 16-3.
Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator
OCnx
FOCn
WGMn1:0
COMnx1:0
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x
directly.
16.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC0x) bit. Forcing compare match will not set the OCF0x Flag or reload/clear the
timer, but the OC0x pin will be updated as if a real compare match had occurred (the COM0x1:0 bits settings
define whether the OC0x pin is set, cleared or toggled).
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16.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0
without triggering an interrupt when the Timer/Counter clock is enabled.
16.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM
when the counter is down counting.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal
mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the
COM0x1:0 bits will take effect immediately.
Compare Match Output Unit
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0
bits for defining the Output Compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control the
OC0x pin output source. Figure 16-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x
Register is reset to “0”.
Figure 16-4.
Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCn
Waveform
Generator
D
Q
1
OCnx
D
DATA BUS
16.6
0
OCnx
Pin
Q
PORT
D
Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either
of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be
set as output before the OC0x value is visible on the pin. The port override function is independent of the
Waveform Generation mode.
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The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled.
Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on
page 101.
16.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes,
setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 101. For
fast PWM mode, refer to Table 16-3 on page 101, and for phase correct PWM refer to Table 16-4 on page 102.
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.
16.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a
compare match (See ”Compare Match Output Unit” on page 94).
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 99.
16.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
16.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The
OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the
compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 16-5. The counter value (TCNT0) increases until a
compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
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Figure 16-5.
CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCn
(Toggle)
Period
(COMnx1:0 = 1)
1
2
3
4
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by
the following equation:
f clk_I/O
f OCnx = -------------------------------------------------2  N   1 + OCRnx 
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
16.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM
waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The
counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared
on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the
output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope
operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), and therefore
reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-6. The
TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
compare matches between OCR0x and TCNT0.
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Figure 16-6.
Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if
the WGM02 bit is set. This option is not available for the OC0B pin (see Table 16-6 on page 102). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0, and
clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to
BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = -----------------N  256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM0A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle
its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency
of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the
double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
16.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform
generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts
repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1,
and OCR0A when WGM2:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared
on the compare match between TCNT0 and OCR0x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower
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maximum operation frequency than single slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 16-7 on page 98. The TCNT0 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches
between OCR0x and TCNT0.
Figure 16-7.
Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting
the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the
WGM02 bit is set. This option is not available for the OC0B pin (see Table 16-7 on page 103). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and TCNT0 when the
counter increments, and setting (or clearing) the OC0x Register at compare match between OCR0x and TCNT0
when the counter decrements. The PWM frequency for the output when using phase correct PWM can be
calculated by the following equation:
f clk_I/O
f OCnxPCPWM = -----------------N  510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
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At the very start of period 2 in Figure 16-7 OCnx has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
16.8
•
OCRnx changes its value from MAX, like in Figure 16-7. When the OCR0A value is MAX the OCn pin value
is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the
OCnx value at MAX must correspond to the result of an up-counting Compare Match.
•
The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the
Compare Match and hence the OCnx change that would have happened on the way up.
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal
in the following figures. The figures include information on when interrupt flags are set. Figure 16-8 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 16-8.
Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 16-9 shows the same timing data, but with the prescaler enabled.
Figure 16-9.
Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 16-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM
mode, where OCR0A is TOP.
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Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 16-11 on page 100 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM
mode where OCR0A is TOP.
Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
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16.9
Register Description
16.9.1 TCCR0A – Timer/Counter Control Register A
Bit
7
6
5
4
3
2
1
0
0x24 (0x44)
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0A
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the
OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting.
Table 16-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (nonPWM).
Table 16-2.
Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
0
Normal port operation, OC0A disconnected
0
1
Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match
1
1
Set OC0A on Compare Match
Table 16-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Compare Output Mode, Fast PWM Mode(1)
Table 16-3.
COM0A1
COM0A0
0
0
Normal port operation, OC0A disconnected
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected
WGM02 = 1: Toggle OC0A on Compare Match
1
0
Clear OC0A on Compare Match, set OC0A at BOTTOM,
(non-inverting mode)
1
1
Set OC0A on Compare Match, clear OC0A at BOTTOM,
(inverting mode)
Note:
1.
Description
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on page 96 for more details.
Table 16-4 on page 102 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
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Compare Output Mode, Phase Correct PWM Mode(1)
Table 16-4.
COM0A1
COM0A0
0
0
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match
when down-counting.
1
1
Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match
when down-counting.
Note:
1.
Description
A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 122 for more details.
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the
OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting.
Table 16-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (nonPWM).
Table 16-5.
Compare Output Mode, non-PWM Mode
COM0B1
COM0B0
Description
0
0
Normal port operation, OC0B disconnected
0
1
Toggle OC0B on Compare Match
1
0
Clear OC0B on Compare Match
1
1
Set OC0B on Compare Match
Table 16-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.
Compare Output Mode, Fast PWM Mode(1)
Table 16-6.
COM0B1
COM0B0
0
0
Normal port operation, OC0B disconnected
0
1
Reserved
1
0
Clear OC0B on Compare Match, set OC0B at BOTTOM,
(non-inverting mode)
1
1
Set OC0B on Compare Match, clear OC0B at BOTTOM,
(inverting mode)
Note:
1.
Description
A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Fast PWM Mode” on page 96 for more details.
Table 16-7 on page 103 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
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Compare Output Mode, Phase Correct PWM Mode(1)
Table 16-7.
COM0B1
COM0B0
0
0
Normal port operation, OC0B disconnected
0
1
Reserved
1
0
Clear OC0B on Compare Match when up-counting.
Set OC0B on Compare Match when down-counting.
1
1
Set OC0B on Compare Match when up-counting.
Clear OC0B on Compare Match when down-counting.
Note:
1.
Description
A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 97 for more details.
• Bits 3, 2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 16-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see ”Modes of Operation”
on page 95).
Table 16-8.
Waveform Generation Mode Bit Description
Timer/Counter
Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Mode
WGM02
WGM01
WGM00
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
4
1
0
0
Reserved
–
–
–
5
1
0
1
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
1
1
0
Reserved
–
–
–
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
Notes:
1.
2.
MAX
= 0xFF
BOTTOM = 0x00
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16.9.2 TCCR0B – Timer/Counter Control Register B
Bit
7
6
5
4
3
2
1
0
0x25 (0x45)
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
Read/Write
W
W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the
FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the
effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the
FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the
effect of the forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the ”TCCR0A – Timer/Counter Control Register A” on page 101.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
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Table 16-9.
Clock Select Bit Description
CS02
CS01
CS00
Description
0
0
0
No clock source (Timer/Counter stopped)
0
0
1
clkI/O/(No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
16.9.3 TCNT0 – Timer/Counter Register
Bit
7
6
5
4
0x26 (0x46)
3
2
1
0
TCNT0[7:0]
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock.
Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match
between TCNT0 and the OCR0x Registers.
16.9.4 OCR0A – Output Compare Register A
Bit
7
6
5
4
0x27 (0x47)
3
2
1
0
OCR0A[7:0]
OCR0A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0A pin.
16.9.5 OCR0B – Output Compare Register B
Bit
7
6
5
4
0x28 (0x48)
3
2
1
0
OCR0B[7:0]
OCR0B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0B pin.
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16.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
(0x6E)
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK0
• Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare
Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs,
i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare
Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0
occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
16.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
0x15 (0x35)
–
–
–
–
–
OCF0B
OCF0A
TOV0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIFR0
• Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output
Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A –
Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match
Interrupt is executed.
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• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the
SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow
interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 16-8, ”Waveform Generation Mode
Bit Description” on page 103.
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17.
16-bit Timer/Counter1 with PWM
17.1
Features
17.2

True 16-bit Design (i.e., allows 16-bit PWM)

Two independent Output Compare Units

Double Buffered Output Compare Registers

One Input Capture Unit

Input Capture Noise Canceler

Clear Timer on Compare Match (Auto Reload)

Glitch-free, Phase Correct Pulse Width Modulator (PWM)

Variable PWM Period

Frequency Generator

External Event Counter

Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the
register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1
counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 17-1 on page 109. For the actual
placement of I/O pins, refer to ”Pinout ATmega48PB/88PB/168PB” on page 3. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the
”Register Description” on page 128.
The PRTIM1 bit in ”PRR – Power Reduction Register” on page 43 must be written to zero to enable
Timer/Counter1 module.
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Figure 17-1.
16-bit Timer/Counter Block Diagram(1)
Count
TOVn
(Int.Req.)
Clear
Direction
Control Logic
Clock Select
clkTn
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
=0
OCnA
(Int.Req.)
Waveform
Generation
=
OCnA
DATA BUS
OCRnA
OCnB
(Int.Req.)
Fixed
TOP
Values
Waveform
Generation
=
OCRnB
OCnB
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
ICRn
Noise
Canceler
ICPn
TCCRnA
Note:
TCCRnB
1. Refer to Figure 2-1 on page 3, Table 15-3 on page 79 and Table 15-9 on page 84 for Timer/Counter1 pin placement and description.
17.2.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section ”Accessing 16-bit Registers” on page 110. The Timer/Counter Control Registers
(TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in
the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time.
The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency
output on the Output Compare pin (OC1A/B). See ”Output Compare Units” on page 116. The compare match
event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare
interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”Analog Comparator” on page 236) The
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Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise
spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM
mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output.
17.2.2 Definitions
The following definitions are used extensively throughout the section:
17.3
BOTTOM
The counter reaches the BOTTOM when it becomes 0x0000.
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP
value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the
OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.
Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit
register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between
all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When
the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as
the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does
not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read
before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates
the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers.
Note that when using “C”, the compiler handles the 16-bit access.
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Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT1H,r17
out
TCNT1L,r16
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
Note:
1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two
instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the
same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted.
Therefore, when both the main code and the interrupt code update the temporary register, the main code must
disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the
OCR1A/B or ICR1 Registers can be done by using the same principle.
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Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note:
1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the
OCR1A/B or ICR1 Registers can be done by using the same principle.
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Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out
TCNT1H,r17
out
TCNT1L,r16
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note:
1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1.
17.3.1 Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte
only needs to be written once. However, note that the same rule of atomic operation described previously also
applies in this case.
17.4
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control
Register B (TCCR1B). For details on clock sources and prescaler, see ”Timer/Counter0 and Timer/Counter1
Prescalers” on page 134.
17.5
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows
a block diagram of the counter and its surroundings.
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Figure 17-2.
Counter Unit Block Diagram
DATA BUS
(8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Count
TCNTnH (8-bit)
TCNTnL (8-bit)
Clear
Direction
TCNTn (16-bit Counter)
Control Logic
clkTn
Edge
Detector
Tn
( From Prescaler )
TOP
BOTTOM
Signal description (internal signals):
Count
Increment or decrement TCNT1 by 1
Direction
Select between increment and decrement.
Clear
Clear TCNT1 (set all bits to zero).
clkT1
Timer/Counter clock.
TOP
Signalize that TCNT1 has reached maximum value.
BOTTOM
Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper
eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value
when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that
will give unpredictable results. The special cases are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be
accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in
the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how
the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more
details about advanced counting sequences and waveform generation, see ”Modes of Operation” on page 119.
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits.
TOV1 can be used for generating a CPU interrupt.
17.6
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a timestamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via
the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate
frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for
creating a log of the events.
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The Input Capture unit is illustrated by the block diagram shown in Figure 17-3. The elements of the block diagram
that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names
indicates the Timer/Counter number.
Figure 17-3.
Input Capture Unit Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit)
ICRnL (8-bit)
TCNTnH (8-bit)
ICRn (16-bit Register)
WRITE
ACO*
Analog
Comparator
ACIC*
TCNTnL (8-bit)
TCNTn (16-bit Counter)
ICNC
ICES
Noise
Canceler
Edge
Detector
ICFn (Int.Req.)
ICPn
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog
Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register
(ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1
Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is
automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by
writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and
then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register
(TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for
defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set
before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be
written to the ICR1H I/O location before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 110.
17.6.1 Input Capture Trigger Source
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively
use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected
as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and
Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must
therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same
technique as for the T1 pin (Figure 18-1 on page 134). The edge detector is also identical. However, when the
noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four
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system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the
Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
17.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control
Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
17.6.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time between two events is critical. If the processor has not read the captured value in the
ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine
as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response
time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a
change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is
used).
17.7
Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals
OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock
cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag
is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software
by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode
(COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (See Section “17.9” on page 119.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter
resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by
the Waveform Generator.
Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names
indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The
elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
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Figure 17-4.
Output Compare Unit, Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
OCRnx Buffer (16-bit Register)
OCRnxH (8-bit)
TCNTnL (8-bit)
TCNTn (16-bit Counter)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
BOTTOM
Waveform Generator
WGMn3:0
OCnx
COMnx1:0
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x
directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the
Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is
not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as
when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the
compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O
location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x
buffer or OCR1x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 110.
17.7.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC1x) bit. Forcing compare match will not set the OCF1x Flag or reload/clear the
timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define
whether the OC1x pin is set, cleared or toggled).
17.7.2 Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without
triggering an interrupt when the Timer/Counter clock is enabled.
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17.7.3 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether
the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will
be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal
mode. The OC1x Register keeps its value even when changing between Waveform Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the
COM1x1:0 bits will take effect immediately.
Compare Match Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0
bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control
the OC1x pin output source. Figure 17-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the
OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x
Register is reset to “0”.
Figure 17-5.
Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCnx
Waveform
Generator
D
Q
1
OCnx
D
DATA BUS
17.8
0
OCnx
Pin
Q
PORT
D
Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either
of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be
set as output before the OC1x value is visible on the pin. The port override function is generally independent of the
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Waveform Generation mode, but there are some exceptions. Refer to Table 17-1 on page 128, Table 17-2 on page
128 and Table 17-3 on page 129 for details.
The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled.
Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on
page 128.
The COM1x1:0 bits have no effect on the Input Capture unit.
17.8.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes,
setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 17-1 on page 128. For
fast PWM mode refer to Table 17-2 on page 128, and for phase correct and phase and frequency correct PWM
refer to Table 17-3 on page 129.
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.
17.9
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a
compare match (See “Compare Match Output Unit” on page 118.)
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 126.
17.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the
Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The
TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the
timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exceed the resolution of the counter. If the interval between events are too long, the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
17.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1)
matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value
for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency.
It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNT1) increases until a
compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
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Figure 17-6.
CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(Toggle)
Period
(COMnA1:0 = 1)
1
2
3
4
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or
ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler
routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when
the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is
not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 =
15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform
generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform
frequency is defined by the following equation:
f clk_I/O
f OCnA = --------------------------------------------------2  N   1 + OCRnA 
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
17.9.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation.
The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode,
the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM.
In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the singleslope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and
phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM
mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The
minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or
OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log  TOP + 1 
R FPWM = ----------------------------------log  2 
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In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A
(WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 17-7. The figure shows fast PWM mode when OCR1A or ICR1 is used to define
TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
compare match occurs.
Figure 17-7.
Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1
Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP
value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and
compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1
Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with
none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of
TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will
then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can
occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written
anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The
OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle
the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the
TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the
COM1x1:0 bits to two will produce a inverted PWM and an non-inverted PWM output can be generated by setting
the COM1x1:0 to three (see Table 17-3 on page 129). The actual OC1x value will only be visible on the port pin if
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the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or
clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the
OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------------------------N   1 + TOP 
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending
on the polarity of the output set by the COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle
its logical level on each compare match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP
value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A
is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of
the Output Compare unit is enabled in the fast PWM mode.
17.9.4 Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a
high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase
and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from
BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is
16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log  TOP + 1 
R PCPWM = ----------------------------------log  2 
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed
values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in
OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1
value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 17-8 on page 123. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define
TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes
represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare
match occurs.
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Figure 17-8.
Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or
ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as
the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to
generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 17-8 on page
123 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result
in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since
the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the
falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new
TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length
gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when
changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no
differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting
the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM1x1:0 to three (See Table 17-3 on page 129). The actual OC1x value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting
(or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments,
and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter
decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
f clk_I/O
f OCnxPCPWM = ---------------------------2  N  TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
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The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the
OC1A output will toggle with a 50% duty cycle.
17.9.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0
= 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase
and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting
Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and
OCR1x while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode,
the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the
single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the
OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 17-8 on page 123 and Figure 17-9 on page
125).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit
(ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation:
log  TOP + 1 
R PFCPWM = ----------------------------------log  2 
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the
value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and
changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram
for the phase correct and frequency correct PWM mode is shown on Figure 17-9 on page 125. The figure shows
phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches
between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs.
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Figure 17-9.
Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated
with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the
OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an
interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT1 and the OCR1x.
As Figure 17-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods.
Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be
equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x
pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be
generated by setting the COM1x1:0 to three (See Table 17-3 on page 129). The actual OC1x value will only be
visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is
generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the
counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1
when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM
can be calculated by the following equation:
f clk_I/O
f OCnxPFCPWM = ---------------------------2  N  TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the
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opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A
output will toggle with a 50% duty cycle.
17.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x
Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 17-10 shows a
timing diagram for the setting of OCF1x.
Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 17-11 shows the same timing data, but with the prescaler enabled.
Figure 17-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 17-12 on page 127 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same,
but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for
modes that set the TOV1 Flag at BOTTOM.
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Figure 17-12. Timer/Counter Timing Diagram, no Prescaling.
clkI/O
clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
New OCRnx Value
Old OCRnx Value
Figure 17-13 shows the same timing data, but with the prescaler enabled.
Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
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17.11 Register Description
17.11.1 TCCR1A – Timer/Counter1 Control Register A
Bit
7
6
5
4
3
2
1
0
(0x80)
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one
or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O
pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal
port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0
bits setting. Table 17-1 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC
mode (non-PWM).
Table 17-1.
Compare Output Mode, non-PWM
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
Toggle OC1A/OC1B on Compare Match.
1
0
Clear OC1A/OC1B on Compare Match (Set output to low level).
1
1
Set OC1A/OC1B on Compare Match (Set output to high level).
Table 17-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Compare Output Mode, Fast PWM(1)
Table 17-2.
COM1A1/COM1B1
COM1A0/COM1B0
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM
(non-inverting mode)
1
1
Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM
(inverting mode)
Note:
1.
Description
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare
match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on page 120 for more details.
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Table 17-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase
and frequency correct, PWM mode.
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
Table 17-3.
COM1A1/COM1B1
COM1A0/COM1B0
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 9 or 11: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on Compare Match when up-counting. Set
OC1A/OC1B on Compare Match when down-counting.
1
1
Set OC1A/OC1B on Compare Match when up-counting. Clear
OC1A/OC1B on Compare Match when down-counting.
Note:
1.
Description
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See ”Phase Correct
PWM Mode” on page 122 for more details.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 17-4. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ”Modes of
Operation” on page 119).
Table 17-4.
Waveform Generation Mode Bit Description(1)
Mode
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation
TOP
Update of
OCR1x at
TOV1 Flag
Set on
0
0
0
0
0
Normal
0xFFFF
Immediate
MAX
1
0
0
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
0
1
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
0
CTC
OCR1A
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
BOTTOM
TOP
6
0
1
1
0
Fast PWM, 9-bit
0x01FF
BOTTOM
TOP
7
0
1
1
1
Fast PWM, 10-bit
0x03FF
BOTTOM
TOP
8
1
0
0
0
PWM, Phase and Frequency
Correct
ICR1
BOTTOM
BOTTOM
9
1
0
0
1
PWM, Phase and Frequency
Correct
OCR1A
BOTTOM
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICR1
TOP
BOTTOM
11
1
0
1
1
PWM, Phase Correct
OCR1A
TOP
BOTTOM
12
1
1
0
0
CTC
ICR1
Immediate
MAX
13
1
1
0
1
(Reserved)
–
–
–
14
1
1
1
0
Fast PWM
ICR1
BOTTOM
TOP
15
1
1
1
1
Fast PWM
OCR1A
BOTTOM
TOP
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Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
17.11.2 TCCR1B – Timer/Counter1 Control Register B
Bit
7
6
5
4
3
2
1
0
(0x81)
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input
from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of
the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the
noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1
bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising
(positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture
Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input
Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the
TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Reserved
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 17-10 on page 126
and Figure 17-11 on page 126.
Table 17-5.
Clock Select Bit Description
CS12
CS11
CS10
Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clkI/O/1 (No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T1 pin. Clock on falling edge.
1
1
1
External clock source on T1 pin. Clock on rising edge.
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If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
17.11.3 TCCR1C – Timer/Counter1 Control Register C
Bit
7
6
5
4
3
2
1
(0x82)
FOC1A
FOC1B
–
–
–
–
–
0
–
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
TCCR1C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. When writing a
logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are
implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the
forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match
(CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.
17.11.4 TCNT1H and TCNT1L – Timer/Counter1
Bit
7
6
5
4
3
(0x85)
TCNT1[15:8]
(0x84)
TCNT1[7:0]
2
1
0
TCNT1H
TCNT1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
”Accessing 16-bit Registers” on page 110.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between
TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare
units.
17.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
Bit
7
6
5
4
3
(0x89)
OCR1A[15:8]
(0x88)
OCR1A[7:0]
2
1
0
OCR1AH
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
17.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
Bit
7
6
5
4
(0x8B)
OCR1B[15:8]
(0x8A)
OCR1B[7:0]
OCR1BH
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High
Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing 16-bit
Registers” on page 110.
17.11.7 ICR1H and ICR1L – Input Capture Register 1
Bit
7
6
5
4
3
(0x87)
ICR1[15:8]
(0x86)
ICR1[7:0]
2
1
0
ICR1H
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or
optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing 16-bit Registers” on
page 110.
17.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
(0x6F)
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK1
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page
55) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Reserved
These bits are unused bits in the ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 55) is executed when the OCF1B Flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 55) is executed when the OCF1A Flag, located in TIFR1, is set.
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• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See ”Interrupts” on page 55) is
executed when the TOV1 Flag, located in TIFR1, is set.
17.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
0x16 (0x36)
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIFR1
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the
WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be
cleared by writing a logic one to its bit location.
• Bit 4, 3 – Reserved
These bits are unused bits in the ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B
(OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively,
OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A
(OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively,
OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set
when the timer overflows. Refer to Table 17-4 on page 129 for the TOV1 Flag behavior when using another
WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1
can be cleared by writing a logic one to its bit location.
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18.
Timer/Counter0 and Timer/Counter1 Prescalers
The ”8-bit Timer/Counter0 with PWM” on page 90 and ”16-bit Timer/Counter1 with PWM” on page 108 share the
same prescaler module, but the Timer/Counters can have different prescaler settings. The description below
applies to both Timer/Counter1 and Timer/Counter0.
18.1
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the
fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a
frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.
18.2
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter, and it is
shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock
select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example
of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.
18.3
External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin
is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is
then passed through the edge detector. Figure 18-1 shows a functional equivalent block diagram of the T1/T0
synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock
(clkI/O). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.
Figure 18-1.
T1/T0 Pin Sampling
Tn
D
Q
D
Q
D
Tn_sync
(To Clock
Select Logic)
Q
LE
clk I/O
Synchronization
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct
sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk <
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fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external
clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the
system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances,
it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 18-2.
Prescaler for Timer/Counter0 and Timer/Counter1(1)
clk I/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clkT1
Note:
clkT0
1. The synchronization logic on the input pins (T1/T0) is shown in Figure 18-1 on page 134.
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18.4
Register Description
18.4.1 GTCCR – General Timer/Counter Control Register
Bit
7
6
5
4
3
2
1
0
0x23 (0x43)
TSM
–
–
–
–
–
PSRASY
PSRSYNC
Read/Write
R/W
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is
written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals
asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value
without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY
and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the
same prescaler and a reset of this prescaler will affect both timers.
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19.
8-bit Timer/Counter2 with PWM and Asynchronous Operation
19.1
Features
Single Channel Counter

Clear Timer on Compare Match (Auto Reload)

Glitch-free, Phase Correct Pulse Width Modulator (PWM)

Frequency Generator

10-bit Clock Prescaler

Overflow and Compare Match Interrupt Sources (TOV2, OCF2A, and OCF2B)

Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of
the 8-bit Timer/Counter is shown in Figure 19-1. For the actual placement of I/O pins, refer to ”Pinout
ATmega48PB/88PB/168PB” on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in
bold. The device-specific I/O Register and bit locations are listed in the ”Register Description” on page 150.
The PRTIM2 bit in ”Minimizing Power Consumption” on page 39 must be written to zero to enable Timer/Counter2
module.
Figure 19-1.
8-bit Timer/Counter Block Diagram
Count
Clear
Direction
TOVn
(Int.Req.)
Control Logic
Clock Select
clkTn
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
=0
OCnA
(Int.Req.)
Waveform
Generation
=
OCnA
OCRnA
DATA BUS
19.2

Fixed
TOP
Value
OCnB
(Int.Req.)
Waveform
Generation
=
OCnB
OCRnB
TCCRnA
TCCRnB
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19.2.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt
request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment (or
decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock
Select logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable
frequency output on the Output Compare pins (OC2A and OC2B). See ”Output Compare Unit” on page 139 for
details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to
generate an Output Compare interrupt request.
19.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in Table 19-1 are also used extensively throughout the section.
Table 19-1.
BOTTOM
MAX
TOP
19.3
Definitions
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the
OCR2A Register. The assignment is dependent on the mode of operation.
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to
logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see ”ASSR – Asynchronous Status Register” on page 156. For details on clock
sources and prescaler, see ”Timer/Counter Prescaler” on page 149.
19.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 19-2 shows a
block diagram of the counter and its surrounding environment.
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Figure 19-2.
Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
TOSC1
count
TCNTn
clear
clk Tn
Control Logic
Prescaler
T/C
Oscillator
direction
bottom
TOSC2
clkI/O
top
Signal description (internal signals):
count
Increment or decrement TCNT2 by 1.
direction
Selects between increment and decrement.
clear
Clear TCNT2 (set all bits to zero).
clkTn
Timer/Counter clock, referred to as clkT2 in the following.
top
Signalizes that TCNT2 has reached maximum value.
bottom
Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be
accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter
Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the
Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform
generation, see ”Modes of Operation” on page 142.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits.
TOV2 can be used for generating a CPU interrupt.
19.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B).
Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output
Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the
Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared
when the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a
logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according
to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom
signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes
of operation (”Modes of Operation” on page 142).
Figure 19-3 on page 140 shows a block diagram of the Output Compare unit.
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Figure 19-3.
Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator
OCnx
FOCn
WGMn1:0
COMnX1:0
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x
directly.
19.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the
timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings
define whether the OC2x pin is set, cleared or toggled).
19.5.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2
without triggering an interrupt when the Timer/Counter clock is enabled.
19.5.3 Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the
Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM
when the counter is downcounting.
The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal
mode. The OC2x Register keeps its value even when changing between Waveform Generation modes.
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Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the
COM2x1:0 bits will take effect immediately.
19.6
Compare Match Output Unit
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0
bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the
OC2x pin output source. Figure 19-4 shows a simplified schematic of the logic affected by the COM2x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the
OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.
Figure 19-4.
Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCnx
Waveform
Generator
D
Q
1
OCnx
DATA BUS
D
0
OCnx
Pin
Q
PORT
D
Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either
of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be
set as output before the OC2x value is visible on the pin. The port override function is independent of the
Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled.
Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on
page 150.
19.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes,
setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 19-5 on page 151. For
fast PWM mode, refer to Table 19-6 on page 151, and for phase correct PWM refer to Table 19-7 on page 152.
A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits.
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19.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a
compare match (See ”Compare Match Output Unit” on page 141).
For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 146.
19.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
19.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The
OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the
compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 19-5. The counter value (TCNT2) increases until a
compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared.
Figure 19-5.
CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCnx
(Toggle)
Period
(COMnx1:0 = 1)
1
2
3
4
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower
than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will
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not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by
the following equation:
f clk_I/O
f OCnx = -------------------------------------------------2  N   1 + OCRnx 
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
19.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency PWM
waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The
counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on
the compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the
output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope
operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), and therefore
reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 19-6. The
TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent
compare matches between OCR2x and TCNT2.
Figure 19-6.
Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. (See Table
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19-3 on page 150). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match
between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = -----------------N  256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM2A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle
its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency
of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the
double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
19.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform
generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts
repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when MGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on
the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower
maximum operation frequency than single slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 19-7 on page 145. The TCNT2 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches
between OCR2x and TCNT2.
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Figure 19-7.
Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 19-4
on page 151). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between
OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match
between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase
correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = -----------------N  510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
Note:
1. At the very start of period 2 in Figure 19-7 OCnx has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.
•
OCR2A changes its value from MAX, like in Figure 19-7. When the OCR2A value is MAX the OCn pin value
is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the
OCn value at MAX must correspond to the result of an up-counting Compare Match.
•
The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the
Compare Match and hence the OCn change that would have happened on the way up.
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19.8
Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown
as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock.
The figures include information on when Interrupt Flags are set. Figure 19-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than
phase correct PWM mode.
Figure 19-8.
Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 19-9 shows the same timing data, but with the prescaler enabled.
Figure 19-9.
Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 19-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 19-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 19-11 on page 147 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
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Figure 19-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
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19.9
Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
1.
Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is:
1.1.
Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
1.1.1.Select clock source by setting AS2 as appropriate.
1.1.2.Write new values to TCNT2, OCR2x, and TCCR2x.
1.1.3.To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.
1.1.4.Clear the Timer/Counter2 Interrupt Flags.
1.1.5.Enable interrupts, if needed.
2.
The CPU main clock frequency must be more than four times the Oscillator frequency.
3.
When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary
register, and latched after two positive edges on TOSC1. The user should not write a new value before the
contents of the temporary register have been transferred to its destination. Each of the five mentioned
registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an
OCR2x write in progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented.
4.
When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or
TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up
the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly
important if any of the Output Compare2 interrupt is used to wake up the device, since the Output Compare
function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters
sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare
match interrupt, and the MCU will not wake up.
5.
If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode,
precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode within
the TOSC1 cycle, the interrupt will immediately occur and the device wake up again. The result is multiple
interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt whether the
time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can
be used to ensure that one TOSC1 cycle has elapsed:
5.1.
Write a value to TCCR2x, TCNT2, or OCR2x.
5.1.1.Wait until the corresponding Update Busy Flag in ASSR returns to zero.
5.1.2.Enter Power-save or ADC Noise Reduction mode.
6.
When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always
running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down
or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second
to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up
or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be
considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon startup, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
7.
Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor can read the
counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
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8.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since
TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register
synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge.
When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as
the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock
after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
8.1.
Wait for the corresponding Update Busy Flag to be cleared.
8.2.
Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes
3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can
read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer
clock and is not synchronized to the processor clock.
19.10 Timer/Counter Prescaler
Figure 19-12. Prescaler for Timer/Counter2
PSRASY
clkT2S/1024
clkT2S/256
clkT2S/128
AS2
clkT2S/64
10-BIT T/C PRESCALER
Clear
clkT2S/32
TOSC1
clkT2S
clkT2S/8
clkI/O
0
CS20
CS21
CS22
TIMER/COUNTER2 CLOCK SOURCE
clkT2
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock
clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This
enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are
disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an
independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and
clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the
prescaler. This allows the user to operate with a predictable prescaler.
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19.11 Register Description
19.11.1 TCCR2A – Timer/Counter Control Register A
Bit
7
6
5
4
3
2
1
0
(0xB0)
COM2A1
COM2A0
COM2B1
COM2B0
–
–
WGM21
WGM20
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR2A
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the
OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting.
Table 19-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (nonPWM).
Table 19-2.
Compare Output Mode, non-PWM Mode
COM2A1
COM2A0
Description
0
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC2A on Compare Match
1
0
Clear OC2A on Compare Match
1
1
Set OC2A on Compare Match
Table 19-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Compare Output Mode, Fast PWM Mode(1)
Table 19-3.
COM2A1
COM2A0
0
0
Normal port operation, OC2A disconnected.
0
1
WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1
0
Clear OC2A on Compare Match, set OC2A at BOTTOM,
(non-inverting mode).
1
1
Set OC2A on Compare Match, clear OC2A at BOTTOM,
(inverting mode).
Note:
1.
Description
A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on page 143 for more details.
Table 19-4 on page 151 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct
PWM mode.
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Compare Output Mode, Phase Correct PWM Mode(1)
Table 19-4.
COM2A1
COM2A0
0
0
Normal port operation, OC2A disconnected.
0
1
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1
0
Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match
when down-counting.
1
1
Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match
when down-counting.
Note:
1.
Description
A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 144 for more details.
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the
OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting.
Table 19-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (nonPWM).
Table 19-5.
Compare Output Mode, non-PWM Mode
COM2B1
COM2B0
Description
0
0
Normal port operation, OC2B disconnected.
0
1
Toggle OC2B on Compare Match
1
0
Clear OC2B on Compare Match
1
1
Set OC2B on Compare Match
Table 19-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode.
Compare Output Mode, Fast PWM Mode(1)
Table 19-6.
COM2B1
COM2B0
0
0
Normal port operation, OC2B disconnected.
0
1
Reserved
1
0
Clear OC2B on Compare Match, set OC2B at BOTTOM,
(non-inverting mode).
1
1
Set OC2B on Compare Match, clear OC2B at BOTTOM,
(inverting mode).
Note:
1.
Description
A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See ”Phase Correct PWM Mode” on page 144 for more details.
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Table 19-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode.
Compare Output Mode, Phase Correct PWM Mode(1)
Table 19-7.
COM2B1
COM2B0
0
0
Normal port operation, OC2B disconnected.
0
1
Reserved
1
0
Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match
when down-counting.
1
1
Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match
when down-counting.
Note:
1.
Description
A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 144 for more details.
• Bits 3:2 – Reserved
These bits are reserved in the ATmega48PB/88PB/168PB and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 19-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see ”Modes of Operation”
on page 142).
Table 19-8.
Waveform Generation Mode Bit Description
Timer/Counter Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
0
Normal
0xFF
Immediate
MAX
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
BOTTOM
MAX
4
1
0
0
Reserved
–
–
–
5
1
0
1
PWM, Phase Correct
OCRA
TOP
BOTTOM
6
1
1
0
Reserved
–
–
–
7
1
1
1
Fast PWM
OCRA
BOTTOM
TOP
Mode
WGM22
WGM21
WGM20
0
0
0
1
0
2
Notes:
1.
2.
MAX= 0xFF
BOTTOM= 0x00
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19.11.2 TCCR2B – Timer/Counter Control Register B
Bit
7
6
5
4
3
2
1
0
(0xB1)
FOC2A
FOC2B
–
–
WGM22
CS22
CS21
CS20
Read/Write
W
W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR2B
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the
FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the
effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when
operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the
FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the
effect of the forced compare.
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 3 – WGM22: Waveform Generation Mode
See the description in the ”TCCR2A – Timer/Counter Control Register A” on page 150.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 19-9.
Table 19-9.
Clock Select Bit Description
CS22
CS21
CS20
Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clkT2S/(No prescaling)
0
1
0
clkT2S/8 (From prescaler)
0
1
1
clkT2S/32 (From prescaler)
1
0
0
clkT2S/64 (From prescaler)
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Table 19-9.
Clock Select Bit Description
CS22
CS21
CS20
Description
1
0
1
clkT2S/128 (From prescaler)
1
1
0
clkT2S/256 (From prescaler)
1
1
1
clkT2S/1024 (From prescaler)
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
19.11.3 TCNT2 – Timer/Counter Register
Bit
7
6
5
4
(0xB2)
3
2
1
0
TCNT2[7:0]
TCNT2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock.
Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match
between TCNT2 and the OCR2x Registers.
19.11.4 OCR2A – Output Compare Register A
Bit
7
6
5
4
(0xB3)
3
2
1
0
OCR2A[7:0]
OCR2A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2A pin.
19.11.5 OCR2B – Output Compare Register B
Bit
7
6
5
4
(0xB4)
3
2
1
0
OCR2B
OCR2B[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2B pin.
19.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
(0x70)
–
–
–
–
–
OCIE2B
OCIE2A
TOIE2
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK2
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2
Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
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• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2
Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the
TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.
19.11.7 TIFR2 – Timer/Counter2 Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
0x17 (0x37)
–
–
–
–
–
OCF2B
OCF2A
TOV2
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIFR2
• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B –
Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B
(Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A –
Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the
flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes
counting direction at 0x00.
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19.11.8 ASSR – Asynchronous Status Register
Bit
7
6
5
4
3
2
1
0
(0xB6)
–
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
Read/Write
R
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
ASSR
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and
an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK
should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this
bit is zero.
• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one,
Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the
value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that OCR2A is ready to be updated with a new value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2A is ready to be updated with a new value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2B is ready to be updated with a new value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated
value might get corrupted and cause an unintentional interrupt to occur.
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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading
TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the
temporary storage register is read.
19.11.9 GTCCR – General Timer/Counter Control Register
Bit
7
6
5
4
3
2
1
0
0x23 (0x43)
TSM
–
–
–
–
–
PSRASY
PSRSYNC
Read/Write
R/W
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
GTCCR
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by
hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until
the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description
of the ”Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 136 for a description of the Timer/Counter
Synchronization mode.
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20.
SPI – Serial Peripheral Interface
20.1
Features
Full-duplex, Three-wire Synchronous Data Transfer

Master or Slave Operation

LSB First or MSB First Data Transfer

Seven Programmable Bit Rates

End of Transmission Interrupt Flag

Write Collision Flag Protection

Wake-up from Idle Mode

Double Speed (CK/2) Master SPI Mode
Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega48PB/88PB/168PB and peripheral devices or between several AVR devices.
The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 196. The PRSPI bit in
”Minimizing Power Consumption” on page 39 must be written to zero to enable SPI module.
Figure 20-1.
SPI Block Diagram(1)
DIVIDER
/2/4/8/16/32/64/128
SPI2X
SPI2X
20.2

Note:
1. Refer to Figure 2-1 on page 3, and Table 15-3 on page 79 for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 20-2 on page 159. The system
consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle
when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in
their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange
data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to
Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by
pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by
user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the
SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock
generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer
Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is
driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not
be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been
completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR
Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 20-2.
SPI Master-slave Interconnection
SHIFT
ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that
bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When
receiving data, however, a received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of
the clock signal, the minimum low and high periods should be:
Low periods: Longer than two CPU clock cycles.
High periods: Longer than two CPU clock cycles.
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 20-1 on page 160. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page
77.
Table 20-1.
Pin
SPI Pin Overrides(1)
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
Note:
1.
See ”Alternate Functions of Port B” on page 79 for a detailed description of how to define the direction of the user
defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins.
DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI
is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
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Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi
r17,(1<<DD_MOSI)|(1<<DD_SCK)
out
DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out
SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out
SPDR,r16
Wait_Transmit:
; Wait for transmission complete
in
r16, SPSR
sbrs
r16, SPIF
rjmp
Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
Note:
1.
See ”About Code Examples” on page 7.
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output,
ldi
out
; Enable SPI
ldi
out
ret
all others input
r17,(1<<DD_MISO)
DDR_SPI,r17
r17,(1<<SPE)
SPCR,r17
SPI_SlaveReceive:
; Wait for reception complete
in r16, SPSR
sbrs r16, SPIF
rjmp
SPI_SlaveReceive
; Read received data and return
in
r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return Data Register */
return SPDR;
}
Note:
1.
See ”About Code Examples” on page 7.
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20.3
SS Pin Functionality
20.3.1 Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is
activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven
high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the
SPI logic will be reset once the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master
clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic,
and drop any partially received data in the Shift Register.
20.3.2 Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the
pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by
peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system
interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus
contention, the SPI system takes the following actions:
1.
2.
The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a
Slave, the MOSI and SCK pins become inputs.
The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt
routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is
driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a
slave select, it must be set by the user to re-enable SPI Master mode.
20.4
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 20-3 on page 164 and Figure 20-4 on
page 164. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for
data signals to stabilize. This is clearly seen by summarizing Table 20-3 on page 165 and Table 20-4 on page 165,
as done in Table 20-2.
Table 20-2.
SPI Modes
SPI Mode
Conditions
Leading Edge
Trailing Edge
0
CPOL=0, CPHA=0
Sample (Rising)
Setup (Falling)
1
CPOL=0, CPHA=1
Setup (Rising)
Sample (Falling)
2
CPOL=1, CPHA=0
Sample (Falling)
Setup (Rising)
3
CPOL=1, CPHA=1
Setup (Falling)
Sample (Rising)
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Figure 20-3.
SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD = 1) LSB
Figure 20-4.
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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20.5
Register Description
20.5.1 SPCR – SPI Control Register
Bit
7
6
5
4
3
2
1
0
0x2C (0x4C)
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global
Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is
configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become
set. The user will then have to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer
to Figure 20-3 on page 164 and Figure 20-4 on page 164 for an example. The CPOL functionality is summarized
below:
Table 20-3.
CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge
of SCK. Refer to Figure 20-3 on page 164 and Figure 20-4 on page 164 for an example. The CPOL functionality is
summarized below:
Table 20-4.
CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the
Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in Table 20-5 on page 166.
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Table 20-5.
Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SCK Frequency
fosc/4
fosc/16
fosc/64
fosc/128
fosc/2
fosc/8
fosc/32
fosc/64
20.5.2 SPSR – SPI Status Register
Bit
7
6
5
4
3
2
1
0
0x2D (0x4D)
SPIF
WCOL
–
–
–
–
–
SPI2X
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global
interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF
Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register
(SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF
bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
• Bit [5:1] – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode
(see Table 20-5 on page 166). This means that the minimum SCK period will be two CPU clock periods. When the
SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower.
The SPI interface on the ATmega48PB/88PB/168PB is also used for program memory and EEPROM downloading
or uploading. See ”Serial Downloading” on page 296 for serial programming and verification.
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20.5.3 SPDR – SPI Data Register
Bit
7
0x2E (0x4E)
MSB
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
LSB
SPDR
Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift
Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive
buffer to be read.
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21.
USART0
21.1
Features
21.2

Full Duplex Operation (Independent Serial Receive and Transmit Registers)

Asynchronous or Synchronous Operation

Master or Slave Clocked Synchronous Operation

High Resolution Baud Rate Generator

Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

Odd or Even Parity Generation and Parity Check Supported by Hardware

Data OverRun Detection

Framing Error Detection

Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

Multi-processor Communication Mode

Double Speed Asynchronous Communication Mode

Start Frame Detection
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial
communication device.
The USART0 can also be used in Master SPI mode, see “USART in SPI Mode” on page 196. The Power
Reduction USART bit, PRUSART0, in ”Minimizing Power Consumption” on page 39 must be disabled by writing a
logical zero to it.
A simplified block diagram of the USART Transmitter is shown in Figure 21-1 on page 169. CPU accessible I/O
Registers and I/O pins are shown in bold.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock
Generator, Transmitter, and Receiver. Control Registers are shared by all units. The Clock Generation logic
consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate
generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of
a single write buffer, a serial Shift Register, Parity Generator, and Control logic for handling different serial frame
formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is
the most complex part of the USART module due to its clock and data recovery units. The recovery units are used
for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control
logic, a Shift Register, and a two level receive buffer (UDRn). The Receiver supports the same frame formats as
the Transmitter, and can detect Frame Error, Data OverRun, and Parity Errors.
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Figure 21-1.
USART Block Diagram(1)
Clock Generator
UBRRn [H:L]
OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN
CONTROL
XCKn
Transmitter
TX
CONTROL
DATA BUS
UDRn(Transmit)
PARITY
GENERATOR
21.3
TxDn
Receiver
UCSRnA
Note:
PIN
CONTROL
TRANSMIT SHIFT REGISTER
CLOCK
RECOVERY
RX
CONTROL
RECEIVE SHIFT REGISTER
DATA
RECOVERY
PIN
CONTROL
UDRn (Receive)
PARITY
CHECKER
UCSRnB
RxDn
UCSRnC
1. Refer to Figure 2-1 on page 3 and Table 15-9 on page 84 for USART0 pin placement.
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four
modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave
synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between
asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn
found in the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the
XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The
XCKn pin is only active when using synchronous mode.
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Figure 21-2 shows a block diagram of the clock generation logic.
Figure 21-2.
Clock Generation Logic, Block Diagram
UBRRn
U2Xn
foscn
Prescaling
Down-Counter
UBRRn+1
/2
/4
/2
0
1
0
OSC
DDR_XCKn
xcki
XCKn
Pin
Sync
Register
Edge
Detector
0
UCPOLn
txclk
UMSELn
1
xcko
DDR_XCKn
1
1
0
rxclk
Signal description:
txclkTransmitter clock (Internal Signal).
rxclkReceiver base clock (Internal Signal).
xckiInput from XCK pin (internal Signal). Used for synchronous slave operation.
xckoClock output to XCK pin (Internal Signal). Used for synchronous master operation.
foscSystem clock frequency.
21.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The
description in this section refers to Figure 21-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable
prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value
each time the counter has counted down to zero or when the UBRRnL Register is written. A clock is generated
each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The
Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate
generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use
a state machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSELn, U2Xn and
DDR_XCKn bits.
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Table 21-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn
value for each mode of operation using an internally generated clock source.
Table 21-1.
Equations for Calculating Baud Rate Register Setting
Equation for Calculating Baud Rate(1)
Equation for Calculating UBRRn Value
Asynchronous Normal mode
(U2Xn = 0)
f OSC
BAUD = -----------------------------------------16  UBRRn + 1 
f OSC
UBRRn = ------------------------ – 1
16BAUD
Asynchronous Double Speed
mode (U2Xn = 1)
f OSC
BAUD = --------------------------------------8  UBRRn + 1 
f OSC
UBRRn = -------------------- – 1
8BAUD
Synchronous Master mode
f OSC
BAUD = --------------------------------------2  UBRRn + 1 
f OSC
UBRRn = -------------------- – 1
2BAUD
Operating Mode
Note:
1.
The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
Baud rate (in bits per second, bps)
fOSC
System Oscillator clock frequency
UBRRn
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 21-6 on page 186.
21.3.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the
asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication. Note however that the Receiver will in this case only use half the number of
samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate
setting and system clock are required when this mode is used. For the Transmitter, there are no downsides.
21.3.3 External Clock
External clocking is used by the synchronous slave modes of operation. The description in this section refers to
Figure 21-2 on page 170 for details.
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External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of metastability. The output from the synchronization register must then pass through an edge detector before it can be
used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the
maximum external XCKn clock frequency is limited by the following equation:
f OSC
f XCK  ----------4
Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin
to avoid possible loss of data due to frequency variations.
21.3.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock
output (Master). The dependency between the clock edges and data sampling or data change is the same. The
basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output
(TxDn) is changed.
Figure 21-3.
Synchronous Mode XCKn Timing.
UCPOL = 1
XCK
RxD / TxD
Sample
XCK
UCPOL = 0
RxD / TxD
Sample
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data
change. As Figure 21-3 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled
at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn
edge.
21.4
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and
optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame
formats:
•
1 start bit
•
5, 6, 7, 8, or 9 data bits
•
no, even or odd parity bit
•
1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 21-4 on page 173 illustrates the possible combinations
of the frame formats. Bits inside brackets are optional.
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Figure 21-4.
Frame Formats
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St
Start bit, always low.
(n)
Data bits (0 to 8).
P
Parity bit. Can be odd or even.
Sp
Stop bit, always high.
IDLE
No transfers on the communication line (RxDn or TxDn). An IDLE line must be high.
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and
UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits
will corrupt all ongoing communication for both the Receiver and Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode
(UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the
USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore
only be detected in the cases where the first stop bit is zero.
21.4.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the
exclusive or is inverted. The relation between the parity bit and data bits is as follows:
P even = d n – 1    d 3  d 2  d 1  d 0  0
P odd = d n – 1    d 3  d 2  d 1  d 0  1
Peven
Parity bit using even parity
Podd
Parity bit using odd parity
dn
Data bit n of the character
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
21.5
USART Initialization
The USART has to be initialized before any communication can take place. The initialization process normally
consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on
the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts
globally disabled) when doing the initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing
transmissions during the period the registers are changed. The TXCn Flag can be used to check that the
Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data in
the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it
is used for this purpose.
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The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed
frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is
assumed to be stored in the r17:r16 Registers.
Assembly Code Example(1)
USART_Init:
; Set baud rate
out
UBRRnH, r17
out
UBRRnL, r16
; Enable receiver and transmitter
ldi
r16, (1<<RXENn)|(1<<TXENn)
out
UCSRnB,r16
; Set frame format: 8data, 2stop bit
ldi
r16, (1<<USBSn)|(3<<UCSZn0)
out
UCSRnC,r16
ret
C Code Example(1)
#define FOSC 1843200 // Clock Speed
#define BAUD 9600
#define MYUBRR FOSC/16/BAUD-1
void main( void )
{
...
USART_Init(MYUBRR)
...
}
void USART_Init( unsigned int ubrr)
{
/*Set baud rate */
UBRR0H = (unsigned char)(ubrr>>8);
UBRR0L = (unsigned char)ubrr;
Enable receiver and transmitter */
UCSR0B = (1<<RXEN0)|(1<<TXEN0);
/* Set frame format: 8data, 2stop bit */
UCSR0C = (1<<USBS0)|(3<<UCSZ00);
}
Note:
1. See ”About Code Examples” on page 7.
More advanced initialization routines can be made that include frame format as parameters, disable interrupts and
so on. However, many applications use a fixed setting of the baud and control registers, and for these types of
applications the initialization code can be placed directly in the main routine, or be combined with initialization code
for other I/O modules.
21.6
Data Transmission – The USART Transmitter
The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the
Transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the
function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once
before doing any transmissions. If synchronous operation is used, the clock on the XCKn pin will be overridden and
used as transmission clock.
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21.6.1 Sending Frames with 5 to 8 Data Bits
A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the
transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the
Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it
is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted.
When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud
Register, U2Xn bit or by XCKn depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the Data Register Empty
(UDREn) Flag. When using frames with less than eight bits, the most significant bits written to the UDRn are
ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be
sent is assumed to be stored in Register R16.
Assembly Code Example(1)
USART_Transmit:
; Wait for empty transmit buffer
in r16, UCSRnA
sbrs r16, UDREn
rjmp
USART_Transmit
; Put data (r16) into buffer, sends the data
out
UDRn,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) )
;
/* Put data into buffer, sends the data */
UDRn = data;
}
Note:
1. See ”About Code Examples” on page 7.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with
new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into
the buffer.
21.6.2 Sending Frames with 9 Data Bit
If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low
byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit
characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
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Assembly Code Example(1)(2)
USART_Transmit:
; Wait for empty transmit buffer
in r16, UCSRnA
sbrs r16, UDREn
rjmp
USART_Transmit
; Copy 9th bit from r17 to TXB8
cbi
UCSRnB,TXB8
sbrc
r17,0
sbi
UCSRnB,TXB8
; Put LSB data (r16) into buffer, sends the data
out
UDRn,r16
ret
C Code Example(1)(2)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn))) )
;
/* Copy 9th bit to TXB8 */
UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRnB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDRn = data;
}
Notes:
1.
2.
These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRnB
is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization.
See ”About Code Examples” on page 7.
The ninth bit can be used for indicating an address frame when using multi processor communication mode or for
other protocol handling as for example synchronization.
21.6.3 Transmitter Flags and Interrupts
The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit
Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit
is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that
has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero
when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data
Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled).
UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty
interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty
interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been
shifted out and there are no new data currently present in the transmit buffer. The TXCn Flag bit is automatically
cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The
TXCn Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where a transmitting
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application must enter receive mode and free the communication bus immediately after completing the
transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART Transmit Complete
Interrupt will be executed when the TXCn Flag becomes set (provided that global interrupts are enabled). When
the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXCn Flag, this is
done automatically when the interrupt is executed.
21.6.4 Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), the
transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent.
21.6.5 Disabling the Transmitter
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending
transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain
data to be transmitted. When disabled, the Transmitter will no longer override the TxDn pin.
21.7
Data Reception – The USART Receiver
The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When
the Receiver is enabled, the normal pin operation of the RxDn pin is overridden by the USART and given the
function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once
before any serial reception can be done. If synchronous operation is used, the clock on the XCKn pin will be used
as transfer clock.
21.7.1 Receiving Frames with 5 to 8 Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled
at the baud rate or XCKn clock, and shifted into the Receive Shift Register until the first stop bit of a frame is
received. A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e., a complete
serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the
receive buffer. The receive buffer can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the Receive Complete
(RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn
will be masked to zero. The USART has to be initialized before the function can be used.
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Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
in r16, UCSRnA
sbrs r16, UDREn
rjmp
USART_Receive
; Get and return received data from buffer
in
r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get and return received data from buffer */
return UDRn;
}
Note:
1.
See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading
the buffer and returning the value.
21.7.2 Receiving Frames with 9 Data Bits
If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading
the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Status Flags as well. Read status from
UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO
and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change.
The following code example shows a simple USART receive function that handles both nine bit characters and the
status bits.
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Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
in r16, UCSRnA
sbrs r16, RXCn
rjmp
USART_Receive
; Get status and 9th bit, then data from buffer
in
r18, UCSRnA
in
r17, UCSRnB
in
r16, UDRn
; If error, return -1
andi
r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
breq
USART_ReceiveNoError
ldi
r17, HIGH(-1)
ldi
r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr
r17
andi
r17, 0x01
ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRnA;
resh = UCSRnB;
resl = UDRn;
/* If error, return -1 */
if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
Note:
1.
See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
The receive function example reads all the I/O Registers into the Register File before any computation is done.
This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early
as possible.
21.7.3 Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one
when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any
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unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the
RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt
will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interruptdriven data reception is used, the receive complete routine must read the received data from UDRn in order to
clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
21.7.4 Receiver Error Flags
The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn).
All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer
together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the
UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer
read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the
flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future
USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive
buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the
stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions
and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver
ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when
writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs
when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last
read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to
zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If
Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set
this bit to zero when writing to UCSRnA. For more details see ”Parity Bit Calculation” on page 173 and Section
“Parity Checker”.
21.7.5 Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be
performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of
the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can
then be read by software to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is
read.
21.7.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will
therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal
function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining
data in the buffer will be lost.
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21.7.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its
contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an
error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how
to flush the receive buffer.
Assembly Code Example(1)
USART_Flush:
in r16, UCSRnA
sbrs r16, RXCn
ret
in
rjmp
r16, UDRn
USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}
Note:
21.8
1.
See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be
replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,
“SBRC”, “SBR”, and “CBR”.
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The
clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming
asynchronous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming
bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends
on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of
bits.
21.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 21-5 on page 181
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for
Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the
synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed
mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no
communication activity).
Figure 21-5.
Start Bit Sampling
RxD
IDLE
START
BIT 0
Sample
(U2X = 0)
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Sample
(U2X = 1)
0
1
2
3
4
5
6
7
8
1
2
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When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection
sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic
then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with
sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three
samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver
starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is
synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.
21.8.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a
state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode.
Figure 21-6 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is
equal to the state of the recovery unit.
Figure 21-6.
Sampling of Data and Parity Bit
RxD
BIT n
Sample
(U2X = 0)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample
(U2X = 1)
1
2
3
4
5
6
7
8
1
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. The center samples are emphasized on the figure by having the sample
number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels,
the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is
registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn
pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that
the Receiver only uses the first stop bit of a frame.
Figure 21-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame.
Figure 21-7.
Stop Bit Sampling and Next Start Bit Sampling
RxD
STOP 1
(A)
(B)
(C)
Sample
(U2X = 0)
1
2
3
4
5
6
7
8
9
10
0/1
0/1
0/1
Sample
(U2X = 1)
1
2
3
4
5
6
0/1
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to
have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 21-7 on
page 182. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The
early start bit detection influences the operational range of the Receiver.
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21.8.3 Asynchronous Operational Range
The operational range of the Receiver is dependent on the mismatch between the received bit rate and the
internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally
generated baud rate of the Receiver does not have a similar (see Table 21-2) base frequency, the Receiver will not
be able to synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate.
 D + 1 S
R slow = ------------------------------------------S – 1 + D  S + SF
 D + 2 S
R fast = ---------------------------------- D + 1 S + S M
DSum of character size and parity size (D = 5 to 10 bit)
SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.
SFFirst sample number used for majority voting. SF = 8 for normal speed and SF = 4
for Double Speed mode.
SMMiddle sample number used for majority voting. SM = 9 for normal speed and
SM = 5 for Double Speed mode.
Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be
accepted in relation to the receiver baud rate.
Table 21-2 and Table 21-3 on page 183 list the maximum receiver baud rate error that can be tolerated. Note that
Normal Speed mode has higher toleration of baud rate variations.
Table 21-2.
Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0)
D
# (Data+Parity Bit)
Rslow [%]
Rfast [%]
Max. Total Error [%]
Recommended Max.
Receiver Error [%]
5
93.20
106.67
+6.67/-6.8
±3.0
6
94.12
105.79
+5.79/-5.88
±2.5
7
94.81
105.11
+5.11/-5.19
±2.0
8
95.36
104.58
+4.58/-4.54
±2.0
9
95.81
104.14
+4.14/-4.19
±1.5
10
96.17
103.78
+3.78/-3.83
±1.5
Table 21-3.
Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1)
D
# (Data+Parity Bit)
Rslow [%]
Rfast [%]
Max Total Error [%]
Recommended Max Receiver
Error [%]
5
94.12
105.66
+5.66/-5.88
±2.5
6
94.92
104.92
+4.92/-5.08
±2.0
7
95.52
104,35
+4.35/-4.48
±1.5
8
96.00
103.90
+3.90/-4.00
±1.5
9
96.39
103.53
+3.53/-3.61
±1.5
10
96.70
103.23
+3.23/-3.30
±1.0
The recommendations of the maximum receiver baud rate error was made under the assumption that the Receiver
and Transmitter equally divides the maximum total error.
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There are two possible sources for the receivers baud rate error. The Receiver’s system clock (XTAL) will always
have some minor instability over the supply voltage range and the temperature range. When using a crystal to
generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2%
depending of the resonators tolerance. The second source for the error is more controllable. The baud rate
generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an
UBRRn value that gives an acceptable low error can be used if possible.
21.8.4 Start Frame Detection
The USART start frame detector can wake up the MCU from Power-down, Standby or ADC Noise Reduction sleep mode
when it detects a start bit.
When a high-to-low transition is detected on RxDn, the internal 8MHz oscillator is powered up and the USART clock is
enabled. After start-up the rest of the data frame can be received, provided that the baud rate is slow enough in relation
to the internal 8MHz oscillator start-up time. Start-up time of the internal 8MHz oscillator varies with supply voltage and
temperature.
The USART start frame detection works both in asynchronous and synchronous modes. It is enabled by writing the Start
Frame Detection Enable bit (SFDEn). If the USART Start Interrupt Enable (RXSIE) bit is set, the USART Receive Start
Interrupt is generated immediately when start is detected.
When using the feature without start interrupt, the start detection logic activates the internal 8MHz oscillator and the
USART clock while the frame is being received, only. Other clocks remain stopped until the Receive Complete Interrupt
wakes up the MCU.
The maximum baud rate in synchronous mode depends on the sleep mode the device is woken up from, as follows:
•
Idle or ADC Noise Reduction sleep mode: system clock frequency divided by four
•
Standby or Power-down: 500kbps
The maximum baud rate in asynchronous mode depends on the sleep mode the device is woken up from, as follows:
•
Idle sleep mode: the same as in active mode
Table 21-4.
Maximum Total Baudrate Error in Normal Speed Mode
Frame Size
Baudrate
5
6
7
8
9
10
0 - 28.8kbps
+6.67
-5.88
+5.79
-5.08
+5.11
-4.48
+4.58
-4.00
+4.14
-3.61
+3.78
-3.30
38.4kbps
+6.63
-5.88
+5.75
-5.08
+5.08
-4.48
+4.55
-4.00
+4.12
-3.61
+3.76
-3.30
57.6kbps
+6.10
-5.88
+5.30
-5.08
+4.69
-4.48
+4.20
-4.00
+3.80
-3.61
+3.47
-3.30
76.8kbps
+5.59
-5.88
+4.85
-5.08
+4.29
-4.48
+3.85
-4.00
+3.48
-3.61
+3.18
-3.30
115.2kbps
+4.57
-5.88
+3.97
-5.08
+3.51
-4.48
+3.15
-4.00
+2.86
-3.61
+2.61
-3.30
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Table 21-5.
Maximum Total Baudrate Error in Double Speed Mode
Frame Size
Baudrate
21.9
5
6
7
8
9
10
0 - 57.6kbps
+5.66
-4.00
+4.92
-3.45
+4.35
-3.03
+3.90
-2.70
+3.53
-2.44
+3.23
-2.22
76.8kbps
+5.59
-4.00
+4.85
-3.45
+4.29
-3.03
+3.85
-2.70
+3.48
-2.44
+3.18
-2.22
115.2kbps
+4.57
-4.00
+3.97
-3.45
+3.51
-3.03
+3.15
-2.70
+2.86
-2.44
+2.61
-2.22
Multi-processor Communication Mode
Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming
frames received by the USART Receiver. Frames that do not contain address information will be ignored and not
put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the
CPU, in a system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by
the MPCMn setting, but has to be used differently when it is a part of a system utilizing the Multi-processor
Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame
contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit
(RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is
one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This
is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU
has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the
received frames until another address frame is received.
21.9.1 Using MPCMn
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n)
must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXB = 0) is being transmitted. The
slave MCUs must in this case be set to use a 9-bit character frame format.
The following procedure should be used to exchange data in Multi-processor Communication mode:
1.
All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is set).
2.
The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the
RXCn Flag in UCSRnA will be set as normal.
3.
Each Slave MCU reads the UDRn Register and determines if it has been selected. If so, it clears the MPCMn
bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting.
4.
The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs,
which still have the MPCMn bit set, will ignore the data frames.
5.
When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and
waits for a new address frame from master. The process then repeats from 2.
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the Receiver must change
between using n and n+1 character frame formats. This makes full-duplex operation difficult since the Transmitter
and Receiver uses the same character size setting. If 5- to 8-bit character frames are used, the Transmitter must
be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the
same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions.
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21.10 Examples of Baud Rate Setting
For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation
can be generated by using the UBRRn settings in Table 21-6 on page 186. UBRRn values which yield an actual
baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are
acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large
serial frames (see ”Asynchronous Operational Range” on page 183). The error values are calculated using the
following equation:
BaudRate Closest Match
- – 1 ² 100%
Error[%] =  ------------------------------------------------------

BaudRate
Table 21-6.
Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
fosc = 1.0000MHz
fosc = 1.8432MHz
Baud
Rate
[bps]
UBRRn
2400
25
0.2%
51
0.2%
47
4800
12
0.2%
25
0.2%
9600
6
-7.0%
12
14.4k
3
8.5%
19.2k
2
28.8k
U2Xn = 0
U2Xn = 1
UBRRn
Error
0.0%
95
0.0%
51
0.2%
103
0.2%
23
0.0%
47
0.0%
25
0.2%
51
0.2%
0.2%
11
0.0%
23
0.0%
12
0.2%
25
0.2%
8
-3.5%
7
0.0%
15
0.0%
8
-3.5%
16
2.1%
8.5%
6
-7.0%
5
0.0%
11
0.0%
6
-7.0%
12
0.2%
1
8.5%
3
8.5%
3
0.0%
7
0.0%
3
8.5%
8
-3.5%
38.4k
1
-18.6%
2
8.5%
2
0.0%
5
0.0%
2
8.5%
6
-7.0%
57.6k
0
8.5%
1
8.5%
1
0.0%
3
0.0%
1
8.5%
3
8.5%
76.8k
–
–
1
-18.6%
1
-25.0%
2
0.0%
1
-18.6%
2
8.5%
115.2k
–
–
0
8.5%
0
0.0%
1
0.0%
0
8.5%
1
8.5%
230.4k
–
–
–
–
–
–
0
0.0%
–
–
–
–
250k
–
–
–
–
–
–
–
–
–
–
0
0.0%
125kbps
UBRRn
Error
U2Xn = 1
UBRRn
62.5kbps
Error
U2Xn = 0
Error
Note:
UBRRn
U2Xn = 1
UBRRn
Max.(1)
Error
U2Xn = 0
fosc = 2.0000MHz
115.2kbps
230.4kbps
Error
125kbps
250kbps
1. UBRRn = 0, Error = 0.0%
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Table 21-7.
Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 3.6864MHz
Baud
Rate
[bps]
U2Xn = 0
fosc = 4.0000MHz
U2Xn = 1
U2Xn = 0
fosc = 7.3728MHz
U2Xn = 1
U2Xn = 0
U2Xn = 1
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
2400
95
0.0%
191
0.0%
103
0.2%
207
0.2%
191
0.0%
383
0.0%
4800
47
0.0%
95
0.0%
51
0.2%
103
0.2%
95
0.0%
191
0.0%
9600
23
0.0%
47
0.0%
25
0.2%
51
0.2%
47
0.0%
95
0.0%
14.4k
15
0.0%
31
0.0%
16
2.1%
34
-0.8%
31
0.0%
63
0.0%
19.2k
11
0.0%
23
0.0%
12
0.2%
25
0.2%
23
0.0%
47
0.0%
28.8k
7
0.0%
15
0.0%
8
-3.5%
16
2.1%
15
0.0%
31
0.0%
38.4k
5
0.0%
11
0.0%
6
-7.0%
12
0.2%
11
0.0%
23
0.0%
57.6k
3
0.0%
7
0.0%
3
8.5%
8
-3.5%
7
0.0%
15
0.0%
76.8k
2
0.0%
5
0.0%
2
8.5%
6
-7.0%
5
0.0%
11
0.0%
115.2k
1
0.0%
3
0.0%
1
8.5%
3
8.5%
3
0.0%
7
0.0%
230.4k
0
0.0%
1
0.0%
0
8.5%
1
8.5%
1
0.0%
3
0.0%
250k
0
-7.8%
1
-7.8%
0
0.0%
1
0.0%
1
-7.8%
3
-7.8%
0.5M
–
–
0
-7.8%
–
–
0
0.0%
0
-7.8%
1
-7.8%
–
–
–
–
–
–
–
–
–
–
0
-7.8%
1M
Max.
(1)
230.4kbps
460.8kbps
250kbps
0.5Mbps
460.8kbps
921.6kbps
1.UBRRn = 0, Error = 0.0%
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187
Table 21-8.
Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 11.0592MHz
fosc = 8.0000MHz
fosc = 14.7456MHz
Baud
Rate
[bps]
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
2400
207
0.2%
416
-0.1%
287
0.0%
575
0.0%
383
0.0%
767
0.0%
4800
103
0.2%
207
0.2%
143
0.0%
287
0.0%
191
0.0%
383
0.0%
9600
51
0.2%
103
0.2%
71
0.0%
143
0.0%
95
0.0%
191
0.0%
14.4k
34
-0.8%
68
0.6%
47
0.0%
95
0.0%
63
0.0%
127
0.0%
19.2k
25
0.2%
51
0.2%
35
0.0%
71
0.0%
47
0.0%
95
0.0%
28.8k
16
2.1%
34
-0.8%
23
0.0%
47
0.0%
31
0.0%
63
0.0%
38.4k
12
0.2%
25
0.2%
17
0.0%
35
0.0%
23
0.0%
47
0.0%
57.6k
8
-3.5%
16
2.1%
11
0.0%
23
0.0%
15
0.0%
31
0.0%
76.8k
6
-7.0%
12
0.2%
8
0.0%
17
0.0%
11
0.0%
23
0.0%
115.2k
3
8.5%
8
-3.5%
5
0.0%
11
0.0%
7
0.0%
15
0.0%
230.4k
1
8.5%
3
8.5%
2
0.0%
5
0.0%
3
0.0%
7
0.0%
250k
1
0.0%
3
0.0%
2
-7.8%
5
-7.8%
3
-7.8%
6
5.3%
0.5M
0
0.0%
1
0.0%
–
–
2
-7.8%
1
-7.8%
3
-7.8%
–
–
0
0.0%
–
–
–
–
0
-7.8%
1
-7.8%
1M
Max.
1.
(1)
U2Xn = 0
U2Xn = 1
0.5Mbps
1Mbps
U2Xn = 0
U2Xn = 1
691.2kbps
U2Xn = 0
1.3824Mbps
921.6kbps
U2Xn = 1
1.8432Mbps
UBRRn = 0, Error = 0.0%
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Table 21-9.
Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
fosc = 16.0000MHz
fosc = 18.4320MHz
fosc = 20.0000MHz
Baud
Rate
[bps]
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
UBRRn
Error
2400
416
-0.1%
832
0.0%
479
0.0%
959
0.0%
520
0.0%
1041
0.0%
4800
207
0.2%
416
-0.1%
239
0.0%
479
0.0%
259
0.2%
520
0.0%
9600
103
0.2%
207
0.2%
119
0.0%
239
0.0%
129
0.2%
259
0.2%
14.4k
68
0.6%
138
-0.1%
79
0.0%
159
0.0%
86
-0.2%
173
-0.2%
19.2k
51
0.2%
103
0.2%
59
0.0%
119
0.0%
64
0.2%
129
0.2%
28.8k
34
-0.8%
68
0.6%
39
0.0%
79
0.0%
42
0.9%
86
-0.2%
38.4k
25
0.2%
51
0.2%
29
0.0%
59
0.0%
32
-1.4%
64
0.2%
57.6k
16
2.1%
34
-0.8%
19
0.0%
39
0.0%
21
-1.4%
42
0.9%
76.8k
12
0.2%
25
0.2%
14
0.0%
29
0.0%
15
1.7%
32
-1.4%
115.2k
8
-3.5%
16
2.1%
9
0.0%
19
0.0%
10
-1.4%
21
-1.4%
230.4k
3
8.5%
8
-3.5%
4
0.0%
9
0.0%
4
8.5%
10
-1.4%
250k
3
0.0%
7
0.0%
4
-7.8%
8
2.4%
4
0.0%
9
0.0%
0.5M
1
0.0%
3
0.0%
–
–
4
-7.8%
–
–
4
0.0%
0
0.0%
1
0.0%
–
–
–
–
–
–
–
–
1M
Max.
1.
(1)
U2Xn = 0
U2Xn = 1
1Mbps
2Mbps
U2Xn = 0
U2Xn = 1
1.152Mbps
U2Xn = 0
2.304Mbps
U2Xn = 1
1.25Mbps
2.5Mbps
UBRRn = 0, Error = 0.0%
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21.11 Register Description
21.11.1 UDRn – USART I/O Data Register n
Bit
7
6
5
4
3
2
1
0
RXB[7:0]
UDRn (Read)
TXB[7:0]
UDRn (Write)
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address
referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for
data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the
Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the
Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set. Data written to UDRn
when the UDREn Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit
buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the
Shift Register is empty. Then the data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is
accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on
this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of
the FIFO.
21.11.2 UCSRnA – USART Control and Status Register n A
Bit
7
6
5
4
3
2
1
0
RXCn
TXCn
UDREn
FEn
DORn
UPEn
U2Xn
MPCMn
Read/Write
R
R/W
R
R
R
R
R/W
R/W
Initial Value
0
0
1
0
0
0
0
0
UCSRnA
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
(i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and
consequently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete
interrupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new
data currently present in the transmit buffer (UDRn). The TXCn Flag bit is automatically cleared when a transmit
complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag can generate
a Transmit Complete interrupt (see description of the TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is
empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see
description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready.
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• Bit 4 – FEn: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop
bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The
FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA.
• Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two
characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is
valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking
was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to
zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer
rate for asynchronous communication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to one, all the incoming
frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is
unaffected by the MPCMn setting. For more detailed information see ”Multi-processor Communication Mode” on
page 185.
21.11.3 UCSRnB – USART Control and Status Register n B
Bit
7
6
5
4
3
2
1
0
RXCIEn
TXCIEn
UDRIEn
RXENn
TXENn
UCSZn2
RXB8n
TXB8n
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
UCSRnB
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated
only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in
UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated
only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in
UCSRnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only
if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in
UCSRnA is set.
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• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn
pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn
Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the
TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn
port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a
frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be
read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits.
Must be written before writing the low bits to UDRn.
21.11.4 UCSRnC – USART Control and Status Register n C
Bit
7
6
5
4
3
2
1
0
UMSELn1
UMSELn0
UPMn1
UPMn0
USBSn
UCSZn1
UCSZn0
UCPOLn
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
1
1
0
UCSRnC
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 21-10.
Table 21-10.
Note:
UMSELn Bits Settings
UMSELn1
UMSELn0
0
0
Asynchronous USART
0
1
Synchronous USART
1
0
(Reserved)
1
1
Master SPI (MSPIM)(1)
1.
Mode
See ”USART in SPI Mode” on page 196 for full description of the Master SPI Mode (MSPIM) operation
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically
generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity
value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in
UCSRnA will be set.
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Table 21-11.
UPMn Bits Settings
UPMn1
UPMn0
Parity Mode
0
0
Disabled
0
1
Reserved
1
0
Enabled, Even Parity
1
1
Enabled, Odd Parity
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
Table 21-12.
USBS Bit Settings
USBSn
Stop Bit(s)
0
1-bit
1
2-bit
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a
frame the Receiver and Transmitter use.
Table 21-13.
UCSZn Bits Settings
UCSZn2
UCSZn1
UCSZn0
Character Size
0
0
0
5-bit
0
0
1
6-bit
0
1
0
7-bit
0
1
1
8-bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9-bit
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn
bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn).
Table 21-14.
UCPOLn
UCPOLn Bit Settings
Transmitted Data Changed (Output of TxDn Pin)
Received Data Sampled (Input on RxDn Pin)
0
Rising XCKn Edge
Falling XCKn Edge
1
Falling XCKn Edge
Rising XCKn Edge
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21.11.5 UCSRnD – USART Control and Status Register n D
Bit
7
6
5
4
3
2
1
(0xC3)
RXSIE
RXS
SFDE
-
-
-
-
0
-
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
UCSRD
• Bit 7 – RXSIE: USART RX Start Interrupt Enable
Writing this bit to one enables the interrupt on the RXS flag. In sleep modes this bit enables start frame detector
that can wake up the MCU when a start condition is detected on the RxD line. The USART RX Start Interrupt is
generated only, if the RXSIE bit, the Global Interrupt flag, and RXS are set.
• Bit 6 – RXS: USART RX Start
The RXS flag is set when a start condition is detected on the RxD line. If the RXSIE bit and the Global Interrupt
Enable flag are set, an RX Start Interrupt will be generated when the flag is set. The flag can only be cleared by
writing a logical one on the RXS bit location.
If the start frame detector is enabled (RXSIE = 1) and the Global Interrupt Enable flag is set, the RX Start Interrupt
will wake up the MCU from all sleep modes.
• Bit 5 – SFDE: Start Frame Detection Enable
Writing this bit to one enables the USART Start Frame Detection mode. The start frame detector is able to wake up
the MCU from sleep mode when a start condition, i.e. a high (IDLE) to low (START) transition, is detected on the
RxD line.
Table 21-15.
USART Start Frame Detection modes
SFDE
RXSIE
RXCIE
Description
0
X
X
Start frame detector disabled
1
0
0
Reserved
1
0
1
Start frame detector enabled. RXC flag wakes up MCU from all
sleep modes
1
1
0
Start frame detector enabled. RXS flag wakes up MCU from all
sleep modes
1
1
1
Start frame detector enabled. Both RXC and RXS wake up the
MCU from all sleep modes
For more information, see xxxxx.
• Bit 4:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
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21.11.6 UBRRnL and UBRRnH – USART Baud Rate Registers
Bit
15
14
13
12
–
–
–
–
11
10
9
8
UBRRn[11:8]
UBRRnH
UBRRn[7:0]
7
Read/Write
Initial Value
6
5
UBRRnL
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• Bit 15:12 – Reserved
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when
UBRRnH is written.
• Bit 11:0 – UBRR[11:0]: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four most significant bits,
and the UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the
Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate
update of the baud rate prescaler.
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22.
USART in SPI Mode
22.1
Features
22.2

Full Duplex, Three-wire Synchronous Data Transfer

Master Operation

Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)

LSB First or MSB First Data Transfer (Configurable Data Order)

Queued Operation (Double Buffered)

High Resolution Baud Rate Generator

High Speed Operation (fXCKmax = fCK/2)

Flexible Interrupt Generation
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master
SPI compliant mode of operation.
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of operation the SPI master
control logic takes direct control over the USART resources. These resources include the transmitter and receiver
shift register and buffers, and the baud rate generator. The parity generator and checker, the data and clock
recovery logic, and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced by a
common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in both
modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the control registers
changes when using MSPIM.
22.3
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode
of operation only internal clock generation (i.e. master operation) is supported. The Data Direction Register for the
XCKn pin (DDR_XCKn) must therefore be set to one (i.e. as output) for the USART in MSPIM to operate correctly.
Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit
set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The
baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 22-1:
Table 22-1.
Equations for Calculating Baud Rate Register Setting
Operating Mode
Synchronous Master mode
Note:
1.
Equation for Calculating Baud Rate(1)
Equation for Calculating UBRRn Value
f OSC
BAUD = --------------------------------------2  UBRRn + 1 
f OSC
UBRRn = -------------------- – 1
2BAUD
The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
Baud rate (in bits per second, bps)
fOSC
System Oscillator clock frequency
UBRRn
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
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22.4
SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined
by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 22-1. Data bits are
shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to
stabilize. The UCPOLn and UCPHAn functionality is summarized in Table 22-2. Note that changing the setting of
any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Table 22-2.
UCPOLn and UCPHAn Functionality
UCPOLn
UCPHAn
SPI Mode
Leading Edge
Trailing Edge
0
0
0
Sample (Rising)
Setup (Falling)
0
1
1
Setup (Rising)
Sample (Falling)
1
0
2
Sample (Falling)
Setup (Rising)
1
1
3
Setup (Falling)
Sample (Rising)
Figure 22-1.
UCPHAn and UCPOLn data transfer timing diagrams.
UCPHA=0
UCPHA=1
UCPOL=0
22.5
UCPOL=1
XCK
XCK
Data setup (TXD)
Data setup (TXD)
Data sample (RXD)
Data sample (RXD)
XCK
XCK
Data setup (TXD)
Data setup (TXD)
Data sample (RXD)
Data sample (RXD)
Frame Formats
A serial frame for the MSPIM is defined to be one character of eight data bits. The USART in MSPIM mode has two
valid frame formats:
•
8-bit data with MSB first
•
8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are
succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new
frame can directly follow it, or the communication line can be set to an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and
Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing
communication for both the Receiver and Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will
then signal that the 16-bit value has been shifted out.
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22.5.1 USART MSPIM Initialization
The USART in MSPIM mode has to be initialized before any communication can take place. The initialization
process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to
one), setting frame format and enabling the Transmitter and the Receiver. Only the transmitter can operate
independently. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and thus
interrupts globally disabled) when doing the initialization.
Note:
To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the
transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired
value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before
enabling the transmitter is not necessary if the initialization is done immediately after a reset since UBRRn is reset to
zero.
Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no
ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the
Transmitter has completed all transfers, and the RXCn Flag can be used to check that there are no unread data in
the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it
is used for this purpose.
The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function
parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers.
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Assembly Code Example(1)
USART_Init:
clr r18
out UBRRnH,r18
out UBRRnL,r18
; Setting the XCKn port pin as output, enables master
mode.
sbi XCKn_DDR, XCKn
; Set MSPI mode of operation and SPI data mode 0.
ldi r18,
(1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
out UCSRnC,r18
; Enable receiver and transmitter.
ldi r18, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r18
; Set baud rate.
; IMPORTANT: The Baud Rate must be set after the
transmitter is enabled!
out UBRRnH, r17
out UBRRnL, r18
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
UBRRn = 0;
/* Setting the XCKn port pin as output, enables master
mode. */
XCKn_DDR |= (1<<XCKn);
/* Set MSPI mode of operation and SPI data mode 0. */
UCSRnC =
(1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);
/* Enable receiver and transmitter. */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set baud rate. */
/* IMPORTANT: The Baud Rate must be set after the
transmitter is enabled */
UBRRn = baud;
}
Note:
1. See ”About Code Examples” on page 7.
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22.6
Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register
is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given
the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn
bit in the UCSRnB register to one. When the receiver is enabled, the normal pin operation of the RxDn pin is
overridden and given the function as the Receiver's serial input. The XCKn will in both cases be used as the
transfer clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to the UDRn I/O
location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The
data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send
a new frame.
Note:
To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for
each byte transmitted. The input buffer operation is identical to normal USART mode, i.e. if an overflow occurs the
character last received will be lost, not the first data in the buffer. This means that if four bytes are transferred, byte 1
first, then byte 2, 3, and 4, and the UDRn is not read before all transfers are completed, then byte 3 to be received will
be lost, and not byte 1.
The following code examples show a simple USART in MSPIM mode transfer function based on polling of the Data
Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The USART has to be initialized before the
function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16 and the
data received will be available in the same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with
new data to be transmitted. The function then waits for data to be present in the receive buffer by checking the
RXCn Flag, before reading the buffer and returning the value.
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Assembly Code Example(1)
USART_MSPIM_Transfer:
; Wait for empty transmit buffer
in r16, UCSRnA
sbrs r16, UDREn
rjmp USART_MSPIM_Transfer
; Put data (r16) into buffer, sends the data
out UDRn,r16
; Wait for data to be received
USART_MSPIM_Wait_RXCn:
in r16, UCSRnA
sbrs r16, RXCn
rjmp USART_MSPIM_Wait_RXCn
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) );
/* Put data into buffer, sends the data */
UDRn = data;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) );
/* Get and return received data from buffer */
return UDRn;
}
Note:
1. See ”About Code Examples” on page 7.
22.6.1 Transmitter and Receiver Flags and Interrupts
The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in
function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use
and is always read as zero.
22.6.2 Disabling the Transmitter or Receiver
The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART
operation.
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22.7
AVR USART MSPIM vs. AVR SPI
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
•
Master mode timing diagram
•
The UCPOLn bit functionality is identical to the SPI CPOL bit
•
The UCPHAn bit functionality is identical to the SPI CPHA bit
•
The UDORDn bit functionality is identical to the SPI DORD bit
However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode
is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only
master operation is supported by the USART in MSPIM mode, the following features differ between the two
modules:
•
The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer
•
The USART in MSPIM mode receiver includes an additional buffer level
•
The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode
•
The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting
UBRRn accordingly
•
Interrupt timing is not compatible
•
Pin control differs due to the master only operation of the USART in MSPIM mode
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 22-3.
Table 22-3.
Comparison of USART in MSPIM mode and SPI pins
USART_MSPIM
SPI
Comments
TxDn
MOSI
Master Out only
RxDn
MISO
Master In only
XCKn
SCK
(Functionally identical)
(N/A)
SS
Not supported by USART in MSPIM
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22.8
Register Description
The following section describes the registers used for SPI operation using the USART.
22.8.1 UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART
operation. See ” UDRn – USART I/O Data Register n” on page 190.
22.8.2 UCSRnA – USART MSPIM Control and Status Register n A
Bit
7
6
5
4
3
2
1
RXCn
TXCn
UDREn
–
–
–
–
0
–
Read/Write
R
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
1
1
0
UCSRnA
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
(i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and
consequently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete
interrupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new
data currently present in the transmit buffer (UDRn). The TXCn Flag bit is automatically cleared when a transmit
complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn Flag can generate
a Transmit Complete interrupt (see description of the TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is
empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see
description of the UDRIE bit). UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must
be written to zero when UCSRnA is written.
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22.8.3 UCSRnB – USART MSPIM Control and Status Register n B
Bit
7
6
5
4
3
2
1
RXCIEn
TXCIEn
UDRIE
RXENn
TXENn
–
-
0
-
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R
R
Initial Value
0
0
0
0
0
1
1
0
UCSRnB
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated
only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in
UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated
only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in
UCSRnA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only
if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA
is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer. Only enabling the
receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0) has no meaning since it is the transmitter that
controls the transfer clock and since only master mode is supported.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the
TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn
port.
• Bit 2:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must
be written to zero when UCSRnB is written.
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22.8.4 UCSRnC – USART MSPIM Control and Status Register n C
Bit
7
6
5
4
3
2
1
0
UMSELn1
UMSELn0
–
–
–
UDORDn
UCPHAn
UCPOLn
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
1
1
0
UCSRnC
• Bit 7:6 – UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 22-4. See ” UCSRnC – USART Control
and Status Register n C” on page 192 for full description of the normal USART operation. The MSPIM is enabled
when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write
operation where the MSPIM is enabled.
Table 22-4.
UMSELn Bits Settings
UMSELn1
UMSELn0
Mode
0
0
Asynchronous USART
0
1
Synchronous USART
1
0
Reserved
1
1
Master SPI (MSPIM)
• Bit 5:3 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must
be written to zero when UCSRnC is written.
• Bit 2 – UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is
transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 – UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn.
Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 – UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings
determine the timing of the data transfer. Refer to the SPI Data Modes and Timing section page 4 for details.
22.8.5 USART MSPIM Baud Rate Registers – UBRRnL and UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation.
See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 195.
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23.
2-wire Serial Interface (I2C)
23.1
Features
23.2

Simple, yet Powerful and Flexible Communication Interface, only two Bus Lines Needed

Both Master and Slave Operation Supported

Device can Operate as Transmitter or Receiver

7-bit Address Space Allows up to 128 Different Slave Addresses

Multi-master Arbitration Support

Up to 400kHz Data Transfer Speed

Slew-rate Limited Output Drivers

Noise Suppression Circuitry Rejects Spikes on Bus Lines

Fully Programmable Slave Address with General Call Support

Address Recognition Causes Wake-up When AVR is in Sleep Mode

Compatible with Phillips’ I2C protocol
2-wire Serial Interface Bus Definition
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows
the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for
clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up
resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and
mechanisms for resolving bus contention are inherent in the TWI protocol.
Figure 23-1.
TWI Bus Interconnection
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
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23.2.1 TWI Terminology
The following definitions are frequently encountered in this section.
Table 23-1.
TWI Terminology
Term
Description
Master
The device that initiates and terminates a transmission. The Master also generates the SCL clock.
Slave
The device addressed by a Master.
Transmitter
The device placing data on the bus.
Receiver
The device reading data from the bus.
The PRTWI bit in ”Minimizing Power Consumption” on page 39 must be written to zero to enable the 2-wire Serial
Interface.
23.2.2 Electrical Interconnection
As depicted in Figure 23-1 on page 206, both bus lines are connected to the positive supply voltage through pull-up
resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wiredAND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when
one or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing
the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered in
order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and
the 7-bit slave address space. Two different sets of specifications are presented there, one relevant for bus speeds
below 100kHz, and one valid for bus speeds up to 400kHz.
23.3
Data Transfer and Frame Format
23.3.1 Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line
must be stable when the clock line is high. The only exception to this rule is for generating start and stop
conditions.
Figure 23-2.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data Change
23.3.2 START and STOP Conditions
The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a
START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START
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and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A
special case occurs when a new START condition is issued between a START and STOP condition. This is
referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer
without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both START and
REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and
STOP conditions are signalled by changing the level of the SDA line when the SCL line is high.
Figure 23-3.
START, REPEATED START and STOP conditions
SDA
SCL
START
STOP
REPEATED START
START
STOP
23.3.3 Address Packet Format
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE
control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a
write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge
by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not
service the Master’s request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit
a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting
of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the
address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general
call is used when a Master wishes to transmit the same message to several slaves in the system. When the
general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general
call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that
acknowledged the general call. Note that transmitting the general call address followed by a Read bit is
meaningless, as this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 23-4.
Address Packet Format
Addr MSB
Addr LSB
R/W
ACK
7
8
9
SDA
SCL
1
2
START
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23.3.4 Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit.
During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is
responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA
line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the
Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 23-5.
Data Packet Format
Data MSB
Data LSB
ACK
8
9
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1
2
SLA+R/W
7
STOP, REPEATED
START or Next
Data Byte
Data Byte
23.3.5 Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP
condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the WiredANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can
extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too
fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the Master. As a
consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
Figure 23-6 shows a typical data transmission. Note that several data bytes can be transmitted between the
SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software.
Figure 23-6.
Typical Data Transmission
Addr MSB
Addr LSB
R/W
ACK
Data MSB
7
8
9
1
Data LSB
ACK
8
9
SDA
SCL
1
START
23.4
2
SLA+R/W
2
7
Data Byte
STOP
Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure
that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time.
Two problems arise in multi-master systems:
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•
An algorithm must be implemented allowing only one of the masters to complete the transmission. All other
masters should cease transmission when they discover that they have lost the selection process. This
selection process is called arbitration. When a contending master discovers that it has lost the arbitration
process, it should immediately switch to Slave mode to check whether it is being addressed by the winning
master. The fact that multiple masters have started transmission at the same time should not be detectable
to the slaves, i.e. the data being transferred on the bus must not be corrupted.
•
Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial
clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the
arbitration process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be
wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high
period. The low period of the combined clock is equal to the low period of the Master with the longest low period.
Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods
when the combined SCL line goes high or low, respectively.
Figure 23-7.
SCL Synchronization Between Multiple Masters
TA low
TA high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TBlow
TBhigh
Masters Start
Counting Low Period
Masters Start
Counting High Period
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read
from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master
can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing
Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA
line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several
masters are trying to address the same Slave, arbitration will continue into the data packet.
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Figure 23-8.
Arbitration Between Two Masters
START
Master A Loses
Arbitration, SDAA SDA
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
Note that arbitration is not allowed between:
•
A REPEATED START condition and a data bit
•
A STOP condition and a data bit
•
A REPEATED START and a STOP condition
It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies
that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In
other words; All transmissions must contain the same number of data packets, otherwise the result of the
arbitration is undefined.
23.5
Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 23-9 on page 212. All registers drawn in
a thick line are accessible through the AVR data bus.
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Overview of the TWI Module
SCL
Slew-rate
Control
SDA
Spike
Filter
Slew-rate
Control
Spike
Filter
Bus Interface Unit
START / STOP
Control
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Address Match Unit
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Ack
Control Unit
Address Register
(TWAR)
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
Address Comparator
TWI Unit
Figure 23-9.
23.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in
order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes
shorter than 50ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits
corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some
systems eliminate the need for external ones.
23.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in
the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation
does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16
times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the
average TWI bus clock period.
The SCL frequency is generated according to the following equation:
CPU Clock frequency
SCL frequency = ----------------------------------------------------------------------------------------16 + 2(TWBR)   PrescalerValue 
•
TWBR = Value of the TWI Bit Rate Register
•
PrescalerValue = Value of the prescaler, see Table 23-8 on page 234
Note:
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table
30-9 on page 309 for value of pull-up resistor.
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23.5.3 Bus Interface Unit
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration
detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes
received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to
be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However,
when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter
mode, the value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and
STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR
MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the
transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is
informed. Correct action can then be taken and appropriate status codes generated.
23.5.4 Address Match Unit
The Address Match unit checks if received address bytes match the seven-bit address in the TWI Address
Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all
incoming address bits will also be compared against the General Call address. Upon an address match, the
Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address,
depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR
MCU is in sleep mode, enabling the MCU to wake up if addressed by a Master.
23.5.5 Control Unit
The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control
Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI
Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a
status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag
is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status
information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application
software to complete its tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
23.6
•
After the TWI has transmitted a START/REPEATED START condition
•
After the TWI has transmitted SLA+R/W
•
After the TWI has transmitted an address byte
•
After the TWI has lost arbitration
•
After the TWI has been addressed by own slave address or general call
•
After the TWI has received a data byte
•
After a STOP or REPEATED START has been received while still addressed as a Slave
•
When a bus error has occurred due to an illegal START or STOP condition
Using the TWI
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a
byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to
carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR
together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the
TWINT Flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT
Flag in order to detect actions on the TWI bus.
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When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this
case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application
software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and
TWDR Registers.
Figure 23-10 is a simple example of how the application can interface to the TWI hardware. In this example, a
Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed
explanation follows later in this section. A simple code example implementing the desired behavior is also
presented.
Application
Action
Figure 23-10. Interfacing the Application to the TWI in a Typical Transmission
1. Application
writes to TWCR to
initiate
transmission of
START
TWI
Hardware
Action
TWI bus
3. Check TWSR to see if START was
sent. Application loads SLA+W into
TWDR, and loads appropriate control
signals into TWCR, makin sure that
TWINT is written to one,
and TWSTA is written to zero.
START
2. TWINT set.
Status code indicates
START condition sent
SLA+W
5. Check TWSR to see if SLA+W was
sent and ACK received.
Application loads data into TWDR, and
loads appropriate control signals into
TWCR, making sure that TWINT is
written to one
A
4. TWINT set.
Status code indicates
SLA+W sent, ACK
received
Data
7. Check TWSR to see if data was sent
and ACK received.
Application loads appropriate control
signals to send STOP into TWCR,
making sure that TWINT is written to one
A
6. TWINT set.
Status code indicates
data sent, ACK received
STOP
Indicates
TWINT set
1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific
value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is
described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to
TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition.
2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with
a status code indicating that the START condition has successfully been sent.
3. The application software should now examine the value of TWSR, to make sure that the START condition was
successfully transmitted. If TWSR indicates otherwise, the application software might take some special action,
like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W
into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the
desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the
SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT
bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as
long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will
initiate transmission of the address packet.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a
status code indicating that the address packet has successfully been sent. The status code will also reflect
whether a Slave acknowledged the packet or not.
5. The application software should now examine the value of TWSR, to make sure that the address packet was
successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the
application software might take some special action, like calling an error routine. Assuming that the status code
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is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be
written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to
write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one
to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet.
6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a
status code indicating that the data packet has successfully been sent. The status code will also reflect whether
a Slave acknowledged the packet or not.
7. The application software should now examine the value of TWSR, to make sure that the data packet was
successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the
application software might take some special action, like calling an error routine. Assuming that the status code
is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a
STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in
the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the
TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate
transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent.
Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be
summarized as follows:
•
When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL
line is pulled low until TWINT is cleared.
•
When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI
bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle.
•
After all TWI Register updates and other pending application software tasks have been completed, TWCR is
written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI
will then commence executing whatever operation was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note that the code below assumes that
several definitions have been made, for example by using include-files.
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Table 23-2.
Assembly and C Code Example
Assembly Code Example
1
2
3
4
ldi
r16,
(1<<TWINT)|(1<<TWSTA
)|
(1<<TWEN)
out
TWCR, r16
wait1:
in
r16,TWCR
sbrs
r16,TWINT
rjmp
wait1
in
r16,TWSR
andi
r16, 0xF8
cpi
r16, START
brne
ERROR
ldi
r16, SLA_W
out
TWDR, r16
ldi
r16, (1<<TWINT) |
(1<<TWEN)
out
TWCR, r16
wait2:
in
r16,TWCR
sbrs
r16,TWINT
rjmp
wait2
C Example
Comments
TWCR =
(1<<TWINT)|(1<<TWSTA)
|
(1<<TWEN)
Send START condition
while (!(TWCR &
(1<<TWINT)))
;
Wait for TWINT Flag set. This
indicates that the START
condition has been transmitted
if ((TWSR & 0xF8) !=
START)
Check value of TWI Status
Register. Mask prescaler bits. If
status different from START go to
ERROR
ERROR();
TWDR = SLA_W;
TWCR = (1<<TWINT) |
(1<<TWEN);
while (!(TWCR &
(1<<TWINT)))
;
Load SLA_W into TWDR
Register. Clear TWINT bit in
TWCR to start transmission of
address
Wait for TWINT Flag set. This
indicates that the SLA+W has
been transmitted, and
ACK/NACK has been received.
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Table 23-2.
Assembly and C Code Example
Assembly Code Example
5
6
7
in
r16,TWSR
andi
r16, 0xF8
cpi
r16, MT_SLA_ACK
brne
ERROR
ldi
r16, DATA
out
TWDR, r16
ldi
r16, (1<<TWINT) |
(1<<TWEN)
out
TWCR, r16
wait3:
in
r16,TWCR
sbrs
r16,TWINT
rjmp
wait3
in
r16,TWSR
andi
r16, 0xF8
cpi
r16, MT_DATA_ACK
brne
ERROR
ldi
r16,
(1<<TWINT)|(1<<TWEN)
|
C Example
Comments
if ((TWSR & 0xF8) !=
MT_SLA_ACK)
Check value of TWI Status
Register. Mask prescaler bits. If
status different from
MT_SLA_ACK go to ERROR
ERROR();
TWDR = DATA;
TWCR = (1<<TWINT) |
(1<<TWEN);
Load DATA into TWDR Register.
Clear TWINT bit in TWCR to start
transmission of data
while (!(TWCR &
(1<<TWINT)))
;
Wait for TWINT Flag set. This
indicates that the DATA has been
transmitted, and ACK/NACK has
been received.
if ((TWSR & 0xF8) !=
MT_DATA_ACK)
Check value of TWI Status
Register. Mask prescaler bits. If
status different from
MT_DATA_ACK go to ERROR
ERROR();
TWCR =
(1<<TWINT)|(1<<TWEN)|
(1<<TWSTO);
Transmit STOP condition
(1<<TWSTO)
out
TWCR, r16
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23.7
Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver
(MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same
application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the
data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the
TWI, and then SR mode would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described along with figures
detailing data transmission in each of the modes. These figures contain the following abbreviations:
S
START condition
Rs
REPEATED START condition
R
Read bit (high level at SDA)
W
Write bit (low level at SDA)
A
Acknowledge bit (low level at SDA)
A
Not acknowledge bit (high level at SDA)
Data
8-bit data byte
P
STOP condition
SLA
Slave Address
In Figure 23-12 on page 221 to Figure 23-18 on page 228, circles are used to indicate that the TWINT Flag is set.
The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these
points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is
suspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For
each status code, the required software action and details of the following serial transfer are given in Table 23-3 on
page 219 to Table 23-6 on page 228. Note that the prescaler bits are masked to zero in these tables.
23.7.1 Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 23-11). In
order to enter a Master mode, a START condition must be transmitted. The format of the following address packet
determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT
mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
Figure 23-11. Data Transfer in Master Transmitter Mode
VCC
Device 1
Device 2
MASTER
TRANSMITTER
SLAVE
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
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A START condition is sent by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START
condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus
and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted,
the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 23-3 on page 219). In
order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
0
X
1
0
X
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a
number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The
appropriate action to be taken for each of these status codes is detailed in Table 23-3 on page 219.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the
data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the
Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
0
X
1
0
X
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP
condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
1
X
1
0
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a
new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves,
Master Transmitter mode and Master Receiver mode without losing control of the bus.
Table 23-3.
Status Code
(TWSR)
Prescaler
Bits are 0
Status Codes for Master Transmitter Mode
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
To/from TWDR
To TWCR
Next Action Taken by TWI Hardware
STA
STO
TWINT
TWEA
0x08
A START condition has been
transmitted
Load SLA+W
0
0
1
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
0x10
A repeated START condition
has been transmitted
Load SLA+W or
0
0
1
X
Load SLA+R
0
0
1
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
0x18
SLA+W has been transmitted;
ACK has been received
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
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Table 23-3.
Status Code
(TWSR)
Prescaler
Bits are 0
0x20
0x28
0x30
0x38
Status Codes for Master Transmitter Mode (Continued)
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
SLA+W has been transmitted;
NOT ACK has been received
Data byte has been transmitted;
ACK has been received
Data byte has been transmitted;
NOT ACK has been received
Arbitration lost in SLA+W or
data bytes
Application Software Response
To/from TWDR
To TWCR
Next Action Taken by TWI Hardware
STA
STO
TWINT
TWEA
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
No TWDR action or
0
0
1
X
No TWDR action
1
0
1
X
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
2-wire Serial Bus will be released and not addressed
Slave mode entered
A START condition will be transmitted when the bus
becomes free
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Figure 23-12. Formats and States in the Master Transmitter Mode
MT
Successfull
transmission
to a slave
receiver
S
SLA
$08
W
A
DATA
$18
A
P
$28
Next transfer
started with a
repeated start
condition
RS
SLA
W
$10
Not acknowledge
received after the
slave address
A
R
P
$20
MR
Not acknowledge
received after a data
byte
A
P
$30
Arbitration lost in slave
address or data byte
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
A
$68
From master to slave
From slave to master
A or A
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
A
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
23.7.2 Master Receiver Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (Slave see Figure 2313 on page 222). In order to enter a Master mode, a START condition must be transmitted. The format of the
following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If
SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes
mentioned in this section assume that the prescaler bits are zero or are masked to zero.
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Figure 23-13. Data Transfer in Master Receiver Mode
VCC
Device 1
Device 2
MASTER
RECEIVER
SLAVE
TRANSMITTER
........
Device 3
Device n
R1
R2
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a
START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and
generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the
TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (See Table 23-3 on page 219). In order
to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value
to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
0
X
1
0
X
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a
number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The
appropriate action to be taken for each of these status codes is detailed in Table 23-4 on page 223. Received data
can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until
the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a
NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
1
X
1
0
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a
new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves,
Master Transmitter mode and Master Receiver mode without losing control over the bus.
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Table 23-4.
Status Code
(TWSR)
Prescaler
Bits are 0
Status codes for Master Receiver Mode
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
Next Action Taken by TWI Hardware
To TWCR
To/from TWD
STA
STO
TWINT
TWEA
0x08
A START condition has been
transmitted
Load SLA+R
0
0
1
X
SLA+R will be transmitted
ACK or NOT ACK will be received
0x10
A repeated START condition
has been transmitted
Load SLA+R or
0
0
1
X
Load SLA+W
0
0
1
X
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
No TWDR action or
0
0
1
X
No TWDR action
1
0
1
X
No TWDR action or
0
0
1
0
No TWDR action
0
0
1
1
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
Read data byte or
0
0
1
0
Read data byte
0
0
1
1
Read data byte or
Read data byte or
1
0
0
1
1
1
X
X
Read data byte
1
1
1
X
0x38
Arbitration lost in SLA+R or
NOT ACK bit
0x40
SLA+R has been transmitted;
ACK has been received
0x48
SLA+R has been transmitted;
NOT ACK has been received
0x50
Data byte has been received;
ACK has been returned
0x58
Data byte has been received;
NOT ACK has been returned
2-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Figure 23-14. Formats and States in the Master Receiver Mode
MR
Successfull
reception
from a slave
receiver
S
SLA
$08
R
A
DATA
$40
A
DATA
$50
A
P
$58
Next transfer
started with a
repeated start
condition
RS
SLA
R
$10
Not acknowledge
received after the
slave address
A
W
P
$48
MT
Arbitration lost in slave
address or data byte
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
A
$68
From master to slave
From slave to master
A
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
A
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
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23.7.3 Slave Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure 23-15). All
the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 23-15. Data transfer in Slave Receiver mode
VCC
Device 1
Device 2
SLAVE
RECEIVER
MASTER
TRANSMITTER
........
Device 3
R1
Device n
R2
SDA
SCL
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
value
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Device’s Own Slave Address
The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a
Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general
call address.
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
0
1
0
0
0
1
0
X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the
acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be
written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the
general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will
operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been
received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each status code is detailed in
Table 23-5 on page 225. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the
Master mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next
received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA
is zero, the TWI does not acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored and
address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to
temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the
interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus
clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the
wake up and until the TWINT Flag is cleared (by writing it to one). Further data reception will be carried out as
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normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL
line may be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when
waking up from these Sleep modes.
Table 23-5.
Status Code
(TWSR)
Prescaler
Bits are 0
Status Codes for Slave Receiver Mode
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
To/from TWDR
To TWCR
Next Action Taken by TWI Hardware
STA
STO
TWINT
TWEA
No TWDR action or
X
0
1
0
0x60
Own SLA+W has been received;
ACK has been returned
No TWDR action
X
0
1
1
0x68
Arbitration lost in SLA+R/W as
Master; own SLA+W has been
received; ACK has been returned
No TWDR action or
X
0
1
0
No TWDR action
X
0
1
1
0x70
General call address has been
received; ACK has been returned
No TWDR action or
X
0
1
0
No TWDR action
X
0
1
1
0x78
Arbitration lost in SLA+R/W as
Master; General call address has
been received; ACK has been returned
No TWDR action or
X
0
1
0
No TWDR action
X
0
1
1
0x80
Previously addressed with own
SLA+W; data has been received;
ACK has been returned
Read data byte or
X
0
1
0
Read data byte
X
0
1
1
0x88
Previously addressed with own
SLA+W; data has been received;
NOT ACK has been returned
Read data byte or
0
0
1
0
Read data byte or
0
0
1
1
Read data byte or
1
0
1
0
Read data byte
1
0
1
1
0x90
Previously addressed with
general call; data has been received; ACK has been returned
Read data byte or
X
0
1
0
Read data byte
X
0
1
1
0x98
Previously addressed with
general call; data has been
received; NOT ACK has been
returned
Read data byte or
0
0
1
0
Read data byte or
0
0
1
1
Read data byte or
1
0
1
0
Read data byte
1
0
1
1
No action
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0xA0
A STOP condition or repeated
START condition has been
received while still addressed as
Slave
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
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Figure 23-16. Formats and States in the Slave Receiver Mode
Reception of the own
slave address and one or
more data bytes. All are
acknowledged
S
SLA
W
A
DATA
$60
A
DATA
$80
A
P or S
$80
$A0
A
P or S
Last data byte received
is not acknowledged
$88
Arbitration lost as master
and addressed as slave
A
$68
Reception of the general call
address and one or more data
bytes
General Call
A
DATA
$70
A
DATA
$90
A
P or S
$90
$A0
A
P or S
Last data byte received is
not acknowledged
$98
Arbitration lost as master and
addressed as slave by general call
A
$78
DATA
From master to slave
A
From slave to master
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
23.7.4 Slave Transmitter Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 23-17). All
the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 23-17. Data Transfer in Slave Transmitter Mode
VCC
Device 1
Device 2
SLAVE
TRANSMITTER
MASTER
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
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To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
value
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Device’s Own Slave Address
The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a
Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general
call address.
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
0
1
0
0
0
1
0
X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the
acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be
written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the
general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will
operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been
received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each status code is detailed in
Table 23-6 on page 228. The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in
the Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or
state 0xC8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final
byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer.
Thus the Master Receiver receives all “1” as serial data. State 0xC8 is entered if the Master demands additional
data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting
NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire Serial Bus is still
monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may
be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the
interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus
clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during
the wake up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be carried out
as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the
SCL line may be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when
waking up from these sleep modes.
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Table 23-6.
Status Code
(TWSR)
Prescaler
Bits are 0
0xA8
0xB0
0xB8
0xC0
0xC8
Status Codes for Slave Transmitter Mode
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
To/from TWDR
To TWCR
Next Action Taken by TWI Hardware
STA
STO
TWINT
TWEA
Load data byte or
X
0
1
0
Load data byte
X
0
1
1
Arbitration lost in SLA+R/W as
Master; own SLA+R has been
received; ACK has been returned
Load data byte or
X
0
1
0
Load data byte
X
0
1
1
Data byte in TWDR has been
transmitted; ACK has been
received
Load data byte or
X
0
1
0
Load data byte
X
0
1
1
Data byte in TWDR has been
transmitted; NOT ACK has been
received
No TWDR action or
0
0
1
0
No TWDR action or
0
0
1
1
No TWDR action or
1
0
1
0
No TWDR action
1
0
1
1
No TWDR action or
0
0
1
0
No TWDR action or
0
0
1
1
No TWDR action or
1
0
1
0
No TWDR action
1
0
1
1
Own SLA+R has been received;
ACK has been returned
Last data byte in TWDR has
been transmitted (TWEA = “0”);
ACK has been received
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be received
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be received
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be received
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Figure 23-18. Formats and States in the Slave Transmitter Mode
Reception of the own
slave address and one or
more data bytes
S
SLA
R
A
DATA
$A8
Arbitration lost as master
and addressed as slave
A
DATA
$B8
A
P or S
$C0
A
$B0
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
A
All 1's
P or S
$C8
From master to slave
From slave to master
DATA
A
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
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23.7.5 Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 23-7.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs
between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus error occurs when a
START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are
during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT
is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to
it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
Table 23-7.
Status Code
(TWSR)
Prescaler
Bits are 0
Miscellaneous States
Application Software Response
Status of the 2-wire Serial
Bus and 2-wire Serial
Interface Hardware
To/from TWDR
0xF8
No relevant state information
available; TWINT = “0”
No TWDR action
0x00
Bus error due to an illegal
START or STOP condition
No TWDR action
To TWCR
STA
STO
Next Action Taken by TWI Hardware
TWINT
TWEA
No TWCR action
0
1
Wait or proceed current transfer
1
X
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
23.7.6 Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider for
example reading data from a serial EEPROM. Typically, such a transfer involves the following steps:
1.
The transfer must be initiated.
2.
The EEPROM must be instructed what location should be read.
3.
The reading must be performed.
4.
The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what
location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave,
implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control
of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle
is violated in a multi master system, another Master can alter the data pointer in the EEPROM between steps
2 and 3, and the Master will read the wrong data location. Such a change in transfer direction is accomplished
by transmitting a REPEATED START between the transmission of the address byte and reception of the data.
After a REPEATED START, the Master keeps ownership of the bus. Figure 23-19 shows the flow in this
transfer.
Figure 23-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter
S
SLA+W
A
ADDRESS
S = START
Master Receiver
A
Rs
SLA+R
A
Rs = REPEATED START
Transmitted from master to slave
DATA
A
P
P = STOP
Transmitted from slave to master
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23.8
Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more
of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be
allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration
situation is depicted below, where two masters are trying to transmit data to a Slave Receiver.
Figure 23-20. An Arbitration Example
VCC
Device 1
Device 2
Device 3
MASTER
TRANSMITTER
MASTER
TRANSMITTER
SLAVE
RECEIVER
........
Device n
R1
R2
SDA
SCL
Several different scenarios may arise during arbitration, as described below:
•
Two or more masters are performing identical communication with the same Slave. In this case, neither the
Slave nor any of the masters will know about the bus contention.
•
Two or more masters are accessing the same Slave with different data or direction bit. In this case,
arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on
SDA while another Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed
Slave mode or wait until the bus is free and transmit a new START condition, depending on application
software action.
•
Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits.
Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters
losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning
Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If
they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
This is summarized in Figure 23-21. Possible status values are given in circles.
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Figure 23-21. Possible Status Codes Caused by Arbitration
START
SLA
Data
Arbitration lost in SLA
Own
Address / General Call
received
No
STOP
Arbitration lost in Data
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Yes
Direction
Write
68/78
Read
B0
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
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23.9
Register Description
23.9.1 TWBR – TWI Bit Rate Register
Bit
7
6
5
4
3
2
1
0
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
(0xB8)
TWBR
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which
generates the SCL clock frequency in the Master modes. See ”Bit Rate Generator Unit” on page 212 for calculating
bit rates.
23.9.2 TWCR – TWI Control Register
Bit
7
6
5
4
3
2
1
0
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
(0xBC)
TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by
applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to
control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write
collision if data is attempted written to TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software response. If
the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag
is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it.
Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that
clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status
Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is
generated on the TWI bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily.
Address recognition can then be resumed by writing the TWEA bit to one again.
• Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI
hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the
bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to
claim the bus Master status. TWSTA must be cleared by software when the START condition has been
transmitted.
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• Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the
STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the
TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI
returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is
cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI
takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters.
If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any
ongoing operation.
• Bit 1 – Reserved
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as
the TWINT Flag is high.
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23.9.3 TWSR – TWI Status Register
Bit
7
6
5
4
3
2
1
0
TWS7
TWS6
TWS5
TWS4
TWS3
–
TWPS1
TWPS0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
1
1
1
1
1
0
0
0
(0xB9)
TWSR
• Bits 7:3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described
later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler
value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes
status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Reserved
This bit is reserved and will always read as zero.
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 23-8.
TWI Bit Rate Prescaler
TWPS1
TWPS0
Prescaler Value
0
0
1
0
1
4
1
0
16
1
1
64
To calculate bit rates, see ”Bit Rate Generator Unit” on page 212. The value of TWPS1...0 is used in the equation.
23.9.4 TWDR – TWI Data Register
Bit
7
6
5
4
3
2
1
0
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
(0xBB)
TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last
byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt
Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first
interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the
bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up
from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus
arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically
by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial
Bus.
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23.9.5 TWAR – TWI (Slave) Address Register
Bit
7
6
5
4
3
2
1
0
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
0
(0xBA)
TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the
TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In
multi master systems, TWAR must be set in masters which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address
comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a
match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
23.9.6 TWAMR – TWI (Slave) Address Mask Register
Bit
7
6
5
(0xBD)
4
3
2
1
0
TWAM[6:0]
–
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0
TWAMR
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the
corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address
match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 2322 on page 235 shows the address match logic in detail.
Figure 23-22. TWI Address Match Logic, Block Diagram
TWAR0
Address
Match
Address
Bit 0
TWAMR0
Address Bit Comparator 0
Address Bit Comparator 6..1
• Bit 0 – Reserved
This bit is an unused bit in the Atmel ATmega48PB/88PB/168PB, and will always read as zero.
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24.
Analog Comparator
24.1
Overview
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the
voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator
output, ACO (on Port E[0]), is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture
function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user
can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its
surrounding logic is shown in Figure 24-1.
The Power Reduction ADC bit, PRADC, in ”Minimizing Power Consumption” on page 39 must be disabled by
writing a logical zero to be able to use the ADC input MUX.
Figure 24-1.
Analog Comparator Block Diagram(2)
BANDGAP
REFERENCE
ACBG
ACME
ADEN
ADC MUL
TIPLEXER
OUTPUT(1)
PE0 (ACO)
ACOE
Notes:
24.2
1. See Table 24-1 on page 236.
2. Refer to Figure 2-1 on page 3 and Table 15-9 on page 84 for Analog Comparator pin placement.
Analog Comparator Multiplexed Input
It is possible to select any of the ADC7...0 pins to replace the negative input to the Analog Comparator. The ADC
multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the
Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in
ADCSRA is zero), MUX2...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator,
as shown in Table 24-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog
Comparator.
Table 24-1.
Analog Comparator Multiplexed Input
ACME
ADEN
MUX2...0
Analog Comparator Negative Input
0
x
xxx
AIN1
1
1
xxx
AIN1
1
0
000
ADC0
1
0
001
ADC1
1
0
010
ADC2
1
0
011
ADC3
1
0
100
ADC4
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Table 24-1.
24.3
Analog Comparator Multiplexed Input (Continued)
ACME
ADEN
MUX2...0
Analog Comparator Negative Input
1
0
101
ADC5
1
0
110
ADC6
1
0
111
ADC7
Register Description
24.3.1 ADCSRB – ADC Control and Status Register B
Bit
7
6
5
4
3
2
1
0
(0x7B)
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer
selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the
negative input of the Analog Comparator. For a detailed description of this bit, see ”Analog Comparator Multiplexed
Input” on page 236.
24.3.2 ACSR0 – Analog Comparator Control and Status Register C
Bit
7
6
5
4
3
2
1
0
0x2F (0x4F)
-
-
-
-
-
-
-
ACOE
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
ACSR0
• Bit 7:1 – Reserved
These bits are unused bits in the Atmel ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 0 – ACOE: Analog Comparator Output Enable
When this bit is set, the analog comparator output is connected to the ACO pin.
24.3.3 ACSR – Analog Comparator Control and Status Register
Bit
7
6
5
4
3
2
1
0
0x30 (0x50)
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
0
0
0
0
0
ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any
time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When
changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When
this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. When the bandgap reference is
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used as input to the Analog Comparator, it will take a certain time for the voltage to stabilize. If not stabilized, the
first conversion may give a wrong value. See ”Internal Voltage Reference” on page 48
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization
introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and
ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI
is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by
writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is
activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog
Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making
the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt.
When written logic zero, no connection between the Analog Comparator and the input capture function exists. To
make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings
are shown in Table 24-2.
Table 24-2.
ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
0
Comparator Interrupt on Output Toggle.
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge.
1
1
Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt
Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
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24.3.4 DIDR1 – Digital Input Disable Register 1
Bit
7
6
5
4
3
2
1
0
(0x7F)
–
–
–
–
–
–
AIN1D
AIN0D
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR1
• Bit 7:2 – Reserved
These bits are unused bits in the Atmel ATmega48PB/88PB/168PB, and will always read as zero.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN
Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the
digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the
digital input buffer.
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25.
Analog-to-Digital Converter
25.1
Features
25.2

10-bit Resolution

0.5 LSB Integral Non-linearity

±2 LSB Absolute Accuracy

13 - 260µs Conversion Time

Up to 76.9ksps (Up to 15ksps at Maximum Resolution)

Six Multiplexed Single Ended Input Channels

Two Additional Multiplexed Single Ended Input Channels (TQFP and VFQFN Package only)

Temperature Sensor Input Channel

Optional Left Adjustment for ADC Result Readout

0 - VCC ADC Input Voltage Range

Selectable 1.1V ADC Reference Voltage

Free Running or Single Conversion Mode

Interrupt on ADC Conversion Complete

Sleep Mode Noise Canceler
Overview
The Atmel ATmega48PB/88PB/168PB features a 10-bit successive approximation ADC. The ADC is connected to
an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port
A. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant
level during conversion. A block diagram of the ADC is shown in Figure 25-1 on page 241.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3V from VCC. See the
paragraph ”ADC Noise Canceler” on page 246 on how to connect this pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage reference must be
externally decoupled at the AREF pin by a capacitor for better noise performance.
The Power Reduction ADC bit, PRADC, in ”Minimizing Power Consumption” on page 39 must be disabled by
writing a logical zero to enable the ADC.
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The
minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB.
Optionally, AVCC or an internal 1.1V reference voltage may be connected to the AREF pin by writing to the REFSn
bits in the ADMUX Register. The internal voltage reference must be decoupled by an external capacitor at the
AREF pin to improve noise immunity.
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Figure 25-1.
Analog to Digital Converter Block Schematic Operation,
ADC CONVERSION
COMPLETE IRQ
ADC[9:0]
ADPS1
0
ADC DATA REGISTER
(ADCH/ADCL)
ADPS0
ADPS2
ADIF
ADFR
ADEN
ADSC
MUX1
15
ADC CTRL. & STATUS
REGISTER (ADCSRA)
MUX0
MUX3
MUX2
ADLAR
REFS0
REFS1
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
ADIF
8-BIT DATA BUS
MUX DECODER
CHANNEL SELECTION
PRESCALER
AVCC
CONVERSION LOGIC
INTERNAL 1.1V
REFERENCE
SAMPLE & HOLD
COMPARATOR
AREF
10-BIT DAC
+
TEMPERATURE
SENSOR
GND
BANDGAP
REFERENCE
ADC7
ADC6
INPUT
MUX
ADC MULTIPLEXER
OUTPUT
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as
GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is
enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not
go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended
to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default,
the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in
ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same
conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been
read, and a conversion completes before ADCH is read, neither register is updated and the result from the
conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the
Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
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25.3
Starting a Conversion
A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in ”Minimizing Power
Consumption” on page 39 by writing a logical zero to it and writing a logical one to the ADC Start Conversion bit,
ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the
conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish
the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger
Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When a positive
edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a
method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a
new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge
will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt
Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the
Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.
Figure 25-2.
ADC Auto Trigger Logic
ADTS[2:0]
PRESCALER
START
ADIF
CLKADC
ADATE
SOURCE 1
.
.
.
.
SOURCE n
CONVERSION
LOGIC
EDGE
DETECTOR
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is
cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
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Prescaling and Conversion Timing
Figure 25-3.
ADC Prescaler
ADEN
START
Reset
7-BIT ADC PRESCALER
CK/64
CK/128
CK/32
CK/8
CK/16
CK/4
CK
CK/2
25.4
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to
get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be
higher than 200kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU
frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from
the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long
as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the
following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in
ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage to
stabilize. If not stabilized, the first value read after the first conversion may be wrong.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC
clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC
Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may
then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from
the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles
after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization
logic.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high. For a summary of conversion times, see Table 25-1 on page 245.
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Figure 25-4.
ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
Conversion
First Conversion
Cycle Number
1
2
12
13
14
16
15
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock
ADEN
ADSC
ADIF
Sign and MSB of Result
ADCH
LSB of Result
ADCL
MUX and REFS
Update
Figure 25-5.
Conversion
Complete
Sample & Hold
MUX and REFS
Update
ADC Timing Diagram, Single Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
3
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample & Hold
Conversion
Complete
MUX and REFS
Update
Figure 25-6.
MUX and REFS
Update
ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Prescaler
Reset
Sample &
Hold
Conversion
Complete
Prescaler
Reset
MUX and REFS
Update
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Figure 25-7.
ADC Timing Diagram, Free Running Conversion
One Conversion
Cycle Number
11
12
Next Conversion
13
1
2
3
4
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample & Hold
Conversion
Complete
Table 25-1.
ADC Conversion Time
Sample & Hold
(Cycles from Start of Conversion)
Condition
Conversion Time
(Cycles)
First conversion
13.5
25
Normal conversions, single ended
1.5
13
2
13.5
Auto Triggered conversions
25.5
MUX and REFS
Update
Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the
CPU has random access. This ensures that the channels and reference selection only takes place at a safe point
during the conversion. The channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for
the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The
user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle
after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken
when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is
changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX
can be safely updated in the following ways:
1.
When ADATE or ADEN is cleared.
1.1.
During conversion, minimum one ADC clock cycle after the trigger event.
1.2.
After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
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25.5.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct
channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the
conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The channel selection may
be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first
conversion to complete, and then change the channel selection. Since the next conversion has already started
automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the
new channel selection.
25.5.2 ADC Voltage Reference
The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that
exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 1.1V reference, or
external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal
bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected
to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the
AREF pin and ground. VREF can also be measured at the AREF pin with a high impedance voltmeter. Note that
VREF is a high impedance source, and only a capacitive load should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage
options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the
AREF pin, the user may switch between AVCC and 1.1V as reference selection. The first ADC conversion result
after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
25.6
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the
CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To
make use of this feature, the following procedure should be used:
1.
Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected
and the ADC conversion complete interrupt must be enabled.
1.1.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has
been halted.
1.2.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the
CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the
CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion
Complete interrupt request will be generated when the ADC conversion completes. The CPU will
remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC
Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid
excessive power consumption.
25.6.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 25-8 on page 247 An analog source
applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that
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channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor
through the series resistance (combined resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source
is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will
depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is
recommended to only use low impedance sources with slowly varying signals, since this minimizes the required
charge transfer to the S/H capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to
avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components
with a low-pass filter before applying the signals as inputs to the ADC.
Figure 25-8.
Analog Input Circuitry
IIH
ADCn
1..100 kΩ
CS/H= 14 pF
IIL
VCC/2
25.6.2 Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog
measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following
techniques:
1.
Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane,
and keep them well away from high-speed switching digital tracks.
1.1.
The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network
as shown in Figure 25-9 on page 248.
1.2.
Use the ADC noise canceler function to reduce induced noise from the CPU.
1.3.
If any ADC [3:0] port pins are used as digital outputs, it is essential that these do not switch while a
conversion is in progress. However, using the 2-wire Interface (ADC4 and ADC5) will only affect the
conversion on ADC4 and ADC5 and not the other ADC channels.
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Analog Ground Plane
PC2 (ADC2)
PC3 (ADC3)
PC4 (ADC4/SDA)
PC5 (ADC5/SCL)
VCC
ADC Power Connections
GND
Figure 25-9.
PC1 (ADC1)
PC0 (ADC0)
ADC7
10µH
GND
AREF
100nF
ADC6
AVCC
PB5
25.6.3 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code
is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
•
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB).
Ideal value: 0 LSB.
Figure 25-10. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
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•
Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to
0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB.
Figure 25-11. Gain Error
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF Input Voltage
•
Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an
actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
Figure 25-12. Integral Non-linearity (INL)
Output Code
INL
Ideal ADC
Actual ADC
VREF
•
Input Voltage
Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two
adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
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Figure 25-13. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
0
25.7
VREF Input Voltage
•
Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
•
Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal
transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and
quantization error. Ideal value: ±0.5 LSB.
ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers
(ADCL, ADCH).
For single ended conversion, the result is
V IN  1024
ADC = -------------------------V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 25-3 on page
252 and Table 25-4 on page 253). 0x000 represents analog ground, and 0x3FF represents the selected reference
voltage minus one LSB.
25.8
Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC8
channel. Selecting the ADC8 channel by writing the MUX3...0 bits in ADMUX register to "1000" enables the
temperature sensor. The internal 1.1V voltage reference must also be selected for the ADC voltage reference
source in the temperature sensor measurement. When the temperature sensor is enabled, the ADC converter can
be used in single conversion mode to measure the voltage over the temperature sensor.
The measured voltage has a linear relationship to the temperature as described in Table 25-2. The voltage
sensitivity is approximately 1 mV/°C and the accuracy of the temperature measurement is ±10°C.
Table 25-2.
Temperature vs. Sensor Output Voltage (Typical Case)
Temperature / C
Voltage / mV
-45C
+25C
+85C
242mV
314mV
380mV
The values described in Table 25-2 are typical values. However, due to the process variation the temperature
sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the
temperature measurement can be calibrated in the application software. The software calibration requires that a
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calibration value is measured and stored in a register or EEPROM for each chip, as a part of the production test.
The software calibration can be done utilizing the formula:
T = { [(ADCH << 8) | ADCL] - TOS} / k
where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sensor offset value
determined and stored into EEPROM as a part of the production test.
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25.9
Register Description
25.9.1 ADMUX – ADC Multiplexer Selection Register
Bit
7
6
5
4
3
2
1
0
REFS1
REFS0
ADLAR
–
MUX3
MUX2
MUX1
MUX0
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
(0x7C)
ADMUX
• Bit 7:6 – REFS[1:0]: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 25-3. If these bits are changed during a
conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal
voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.
Table 25-3.
•
Voltage Reference Selections for ADC
REFS1
REFS0
Voltage Reference Selection
0
0
AREF, Internal Vref turned off
0
1
AVCC with external capacitor at AREF pin
1
0
Reserved
1
1
Internal 1.1V Voltage Reference with external capacitor at AREF pin
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to
ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC
Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see
”ADCL and ADCH – The ADC Data Register” on page 254.
• Bit 4 – Reserved
This bit is an unused bit in the Atmel ATmega48PB/88PB/168PB, and will always read as zero.
• Bits 3:0 – MUX[3:0]: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. See Table 25-4 on page 253 for
details. If these bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
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Table 25-4.
Input Channel Selections
MUX3...0
Single Ended Input
0000
ADC0
0001
ADC1
0010
ADC2
0011
ADC3
0100
ADC4
0101
ADC5
0110
ADC6
0111
ADC7
1000
ADC8(1)
1001
(reserved)
1010
(reserved)
1011
(reserved)
1100
(reserved)
1101
(reserved)
1110
1.1V (VBG)
1111
0V (GND)
Note:
1. For Temperature Sensor.
25.9.2 ADCSRA – ADC Control and Status Register A
Bit
7
6
5
4
3
2
1
0
(0x7A)
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRA
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a
conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to
one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled,
or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal
13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero.
Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive
edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in
ADCSRB.
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• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion
Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the
flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies
if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
• Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the ADC.
Table 25-5.
ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
25.9.3 ADCL and ADCH – The ADC Data Register
25.9.3.1 ADLAR = 0
Bit
15
14
13
12
11
10
9
8
(0x79)
–
–
–
–
–
–
ADC9
ADC8
ADCH
(0x78)
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Initial Value
25.9.3.2 ADLAR = 1
Bit
15
14
13
12
11
10
9
8
(0x79)
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
(0x78)
ADC1
ADC0
–
–
–
–
–
–
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Initial Value
When an ADC conversion is complete, the result is found in these two registers.
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When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read
first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on page 250.
25.9.4 ADCSRB – ADC Control and Status Register B
Bit
7
6
5
4
3
2
1
0
(0x7B)
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 7, 5:3 – Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to
zero when ADCSRB is written.
• Bit 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of
the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching
to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 25-6.
ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
0
0
Free Running mode
0
0
1
Analog Comparator
0
1
0
External Interrupt Request 0
0
1
1
Timer/Counter0 Compare Match A
1
0
0
Timer/Counter0 Overflow
1
0
1
Timer/Counter1 Compare Match B
1
1
0
Timer/Counter1 Overflow
1
1
1
Timer/Counter1 Capture Event
25.9.5 DIDR0 – Digital Input Disable Register 0
Bit
7
6
5
4
3
2
1
0
(0x7E)
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR0
• Bit 7:0 – ADC7D...ADC0D: ADC7...0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The
corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the
ADC7...0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power
consumption in the digital input buffer.
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25.9.6 Device ID
Each individual part has a specific unique device ID. This can be used to identify a specify part while it is in the
field. The Device ID is consist of nine bytes in which the user can access directly from registers. The register
address locations are located at 0xF0 to 0xF8.
25.9.6.1 DIDRx – Device ID byte 8 to 0
Bit
7
6
5
4
3
2
1
0
0xF8
Device ID byte 8
DIDR8
0xF7
Device ID byte 7
DIDR7
0xF6
Device ID byte 6
DIDR6
0xF5
Device ID byte 5
DIDR5
0xF4
Device ID byte 4
DIDR4
0xF3
Device ID byte 3
DIDR3
0xF2
Device ID byte 2
DIDR2
0xF1
Device ID byte 1
DIDR1
0xF0
Device ID byte 0
DIDR0
Read/Write
Initial Value
R
R
R
R
R
R
R
R
Device ID value
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26.
debugWIRE On-chip Debug System
26.1
Features
26.2

Complete Program Flow Control

Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin

Real-time Operation

Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

Unlimited Number of Program Break Points (Using Software Break Points)

Non-intrusive Operation

Electrical Characteristics Identical to Real Device

Automatic Configuration System

High-speed Operation

Programming of Non-volatile Memories
Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow,
execute AVR instructions in the CPU and to program the different non-volatile memories.
26.3
Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE
system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bidirectional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator.
Figure 26-1.
The debugWIRE Setup
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure 26-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The
system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses.
When designing a system where debugWIRE will be used, the following observations must be made for correct
operation:
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26.4
•
Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required
for debugWIRE functionality
•
Connecting the RESET pin directly to VCC will not work
•
Capacitors connected to the RESET pin must be disconnected when using debugWire
•
All external reset sources must be disconnected
Software Break Points
debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in
Atmel Studio will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK
instruction will be stored. When program execution is continued, the stored instruction will be executed before
continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the
program.
The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by
Atmel Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Flash Data
retention. Devices used for debugging purposes should not be shipped to end customers.
26.5
Limitations of debugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An
External Reset source is therefore not supported when the debugWIRE is enabled.
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will
increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not
used.
26.6
Register Description
The following section describes the registers used with the debugWire.
26.6.1 DWDR – debugWire Data Register
Bit
7
6
5
4
3
2
1
0
DWDR[7:0]
DWDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The DWDR Register provides a communication channel from the running program in the MCU to the debugger.
This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in
the normal operations.
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27.
Self-Programming the Flash, ATmega48PB
27.1
Overview
In ATmega48PB there is no Read-While-Write support, and no separate Boot Loader Section. The SPM instruction
can be executed from the entire Flash.
The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU
itself. The Self-Programming can use any available data interface and associated protocol to read code and write
(program) that code into the Program memory.
The Program memory is updated in a page by page fashion. Before programming a page with the data stored in
the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using
SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page
Write operation:
Alternative 1, fill the buffer before a Page Erase
•
Fill temporary page buffer
•
Perform a Page Erase
•
Perform a Page Write
Alternative 2, fill the buffer after Page Erase
•
Perform a Page Erase
•
Fill temporary page buffer
•
Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary
page buffer) before the erase, and then be re-written. When using alternative 1, the Boot Loader provides an
effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary
changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while
loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is
essential that the page address used in both the Page Erase and Page Write operation is addressing the same
page.
27.1.1 Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and execute SPM
within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be
written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
•
Note:
The CPU is halted during the Page Erase operation
If an interrupt occurs in the time sequence the four cycle access cannot be guaranteed. In order to ensure atomic operation you should disable interrupts before writing to SPMCSR.
27.1.2 Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used
to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by
writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write
more than one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
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27.1.3 Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within
four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to
PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
•
27.2
The CPU is halted during the Page Write operation
Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Bit
15
14
13
12
11
10
9
8
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
7
6
5
4
3
2
1
0
Since the Flash is organized in pages (see Table 29-9 on page 287), the Program Counter can be treated as
having two different sections. One section, consisting of the least significant bits, is addressing the words within a
page, while the most significant bits are addressing the pages. This is shown in Figure 28-3 on page 272. Note that
the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that
the software addresses the same page in both the Page Erase and Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-bybyte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 27-1.
Addressing the Flash During SPM(1)
BIT
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
1. The different variables used in Figure 28-3 on page 272 are listed in Table 29-9 on page 287.
27.2.1 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock
bits from software will also be prevented during the EEPROM write operation. It is recommended that the user
checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
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27.2.2 Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with
0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU
cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the
destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no
LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Bit
7
6
5
4
3
2
1
0
Rd
–
–
–
–
–
–
LB2
LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To
read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When
an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. See Table 29-5 on
page 285 for a detailed description and mapping of the Fuse Low byte.
Bit
7
6
5
4
3
2
1
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction is
executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse
High byte will be loaded in the destination register as shown below. See Table 29-5 on page 285 for detailed
description and mapping of the Extended Fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is
executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended
Fuse byte will be loaded in the destination register as shown below. See Table 29-5 on page 285 for detailed
description and mapping of the Extended Fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be
read as one.
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27.2.3 Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU
and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the
same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute
instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not,
an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
2.
Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash
from unintentional writes.
27.2.4Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 27-1 shows the typical programming time for
Flash accesses from the CPU.
Table 27-1.
SPM Programming Time(1)
Symbol
Min. Programming Time
Max Programming Time
Flash write (Page Erase, Page Write, and write Lock
bits by SPM)
3.2ms
3.4ms
Note:
1.
Minimum and maximum programming time is per individual operation.
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27.2.5 Simple Assembly Code Example for a Boot Loader
Note that the RWWSB bit will always be read as zero in Atmel ATmega48PB. Nevertheless, it is recommended to
check this bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ
PAGESIZEB = PAGESIZE*2
;PAGESIZEB is page size in
BYTES, not words
.org SMALLBOOTSTART
Write_page:
;
Page Erase
ldi
spmcrval, (1<<PGERS) | (1<<SPMEN)
rcall
Do_spm
;
re-enable the RWW section
ldi
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcall
Do_spm
;
transfer data from RAM to Flash page buffer
ldi
looplo, low(PAGESIZEB)
;init loop variable
ldi
loophi, high(PAGESIZEB) ;not required for
PAGESIZEB<=256
Wrloop:
ld
r0, Y+
ld
r1, Y+
ldi
spmcrval, (1<<SPMEN)
rcall
Do_spm
adiw
ZH:ZL, 2
sbiw
loophi:looplo, 2
;use subi for PAGESIZEB<=256
brne
Wrloop
;
execute Page Write
subi
ZL, low(PAGESIZEB)
;restore pointer
sbci
ZH, high(PAGESIZEB)
;not required for
PAGESIZEB<=256
ldi
spmcrval, (1<<PGWRT) | (1<<SPMEN)
rcall
Do_spm
;
re-enable the RWW section
ldi
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcall
Do_spm
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;
read back and check, optional
ldi
looplo, low(PAGESIZEB)
ldi
loophi, high(PAGESIZEB)
PAGESIZEB<=256
subi
YL, low(PAGESIZEB)
sbci
YH, high(PAGESIZEB)
Rdloop:
lpm
r0, Z+
ld
r1, Y+
cpse
r0, r1
rjmp
Error
sbiw
loophi:looplo, 1
brne
Rdloop
;init loop variable
;not required for
;restore pointer
;use subi for PAGESIZEB<=256
;
return to RWW section
;
verify that RWW section is safe to read
Return:
in
temp1, SPMCSR
sbrs
temp1, RWWSB
; If RWWSB is set, the RWW
section is not ready yet
ret
;
re-enable the RWW section
ldi
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcall
Do_spm
rjmp
Return
Do_spm:
;
Wait_spm:
in
sbrc
rjmp
;
;
in
cli
;
Wait_ee:
sbic
rjmp
;
out
spm
;
out
ret
check for previous SPM complete
temp1, SPMCSR
temp1, SPMEN
Wait_spm
input: spmcrval determines SPM action
disable interrupts if enabled, store status
temp2, SREG
check that no EEPROM write access is present
EECR, EEPE
Wait_ee
SPM timed sequence
SPMCSR, spmcrval
restore SREG (to enable interrupts if originally enabled)
SREG, temp2
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27.3
Register Description
27.3.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Program
memory operations.
Bit
7
6
5
4
3
2
1
0
0x37 (0x57)
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPMCSR
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will
be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is
cleared. The interrupt will not be generated during EEPROM write or SPM.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero in ATmega48PB.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read
a byte from the signature row into the destination register. see ”Reading the Signature Row from Software” on
page 275 for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.
This operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The functionality of this bit in ATmega48PB is a subset of the functionality in ATmega48PB/88PB/168PB. If the
RWWSRE bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the
data will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
The functionality of this bit in ATmega48PB is a subset of the functionality in ATmega48PB/88PB/168PB. An LPM
instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read either the Lock
bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See ”Reading the Fuse and
Lock Bits from Software” on page 261 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes
Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if
no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes
Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire Page Write operation.
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• Bit 0 – SPMEN: Store Program Memory
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE,
BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If
only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of
an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page
Write, the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no
effect.
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28.
Boot Loader Support – Read-While-Write Self-Programming
The Boot Loader Support applies to Atmel ATmega48PB/88PB/168PB
28.1
Features

Read-While-Write Self-Programming

Flexible Boot Memory Size

High Security (Separate Boot Lock Bits for a Flexible Protection)

Separate Fuse to Select Reset Vector

Optimized Page(1) Size

Code Efficient Algorithm

Efficient Read-Modify-Write Support
Note:
28.2
1. A page is a section in the Flash consisting of several bytes (see Table 29-9 on page 287) used during programming. The page organization does not affect normal operation.
Overview
In ATmega48PB/88PB/168PB the Boot Loader Support provides a real Read-While-Write Self-Programming
mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application
software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program
can use any available data interface and associated protocol to read code and write (program) that code into the
Flash memory, or read the code from the program memory. The program code within the Boot Loader section has
the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even
modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot
Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can
be set independently. This gives the user a unique flexibility to select different levels of protection.
28.3
Application and Boot Loader Flash Sections
The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see
Figure 28-2 on page 270). The size of the different sections is configured by the BOOTSZ Fuses as shown in Table
28-7 on page 279 and Figure 28-2 on page 270. These two sections can have different level of protection since
they have different sets of Lock bits.
28.3.1 Application Section
The Application section is the section of the Flash that is used for storing the application code. The protection level
for the Application section can be selected by the application Boot Lock bits (Boot Lock bits 0), see Table 28-2 on
page 271. The Application section can never store any Boot Loader code since the SPM instruction is disabled
when executed from the Application section.
28.3.2 BLS – Boot Loader Section
While the Application section is used for storing the application code, the The Boot Loader software must be
located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The
SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader
section can be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 28-3 on page 271.
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28.4
Read-While-Write and No Read-While-Write Flash Sections
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is
dependent on which address that is being programmed. In addition to the two sections that are configurable by the
BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write
(RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWW- and NRWW sections
is given in Table 28-8 on page 279 and Figure 28-2 on page 270. The main difference between the two sections is:
•
When erasing or writing a page located inside the RWW section, the NRWW section can be read during the
operation
•
When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire
operation
Note that the user software can never read any code that is located inside the RWW section during a Boot Loader
software operation. The syntax “Read-While-Write section” refers to which section that is being programmed
(erased or written), not which section that actually is being read during a Boot Loader software update.
28.4.1 RWW – Read-While-Write Section
If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from
the Flash, but only code that is located in the NRWW section. During an on-going programming, the software must
ensure that the RWW section never is being read. If the user software is trying to read code that is located inside
the RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an
unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader section. The
Boot Loader section is always located in the NRWW section. The RWW Section Busy bit (RWWSB) in the Store
Program Memory Control and Status Register (SPMCSR) will be read as logical one as long as the RWW section
is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading
code located in the RWW section. See Section “28.9.1” on page 281. for details on how to clear RWWSB.
28.4.2 NRWW – No Read-While-Write Section
The code located in the NRWW section can be read when the Boot Loader software is updating a page in the
RWW section. When the Boot Loader code updates the NRWW section, the CPU is halted during the entire Page
Erase or Page Write operation.
Table 28-1.
Read-While-Write Features
Which Section does the Zpointer Address during the
Programming?
Which Section can be read
during Programming?
CPU Halted?
Read-While-Write
Supported?
RWW Section
NRWW Section
No
Yes
NRWW Section
None
Yes
No
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Figure 28-1.
Read-While-Write vs. No Read-While-Write
Read-While-Write
(RWW) Section
Z-pointer
Addresses RWW
Section
Z-pointer
Addresses NRWW
Section
No Read-While-Write
(NRWW) Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation
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Figure 28-2.
Memory Sections
Program Memory
BOOTSZ = '10'
Program Memory
BOOTSZ = '11'
0x0000
Read-While-Write Section
Application Flash Section
End RWW
Start NRWW
Application Flash Section
Boot Loader Flash Section
End Application
Start Boot Loader
Flashend
No Read-While-Write Section
No Read-While-Write Section
Read-While-Write Section
0x0000
Program Memory
BOOTSZ = '01'
Application Flash Section
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend
Program Memory
BOOTSZ = '00'
Note:
28.5
Read-While-Write Section
0x0000
Application Flash Section
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend
No Read-While-Write Section
No Read-While-Write Section
Read-While-Write Section
0x0000
Application Flash Section
End RWW, End Application
Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
1. The parameters in the figure above are given in Table 28-7 on page 279.
Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two
separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select
different levels of protection.
The user can select:
•
To protect the entire Flash from a software update by the MCU
•
To protect only the Boot Loader Flash section from a software update by the MCU
•
To protect only the Application Flash section from a software update by the MCU
•
Allow software update in the entire Flash
See Table 28-2 on page 271 and Table 28-3 on page 271 for further details. The Boot Lock bits can be set in
software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The
general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction.
Similarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is
attempted.
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Table 28-2.
BLB0 Mode
BLB02
BLB01
1
1
1
No restrictions for SPM or LPM accessing the Application section.
2
1
0
SPM is not allowed to write to the Application section.
Note:
Protection
3
0
0
SPM is not allowed to write to the Application section, and LPM executing
from the Boot Loader section is not allowed to read from the Application
section. If Interrupt Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
4
0
1
LPM executing from the Boot Loader section is not allowed to read from the
Application section. If Interrupt Vectors are placed in the Boot Loader section,
interrupts are disabled while executing from the Application section.
1.
Table 28-3.
“1” means unprogrammed, “0” means programmed.
Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)
BLB1 Mode
BLB12
BLB11
1
1
1
No restrictions for SPM or LPM accessing the Boot Loader section.
2
1
0
SPM is not allowed to write to the Boot Loader section.
Note:
28.6
Boot Lock Bit0 Protection Modes (Application Section)(1)
Protection
3
0
0
SPM is not allowed to write to the Boot Loader section, and LPM executing
from the Application section is not allowed to read from the Boot Loader
section. If Interrupt Vectors are placed in the Application section, interrupts
are disabled while executing from the Boot Loader section.
4
0
1
LPM executing from the Application section is not allowed to read from the
Boot Loader section. If Interrupt Vectors are placed in the Application section,
interrupts are disabled while executing from the Boot Loader section.
1.
“1” means unprogrammed, “0” means programmed
Entering the Boot Loader Program
Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a
trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be
programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot
Loader is started after a reset. After the application code is loaded, the program can start executing the application
code. Note that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is
programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed
through the serial or parallel programming interface.
Table 28-4.
Boot Reset Fuse(1)
BOOTRST
Note:
Reset Address
1
Reset Vector = Application Reset (address 0x0000)
0
Reset Vector = Boot Loader Reset (see Table 28-7 on page 279)
1.
“1” means unprogrammed, “0” means programmed
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28.7
Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Bit
15
14
13
12
11
10
9
8
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
7
6
5
4
3
2
1
0
Since the Flash is organized in pages (see Table 29-9 on page 287), the Program Counter can be treated as
having two different sections. One section, consisting of the least significant bits, is addressing the words within a
page, while the most significant bits are addressing the pages. This is1 shown in Figure 28-3. Note that the Page
Erase and Page Write operations are addressed independently. Therefore it is of major importance that the Boot
Loader software addresses the same page in both the Page Erase and Page Write operation. Once a
programming operation is initiated, the address is latched and the Z-pointer can be used for other operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Zpointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store
the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 28-3.
Addressing the Flash During SPM(1)
BIT
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PROGRAM MEMORY
PAGE
PCWORD
WORD ADDRESS
WITHIN A PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
1. The different variables used in Figure 28-3 are listed in Table 28-9 on page 279.
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28.8
Self-Programming the Flash
The program memory is updated in a page by page fashion. Before programming a page with the data stored in the
temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM
and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write
operation:
Alternative 1, fill the buffer before a Page Erase
•
Fill temporary page buffer
•
Perform a Page Erase
•
Perform a Page Write
Alternative 2, fill the buffer after Page Erase
•
Perform a Page Erase
•
Fill temporary page buffer
•
Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary
page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an
effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary
changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while
loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is
essential that the page address used in both the Page Erase and Page Write operation is addressing the same
page. See ” Simple Assembly Code Example for a Boot Loader” on page 276 for an assembly code example.
28.8.1 Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM
within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be
written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
•
Page Erase to the RWW section: The NRWW section can be read during the Page Erase
•
Page Erase to the NRWW section: The CPU is halted during the operation
28.8.2 Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used
to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by
writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write
more than one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
28.8.3 Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within
four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to
PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
•
Page Write to the RWW section: The NRWW section can be read during the Page Write
•
Page Write to the NRWW section: The CPU is halted during the operation
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28.8.4 Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in
SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in
software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an
interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in
”Interrupts” on page 55.
28.8.5 Consideration While Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11
unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further
software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is
recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
28.8.6 Prevent Reading the RWW Section During Self-Programming
During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The
user software itself must prevent that this section is addressed during the self programming operation. The
RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Programming the Interrupt
Vector table should be moved to the BLS as described in ”Watchdog Timer” on page 49, or the interrupts must be
disabled. Before addressing the RWW section after the programming is completed, the user software must clear
the RWWSB by writing the RWWSRE. See ” Simple Assembly Code Example for a Boot Loader” on page 276 for
an example.
28.8.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR.
Bit
7
6
5
4
3
2
1
0
R0
1
1
BLB12
BLB11
BLB02
BLB01
LB2
LB1
See Table 28-2 on page 271 and Table 28-3 on page 271 for how the different settings of the Boot Loader bits
affect the Flash access.
If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction is
executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this
operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for
reading the lOck bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when writing
the Lock bits. When programming the Lock bits the entire Flash can be read during the operation.
28.8.8 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock
bits from software will also be prevented during the EEPROM write operation. It is recommended that the user
checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
28.8.9 Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with
0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU
cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the
destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no
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LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Bit
7
6
5
4
3
2
1
0
Rd
–
–
BLB12
BLB11
BLB02
BLB01
LB2
LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To
read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When
an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 29-5 on
page 285 for a detailed description and mapping of the Fuse Low byte.
Bit
7
6
5
4
3
2
1
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte
(FHB) will be loaded in the destination register as shown below. Refer to Table 29-6 on page 285 for detailed
description and mapping of the Fuse High byte.
Bit
7
6
5
4
3
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within
three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte
(EFB) will be loaded in the destination register as shown below. Refer to Table 29-5 on page 285 for detailed
description and mapping of the Extended Fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd
–
–
–
–
EFB3
EFB2
EFB1
EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be
read as one.
28.8.10 Reading the Signature Row from Software
To read the Signature Row from software, load the Z-pointer with the signature byte address given in Table 28-5
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles
after the SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the destination
register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if
no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as
described in the Instruction set Manual.
Table 28-5.
Signature Row Addressing
Signature Byte
Z-Pointer Address
Device Signature Byte 1
0x0000
Device Signature Byte 2
0x0002
Device Signature Byte 3
0x0004
RC Oscillator Calibration Byte
0x0001
Note:
All other addresses are reserved for future use.
28.8.11 Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU
and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the
same design solutions should be applied.
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A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute
instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent
any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an
external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the
write operation will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash
from unintentional writes.
28.8.12 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 28-6 shows the typical programming time for
Flash accesses from the CPU.
Table 28-6.
SPM Programming Time(1)
Symbol
Flash write (Page Erase, Page Write, and write Lock bits by
SPM)
Note:
1.
Min. Programming Time
Max. Programming Time
3.2ms
3.4ms
Minimum and maximum programming time is per individual operation.
28.8.13 Simple Assembly Code Example for a Boot Loader
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ
PAGESIZEB = PAGESIZE*2
;PAGESIZEB is page size in
BYTES, not words
.org SMALLBOOTSTART
Write_page:
;
Page Erase
ldi
spmcrval, (1<<PGERS) | (1<<SPMEN)
call
Do_spm
;
ldi
call
re-enable the RWW section
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
Do_spm
;
transfer data from RAM to Flash page buffer
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ldi
ldi
PAGESIZEB<=256
Wrloop:
ld
ld
ldi
call
adiw
sbiw
brne
looplo, low(PAGESIZEB)
loophi, high(PAGESIZEB)
r0, Y+
r1, Y+
spmcrval, (1<<SPMEN)
Do_spm
ZH:ZL, 2
loophi:looplo, 2
Wrloop
;init loop variable
;not required for
;use subi for PAGESIZEB<=256
;
execute Page Write
subi
ZL, low(PAGESIZEB)
;restore pointer
sbci
ZH, high(PAGESIZEB)
;not required for
PAGESIZEB<=256
ldi
spmcrval, (1<<PGWRT) | (1<<SPMEN)
call
Do_spm
;
ldi
call
re-enable the RWW section
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
Do_spm
;
read back and check, optional
ldi
looplo, low(PAGESIZEB)
ldi
loophi, high(PAGESIZEB)
PAGESIZEB<=256
subi
YL, low(PAGESIZEB)
sbci
YH, high(PAGESIZEB)
Rdloop:
lpm
r0, Z+
ld
r1, Y+
cpse
r0, r1
jmp
Error
sbiw
loophi:looplo, 1
brne
Rdloop
;init loop variable
;not required for
;restore pointer
;use subi for PAGESIZEB<=256
;
return to RWW section
;
verify that RWW section is safe to read
Return:
in
temp1, SPMCSR
sbrs
temp1, RWWSB
; If RWWSB is set, the RWW
section is not ready yet
ret
;
re-enable the RWW section
ldi
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call
Do_spm
rjmp
Return
Do_spm:
;
Wait_spm:
in
sbrc
rjmp
check for previous SPM complete
temp1, SPMCSR
temp1, SPMEN
Wait_spm
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;
;
in
cli
;
Wait_ee:
sbic
rjmp
;
out
spm
;
out
ret
input: spmcrval determines SPM action
disable interrupts if enabled, store status
temp2, SREG
check that no EEPROM write access is present
EECR, EEPE
Wait_ee
SPM timed sequence
SPMCSR, spmcrval
restore SREG (to enable interrupts if originally enabled)
SREG, temp2
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28.8.14 ATmega88PB Boot Loader Parameters
In Table 28-7 through Table 28-9, the parameters used in the description of the self programming are given.
Table 28-7.
Boot Size Configuration, ATmega88PB
BOOTSZ1
BOOTSZ0
Boot Size
Pages
Application
Flash Section
Boot Loader
Flash Section
End Application
Section
Boot Reset Address
(Start Boot Loader Section)
1
1
128 words
4
0x000 - 0xF7F
0xF80 - 0xFFF
0xF7F
0xF80
1
0
256 words
8
0x000 - 0xEFF
0xF00 - 0xFFF
0xEFF
0xF00
0
1
512 words
16
0x000 - 0xDFF
0xE00 - 0xFFF
0xDFF
0xE00
0
0
1024 words
32
0x000 - 0xBFF
0xC00 - 0xFFF
0xBFF
0xC00
Note:
Table 28-8.
The different BOOTSZ Fuse configurations are shown in Figure 28-2 on page 270.
Read-While-Write Limit, ATmega88PB
Section
Pages
Address
Read-While-Write section (RWW)
96
0x000 - 0xBFF
No Read-While-Write section (NRWW)
32
0xC00 - 0xFFF
For details about these two section, see ”NRWW – No Read-While-Write Section” on page 268 and ”RWW – Read-WhileWrite Section” on page 268.
Table 28-9.
Explanation of Different Variables used in Figure 28-3 and the Mapping to the Z-pointer, ATmega88PB
Corresponding
Z-value(1)
Variable
Description
PCMSB
11
Most significant bit in the Program Counter. (The Program Counter is
12 bits PC[11:0])
PAGEMSB
4
Most significant bit which is used to address the words within one
page (32 words in a page requires 5 bits PC [4:0]).
ZPCMSB
Z12
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,
the ZPCMSB equals PCMSB + 1.
ZPAGEMSB
Z5
Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not
used, the ZPAGEMSB equals PAGEMSB + 1.
PCPAGE
PC[11:5]
Z12:Z6
Program counter page address: Page select, for page erase and
page write
PCWORD
PC[4:0]
Z5:Z1
Program counter word address: Word select, for filling temporary
buffer (must be zero during page write operation)
Note:
1. Z15:Z13: always ignored
Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See ”Addressing the Flash During Self-Programming” on page 272 for details about the use of Z-pointer during SelfProgramming.
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28.8.15 ATmega168PB Boot Loader Parameters
In Table 28-10 through Table 28-12, the parameters used in the description of the self programming are given.
Table 28-10.
Boot Size Configuration, ATmega168PB
Application
Flash Section
Boot Loader
Flash Section
End Application
Section
Boot Reset Address
(Start Boot Loader Section)
2
0x0000 - 0x1F7F
0x1F80 - 0x1FFF
0x1F7F
0x1F80
256 words
4
0x0000 - 0x1EFF
0x1F00 - 0x1FFF
0x1EFF
0x1F00
1
512 words
8
0x0000 - 0x1DFF
0x1E00 - 0x1FFF
0x1DFF
0x1E00
0
1024 words
16
0x0000 - 0x1BFF
0x1C00 - 0x1FFF
0x1BFF
0x1C00
BOOTSZ1
BOOTSZ0
Boot Size
Pages
1
1
128 words
1
0
0
0
Note:
Table 28-11.
The different BOOTSZ Fuse configurations are shown in Figure 28-2 on page 270.
Read-While-Write Limit, ATmega168PB
Section
Pages
Address
Read-While-Write section (RWW)
112
0x0000 - 0x1BFF
No Read-While-Write section (NRWW)
16
0x1C00 - 0x1FFF
For details about these two section, see ”NRWW – No Read-While-Write Section” on page 268 and ”RWW – Read-WhileWrite Section” on page 268.
Table 28-12.
Explanation of Different Variables used in Figure 28-3 on page 272 and the Mapping to the Z-pointer,
ATmega168PB
Corresponding
Z-value(1)
Variable
Description
PCMSB
12
Most significant bit in the Program Counter. (The Program Counter
is 13 bits PC[12:0])
PAGEMSB
5
Most significant bit which is used to address the words within one
page (64 words in a page requires 6 bits PC [5:0])
ZPCMSB
Z13
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,
the ZPCMSB equals PCMSB + 1.
ZPAGEMSB
Z6
Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not
used, the ZPAGEMSB equals PAGEMSB + 1.
PCPAGE
PC[12:6]
Z13:Z7
Program counter page address: Page select, for page erase and
page write
PCWORD
PC[5:0]
Z6:Z1
Program counter word address: Word select, for filling temporary
buffer (must be zero during page write operation)
Note:
1. Z15:Z14: always ignored
Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See ”Addressing the Flash During Self-Programming” on page 272 for details about the use of Z-pointer during SelfProgramming.
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28.9
Register Description
28.9.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Boot
Loader operations.
Bit
7
6
5
4
3
2
1
0
0x37 (0x57)
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPMCSR
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will
be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is
cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB will
be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit
will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively
the RWWSB bit will automatically be cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read
a byte from the signature row into the destination register. see ”Reading the Signature Row from Software” on
page 275 for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.
This operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the
RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the
programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time
as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section
cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE
bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot
Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are
ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction
is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read either
the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See ”Reading the
Fuse and Lock Bits from Software” on page 274 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes
Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if
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no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if
the NRWW section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes
Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Store Program Memory
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE,
BLBSET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If
only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of
an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page
Write, the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no
effect.
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29.
Memory Programming
29.1
Program And Data Memory Lock Bits
The ATmega48PB provides two Lock bits and the ATmega48PB/88PB/168PBprovides six Lock bits. These can be
left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 29-2. The Lock
bits can only be erased to “1” with the Chip Erase command.
The ATmega48PB has no separate Boot Loader section, and the SPM instruction is enabled for the whole Flash if
the SELFPRGEN fuse is programmed (“0”). Otherwise the SPM instruction is disabled.
Table 29-1.
Lock Bit Byte(1)
Lock Bit Byte
Bit No.
Description
Default Value
7
–
1 (unprogrammed)
6
–
1 (unprogrammed)
(2)
5
Boot Lock bit
1 (unprogrammed)
BLB11(2)
4
Boot Lock bit
1 (unprogrammed)
BLB02
(2)
3
Boot Lock bit
1 (unprogrammed)
BLB01
(2)
2
Boot Lock bit
1 (unprogrammed)
LB2
1
Lock bit
1 (unprogrammed)
LB1
0
Lock bit
1 (unprogrammed)
BLB12
Notes:
1.
2.
Table 29-2.
“1” means unprogrammed, “0” means programmed.
Only on ATmega48PB/88PB/168PB.
Lock Bit Protection Modes(1)(2)
Memory Lock Bits
LB Mode
LB2
LB1
1
1
1
No memory lock features enabled.
2
1
0
Further programming of the Flash and EEPROM is disabled in Parallel and Serial
Programming mode. The Fuse bits are locked in both Serial and Parallel
Programming mode.(1)
3
0
0
Further programming and verification of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Boot Lock bits and Fuse bits are locked
in both Serial and Parallel Programming mode.(1)
Notes:
1.
2.
Protection Type
Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
“1” means unprogrammed, “0” means programmed.
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Lock Bit Protection Modes(1)(2). Only ATmega48PB/88PB/168PB
Table 29-3.
BLB0 Mode
BLB02
BLB01
1
1
1
No restrictions for SPM or LPM accessing the Application section.
2
1
0
SPM is not allowed to write to the Application section.
3
0
0
SPM is not allowed to write to the Application section, and LPM executing from the
Boot Loader section is not allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts are disabled while executing
from the Application section.
4
0
1
LPM executing from the Boot Loader section is not allowed to read from the
Application section. If Interrupt Vectors are placed in the Boot Loader section,
interrupts are disabled while executing from the Application section.
BLB1 Mode
BLB12
BLB11
1
1
1
No restrictions for SPM or LPM accessing the Boot Loader section.
2
1
0
SPM is not allowed to write to the Boot Loader section.
Notes:
29.2
3
0
0
SPM is not allowed to write to the Boot Loader section, and LPM executing from the
Application section is not allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Application section, interrupts are disabled while executing
from the Boot Loader section.
4
0
1
LPM executing from the Application section is not allowed to read from the Boot
Loader section. If Interrupt Vectors are placed in the Application section, interrupts
are disabled while executing from the Boot Loader section.
1.
2.
Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
“1” means unprogrammed, “0” means programmed.
Fuse Bits
The ATmega48PB/88PB/168PB has three Fuse bytes. Table 29-4 and Table 29-7 on page 285 describe briefly the
functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical
zero, “0”, if they are programmed.
Table 29-4.
Extended Fuse Byte for ATmega48PB
Extended Fuse Byte
Bit No.
Description
Default Value
–
7
–
1
–
6
–
1
–
5
–
1
–
4
–
1
–
3
–
1
–
2
–
1
–
1
–
1
SELFPRGEN
0
Self Programming Enable
1 (unprogrammed)
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Table 29-5.
Extended Fuse Byte for ATmega88PB/168PB
Extended Fuse Byte
Bit No.
Description
Default Value
–
7
–
1
–
6
–
1
–
5
–
1
–
4
–
1
–
3
–
1
BOOTSZ1
2
Select Boot Size
(see Table 28-7 on page 279 and
Table 28-10 on page 280 for details)
0 (programmed)(1)
BOOTSZ0
1
Select Boot Size
(see Table 28-7 on page 279 and
Table 28-10 on page 280 for details)
0 (programmed)(1)
BOOTRST
0
Select Reset Vector
1 (unprogrammed)
Note:
1.
The default value of BOOTSZ[1:0] results in maximum Boot Size. See ”Pin Name Mapping” on page 288.
Table 29-6.
Fuse High Byte for ATmega48PB/88PB/168PB
High Fuse Byte
(1)
Bit No.
Description
Default Value
RSTDISBL
7
External Reset Disable
1 (unprogrammed)
DWEN
6
debugWIRE Enable
1 (unprogrammed)
SPIEN(2)
5
Enable Serial Program and Data
Downloading
0 (programmed, SPI
programming enabled)
WDTON(3)
4
Watchdog Timer Always On
1 (unprogrammed)
EESAVE
3
EEPROM memory is preserved through
the Chip Erase
1 (unprogrammed), EEPROM
not reserved
BODLEVEL2(4)
2
Brown-out Detector trigger level
1 (unprogrammed)
(4)
1
Brown-out Detector trigger level
1 (unprogrammed)
(4)
0
Brown-out Detector trigger level
1 (unprogrammed)
BODLEVEL1
BODLEVEL0
Notes:
1.
2.
3.
4.
Table 29-7.
See ”Alternate Functions of Port C” on page 82 for description of RSTDISBL Fuse.
The SPIEN Fuse is not accessible in serial programming mode.
See ”WDTCSR – Watchdog Timer Control Register” on page 52 for details.
See Table 30-7 on page 306 for BODLEVEL Fuse decoding.
Fuse Low Byte
Low Fuse Byte
Description
Default Value
7
Divide clock by 8
0 (programmed)
CKOUT(3)
6
Clock output
1 (unprogrammed)
SUT1
5
Select start-up time
1 (unprogrammed)(1)
SUT0
4
Select start-up time
0 (programmed)(1)
CKSEL3
3
Select Clock source
0 (programmed)(2)
(4)
CKDIV8
Bit No.
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Fuse Low Byte (Continued)
Table 29-7.
Low Fuse Byte
Bit No.
Description
Default Value
CKSEL2
2
Select Clock source
0 (programmed)(2)
CKSEL1
1
Select Clock source
1 (unprogrammed)(2)
CKSEL0
0
Select Clock source
0 (programmed)(2)
Note:
1.
2.
3.
4.
The default value of SUT1...0 results in maximum start-up time for the default clock source. See Table 10-12 on
page 32 for details.
The default setting of CKSEL3...0 results in internal RC Oscillator @ 8MHz. See Table 10-11 on page 32 for
details.
The CKOUT Fuse allows the system clock to be output on PORTB0. See ”Clock Output Buffer” on page 34 for
details.
See ”System Clock Prescaler” on page 34 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is
programmed. Program the Fuse bits before programming the Lock bits.
29.2.1 Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of the fuse values will have
no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect
once it is programmed. The fuses are also latched on Power-up in Normal mode.
29.3
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in
both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATmega48PB/88PB/168PB the signature bytes are given in Table 29-8.
Table 29-8.
Device ID
Signature Bytes Address
29.4
Part
0x000
0x001
0x002
ATmega48PB
0x1E
0x92
0x10
ATmega88PB
0x1E
0x93
0x16
ATmega168PB
0x1E
0x94
0x15
Calibration Byte
The ATmega48PB/88PB/168PB has a byte calibration value for the Internal RC Oscillator. This byte resides in the
high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the
OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
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29.5
Page Size
Table 29-9.
No. of Words in a Page and No. of Pages in the Flash
Flash Size
Page Size
PCWORD
No. of
Pages
PCPAGE
PCMSB
ATmega48PB
2K words
(4Kbytes)
32 words
PC[4:0]
64
PC[10:5]
10
ATmega88PB
4K words
(8Kbytes)
32 words
PC[4:0]
128
PC[11:5]
11
64 words
PC[5:0]
128
PC[12:6]
12
Device
ATmega168PB
Table 29-10.
29.6
8K words
(16Kbytes)
No. of Words in a Page and No. of Pages in the EEPROM
Device
EEPROM
Size
Page
Size
PCWORD
No. of
Pages
PCPAGE
EEAMSB
ATmega48PB
256bytes
4bytes
EEA[1:0]
64
EEA[7:2]
7
ATmega88PB
512bytes
4bytes
EEA[1:0]
128
EEA[8:2]
8
ATmega168PB
512bytes
4bytes
EEA[1:0]
128
EEA[8:2]
8
Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory,
Memory Lock bits, and Fuse bits in the ATmega48PB/88PB/168PB. Pulses are assumed to be at least 250ns
unless otherwise noted.
29.6.1 Signal Names
In this section, some pins of the ATmega48PB/88PB/168PB are referenced by signal names describing their
functionality during parallel programming, see Figure 29-1 on page 288 and Table 29-11 on page 288. Pins not
described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is
shown in Table 29-13 on page 288.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are
shown in Table 29-14 on page 289.
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Figure 29-1.
Parallel Programming
+4.5 - 5.5V
RDY/BSY
PD1
OE
PD2
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12 V
VCC
+4.5 - 5.5V
AVCC
PC[1:0]:PB[5:0]
DATA
RESET
BS2
PC2
XTAL1
GND
VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V
Note:
Table 29-11.
Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O
Function
RDY/BSY
PD1
O
0: Device is busy programming, 1: Device is ready for
new command
OE
PD2
I
Output Enable (Active low)
WR
PD3
I
Write Pulse (Active low)
BS1
PD4
I
Byte Select 1 (“0” selects Low byte, “1” selects High byte)
XA0
PD5
I
XTAL Action Bit 0
XA1
PD6
I
XTAL Action Bit 1
PAGEL
PD7
I
Program memory and EEPROM Data Page Load
BS2
PC2
I
Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High
byte)
{PC[1:0]: PB[5:0]}
I/O
DATA
Table 29-12.
Bi-directional Data bus (Output when OE is low)
Pin Values Used to Enter Programming Mode
Pin
Symbol
Value
PAGEL
Prog_enable[3]
0
XA1
Prog_enable[2]
0
XA0
Prog_enable[1]
0
BS1
Prog_enable[0]
0
Table 29-13.
XA1 and XA0 Coding
XA1
XA0
Action when XTAL1 is Pulsed
0
0
Load Flash or EEPROM Address (High or low address byte determined by BS1)
0
1
Load Data (High or Low data byte for Flash determined by BS1)
1
0
Load Command
1
1
No Action, Idle
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Table 29-14.
Command Byte Bit Coding
Command Byte
29.7
Command Executed
1000 0000
Chip Erase
0100 0000
Write Fuse bits
0010 0000
Write Lock bits
0001 0000
Write Flash
0001 0001
Write EEPROM
0000 1000
Read Signature Bytes and Calibration byte
0000 0100
Read Fuse and Lock bits
0000 0010
Read Flash
0000 0011
Read EEPROM
Parallel Programming
29.7.1 Enter Programming Mode
The following algorithm puts the device in Parallel (High-voltage) Programming mode:
1. Set Prog_enable pins listed in Table 29-12 on page 288 to “0000”, RESET pin to 0V and VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
Ensure that VCC reaches at least 1.8V within the next 20µs.
3. Wait 20 - 60µs, and apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the
Prog_enable Signature has been latched.
5. Wait at least 300µs before giving any parallel programming commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be
used.
1. Set Prog_enable pins listed in Table 29-12 on page 288 to “0000”, RESET pin to 0V and VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the
Prog_enable Signature has been latched.
5. Wait until VCC actually reaches 4.5 - 5.5V before giving any parallel programming commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
29.7.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient programming, the
following should be considered.
•
The command needs only be loaded once when writing or reading multiple memory locations.
•
Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is
programmed) and Flash after a Chip Erase.
•
Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or
256 byte EEPROM. This consideration also applies to Signature bytes reading.
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29.7.3 Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the
program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed
before the Flash and/or EEPROM are reprogrammed.
Note:
1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”:
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.
29.7.4 Programming the Flash
The Flash is organized in pages, see Table 29-9 on page 287. When programming the Flash, the program data is
latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following
procedure describes how to program the entire Flash memory:
A. Load Command “Write Flash”.
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte.
1.
Set XA1, XA0 to “00”. This enables address loading.
2.
Set BS1 to “0”. This selects low address.
3.
Set DATA = Address low byte (0x00 - 0xFF).
4.
Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte.
1.
Set XA1, XA0 to “01”. This enables data loading.
2.
Set DATA = Data low byte (0x00 - 0xFF).
3.
Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte.
1.
Set BS1 to “1”. This selects high data byte.
2.
Set XA1, XA0 to “01”. This enables data loading.
3.
Set DATA = Data high byte (0x00 - 0xFF).
4.
Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data.
1.
Set BS1 to “1”. This selects high data byte.
2.
Give PAGEL a positive pulse. This latches the data bytes. (See Figure 29-3 on page 292 for signal waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages within
the FLASH. This is illustrated in Figure 29-2. Note that if less than eight bits are required to address words in the
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page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when
performing a Page Write.
G. Load Address High byte.
1.
Set XA1, XA0 to “00”. This enables address loading.
2.
Set BS1 to “1”. This selects high address.
3.
Set DATA = Address high byte (0x00 - 0xFF).
4.
Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page.
1.
Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.
2.
Wait until RDY/BSY goes high (See Figure 29-3 on page 292 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been programmed.
J. End Page Programming.
1.
1. Set XA1, XA0 to “10”. This enables command loading.
2.
Set DATA to “0000 0000”. This is the command for No Operation.
3.
Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.
Figure 29-2.
Addressing the Flash Which is Organized in Pages(1)
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PCWORD
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
1. PCPAGE and PCWORD are listed in Table 29-9 on page 287.
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Figure 29-3.
Programming the Flash Waveforms(1)
F
DATA
A
B
0x10
ADDR. LOW
C
DATA LOW
D
E
DATA HIGH
XX
B
ADDR. LOW
C
D
DATA LOW
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. “XX” is don’t care. The letters refer to the programming description above.
29.7.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 29-10 on page 287. When programming the EEPROM, the
program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The
programming algorithm for the EEPROM data memory is as follows (refer to ”Programming the Flash” on page 290
for details on Command, Address and Data loading):
1.
A: Load Command “0001 0001”.
2.
G: Load Address High Byte (0x00 - 0xFF).
3.
B: Load Address Low Byte (0x00 - 0xFF).
4.
C: Load Data (0x00 - 0xFF).
5.
E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1.
Set BS1 to “0”.
2.
Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
3.
Wait until to RDY/BSY goes high before programming the next page (See Figure 29-4 on page 293 for signal
waveforms).
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Figure 29-4.
Programming the EEPROM Waveforms
K
DATA
A
G
0x11
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
C
ADDR. LOW
DATA
E
L
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
29.7.6 Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on page 290 for details
on Command and Address loading):
1.
A: Load Command “0000 0010”.
2.
G: Load Address High Byte (0x00 - 0xFF).
3.
B: Load Address Low Byte (0x00 - 0xFF).
4.
Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5.
Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6.
Set OE to “1”.
29.7.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash” on page 290 for
details on Command and Address loading):
1. A: Load Command “0000 0011”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5. Set OE to “1”.
29.7.8 Programming the Fuse Low Bits
The algorithm for programming the Fuse Low bits is as follows (refer to ”Programming the Flash” on page 290 for
details on Command and Data loading):
1.
A: Load Command “0100 0000”.
2.
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3.
Give WR a negative pulse and wait for RDY/BSY to go high.
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29.7.9 Programming the Fuse High Bits
The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the Flash” on page 290 for
details on Command and Data loading):
1.
A: Load Command “0100 0000”.
2.
C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3.
Set BS1 to “1” and BS2 to “0”. This selects high data byte.
4.
Give WR a negative pulse and wait for RDY/BSY to go high.
5.
Set BS1 to “0”. This selects low data byte.
29.7.10 Programming the Extended Fuse Bits
The algorithm for programming the Extended Fuse bits is as follows (refer to ”Programming the Flash” on page 290
for details on Command and Data loading):
1.
1. A: Load Command “0100 0000”.
2.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3.
3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.
4.
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5.
5. Set BS2 to “0”. This selects low data byte.
Figure 29-5.
Programming the FUSES Waveforms
Write Fuse Low byte
DATA
A
C
0x40
DATA
XX
Write Fuse high byte
A
C
0x40
DATA
XX
Write Extended Fuse byte
A
C
0x40
DATA
XX
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
29.7.11 Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 290 for details
on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is
programmed), it is not possible to program the Boot Lock bits by any External Programming mode.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
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29.7.12 Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash” on page 290 for
details on Command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means
programmed).
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means
programmed).
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0”
means programmed).
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means
programmed).
6. Set OE to “1”.
Figure 29-6.
Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
Fuse Low Byte
0
Extended Fuse Byte
1
0
DATA
BS2
0
Lock Bits
1
Fuse High Byte
1
BS1
BS2
29.7.13 Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 290 for
details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
29.7.14 Reading the Calibration Byte
The algorithm for reading the Calibration byte is as follows (refer to ”Programming the Flash” on page 290 for
details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
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29.7.15 Parallel Programming Characteristics
For characteristics of the Parallel Programming, see ”Parallel Programming Characteristics” on page 312.
29.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled
to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the
Programming Enable instruction needs to be executed first before program/erase operations can be executed.
NOTE, in Table 29-15, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for
the internal SPI interface.
Figure 29-7.
Serial Programming and Verify(1)
+1.8 - 5.5V
VCC
+1.8 - 5.5V(2)
MOSI
AVCC
MISO
SCK
XTAL1
RESET
GND
Notes:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the
Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation
turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low:> Two CPU clock cycles for fck < 12MHz, three CPU clock cycles for fck  12MHz
High:> Two CPU clock cycles for fck < 12MHz, three CPU clock cycles for fck  12MHz
29.8.1 Serial Programming Pin Mapping
Table 29-15.
Pin Mapping Serial Programming
Symbol
Pins
I/O
Description
MOSI
PB3
I
Serial Data in
MISO
PB4
O
Serial Data out
SCK
PB5
I
Serial Clock
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29.8.2 Serial Programming Algorithm
When writing serial data to the ATmega48PB/88PB/168PB, data is clocked on the rising edge of SCK.
When reading data from the ATmega48PB/88PB/168PB, data is clocked on the falling edge of SCK. See Figure
29-9 on page 299 for timing details.
To program and verify the ATmega48PB/88PB/168PB in the serial programming mode, the following sequence is
recommended (See Serial Programming Instruction set in Table 29-17 on page 298):
1.
Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive
pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
2.
Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to
pin MOSI.
3.
The serial programming instructions will not work if the communication is out of synchronization. When in sync.
the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction.
Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo
back, give RESET a positive pulse and issue a new Programming Enable command.
4.
The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the
6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct
loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The
Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the
address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page
(See Table 29-16). Accessing the serial programming interface before the Flash write operation completes can
result in incorrect programming.
5.
A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is
written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte
(See Table 29-16). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by
supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The
EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of
the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory
Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the
used must wait at least tWD_EEPROM before issuing the next byte (See Table 29-16). In a chip erased device, no
0xFF in the data file(s) need to be programmed.
6.
Any memory location can be verified by using the Read instruction which returns the content at the selected
address at serial output MISO.
7.
At the end of the programming session, RESET can be set high to commence normal operation.
8.
Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
Table 29-16.
Typical Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol
Minimum Wait Delay
tWD_FLASH
2.6ms
tWD_EEPROM
3.6ms
tWD_ERASE
10.5ms
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29.8.3 Serial Programming Instruction set
Table 29-17 and Figure 29-8 on page 299 describes the Instruction set.
Table 29-17.
Serial Programming Instruction Set (Hexadecimal values)
Instruction Format
Instruction/Operation
Byte 1
Byte 2
Byte 3
Byte 4
Programming Enable
$AC
$53
$00
$00
Chip Erase (Program Memory/EEPROM)
$AC
$80
$00
$00
Poll RDY/BSY
$F0
$00
$00
data byte out
Load Extended Address byte(1)
$4D
$00
Extended adr
$00
Load Program Memory Page, High byte
$48
$00
adr LSB
high data byte in
Load Program Memory Page, Low byte
$40
$00
adr LSB
low data byte in
Load EEPROM Memory Page (page access)
$C1
$00
0000 000aa
data byte in
Read Program Memory, High byte
$28
adr MSB
adr LSB
high data byte out
Read Program Memory, Low byte
$20
adr MSB
adr LSB
low data byte out
Read EEPROM Memory
$A0
0000 00aa
aaaa aaaa
data byte out
Read Lock bits
$58
$00
$00
data byte out
Read Signature Byte
$30
$00
0000 000aa
data byte out
Read Fuse bits
$50
$00
$00
data byte out
Read Fuse High bits
$58
$08
$00
data byte out
Read Extended Fuse Bits
$50
$08
$00
data byte out
Read Calibration Byte
$38
$00
$00
data byte out
Write Program Memory Page
$4C
adr MSB(8)
adr LSB(8)
$00
Write EEPROM Memory
$C0
0000 00aa
aaaa aaaa
data byte in
Write EEPROM Memory Page (page access)
$C2
0000 00aa
aaaa aa00
$00
Write Lock bits
$AC
$E0
$00
data byte in
Write Fuse bits
$AC
$A0
$00
data byte in
Write Fuse High bits
$AC
$A8
$00
data byte in
Write Extended Fuse Bits
$AC
$A4
$00
data byte in
Load Instructions
Read Instructions
Write Instructions
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
(6)
Not all instructions are applicable for all parts.
a = address.
Bits are programmed ‘0’, unprogrammed ‘1’.
To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
Instructions accessing program memory use a word address. This address may be random within the page range.
See http://www.atmel.com/avr for Application Notes regarding programming and programmers.
WORDS.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’
before the next instruction is carried out.
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Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 29-8.
Figure 29-8.
Serial Programming Instruction example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1
Byte 2
Adr
A
drr MS
M
MSB
SB
Byte 3
Write Program Memory Page/
Write EEPROM Memory Page
Byte 1
Byte 4
Byte 2
Adr LSB
Bit 15 B
Adr MSB
Byte 3
Adr
A
dr LSB
LS
SB
Bit 15 B
0
Byte 4
0
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/
EEPROM Memory
29.8.4 SPI Serial Programming Characteristics
Figure 29-9.
Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
(MISO)
MSB
LSB
SERIAL CLOCK INPUT
(SCK)
SAMPLE
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30.
Electrical Characteristics
30.1
Absolute Maximum Ratings*
*NOTICE:
Operating Temperature. . . . . . . . . . . -55C to +125C
Storage Temperature . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground . . . . . . . . . . -0.5V to VCC+0.5V
Voltage on RESET with respect to Ground-0.5V to +13.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . . 6.0V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Current per I/O Pin . . . . . . . . . . . . . . . . . . 40.0mA
DC Current VCC and GND Pins . . . . . . . . . . 200.0mA
30.2
DC Characteristics
Table 30-1.
Symbol
Common DC characteristics TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter
Condition
Min.
Typ.
Max.
(1)
Units
VIL
Input Low Voltage, except
XTAL1 and RESET pin
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
-0.5
-0.5
0.2VCC
0.3VCC(1)
V
VIH
Input High Voltage, except
XTAL1 and RESET pins
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.7VCC(2)
0.6VCC(2)
VCC + 0.5
VCC + 0.5
V
VIL1
Input Low Voltage,
XTAL1 pin
VCC = 1.8V - 5.5V
-0.5
0.1VCC(1)
V
VIH1
Input High Voltage,
XTAL1 pin
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.8VCC(2)
0.7VCC(2)
VCC + 0.5
VCC + 0.5
V
VIL2
Input Low Voltage,
RESET pin
VCC = 1.8V - 5.5V
-0.5
0.1VCC(1)
V
VIH2
Input High Voltage,
RESET pin
VCC = 1.8V - 5.5V
0.9VCC(2)
VCC + 0.5
V
VIL3
Input Low Voltage,
RESET pin as I/O
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
-0.5
-0.5
0.2VCC(1)
0.3VCC(1)
V
VIH3
Input High Voltage,
RESET pin as I/O
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.7VCC(2)
0.6VCC(2)
VCC + 0.5
VCC + 0.5
V
VOL
Output Low Voltage(4)
except RESET pin
IOL = 20mA, VCC = 5V
IOL = 10mA, VCC = 3V
VOH
Output High Voltage(3)
except Reset pin
TA=85C
0.9
TA=105C
1.0
TA=85C
0.6
TA=105C
0.7
IOH = -20mA, VCC =
5V
TA=85C
4.2
TA=105C
4.1
IOH = -10mA, VCC =
3V
TA=85C
2.3
TA=105C
2.1
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V
300
Table 30-1.
Common DC characteristics TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued)
Symbol
Parameter
Condition
IIL
Input Leakage
Current I/O Pin
IIH
Input Leakage
Current I/O Pin
RRST
Reset Pull-up Resistor
RPU
I/O Pin Pull-up Resistor
VACIO
Analog Comparator
Input Offset Voltage
VCC = 5V
Vin = VCC/2
IACLK
Analog Comparator
Input Leakage Current
VCC = 5V
Vin = VCC/2
tACID
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 4.0V
Notes:
Min.
Typ.
Max.
Units
VCC = 5.5V, pin low
(absolute value)
1
µA
VCC = 5.5V, pin high
(absolute value)
1
µA
30
60
k
20
50
k
40
mV
50
nA
<10
-50
750
500
ns
1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min.” means the lowest value where the pin is guaranteed to be read as high
3. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega48PB/88PB/168PB:
1] The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150mA.
2] The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150mA.
If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
4. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega48PB/88PB/168PB:
1] The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100mA.
2] The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA.
3] The sum of all IOL, for ports D0 - D4, RESET should not exceed 100mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
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30.2.1 ATmega48PB/88PB DC Characteristics
Table 30-2.
Symbol
ATmega48PB/88PB DC characteristics - TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter
Typ.(2)
Max.
T = 85°C
0.21
0.5
T = 105°C
0.21
0.6
T = 85°C
1.27
2.5
T = 105°C
1.27
2.75
T = 85°C
4.61
9
T = 105°C
4.61
10
T = 85°C
0.035
0.15
T = 105°C
0.035
0.17
T = 85°C
0.22
0.7
T = 105°C
0.22
0.8
T = 85°C
0.84
2.7
T = 105°C
0.84
3
32kHz TOSC enabled,
VCC = 1.8V
T = 85°C
1.42
T = 105°C
1.42
32kHz TOSC enabled,
VCC = 3V
T = 85°C
1.62
T = 105°C
1.62
T = 85°C
2.62
8
T = 105°C
2.62
10
T = 85°C
0.53
2
T = 105°C
0.53
5
Condition
Min.
Active 1MHz, VCC = 2V
Active 4MHz, VCC = 3V
Active 8MHz, VCC = 5V
Power Supply Current(1)
Idle 1MHz, VCC = 2V
Idle 4MHz, VCC = 3V
ICC
Idle 8MHz, VCC = 5V
Power-save mode(3)
WDT enabled, VCC = 3V
(3)(4)
Power-down mode
WDT disabled, VCC = 3V
Notes:
1.
2.
3.
4.
Units
mA
µA
Values with “Minimizing Power Consumption” enabled (0xFF).
Typical values at 25C. Maximum values are test limits in production.
The current consumption values include input leakage current.
No clk is applied to the pad during power-down mode.
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30.2.2 ATmega168PB DC Characteristics
Table 30-3.
Symbol
ATmega168PB DC characteristics - TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted)
Parameter
Typ.(2)
Max.
T = 85°C
0.23
0.5
T = 105°C
0.23
0.6
T = 85°C
1.37
2.5
T = 105°C
1.37
2.75
T = 85°C
5.11
9
T = 105°C
5.11
10
T = 85°C
0.06
0.15
T = 105°C
0.06
0.2
T = 85°C
0.37
0.7
T = 105°C
0.37
0.8
T = 85°C
1.46
2.7
T = 105°C
1.46
3
32kHz TOSC enabled,
VCC = 1.8V
T = 85°C
1.42
T = 105°C
1.42
32kHz TOSC enabled,
VCC = 3V
T = 85°C
1.62
T = 105°C
4.62
T = 85°C
2.84
8
T = 105°C
2.84
10
T = 85°C
0.4
2
T = 105°C
0.4
5
Condition
Min.
Active 1MHz, VCC = 2V
Active 4MHz, VCC = 3V
Active 8MHz, VCC = 5V
Power Supply Current(1)
Idle 1MHz, VCC = 2V
Idle 4MHz, VCC = 3V
ICC
Idle 8MHz, VCC = 5V
Power-save mode(3)
WDT enabled, VCC = 3V
(3)(4)
Power-down mode
WDT disabled, VCC = 3V
Notes:
1.
2.
3.
4.
Units
mA
µA
Values with “Minimizing Power Consumption” enabled (0xFF).
Typical values at 25C. Maximum values are test limits in production.
The current consumption values include input leakage current.
No clk is applied to the pad during power-down mode.
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30.3
Speed Grades
Maximum frequency is dependent on VCC. As shown in Figure 30-1, the Maximum Frequency vs. VCC curve is
linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.
Figure 30-1.
Maximum Frequency vs. VCC
20 MHz
10 MHz
Safe Operating Area
4 MHz
1.8V
2.7V
4.5V
5.5V
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30.4
Clock Characteristics
30.4.1 Calibrated Internal RC Oscillator Accuracy
Table 30-4.
Calibration Accuracy of Internal RC Oscillator
Frequency
VCC
Temperature
Calibration Accuracy
Factory
Calibration
8.0MHz
3V
25C
±3%
User
Calibration
7.3 - 8.1MHz
1.8V - 5.5V
-40C - 85C
±1%
30.4.2 External Clock Drive Waveforms
Figure 30-2.
External Clock Drive Waveforms
V IH1
V IL1
30.4.3 External Clock Drive
Table 30-5.
External Clock Drive
VCC= 1.8 - 5.5V
VCC= 2.7 - 5.5V
VCC= 4.5 - 5.5V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
1/tCLCL
Oscillator Frequency
0
4
0
10
0
20
MHz
tCLCL
Clock Period
250
100
50
ns
tCHCX
High Time
100
40
20
ns
tCLCX
Low Time
100
40
20
ns
tCLCH
Rise Time
2.0
1.6
0.5
s
tCHCL
Fall Time
2.0
1.6
0.5
s
tCLCL
Change in period from
one clock cycle to the
next
2
2
2
%
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30.5
System and Reset Characteristics
Table 30-6.
Symbol
VPOT
Reset, Brown-out and Internal Voltage Characteristics(1)
Parameter
Power-on Reset Threshold Voltage (rising)
Power-on Reset Threshold Voltage (falling)
SRON
Power-on Slope Rate
VRST
RESET Pin Threshold Voltage
tRST
Minimum pulse width on RESET Pin
VHYST
(2)
Min.
Typ
Max
Units
1.1
1.4
1.6
V
0.6
1.3
1.6
V
0.01
10
V/ms
0.2 VCC
0.9 VCC
V
2.5
µs
Brown-out Detector Hysteresis
50
mV
tBOD
Min. Pulse Width on Brown-out Reset
2
µs
VBG
Bandgap reference voltage
VCC=2.7
TA=25°C
tBG
Bandgap reference start-up time
IBG
Bandgap reference current consumption
Notes:
1.0
1.1
1.2
V
VCC=2.7
TA=25°C
40
70
µs
VCC=2.7
TA=25°C
10
µA
1. Values are guidelines only.
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
Table 30-7.
BODLEVEL Fuse Coding(1)(2)
BODLEVEL 2:0 Fuses
Min. VBOT
111
Typ VBOT
Max VBOT
Units
BOD Disabled
110
1.7
1.8
2.0
101
2.5
2.7
2.9
100
4.1
4.3
4.5
V
011
010
001
Reserved
000
Notes:
1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is
tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops
to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 110, 101 and 100.
2. VBOT tested at 25C and 85C in production
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30.6
SPI Timing Characteristics
See Figure 30-3 and Figure 30-4 for details.
Table 30-8.
SPI Timing Parameters
Description
Mode
1
SCK period
Master
See Table 19-5
2
SCK high/low
Master
50% duty cycle
3
Rise/Fall time
Master
3.6
4
Setup
Master
10
5
Hold
Master
10
6
Out to SCK
Master
0.5 • tsck
7
SCK to out
Master
10
8
SCK to out high
Master
10
9
SS low to out
Slave
15
10
SCK period
Slave
4 • tck
11
SCK high/low(1)
Slave
2 • tck
12
Rise/Fall time
Slave
13
Setup
Slave
10
14
Hold
Slave
tck
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Note:
1.
Figure 30-3.
Min.
Typ
Max
ns
1600
15
20
10
20
In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12MHz
- 3 tCLCL for fCK > 12MHz
SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
4
MISO
(Data Input)
5
3
MSB
...
LSB
7
MOSI
(Data Output)
MSB
8
...
LSB
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Figure 30-4.
SPI Interface Timing Requirements (Slave Mode)
SS
10
9
16
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
MOSI
(Data Input)
14
12
MSB
...
LSB
15
MISO
(Data Output)
MSB
17
...
LSB
X
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30.7
Two-wire Serial Interface Characteristics
Table 30-9 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega48PB/88PB/168PB 2wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 30-5.
Table 30-9.
Two-wire Serial Bus Requirements
Symbol
Parameter
VIL
VIH
Max
Units
Input Low-voltage
-0.5
0.3 VCC
V
Input High-voltage
0.7 VCC
VCC + 0.5
V
–
V
0
0.4
V
20 + 0.1Cb(3)(2)
300
ns
0.1Cb(3)(2)
250
ns
(2)
ns
Hysteresis of Schmitt Trigger Inputs
(1)
Output Low-voltage
Vhys
VOL
Min.
(1)
tr(1)
tof(1)
Output Fall Time from VIHmin to VILmax
Spikes Suppressed by Input Filter
Ii
Input Current each I/O Pin
Ci(1)
Capacitance for each I/O Pin
Rp
SCL Clock Frequency
Value of Pull-up resistor
tHD;STA
Hold Time (repeated) START Condition
tLOW
Low Period of the SCL Clock
tHIGH
High period of the SCL clock
tSU;STA
Set-up time for a repeated START
condition
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and
START condition
Notes:
0.05
3mA sink current
Rise Time for both SDA and SCL
tSP(1)
fSCL
Condition
(3)
10pF < Cb < 400pF
20 +
VCC(2)
0
0.1VCC < Vi < 0.9VCC
fCK(4)
50
-10
10
µA
–
10
pF
0
400
kHz
fSCL  100kHz
V CC – 0,4V
---------------------------3mA
1000ns
----------------Cb

fSCL > 100kHz
V CC – 0,4V
---------------------------3mA
300ns
-------------Cb

fSCL  100kHz
4.0
–
µs
fSCL > 100kHz
0.6
–
µs
fSCL  100kHz
4.7
–
µs
fSCL > 100kHz
1.3
–
µs
fSCL  100kHz
4.0
–
µs
fSCL > 100kHz
0.6
–
µs
fSCL  100kHz
4.7
–
µs
fSCL > 100kHz
0.6
–
µs
fSCL  100kHz
0
3.45
µs
fSCL > 100kHz
0
0.9
µs
fSCL  100kHz
250
–
ns
fSCL > 100kHz
100
–
ns
fSCL  100kHz
4.0
–
µs
fSCL > 100kHz
0.6
–
µs
fSCL  100kHz
4.7
–
µs
fSCL > 100kHz
1.3
–
µs
(5)
> max(16fSCL, 250kHz)
1. In ATmega48PB/88PB/168PB, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100kHz.
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3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega48PB/88PB/168PB 2-wire Serial Interface operation. Other devices connected to the
2-wire Serial Bus need only obey the general fSCL requirement.
Figure 30-5.
Two-wire Serial Bus Timing
tof
tHIGH
tLOW
tr
tLOW
SCL
tSU;STA
SDA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
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30.8
ADC Characteristics
Table 30-10.
Symbol
ADC Characteristics
Parameter
Condition
Min.
Resolution
Typ
Max
Units
10
Bits
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
2
LSB
VREF = 4V, VCC = 4V,
ADC clock = 1MHz
4.5
LSB
2
LSB
VREF = 4V, VCC = 4V,
ADC clock = 1MHz
Noise Reduction Mode
4.5
LSB
Integral Non-Linearity (INL)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
0.5
LSB
Differential Non-Linearity
(DNL)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
0.25
LSB
Gain Error
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
2
LSB
Offset Error
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
2
LSB
Conversion Time
Free Running Conversion
Absolute accuracy (Including
INL, DNL, quantization error,
gain and offset error)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
Noise Reduction Mode
Clock Frequency
AVCC(1)
VREF
VIN
Analog Supply Voltage
Reference Voltage
Input Voltage
13
260
µs
50
1000
kHz
VCC - 0.3
VCC + 0.3
V
1.0
AVCC
V
GND
VREF
V
Input Bandwidth
38.5
VINT
Internal Voltage Reference
RREF
Reference Input Resistance
32
k
RAIN
Analog Input Resistance
100
M
Note:
1.0
1.1
kHz
1.2
V
1. AVCC absolute min./max: 1.8V/5.5V
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30.9
Parallel Programming Characteristics
Table 30-11.
Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol
Parameter
Min.
VPP
Programming Enable Voltage
11.5
IPP
Programming Enable Current
tDVXH
Data and Control Valid before XTAL1 High
67
ns
tXLXH
XTAL1 Low to XTAL1 High
200
ns
tXHXL
XTAL1 Pulse Width High
150
ns
tXLDX
Data and Control Hold after XTAL1 Low
67
ns
tXLWL
XTAL1 Low to WR Low
0
ns
tXLPH
XTAL1 Low to PAGEL high
0
ns
tPLXH
PAGEL low to XTAL1 high
150
ns
tBVPH
BS1 Valid before PAGEL High
67
ns
tPHPL
PAGEL Pulse Width High
150
ns
tPLBX
BS1 Hold after PAGEL Low
67
ns
tWLBX
BS2/1 Hold after RDY/BSY high
67
ns
tPLWL
PAGEL Low to WR Low
67
ns
tBVWL
BS1 Valid to WR Low
67
ns
tWLWH
WR Pulse Width Low
150
ns
tWLRL
WR Low to RDY/BSY Low
(1)
Typ
Max
Units
12.5
V
250
A
0
1
s
tWLRH
WR Low to RDY/BSY High
3.2
3.4
ms
tWLRH_CE
WR Low to RDY/BSY High for Chip Erase(2)
9.8
10.5
ms
tXLOL
XTAL1 Low to OE Low
0
tBVDV
BS1 Valid to DATA valid
0
tOLDV
tOHDZ
Notes:
1.
2.
ns
350
ns
OE Low to DATA Valid
350
ns
OE High to DATA Tri-stated
250
ns
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
tWLRH_CE is valid for the Chip Erase command.
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Figure 30-6.
Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
XTAL1
tDVXH
tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tPLBX
tBVPH
PAGEL
tWLBX
t BVWL
tPHPL
tWLWH
WR
tPLWL
WLRL
RDY/BSY
tWLRH
Figure 30-7.
Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA LOAD DATA
(HIGH BYTE)
LOAD DATA
(LOW BYTE)
tXLPH
t XLXH
LOAD ADDRESS
(LOW BYTE)
tPLXH
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 30-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 30-8.
Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE
DATA
tOHDZ
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 30-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
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31.
Typical Characteristics
31.1
ATmega48PB/88PB Typical Characteristics
31.1.1 Active Supply Current
Figure 31-1.
ATmega48PB/88PB: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
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ATmega48PB/88PB: Active Supply Current vs. Frequency (1-20MHz)
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Figure 31-2.
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314
Figure 31-3.
ATmega48PB/88PB: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
7HPSHUDWXUH>&@
ϭϬϱ
ϴϱ
,&& >[email protected]
Ϯϱ
ͲϰϬ
9&& >[email protected]
ATmega48PB/88PB: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
,&& >[email protected]
Figure 31-4.
7HPSHUDWXUH>&@
ϭϬϱ
ϴϱ
Ϯϱ
ͲϰϬ
9&& >[email protected]
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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315
Figure 31-5.
ATmega48PB/88PB: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
7HPSHUDWXUH>&@
ϭϬϱ
ϴϱ
,&& >[email protected]
Ϯϱ
ͲϰϬ
9&& >[email protected]
31.1.2 Idle Supply Current
ATmega48PB/88PB: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
9FF>[email protected]
ϱ͘ϱ
ϱ
ϰ͘ϱ
,&& >[email protected]
Figure 31-6.
ϰ
ϯ͘ϯ
Ϯ͘ϳ
ϭ͘ϴ
)UHTXHQF\>0+]@
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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316
Figure 31-7.
ATmega48PB/88PB: Idle Supply Current vs. Frequency (1-20MHz)
7HPSHUDWXUH>&
ϱ͘ϱ
ϱ
,&& >[email protected]
ϰ͘ϱ
ϰ
ϯ͘ϯ
Ϯ͘ϳ
ϭ͘ϴ
)UHTXHQF\>0+]@
Figure 31-8.
ATmega48PB/88PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
ϭϬϱ
ϴϱ
,&& >[email protected]
Ϯϱ
ͲϰϬ
9&& >[email protected]
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
317
Figure 31-9.
ATmega48PB/88PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
ϭϬϱ
ϴϱ
Ϯϱ
,&& P$
ͲϰϬ
9&& 9
Figure 31-10. ATmega48PB/88PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
ϭϬϱ
ϴϱ
Ϯϱ
,&& P$
ͲϰϬ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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318
31.1.3 ATmega48PB/88PB Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power
Reduction Register. See ”Power Reduction Register” on page 39 for details.
Table 31-1.
PRR bit
ATmega48PB/88PB: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers @ 25°C
VCC = 2V, F = 1MHz
VCC = 3V, F = 4MHz
VCC = 5V, F = 8MHz
PRUSART0
4.66µA
28.73µA
103.38µA
PRTWI
6.63µA
41.89µA
148.00µA
PRTIM2
6.64µA
37.74µA
137.36µA
PRTIM1
4.36µA
29.65µA
112.13µA
PRTIM0
1.61µA
9.59µA
32.13µA
PRSPI
5.55µA
37.15µA
136.38µA
PRADC
7.01µA
43.31µA
158.38µA
Table 31-2.
ATmega48PB/88PB: Additional Current Consumption (percentage) in Active and Idle mode
(VCC = 2V, F = 1MHz)
PRR bit
Additional Current consumption compared to
Active with external clock (see Figure 31-47
on page 338 and Figure 31-48 on page 338)
Additional Current consumption compared to
Idle with external clock (see Figure 31-52 on
page 340 and Figure 31-53 on page 341)
PRUSART0
2.20%
13.12%
PRTWI
3.13%
18.65%
PRTIM2
3.13%
18.69%
PRTIM1
2.06%
12.28%
PRTIM0
0.76%
4.54%
PRSPI
2.62%
15.63%
PRADC
3.31%
19.74%
It is possible to calculate the typical current consumption based on the numbers from Table 31-4 on page 343 for
other VCC and frequency settings than listed in Table 31-3 on page 343.
31.1.3.1 Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-4 on page 343, third column, we see that we need to add 12.28% for the TIMER1,
19.74% for the ADC, and 15.63% for the SPI module. Reading from Figure 31-52 on page 340, we find that the idle
current consumption is ~0.036 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with
TIMER1, ADC, and SPI enabled, gives:
I CC total  0.036 mA  (1 + 0.123 + 0.197 + 0.156)  0.053mA
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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319
31.1.4 Power-down Supply Current
Figure 31-11. ATmega48PB/88PB: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
ϭϬϱΣ
,&& —$
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
Figure 31-12. ATmega48PB/88PB: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
,&& —$
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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320
31.1.5 Pin Pull-Up
Figure 31-13. ATmega48PB/88PB: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
,23 —$
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
923 9
Figure 31-14. ATmega48PB/88PB: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
,23 —$
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
923 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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321
Figure 31-15. ATmega48PB/88PB: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
,23 —$
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
923 9
Figure 31-16. ATmega48PB/88PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 1.8V)
,5(6( 7 X$
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
95(6( 7 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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322
Figure 31-17. ATmega48PB/88PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 2.7V)
,5(6( 7 —$
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
95(6( 7 9
Figure 31-18. ATmega48PB/88PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
,5(6( 7 —$
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
95(6( 7 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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31.1.6 Pin Driver Strength
Figure 31-19. ATmega48PB/88PB: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
ϭϬϱΣ
ϴϱΣ
92/ 9
ϮϱΣ
ͲϰϬΣ
,2/ P$
Figure 31-20. ATmega48PB/88PB: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
ϭϬϱΣ
92/ 9
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
,2/ P$
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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Figure 31-21. ATmega48PB/88PB: I/O Pin Output Voltage vs. Source Current (VCC = 3V)
92+ 9
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
,2+ P$
Figure 31-22. ATmega48PB/88PB: I/O Pin Output Voltage vs. Source Current (VCC = 5V)
92+ 9
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
,2+ P$
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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31.1.7 Pin Threshold and Hysteresis
Figure 31-23. ATmega48PB/88PB: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
7KUHVKROG9
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
Figure 31-24. ATmega48PB/88PB: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
ϭϬϱΣ
7KUHVKROG9
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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326
Figure 31-25. ATmega48PB/88PB: I/O Pin Input Hysteresis vs. VCC
ϭϬϱΣ
,QS XW+\V WHUHVLVP9
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
Figure 31-26. ATmega48PB/88PB: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
ϭϬϱΣ
7KUHVKROG9
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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327
Figure 31-27. ATmega48PB/88PB: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
7KUHVKROG9
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
Figure 31-28. ATmega48PB/88PB: Reset Pin Input Hysteresis vs. VCC
,QS XW+\V WHUHVLVP9
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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328
31.1.8 BOD Threshold
Figure 31-29. ATmega48PB/88PB: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
ZŝƐŝŶŐ
7KUHVKROG9
&ĂůůŝŶŐ
7HPSHUDWXUH&
Figure 31-30. ATmega48PB/88PB: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)
7KUHVKROG9
ZŝƐŝŶŐ
&ĂůůŝŶŐ
7HPSHUDWXUH&
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
329
Figure 31-31. ATmega48PB/88PB: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
ZŝƐŝŶŐ
7KUHVKROG9
&ĂůůŝŶŐ
7HPSHUDWXUH&
Figure 31-32. ATmega48PB/88PB: Calibrated Bandgap Voltage vs. Temperature
ϰ͘ϱs
ϰ͘Ϭs
%DQGJDS9ROWDJH9
ϯ͘ϯs
Ϯ͘ϳs
ϭ͘ϴs
ϱ͘ϱs
7HPSHUDWXUH&
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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330
Figure 31-33. ATmega48PB/88PB: Calibrated Bandgap Voltage vs. Vcc
%DQGJ DS9ROWDJH9
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9FF9
31.1.9 Internal Oscillator Speed
Figure 31-34. ATmega48PB/88PB: Watchdog Oscillator Frequency vs. Temperature
) 5& N+]
ϱ͘ϱs
ϱ͘Ϭs
ϰ͘ϱs
ϰ͘Ϭs
ϯ͘ϯs
Ϯ͘ϳs
7HPSHUDWXUH
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
331
Figure 31-35. ATmega48PB/88PB: Watchdog Oscillator Frequency vs. VCC
ϭϬϱΣ
) 5& N+]
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
Figure 31-36. ATmega48PB/88PB: Calibrated 8MHz RC Oscillator Frequency vs. VCC
) 5& 0+]
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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Figure 31-37. ATmega48PB/88PB: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
ϱ͘ϱs
) 5& 0+]
ϱ͘Ϭs
ϰ͘ϱs
ϯ͘ϯs
ϯ͘Ϭs
ϭ͘sϴ
7HPSHUDWXUH
Figure 31-38. ATmega48PB/88PB: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
) 5& 0+]
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
26&&$/;
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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31.1.10 Current Consumption of Peripheral Units
Figure 31-39. ATmega48PB/88PB: ADC Current vs. VCC (AREF = AVCC)
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
,&& X$
ͲϰϬΣ
9&& 9
Figure 31-40. ATmega48PB/88PB: Analog Comparator Current vs. VCC
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
,&& X$
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
334
Figure 31-41. ATmega48PB/88PB: AREF External Reference Current vs. VCC
ϭϬϱΣ
ϴϱΣ
,&& X$
ϮϱΣ
ͲϰϬΣ
9&& 9
Figure 31-42. ATmega48PB/88PB: Brownout Detector Current vs. VCC
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
,&& —$
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
335
Figure 31-43. ATmega48PB/88PB: Programming Current vs. VCC
,FF P$
ƒ&
ƒ&
ƒ&
ƒ&
9&&9
31.1.11 Current Consumption in Reset and Reset Pulse width
Figure 31-44. ATmega48PB/88PB: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
ϱ͘ϱs
ϱ͘Ϭs
,&& P$
ϰ͘ϱs
ϰ͘Ϭs
ϯ͘ϯs
Ϯ͘ϳs
ϭ͘ϴs
)UHTXHQF\0+]
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
336
Figure 31-45. ATmega48PB/88PB: Reset Supply Current vs. Frequency (1MHz - 20MHz)
ϱ͘ϱs
,&& P$
ϱ͘Ϭs
ϰ͘ϱs
ϰ͘Ϭs
ϯ͘ϲs
Ϯ͘ϳs
ϭ͘ϴs
)UHTXHQF\0+]
Figure 31-46. ATmega48PB/88PB: Minimum Reset Pulse Width vs. Vcc
3XOVHZLGWKQV
ϭϬϱΣ
ϴϱΣ
ϮϱΣ
ͲϰϬΣ
9&& 9
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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337
31.2
ATmega168PB Typical Characteristics
31.2.1 Active Supply Current
Figure 31-47. ATmega168PB: Active Supply Current vs. Low Frequency (0.1-1.0MHz)
ICC (mA)
0.8
0.7
5.5V
0.6
5.0V
0.5
4.5V
0.4
4.0V
0.3
3.3V
0.2
2.7V
0.1
1.8V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency ( Mhz)
Figure 31-48. ATmega168PB: Active Supply Current vs. Frequency (1-20MHz)
14
5.5V
12
5.0V
ICC (mA)
10
4.5V
8
4.0V
6
3.6V
4
2.7V
2
1.8V
0
0
5
10
15
20
Frequency (Mhz)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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338
Figure 31-49. ATmega168PB: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.14
0.12
ICC (mA)
0.10
105°C
0.08
85°C
0.06
25°C
- 40°C
0.04
0.02
0
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
VCC (V)
Figure 31-50. ATmega168PB: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
1.2
ICC (mA)
1.0
105°C
0.8
85°C
0.6
25°C
0.4
-40°C
0.2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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Figure 31-51. ATmega168PB: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
6
5
105°C
ICC (mA)
4
85°C
3
25°C
2
-40°C
1
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
31.2.2 Idle Supply Current
Figure 31-52. ATmega168PB: Idle Supply Current vs. Low Frequency (0.1-1.0MHz)
0.25
5.5V
ICC (mA)
0.20
5.0V
4.5V
0.15
4.0V
0.10
3.6V
2.7V
0.05
1.8V
0
0
0.2
0.4
0.6
0.8
1.0
Frequency (Mhz)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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340
Figure 31-53. ATmega168PB: Idle Supply Current vs. Frequency (1-20MHz)
ICC (mA)
4.5
4.0
5.5V
3.5
5.0V
3.0
4.5V
2.5
4.0V
2.0
1.5
3.6V
1.0
2.7V
0.5
1.8V
0
0
5
10
15
20
Frequency (MHz)
Figure 31-54. ATmega168PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.045
0.040
0.035
105°C
ICC (mA)
0.030
0.025
85°C
0.020
25°C
0.015
-40°C
0.010
0.005
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
341
Figure 31-55. ATmega168PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.7
0.6
ICC (mA)
0.5
105°C
0.4
85°C
0.3
25°C
0.2
-40°C
0.1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 31-56. ATmega168PB: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
2.0
1.8
1.6
ICC (mA)
1.4
105°C
1.2
85°C
1.0
0.8
25°C
0.6
-40°C
0.4
0.2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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342
31.2.3 ATmega168PB Supply Current of IO Modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power
Reduction Register. See ”Power Reduction Register” on page 39 for details.
Table 31-3.
PRR bit
ATmega168PB: Additional Current Consumption for the different I/O modules (absolute values)
Typical numbers @ 25°C
VCC = 2V, F = 1MHz
VCC = 3V, F = 4MHz
VCC = 5V, F = 8MHz
PRUSART0
4.56µA
27.0µA
119.75µA
PRTWI
7.81µA
47.38µA
177.75µA
PRTIM2
6.09µA
35.00µA
140.75µA
PRTIM1
5.36µA
35.89µA
134.36µA
PRTIM0
1.00µA
11.41µA
39.88µA
PRSPI
4.79µA
30.5µA
118.13µA
PRADC
4.89µA
32.36µA
128.63µA
Table 31-4.
ATmega168PB: Additional Current Consumption (percentage) in Active and Idle mode
(VCC = 2V, F = 1MHz)
PRR bit
Additional Current consumption compared to
Active with external clock (see Figure 31-47
on page 338 and Figure 31-48 on page 338)
Additional Current consumption compared to
Idle with external clock (see Figure 31-52 on
page 340 and Figure 31-53 on page 341)
PRUSART0
2.03%
7.58%
PRTWI
3.47%
12.99%
PRTIM2
2.70%
10.12%
PRTIM1
2.38%
8.91%
PRTIM0
0.44%
1.66%
PRSPI
2.13%
7.96%
PRADC
2.17%
8.12%
It is possible to calculate the typical current consumption based on the numbers from Table 31-4 on page 343 for
other VCC and frequency settings than listed in Table 31-3 on page 343.
31.2.3.1 Example
Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and
F = 1MHz. From Table 31-4 on page 343, third column, we see that we need to add 8.91% for the TIMER1, 8.12%
for the ADC, and 7.96% for the SPI module. Reading from Figure 31-52 on page 340, we find that the idle current
consumption is ~0.06 mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1,
ADC, and SPI enabled, gives:
I CC total  0.06 mA  (1 + 0.0891 + 0.0812 + 0.0796)  0.075mA
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
343
31.2.4 Power-down Supply Current
Figure 31-57. ATmega168PB: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)
6
ICC (µA)
5
4
105°C
85°C
25°C
3
2
1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 31-58. ATmega168PB: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
9
ICC (µA)
8
7
105°C
6
85°C
5
4
25°C
3
-40°C
2
1
1.5
2.5
3.5
4.5
5.5
V CC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
344
31.2.5 Pin Pull-Up
Figure 31-59. ATmega168PB: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
0.07
0.06
IOP (mA)
0.05
0.04
105°C
0.03
85°C
0.02
25°C
0.01
-40°C
0.00
0.0
0.3
0.6
0.9
1.2
1.5
1.8
VOP (V)
Figure 31-60. ATmega168PB: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
0.12
IOP (mA)
0.10
0.08
105°C
0.06
85°C
0.04
25°C
0.02
-40°C
0.00
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOP (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
345
Figure 31-61. ATmega168PB: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
0.24
0.21
IOP (mA)
0.18
105°C
0.15
85°C
0.12
25°C
0.09
-40°C
0.06
0.03
0.00
0
1
2
3
4
5
VOP (V)
Figure 31-62. ATmega168PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 1.8V)
0.045
0.040
IRESET (mA)
0.035
0.030
105°C
0.025
0.020
85°C
0.015
25°C
0.010
-40°C
0.005
0.000
0.0
0.3
0.6
0.9
1.2
1.5
1.8
VRESET (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
346
Figure 31-63. ATmega168PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage
(VCC = 2.7V)
ATmega168PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
0.07
IRESET (mA)
0.06
0.05
0.04
105°C
0.03
85°C
0.02
25°C
0.01
0.00
0.0
-40°C
0.5
1.0
1.5
2.0
2.5
3.0
VRESET (V)
Figure 31-64. ATmega168PB: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
0.14
IRESET (mA)
0.12
0.10
0.08
105°C
0.06
85°C
0.04
25°C
-40°C
0.02
0.00
0
1
2
3
4
5
VRESET (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
347
31.2.6 Pin Driver Strength
Figure 31-65. ATmega168PB: I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
VOL (V)
1.2
105°C
1.0
85°C
0.8
25°C
-40°C
0.6
0.4
0.2
0.0
0
5
10
IOL (mA)
15
20
Figure 31-66. ATmega168PB: I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.7
105°C
0.6
85°C
VOL (V)
0.5
25°C
-40°C
0.4
0.3
0.2
0.1
0
0
5
10
IOL (mA)
15
20
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
348
Figure 31-67. ATmega168PB: I/O Pin Output Voltage vs. Source Current (VCC = 3V)
3.0
2.5
-40°C
2.0
VOH (V)
25°C
85°C
105°C
1.5
1.0
0.5
0.0
0
5
10
IOH (mA)
15
20
Figure 31-68. ATmega168PB I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5.0
4.9
4.8
VOH (V)
4.7
4.6
4.5
4.4
-40°C
4.3
25°C
4.2
85°C
105°C
4.1
4.0
0
5
10
IOH (mA)
15
20
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
349
31.2.7 Pin Threshold and Hysteresis
Figure 31-69. ATmega168PB I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
Threshold (V)
4.0
3.5
105°C
3.0
85°C
2.5
25°C
2.0
-40°C
1.5
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
VCC (V)
4.0
4.5
5.0
5.5
Figure 31-70. ATmega168PB I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5
-40°C
Threshold (V)
2.0
25°C
105°C
85°C
1.5
1.0
0.5
0.0
1.5
2.0
2.5
3.0
3.5
VCC (V)
4.0
4.5
5.0
5.5
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
350
Figure 31-71. ATmega168PB I/O Pin Input Hysteresis vs. VCC
1.4
-40°C
Input Hyteresis (V)
1.2
25°C
1.0
85°C
0.8
105°C
0.6
0.4
0.2
0.0
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Vcc(V)
Figure 31-72. ATmega168PB: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’)
3.0
105°C
85°C
Threshold (V)
2.5
25°C
2.0
-40°C
1.5
1.0
0.5
0.0
1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
351
Figure 31-73. ATmega168PB: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’)
2.5
2.3
Threshold (V)
2.1
1.9
105°C
1.7
85°C
25°C
1.5
-40°C
1.3
1.1
0.9
0.7
0.5
1.8
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
5.4
VCC (V)
Figure 31-74. ATmega168PB: Reset Pin Input Hysteresis vs. VCC
0.7
Input Hysteresis (V)
0.6
0.5
105°C
0.4
0.3
0.2
25°C
85°C
0.1
- 40°C
0.0
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Vcc (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
352
31.2.8 BOD Threshold
Figure 31-75. ATmega168PB: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)
1.79
Threshold (mA)
1.78
Rising
1.77
1.76
1.75
1.74
Falling
1.73
1.72
-60
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 31-76. ATmega168PB: BOD ThresholdsG vs.
(BODLEVEL is 2.7V)
68 Temperature
O
2.76
2.74
Rising
Threshold (V)
2.72
2.70
2.68
2.66
Falling
2.64
2.62
- 60
-40
-20
0
20
40
Temperature (°C)
60
80
100
120
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
353
Figure 31-77. ATmega168PB: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)
4.42
4.40
Rising
Threshold
4.38
4.36
4.34
4.32
4.30
Falling
4.28
4.26
-60
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 31-78. ATmega168PB: Calibrated Bandgap Voltage vs. Temperature
1.125
5.5V
Ban d g ap Voltage (V)
1.120
5.0V
4.5V
1.115
3.3V
1.110
3.0V
2.7V
1.105
1.8V
1.100
1.095
-50
-30
-10
10
30
50
70
90
110
Temperature (C)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
354
Figure 31-79. ATmega168PB: Calibrated Bandgap Voltage vs. Vcc
1.125
Ban d g ap Vo ltage (V)
1.120
1.115
105°C
85°C
1.110
25°C
1.105
-40°C
1.100
1.095
1.090
1.085
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
31.2.9 Internal Oscillator Speed
Figure 31-80. ATmega168PB: Watchdog Oscillator Frequency vs. Temperature
FRC (kHz)
124
122
5.5V
120
5.0V
118
4.5V
116
4.0V
114
3.3V
112
2.7V
110
108
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100
Temperature (°C)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
355
Figure 31-81. ATmega168PB: Watchdog Oscillator Frequency vs. VCC
130
128
FRC (kHz)
126
124
105°C
122
85°C
120
118
25°C
116
-40°C
114
112
110
2
3
4
5
6
VCC (V)
Figure 31-82. ATmega168PB: Calibrated 8MHz RC Oscillator Frequency vs. VCC
8.5
8.4
8.3
F RC (MHz)
8.2
105°C
85°C
25°C
8.1
8.0
7.9
-40°C
7.8
7.7
7.6
7.5
1.8
2.3
2.8
3.3
3.8
4.3
4.8
5.3
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
356
Figure 31-83. ATmega168PB: Calibrated 8MHz RC Oscillator Frequency vs. Temperature
8.4
F RC (MHz)
8.3
8.2
5.5V
8.1
5.0V
8.0
4.5V
7.9
3.3V
7.8
3.0V
1.8V
7.7
7.6
7.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
Temperature (C)
Figure 31-84. ATmega168PB: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value
20.0
105°C
FRC (MHz)
18.0
16.0
85°C
14.0
25°C
12.0
-40°C
10.0
8.0
6.0
4.0
2.0
0
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
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31.2.10 Current Consumption of Peripheral Units
Figure 31-85. ATmega168PB: ADC Current vs. VCC (AREF = AVCC)
0.40
0.35
ICC (mA)
0.30
105°C
0.25
85°C
0.20
25°C
0.15
-40°C
0.10
0.05
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
Figure 31-86. ATmega168PB: Analog Comparator Current vs. VCC
0.16
0.14
ICC (mA)
0.12
105°C
0.10
85°C
0.08
25°C
0.06
-40°C
0.04
0.02
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
358
Figure 31-87. ATmega168PB: AREF External Reference Current vs. VCC
0.12
105°C
0.11
85°C
0.10
25°C
ICC (mA)
0.09
-40°C
0.08
0.07
0.06
0.05
0.04
0.03
0.02
1.5
2.0
2.5
3.0
3.5
VCC (V)
4.0
4.5
5.0
5.5
Figure 31-88. ATmega168PB: Brownout Detector Current vs. VCC
0.035
ICC (mA)
0.030
0.025
105°C
0.020
85°C
0.015
25°C
0.010
-40°C
0.005
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
359
Figure 31-89. ATmega168PB: Programming Current vs. VCC
10
9
8
105°C
Icc (mA)
7
6
85°C
5
25°C
4
-40°C
3
2
1
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
31.2.11 Current Consumption in Reset and Reset Pulse width
Figure 31-90. ATmega168PB: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz)
ICC (mA)
0.20
0.18
5.5V
0.16
5.0V
0.14
4.5V
0.12
4.0V
0.10
3.3V
0.08
0.06
1.8V
0.04
0.02
0.00
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (MHz)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
360
Figure 31-91. ATmega168PB: Reset Supply Current vs. Frequency (1MHz - 20MHz)
4.5
4.0
ICC (mA)
3.5
5.5V
3.0
5.0V
2.5
4.5V
2.0
4.0V
1.5
3.6V
1.0
2.7V
0.5
1.8V
0.0
0
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
Figure 31-92. ATmega168PB: Minimum Reset Pulse Width vs. Vcc
3000
Pulsewidth (nS)
2500
105°C
2000
85°C
1500
25°C
1000
-40°C
500
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC (V)
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
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32.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xFF)
Reserved
–
–
–
–
–
–
–
–
Page
(0xFE)
Reserved
–
–
–
–
–
–
–
–
(0xFD)
Reserved
–
–
–
–
–
–
–
–
(0xFC)
Reserved
–
–
–
–
–
–
–
–
(0xFB)
Reserved
–
–
–
–
–
–
–
–
(0xFA)
Reserved
–
–
–
–
–
–
–
–
(0xF9)
Reserved
–
–
–
–
–
–
–
–
(0xF8)
Reserved
Device ID byte 8
256
(0xF7)
Reserved
Device ID byte 7
262
(0xF6)
Reserved
Device ID byte 6
262
(0xF5)
Reserved
Device ID byte 5
262
(0xF4)
Reserved
Device ID byte 4
262
(0xF3)
Reserved
Device ID byte 3
262
(0xF2)
Reserved
Device ID byte 2
262
(0xF1)
Reserved
Device ID byte 1
262
(0xF0)
Reserved
Device ID byte 0
(0xEF)
Reserved
–
–
–
–
–
–
–
–
262
(0xEE)
Reserved
–
–
–
–
–
–
–
–
(0xED)
Reserved
–
–
–
–
–
–
–
–
(0xEC)
Reserved
–
–
–
–
–
–
–
–
(0xEB)
Reserved
–
–
–
–
–
–
–
–
(0xEA)
Reserved
–
–
–
–
–
–
–
–
(0xE9)
Reserved
–
–
–
–
–
–
–
–
(0xE8)
Reserved
–
–
–
–
–
–
–
–
(0xE7)
Reserved
–
–
–
–
–
–
–
–
(0xE6)
Reserved
–
–
–
–
–
–
–
–
(0xE5)
Reserved
–
–
–
–
–
–
–
–
(0xE4)
Reserved
–
–
–
–
–
–
–
–
(0xE3)
Reserved
–
–
–
–
–
–
–
–
(0xE2)
Reserved
–
–
–
–
–
–
–
–
(0xE1)
Reserved
–
–
–
–
–
–
–
–
(0xE0)
Reserved
–
–
–
–
–
–
–
–
(0xDF)
Reserved
–
–
–
–
–
–
–
–
(0xDE)
Reserved
–
–
–
–
–
–
–
–
(0xDD)
Reserved
–
–
–
–
–
–
–
–
(0xDC)
Reserved
–
–
–
–
–
–
–
–
(0xDB)
Reserved
–
–
–
–
–
–
–
–
(0xDA)
Reserved
–
–
–
–
–
–
–
–
(0xD9)
Reserved
–
–
–
–
–
–
–
–
(0xD8)
Reserved
–
–
–
–
–
–
–
–
(0xD7)
Reserved
–
–
–
–
–
–
–
–
(0xD6)
Reserved
–
–
–
–
–
–
–
–
(0xD5)
Reserved
–
–
–
–
–
–
–
–
(0xD4)
Reserved
–
–
–
–
–
–
–
–
(0xD3)
Reserved
–
–
–
–
–
–
–
–
(0xD2)
Reserved
–
–
–
–
–
–
–
–
(0xD1)
Reserved
–
–
–
–
–
–
–
–
(0xD0)
Reserved
–
–
–
–
–
–
–
–
(0xCF)
Reserved
–
–
–
–
–
–
–
–
(0xCE)
Reserved
–
–
–
–
–
–
–
–
(0xCD)
Reserved
–
–
–
–
–
–
–
–
(0xCC)
Reserved
–
–
–
–
–
–
–
–
(0xCB)
Reserved
–
–
–
–
–
–
–
–
(0xCA)
Reserved
–
–
–
–
–
–
–
–
(0xC9)
Reserved
–
–
–
–
–
–
–
–
(0xC8)
Reserved
–
–
–
–
–
–
–
–
(0xC7)
Reserved
–
–
–
–
–
–
–
–
(0xC6)
UDR0
(0xC5)
UBRR0H
USART I/O Data Register
–
–
–
–
190
USART Baud Rate Register High
195
(0xC4)
UBRR0L
(0xC3)
UCSR0D
RXSIE
RXS
SFDE
USART Baud Rate Register Low
–
–
–
–
–
195
194
(0xC2)
UCSR0C
UMSEL01
UMSEL00
UPM01
UPM00
USBS0
UCSZ01 /UDORD0
UCSZ00 / UCPHA0
UCPOL0
192/205
(0xC1)
UCSR0B
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
191
(0xC0)
UCSR0A
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
190
(0xBF)
Reserved
–
–
–
–
–
–
–
–
(0xBE)
Reserved
–
–
–
–
–
–
–
–
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
362
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBD)
TWAMR
TWAM6
TWAM5
TWAM4
TWAM3
TWAM2
TWAM1
TWAM0
–
235
(0xBC)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
232
(0xBB)
TWDR
(0xBA)
TWAR
TWA6
TWA5
TWA4
TWS7
TWS6
TWS5
2-wire Serial Interface Data Register
(0xB9)
TWSR
(0xB8)
TWBR
(0xB7)
Reserved
–
(0xB6)
ASSR
–
(0xB5)
Reserved
–
234
TWA3
TWA2
TWA1
TWA0
TWGCE
235
TWS4
TWS3
–
TWPS1
TWPS0
234
2-wire Serial Interface Bit Rate Register
232
–
–
–
–
–
–
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
–
–
–
–
–
–
–
156
(0xB4)
OCR2B
Timer/Counter2 Output Compare Register B
154
(0xB3)
OCR2A
Timer/Counter2 Output Compare Register A
154
(0xB2)
TCNT2
(0xB1)
TCCR2B
FOC2A
FOC2B
–
Timer/Counter2 (8-bit)
–
WGM22
CS22
CS21
CS20
154
153
(0xB0)
TCCR2A
COM2A1
COM2A0
COM2B1
COM2B0
–
–
WGM21
WGM20
150
(0xAF)
Reserved
–
–
–
–
–
–
–
–
(0xAE)
Reserved
–
–
–
–
–
–
–
–
(0xAD)
Reserved
–
–
–
–
–
–
–
–
(0xAC)
Reserved
–
–
–
–
–
–
–
–
(0xAB)
Reserved
–
–
–
–
–
–
–
–
(0xAA)
Reserved
–
–
–
–
–
–
–
–
(0xA9)
Reserved
–
–
–
–
–
–
–
–
(0xA8)
Reserved
–
–
–
–
–
–
–
–
(0xA7)
Reserved
–
–
–
–
–
–
–
–
(0xA6)
Reserved
–
–
–
–
–
–
–
–
(0xA5)
Reserved
–
–
–
–
–
–
–
–
(0xA4)
Reserved
–
–
–
–
–
–
–
–
(0xA3)
Reserved
–
–
–
–
–
–
–
–
(0xA2)
Reserved
–
–
–
–
–
–
–
–
(0xA1)
Reserved
–
–
–
–
–
–
–
–
(0xA0)
Reserved
–
–
–
–
–
–
–
–
(0x9F)
Reserved
–
–
–
–
–
–
–
–
(0x9E)
Reserved
–
–
–
–
–
–
–
–
(0x9D)
Reserved
–
–
–
–
–
–
–
–
(0x9C)
Reserved
–
–
–
–
–
–
–
–
(0x9B)
Reserved
–
–
–
–
–
–
–
–
(0x9A)
Reserved
–
–
–
–
–
–
–
–
(0x99)
Reserved
–
–
–
–
–
–
–
–
(0x98)
Reserved
–
–
–
–
–
–
–
–
(0x97)
Reserved
–
–
–
–
–
–
–
–
(0x96)
Reserved
–
–
–
–
–
–
–
–
(0x95)
Reserved
–
–
–
–
–
–
–
–
(0x94)
Reserved
–
–
–
–
–
–
–
–
(0x93)
Reserved
–
–
–
–
–
–
–
–
(0x92)
Reserved
–
–
–
–
–
–
–
–
(0x91)
Reserved
–
–
–
–
–
–
–
–
(0x90)
Reserved
–
–
–
–
–
–
–
–
(0x8F)
Reserved
–
–
–
–
–
–
–
–
(0x8E)
Reserved
–
–
–
–
–
–
–
–
(0x8D)
Reserved
–
–
–
–
–
–
–
–
(0x8C)
Reserved
–
–
–
–
–
–
–
–
(0x8B)
OCR1BH
Timer/Counter1 - Output Compare Register B High Byte
131
(0x8A)
OCR1BL
Timer/Counter1 - Output Compare Register B Low Byte
131
(0x89)
OCR1AH
Timer/Counter1 - Output Compare Register A High Byte
131
(0x88)
OCR1AL
Timer/Counter1 - Output Compare Register A Low Byte
131
(0x87)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
132
(0x86)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
132
(0x85)
TCNT1H
Timer/Counter1 - Counter Register High Byte
131
(0x84)
TCNT1L
Timer/Counter1 - Counter Register Low Byte
131
(0x83)
Reserved
–
–
–
–
–
–
–
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
131
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
130
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
128
(0x7F)
DIDR1
–
–
–
–
–
–
AIN1D
AIN0D
239
(0x7E)
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
255
(0x7D)
Reserved
–
–
–
–
–
–
–
–
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
–
MUX3
MUX2
MUX1
MUX0
252
(0x7B)
ADCSRB
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
255
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
253
–
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
363
Address
Name
(0x79)
ADCH
Bit 7
Bit 6
Bit 5
ADC Data Register High byte
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
254
(0x78)
ADCL
ADC Data Register Low byte
254
(0x77)
Reserved
–
–
–
–
–
–
–
–
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
Reserved
–
–
–
–
–
–
–
–
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
TIMSK2
–
–
–
–
–
OCIE2B
OCIE2A
TOIE2
154
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
132
(0x6E)
TIMSK0
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
106
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
71
(0x6C)
PCMSK1
–
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
71
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
71
(0x6A)
Reserved
–
–
–
–
–
–
–
–
(0x69)
EICRA
–
–
–
–
ISC11
ISC10
ISC01
ISC00
(0x68)
PCICR
–
–
–
–
–
PCIE2
PCIE1
PCIE0
(0x67)
Reserved
–
–
–
–
–
–
–
–
(0x66)
OSCCAL
(0x65)
Reserved
–
–
–
–
–
–
–
–
(0x64)
PRR
PRTWI
PRTIM2
PRTIM0
–
PRTIM1
PRSPI
PRUSART0
PRADC
(0x63)
Reserved
–
–
–
–
–
–
–
–
(0x62)
Reserved
–
–
–
–
–
–
–
–
(0x61)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
35
(0x60)
WDTCSR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
52
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
9
0x3E (0x5E)
SPH
–
–
–
–
–
(SP10) 4.
SP9
SP8
12
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
12
0x3C (0x5C)
Reserved
–
–
–
–
–
–
–
–
0x3B (0x5B)
Reserved
–
–
–
–
–
–
–
–
0x3A (0x5A)
Reserved
–
–
–
–
–
–
–
–
0x39 (0x59)
Reserved
–
–
–
–
–
–
–
–
0x38 (0x58)
Reserved
–
–
–
–
–
–
–
–
0x37 (0x57)
SPMCSR
SPMIE
(RWWSB)4.
SIGRD
(RWWSRE)4.
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
–
–
–
–
–
–
–
–
0x35 (0x55)
MCUCR
–
BODS
BODSE
PUD
–
–
IVSEL
IVCE
0x34 (0x54)
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
52
0x33 (0x53)
SMCR
–
–
–
–
SM2
SM1
SM0
SE
38
0x32 (0x52)
Reserved
–
–
–
–
–
–
–
–
0x31 (0x51)
Reserved
–
–
–
–
–
–
–
–
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
237
0x2F (0x4F)
ACSR0
–
–
–
–
–
–
–
ACOE
237
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
–
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
Timer/Counter0 Output Compare Register B
0x27 (0x47)
OCR0A
Timer/Counter0 Output Compare Register A
0x26 (0x46)
TCNT0
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
–
–
WGM01
WGM00
0x23 (0x43)
GTCCR
TSM
–
–
–
–
–
PSRASY
PSRSYNC
0x22 (0x42)
EEARH
(EEPROM Address Register High Byte) 4.
0x21 (0x41)
EEARL
EEPROM Address Register Low Byte
21
0x20 (0x40)
EEDR
EEPROM Data Register
21
Oscillator Calibration Register
35
SPI Data Register
–
–
–
68
39
281
43/65/88
167
–
–
–
–
SPI2X
166
MSTR
CPOL
CPHA
SPR1
SPR0
165
–
25
25
–
–
–
–
Timer/Counter0 (8-bit)
–
–
EEPM1
EEPM0
EERIE
136/157
21
0x1F (0x3F)
EECR
0x1E (0x3E)
GPIOR0
EEMPE
EEPE
EERE
21
0x1D (0x3D)
EIMSK
–
–
–
–
–
–
INT1
INT0
69
0x1C (0x3C)
EIFR
–
–
–
–
–
–
0x1B (0x3B)
PCIFR
–
–
–
–
–
PCIF2
INTF1
INTF0
69
PCIF1
PCIF0
0x1A (0x3A)
Reserved
–
–
–
–
–
–
–
–
0x19 (0x39)
Reserved
–
–
–
–
–
–
–
–
0x18 (0x38)
Reserved
–
–
–
–
–
–
–
–
0x17 (0x37)
TIFR2
–
–
–
–
–
OCF2B
OCF2A
TOV2
155
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
133
General Purpose I/O Register 0
25
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
364
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x15 (0x35)
TIFR0
–
–
–
–
–
OCF0B
OCF0A
TOV0
Page
0x14 (0x34)
Reserved
–
–
–
–
–
–
–
–
0x13 (0x33)
Reserved
–
–
–
–
–
–
–
–
0x12 (0x32)
Reserved
–
–
–
–
–
–
–
–
0x11 (0x31)
Reserved
–
–
–
–
–
–
–
–
0x10 (0x30)
Reserved
–
–
–
–
–
–
–
–
0x0F (0x2F)
Reserved
–
–
–
–
–
–
–
–
0x0E (0x2E)
PORTE
–
–
–
–
PORTE3
PORTE2
PORTE1
PORTE0
89
0x0D (0x2D)
DDRE
–
–
–
–
DDRE3
DDRE2
DDRE1
DDRE0
89
0x0C (0x2C)
PINE
–
–
–
–
PINE3
PINE2
PINE1
PINE0
89
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
89
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
89
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
89
0x08 (0x28)
PORTC
–
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
88
0x07 (0x27)
DDRC
–
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
88
89
0x06 (0x26)
PINC
–
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
88
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
88
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
88
0x02 (0x22)
Reserved
–
–
–
–
–
–
–
–
0x01 (0x21)
Reserved
–
–
–
–
–
–
–
–
0x0 (0x20)
Reserved
–
–
–
–
–
–
–
–
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel
ATmega48PB/88PB/168PB is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
365
33.
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd  Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl  Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd  Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd  Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd  Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd  Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl  Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd  Rd · Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd  Rd · K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd  Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd  Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd  Rd Å Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd  0xFF - Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd  0x00 - Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd  Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd Rd · (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd  Rd - 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd  Rd · Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd  Rd Å Rd
Z,N,V
1
SER
Rd
Set Register
Rd  0xFF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0  Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0  Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0  Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0  (Rd x Rr) << 1
Z,C
2
FMULS
Rd, Rr
Fractional Multiply Signed
R1:R0  (Rd x Rr) << 1
Z,C
2
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
R1:R0  (Rd x Rr) << 1
Z,C
2
Relative Jump
PC  PC + k + 1
None
2
Indirect Jump to (Z)
PC  Z
None
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
JMP(1)
k
Direct Jump
PC  k
None
3
RCALL
k
Relative Subroutine Call
PC  PC + k + 1
None
3
Indirect Call to (Z)
PC  Z
None
3
Direct Subroutine Call
PC  k
None
4
RET
Subroutine Return
PC  STACK
None
4
RETI
Interrupt Return
PC  STACK
I
ICALL
CALL(1)
k
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC  PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd - Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd - K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC  PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC  PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC  PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC  PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PCPC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PCPC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC  PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC  PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC  PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC  PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC  PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC  PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC  PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N Å V= 0) then PC  PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N Å V= 1) then PC  PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC  PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC  PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC  PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC  PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC  PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC  PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC  PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC  PC + k + 1
None
1/2
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1
366
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b)  1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b)  0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1)  Rd(n), Rd(0)  0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n)  Rd(n+1), Rd(7)  0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)  Rd(n+1), n=0...6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3...0)Rd(7...4),Rd(7...4)Rd(3...0)
None
1
BSET
s
Flag Set
SREG(s)  1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)  0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T  Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)  T
None
1
SEC
Set Carry
C1
C
1
CLC
Clear Carry
C0
C
1
SEN
Set Negative Flag
N1
N
1
CLN
Clear Negative Flag
N0
N
1
SEZ
Set Zero Flag
Z1
Z
1
CLZ
Clear Zero Flag
Z0
Z
1
SEI
Global Interrupt Enable
I1
I
1
CLI
Global Interrupt Disable
I0
I
1
SES
Set Signed Test Flag
S 1
S
1
CLS
Clear Signed Test Flag
S0
S
1
SEV
Set Twos Complement Overflow.
V1
V
1
CLV
Clear Twos Complement Overflow
V0
V
1
SET
Set T in SREG
T1
T
1
CLT
Clear T in SREG
T0
T
1
SEH
Set Half Carry Flag in SREG
H1
H
1
CLH
Clear Half Carry Flag in SREG
H0
H
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
Rd  Rr
None
1
MOVW
Rd, Rr
Copy Register Word
Rd+1:Rd  Rr+1:Rr
None
1
LDI
Rd, K
Load Immediate
Rd  K
None
1
LD
Rd, X
Load Indirect
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd  (X)
Rd  (X), X 
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X X - 1, Rd  (X)
None
2
LD
Rd, Y
Load Indirect
Rd  (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd  (Y), Y  Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y  Y - 1, Rd  (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd  (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd  (Z), Z  Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z  Z - 1, Rd  (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd  (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd  (k)
None
2
ST
X, Rr
Store Indirect
(X)  Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X)  Rr, X  X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X  X - 1, (X) ¬ Rr
None
2
ST
Y, Rr
Store Indirect
(Y)  Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y)  Rr, Y  Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y  Y - 1, (Y)  Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q)  Rr
None
2
ST
Z, Rr
Store Indirect
(Z)  Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z)  Rr, Z  Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z  Z - 1, (Z)  Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)  Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k)  Rr
None
2
Load Program Memory
R0  (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd  (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd  (Z), Z  Z+1
None
3
Store Program Memory
(Z)  R1:R0
None
-
SPM
IN
Rd, P
In Port
Rd  P
None
1
OUT
P, Rr
Out Port
P  Rr
None
1
PUSH
Rr
Push Register on Stack
STACK  Rr
None
2
POP
Rd
Pop Register from Stack
Rd  STACK
None
2
None
1
None
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
SLEEP
Sleep
(see specific descr. for Sleep function)
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Mnemonics
WDR
BREAK
Note:
Operands
Description
Operation
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
Flags
#Clocks
None
None
1
N/A
1. These instructions are only available in ATmega168PB
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34.
Ordering Information
34.1
ATmega48PB
Speed [MHz](3)
20
Note:
Power Supply [V]
1.8 - 5.5
Ordering Code(2)
Package(1)
ATmega48PB-AU
ATmega48PB-AUR(4)
ATmega48PB-MU
ATmega48PB-MUR(4)
32A
32A
32MS1
32MS1
Industrial
(-40C to 85C)
ATmega48PB-AN
ATmega48PB-ANR(4)
ATmega48PB-MN
ATmega48PB-MNR(4)
32A
32A
32MS1
32MS1
Industrial
(-40C to 105C)
Operational Range
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. See ”Speed Grades” on page 304.
4. Tape & Reel.
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32MS1
32-pad, 5.0x5.0x0.9mm body, Lead Pitch 0.50mm, Very-thin Fine pitch, Quad Flat No Lead Package (VFQFN)
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34.2
ATmega88PB
Speed [MHz](3)
20
Note:
Power Supply [V]
1.8 - 5.5
Ordering Code(2)
Package(1)
ATmega88PB-AU
ATmega88PB-AUR(4)
ATmega88PB-MU
ATmega88PB-MUR(4)
32A
32A
32MS1
32MS
Industrial
(-40C to 85C)
ATmega88PB-AN
ATmega88PB-ANR(4)
ATmega88PB-MN
ATmega88PB-MNR(4)
32A
32A
32MS1
32MS1
Industrial
(-40C to 105C)
Operational Range
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See ”Speed Grades” on page 304.
4. Tape & Reel.
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32MS1
32-pad, 5.0x5.0x0.9mm body, Lead Pitch 0.50mm, Very-thin Fine pitch, Quad Flat No Lead Package (VFQFN)
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34.3
ATmega168PB
Speed [MHz]
20
Note:
Power Supply [V]
1.8 - 5.5
Ordering Code(2)
Package(1)
ATmega168PB-AU
ATmega168PB-AUR(3)
ATmega168PB-MU
ATmega168PB-MUR(3)
32A
32A
32MS1
32MS1
Industrial
(-40C to 85C)
ATmega168PB-AN
ATmega168PB-ANR(3)
ATmega168PB-MN
ATmega168PB-MNR(3)
32A
32A
32MS1
32MS1
Industrial
(-40C to 105C)
Operational Range
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. Tape & Reel.
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32MS1
32-pad, 5.0x5.0x0.9mm body, Lead Pitch 0.50mm, Very-thin Fine pitch, Quad Flat No Lead Package (VFQFN)
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35.
Packaging Information
35.1
32A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of measure = mm)
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
8.75
9.00
9.25
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
D1
6.90
7.00
7.10
E
8.75
9.00
9.25
E1
6.90
7.00
7.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
DRAWING NO.
TITLE
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
32A
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C
372
35.2
32MS1
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36.
Errata
36.1
Errata ATmega48PB
The revision letter in this section refers to the revision of the ATmega48PB device.
36.1.1 Rev. A
–
–
–
–
Wrong device ID when using debugWire
Power consumption in power save modes
USART start-up functionality not working
External capacitor on AREF pin
1.) Wrong device ID when using debugWire
The device ID returned using debugWire is incorrect.
Problem Fix/Workaround
None.
2.) Power consumption in power save modes
Power consumption in power save modes will be higher due to improper control of internal power
management.
Problem Fix/Workaround
None.
3.) USART start-up functionality not working
While in power save modes, the USART start bit detection logic fails to wakeup the device.
Problem Fix/Workaround
None.
4.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
36.1.2 Rev. B
– External capacitor on AREF pin
1.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
36.1.3 Rev. C
No known errata.
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36.2
Errata ATmega88PB
The revision letter in this section refers to the revision of the ATmega88PB device.
36.2.1 Rev. A
–
–
–
–
Wrong device ID when using debugWire
Power consumption in power save modes
USART start-up functionality not working
External capacitor on AREF pin
1.) Wrong device ID when using debugWire
The device ID returned using debugWire is incorrect.
Problem Fix/Workaround
None.
2.) Power consumption in power save modes
Power consumption in power save modes will be higher due to improper control of internal power
management.
Problem Fix/Workaround
None.
3.) USART start-up functionality not working
While in power save modes, the USART start bit detection logic fails to wakeup the device.
Problem Fix/Workaround
None.
4.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
36.2.2 Rev. B
– External capacitor on AREF pin
1.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
36.2.3 Rev. C
No known errata.
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36.3
Errata ATmega168PB
The revision letter in this section refers to the revision of the ATmega168PB device.
36.3.1 Rev. A
– Wrong device ID when using debugWire
– Power consumption in power save modes
– USART start-up functionality not working
– External capacitor on AREF pin 1.) Wrong device ID when using debugWire
The device ID returned using debugWire is incorrect.
Problem Fix/Workaround
None.
2.) Power consumption in power save modes
Power consumption in power save modes will be higher due to improper control of internal power
management.
Problem Fix/Workaround
None
3.) USART start-up functionality not working
While in power save modes, the USART start bit detection logic fails to wakeup the device.
Problem Fix/Workaround
None.
4.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
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36.3.2 Rev. B
– Power consumption in power save modes
– External capacitor on AREF pin
1.) Power consumption in power save modes
Power consumption in power save modes will be higher due to improper control of internal power
management.
Problem Fix/Workaround
None
2.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
36.3.3 Rev. C
– External capacitor on AREF pin
1.) External capacitor on AREF pin
If an external capacitor is used on the analog reference pin (AREF), it should be equal to or larger than
100nF. Smaller capacitor value can make the AREF buffer unstable with large ringing which will reduce the
accuracy of the ADC.
Problem Fix/Workaround
None.
36.3.4 Rev. D
No known errata.
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37.
Datasheet Revision History
Note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
37.1
37.2
37.3
Rev. 42176D – 04/2015
1.
Added ”ATmega48PB/88PB DC Characteristics” on page 302.
2.
Added ”ATmega48PB/88PB Typical Characteristics” on page 314.
3.
Updated numbers in ”ATmega168PB DC Characteristics” on page 303
4.
Updated numbers in ”ATmega168PB Supply Current of IO Modules” on page 343.
Rev. 42176C – 03/2015
1.
“Clock Characteristics” :
Updated factory calibration accuracy from ±10% to ±3%in ”Calibrated Internal RC Oscillator Accuracy” on page 305.
2.
“Errata” :
Updated ”Errata ATmega48PB” on page 374, ”Errata ATmega88PB” on page 375 and ”Errata ATmega168PB” on
page 376.
Rev. 42176B – 11/2014
1.
Additional Delay from Reset (VCC=5V) updated from 14CK to 19CK in the following sections / tables:
•
•
•
•
•
•
37.4
“Low Power Crystal Oscillator” / Table 10-4 on page 29.
“Low Frequency Crystal Oscillator” / Table 10-6 on page 30.
“Low Frequency Crystal Oscillator” / Table 10-9 on page 31.
“Calibrated Internal RC Oscillator” / Table 10-12 on page 32.
“128kHz Internal Oscillator” / Table 10-14 on page 33.
“External Clock” / Table 10-16 on page 33.
Rev. 42176A – 11/2014
1.
Initial release.
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_04/2015
378
Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features1
1.
Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
3.
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1
3.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Comparison Between Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.
Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
5.
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
6.
About Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
7.
Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
7.1
8.
AVR CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9.
QTouch Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
ALU – Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
General Purpose Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset and Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
AVR Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
9.1
9.2
9.3
9.4
9.5
9.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
In-System Reprogrammable Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
SRAM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
10. System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
Clock Systems and their Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Low Power Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Full Swing Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Low Frequency Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Calibrated Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
128kHz Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Clock Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Timer/Counter Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
System Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_03/2015
1
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
BOD Disable(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ADC Noise Reduction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power-save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Extended Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power Reduction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Minimizing Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Resetting the AVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Brown-out Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Watchdog System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
13. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
13.1
13.2
13.3
13.4
Interrupt Vectors in ATmega48PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Interrupt Vectors in ATmega88PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Interrupt Vectors in ATmega168PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
14. External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
14.1
14.2
Pin Change Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
15. I/O-Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
15.1
15.2
15.3
15.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Ports as General Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
16. 8-bit Timer/Counter0 with PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Timer/Counter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Output Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Compare Match Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
17. 16-bit Timer/Counter1 with PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
17.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_03/2015
2
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10
17.11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Accessing 16-bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Timer/Counter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Input Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Output Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Compare Match Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
18. Timer/Counter0 and Timer/Counter1 Prescalers . . . . . . . . . . . . . . . . . . . . . . . . . .134
18.1
18.2
18.3
18.4
Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Prescaler Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
19. 8-bit Timer/Counter2 with PWM and Asynchronous Operation . . . . . . . . . . . . . .137
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Timer/Counter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Output Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Compare Match Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Asynchronous Operation of Timer/Counter2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Timer/Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
20. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
20.1
20.2
20.3
20.4
20.5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
SS Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
21. USART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
USART Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Data Transmission – The USART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
Data Reception – The USART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Asynchronous Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Multi-processor Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Examples of Baud Rate Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
22. USART in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
22.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
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22.2
22.3
22.4
22.5
22.6
22.7
22.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
SPI Data Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
AVR USART MSPIM vs. AVR SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
23. 2-wire Serial Interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
2-wire Serial Interface Bus Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Data Transfer and Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Multi-master Bus Systems, Arbitration and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Overview of the TWI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Using the TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Multi-master Systems and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
24. Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
24.1
24.2
24.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Analog Comparator Multiplexed Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
25. Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Starting a Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
Prescaling and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Changing Channel or Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
ADC Noise Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
ADC Conversion Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
26. debugWIRE On-chip Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
26.1
26.2
26.3
26.4
26.5
26.6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Software Break Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Limitations of debugWIRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
27. Self-Programming the Flash, ATmega48PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
27.1
27.2
27.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Addressing the Flash During Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
28. Boot Loader Support – Read-While-Write Self-Programming . . . . . . . . . . . . . . . .267
28.1
28.2
28.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Application and Boot Loader Flash Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
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28.4
28.5
28.6
28.7
28.8
28.9
Read-While-Write and No Read-While-Write Flash Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
Boot Loader Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Entering the Boot Loader Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Addressing the Flash During Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Self-Programming the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
29. Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
Program And Data Memory Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Fuse Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Signature Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Calibration Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
Parallel Programming Parameters, Pin Mapping, and Commands . . . . . . . . . . . . . . . . . . . . . . . . .287
Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
30. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
30.9
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
System and Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Two-wire Serial Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
Parallel Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
31. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
31.1
31.2
ATmega48PB/88PB Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
ATmega168PB Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
32. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
33. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
34. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
34.1
34.2
34.3
ATmega48PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
ATmega88PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
ATmega168PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
35. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
35.1
35.2
32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
32MS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
36. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
36.1
36.2
36.3
Errata ATmega48PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
Errata ATmega88PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
Errata ATmega168PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
37. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
37.1
37.2
Rev. 42176D – 04/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
Rev. 42176C – 03/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
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37.3
37.4
Rev. 42176B – 11/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
Rev. 42176A – 11/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table of Contents1
ATmega48PB/88PB/168PB [PRELIMINARY DATASHEET]
Atmel-42176D–AVR-ATmega48PB-88PB-168PB_Datasheet_03/2015
6
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