M61522FP 8ch ELECTRONIC VOLUME WITH 8 INPUT SELECTOR REJ03F0034-0100Z Rev.1.0 Sep.19.2003 Feature FUNCTION FEATURE Electronic Volume 8 channel Dependant Electronic Volume with High Voltage Transistor. (0~-99dB/ 1dBstep, -∞dB) Input Selector (1) Front L/R channel 8 Input Selector.(Main/Sub) (2) 2 channel Selector Output. Multi Channel Input External Input All channel 2 Input Selector. 2 External Input.(C/SBLch) REC Output Input ATT 4 Lines REC Output (Both L and R channels) Input ATT (0/-3/-6/-9/-12dB) Output Gain Control Balance Out Output Gain Control (0/+3/+6/+9/+10/+12dB) Built-in Balance Output (for ADC) Application Receiver, AV Amp, Mini Stereo etc. Recommended Operating Condition Rated Supply Voltage ……AVCC=7.0V(typ), AVEE=-7.0V(typ), DVDD=3.3V(typ) Rev.1.0, Sep.19.2003, page 1 of 17 M61522FP Multi FRin CLOCK LOUT ROUT RECOUTL Multi FLin LATCH DATA System Block Diagram MCU I/F 1 Output Gain Control 2 FLout 3 Output Gain Control 4 Lch 5 6 7 AVCC MA IN L Multi Cin /External INA Output Gain Control Multi SBLi n /External INB Output Gain Control Cout AVEE 8 DVDD MA IN R DGND 1 2 FRout SUB L SUB R InputATT 3 Balance Output L channel 4 Rch InputATT 5 6 Balance Output R channel 7 8 RECOUTR Rev.1.0, Sep.19.2003, page 2 of 17 Multi SLin Output Gain Control Multi SBRin Output Gain Control Multi SRin Output Gain Control Multi SWin Output Gain Control GND SBLout SLout SBRout SRout SWout M61522FP CLOCK FRSELOUT 42 MCU I/F Output Gain Control GND 43 FRIN2 44 25 DVDD 27 DATA 26 LA TCH 24 GND DATA LATCH FRVIN 41 28 CLOCK 29 DGND 30 AVCC 31 GND 32 FLOUT 33 SLOUT 34 SBLOUT 35 COUT 36 SWOUT 37 SROUT 38 SBROUT 39 FROUT 40 GND Block Diagram and Pin Configuration (Top View) 23 FLVIN 22 FLSELOUT Output Gain Control SBRIN2 45 SRIN2 46 21 GND FLchVOL 20 FRIN1 FRchVOL 19 SBRIN1 Output Gain Control SWIN2 47 CIN2 48 Output Gain Control Output Gain Control Output Gain Control Output Gain Control Output Gain Control 18 SRIN1 17 SWIN1 SBLIN2 49 16 CIN1 SLIN2 50 FRch SBRchVOLSRchVOLSWchVOL CchVOL SBLchVOL SLchVOL 15 SBLIN1 FLch FLIN2 51 14 SLIN1 GND 52 13 FLIN1 GND 53 12 GND CIN3 54 11 BALANCE R/+ (External INA) Rch SBLIN3 55 (External INB) GND 56 9 GND Balance Out RECR4 57 10 BALANCE R/8 BALANCE L/- InputATT Lch InputATT RECR3 58 7 BALANCE L/+ RECR2 59 6 RECL4 RECR1 60 5 RECL3 ROUT 61 4 RECL2 MAIN L SUB R LOUT 62 MAIN R S UB L 3 RECL1 Rev.1.0, Sep.19.2003, page 3 of 17 INLH 80 INLG 79 INLF 78 INLE 77 INLD 76 INLC 75 INLB 74 INLA 73 AVEE 72 INRA 71 INRB 70 INRC 69 INRD 68 1 INRE 67 INRH 64 INRF 66 2 GND INRG 65 GND 63 NC M61522FP Pin Description PIN No. Name Function 1 NC Non-connection terminal 2,9,12,21,24,31, 40,43,52,53,56,63 GND Analog Ground 3,4,5,6, 57,58,59,60 7,8 REC L1,L2,L3,L4 /REC R1,R2,R3,R4 BALANCE L/+,L/- Output pin of REC (Lch and Rch) 10,11 13,51 BALANCE R/+,R/FLIN1/FLIN2 Output pin of R channel Balance Output(+/-) Input pin of FL channel (2 Input Selector) 14,50 15,49 SLIN1/SLIN2 SBLIN1/SBLIN2 Input pin of SL channel (2 Input Selector) Input pin of SBL channel (2 Input Selector) 16,48 17,47 CIN1/CIN2 SWIN1/SWIN2 Input pin of C channel (2 Input Selector) Input pin of SW channel (2 Input Selector) 18,46 19,45 SRIN1/SRIN2 SBRIN1/SBRIN2 Input pin of SR channel (2 Input Selector) Input pin of SBR channel (2 Input Selector) 20,44 22 FRIN1/FRIN2 FLSELOUT Input pin of FR channel (2 Input Selector) Output pin of FL channel volume input selector 23 25 FLVIN DVDD Input pin of FL channel volume Power supply to internal logic circuit 29 26,27,28 DGND LATCH,DATA,CLOCK Ground of internal logic circuit Input pin of Control trigger/data/clock 30 32 AVCC FLOUT Positive power supply to internal analog circuit Output pin of FL channel 33 34 SLOUT SBLOUT Output pin of SL channel Output pin of SBL channel 35 36 COUT SWOUT Output pin of C channel Output pin of SW channel 37 38 SBROUT SROUT Output pin of SBR channel Output pin of SR channel 39 41 FROUT FRVIN Output pin of FR channel Input pin of FR channel volume 42 54 FRSELOUT CIN3 Output pin of FR channel volume input selector External input pinA(Input pin of C channel) 55 61,62 SBLIN3 ROUT/LOUT External input pinB(Input pin of SBL channel) Output pin of Input selector 64,65,66,67,68,69, 70,71 73,74,75,76,77,78, 79,80 INRA,B,C,D,E,F,G,H Input pin of R channel (8 Input Selector) INLA,B,C,D,E,F,G,H Input pin of L channel (8 Input Selector) 72 AVEE Negative power supply to internal analog circuit Rev.1.0, Sep.19.2003, page 4 of 17 Output pin of L channel Balance Output(+/-) M61522FP Absolute Maximum Ratings (Ta=25°C, unless otherwise noted) Symbol Parameter Condition Ratings Unit Supply voltage Power supply AVCC-AVEE ±7.8 V DVDD-GND Ta≤25°C 6.0 1250 Pd Power dissipation Kθ Topr Thermal derating Operating temperature mW Ta>25°C 12.5 -20~+55 mW/°C °C Tstg Storage temperature -40~+125 °C THERMAL DERATINGS (MAXIMU M RATING) POWER DISSIPATION Pd(W) 1.5 1.0 0.5 0 55 0 25 50 75 100 125 150 AM BIENT TEMPERATURE Ta (˚C) Recommended Operating Conditions (Ta=25°C, unless otherwise noted) Parameter Symbol Analog supply voltage (Positive) AVCC Condition Analog supply voltage (Negative) AVEE -7.3 -7.0 -4.5 V Digital supply voltage Logic ìHî level input voltage DVDD VIH DGND reference 3.0 2.4 3.3 — 3.6 DVDD V V Logic ì Lî level input voltage VIL DGND reference DGND — 0.5 V Note1: VEE≤DGND<VDD≤VCC Note2: After applying AVCC, then apply AVEE and DVDD. Rev.1.0, Sep.19.2003, page 5 of 17 MIN TYP MAX Unit 4.5 7.0 7.3 V M61522FP Relationship between Data and Clock LA TCH SIGNAL H DATA D0 L D1 D29 D30 D31 D0 H CLOCK L H LA TCH L DATA signal is readat the rising edgeof the CLOCK. Serial data (D0 - D31) is loadedat the risingedgeof the LATCH signal. Clock and Data Timings tSC tcr 75% CLOCK 25% 25% tr tf tWHC tWLC 75% DATA 25% tr tf tSD LATCH tHD tr tSL tWHC tf 75% 25% Rev.1.0, Sep.19.2003, page 6 of 17 M61522FP Timing Definition of Digital Block Symbol Parameter Limits Min typ Max Unit tcr tWHC Clock cycle time Clock pulse width (ìHî level) 4 1.6 — — — µsec tWLC tr Clock pulse width (ìLî level) Rising time of clock, data and latch 1.6 — — — tf tSD Falling time of clock, data and latch Data setup time — 0.8 — — — tHD tSL Data hold time Latch setup time 0.8 1 — — — — tWHL tSC Latch pulse width Clock setup time 1.6 4 — — — — Rev.1.0, Sep.19.2003, page 7 of 17 — — 0.4 0.4 Rev.1.0, Sep.19.2003, page 8 of 17 Slot 2 Slot 1 Slot 0 SRch Volume Output Gain Control SLch Volume Input ATT FRch Volume Input Selector (SUB) FLch Volume Input Selector (MAIN) 0 SBRchVolume 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 SWch Volume All ch REC REC REC REC Output Output Output Output Output VOL Mute 1 2 3 4 Input Selector SW SR SL SBR Cch Volume C/SBL VOL Input Selector SBLch Volume FL/FR VOL Input Selector D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Three types of input format can be selected by changing the D30/D31slot setting status. (Initialize all data of the3 formats when Digital Powersupply (DVDD) turn on). M61522FP Data Control Specification M61522FP Setting Code (4)FL/FR channel Volume Input Selector (D30=0,D31=0) (1)Input Selector(MAI N/SUB) (D30=0,D31=0) MAI N D0 D1 D2 D3 Setting D14 D15 SUB D4 D5 D6 D7 Bypass 0 0 AL L OFF 0 0 0 0 Multi IN1 0 1 A 0 0 0 1 Multi IN2 1 0 B 0 0 1 0 C 0 0 1 1 D 0 1 0 0 Setting D16 D17 E 0 1 0 1 External IN 0 0 F 0 1 1 0 Multi IN1 0 1 G 0 1 1 1 Multi IN2 1 0 H 1 0 0 0 Setting (6)SW/SR/SL/SBR channel VolumeInput Selector (D30=0,D31=0) (2) Input ATT (D30=0,D31=0) Setting (5)C/SBL channel Volume Input Selector (D30=0,D31=0) D8 D9 D10 0dB 0 0 0 -3dB 0 0 1 -6dB 0 1 0 -9dB 0 1 1 -12dB 1 0 0 (3)Output Gain Control (D30=0,D31=0) Setting D18 Multi IN1 0 Multi IN2 1 (7)All channel Output Mute (D30=0,D31=0) Setting D19 Mute OFF 0 Mute ON 1 (8)REC Output (D30=0,D31=0) Setting D11 D12 D13 0dB 0 0 0 RECoutput +3dB 0 0 1 Setting D20 D21 D22 D23 +6dB 0 1 0 OFF 0 0 0 0 +9dB 0 1 1 ON 1 1 1 1 +10dB 1 0 0 +12dB 1 0 1 Note : Please don't input except specification data. Rev.1.0, Sep.19.2003, page 9 of 17 REC1 REC2 REC3 REC4 It's initial setting when DVDD turn on. M61522FP (9)8 channel Volume(FLch,FRch,Cch,SWch:D30=0,D31=1 / SLch,SRch,SBLch,SBRch:D30=1,D31=0) FLch FLch D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 D6 SLch SLch ATT FRch ATT FRch SRch D7 D8 D9 D10 D11 D12 SRch D7 D8 D9 D10 D11 D12 D13 Cch Cch SBLch D14 D15 D16 D17 D18 D19 SBLch D14 D15 D16 D17 D18 D19 D20 SWch SWch SBRch D21 D22 D23 D24 D25 D26 SBRch D21 D22 D23 D24 D25 D26 D27 D6 D13 D20 D27 0dB 0 0 0 0 0 0 0 -28dB 0 0 1 1 1 0 0 -1dB 0 0 0 0 0 0 1 -29dB 0 0 1 1 1 0 1 -2dB 0 0 0 0 0 1 0 -30dB 0 0 1 1 1 1 0 -3dB 0 0 0 0 0 1 1 -31dB 0 0 1 1 1 1 1 -4dB 0 0 0 0 1 0 0 -32dB 0 1 0 0 0 0 0 -5dB 0 0 0 0 1 0 1 -33dB 0 1 0 0 0 0 1 -6dB 0 0 0 0 1 1 0 -34dB 0 1 0 0 0 1 0 -7dB 0 0 0 0 1 1 1 -35dB 0 1 0 0 0 1 1 -8dB 0 0 0 1 0 0 0 -36dB 0 1 0 0 1 0 0 -9dB 0 0 0 1 0 0 1 -37dB 0 1 0 0 1 0 1 -10dB 0 0 0 1 0 1 0 -38dB 0 1 0 0 1 1 0 -11dB 0 0 0 1 0 1 1 -39dB 0 1 0 0 1 1 1 -12dB 0 0 0 1 1 0 0 -40dB 0 1 0 1 0 0 0 -13dB 0 0 0 1 1 0 1 -41dB 0 1 0 1 0 0 1 -14dB 0 0 0 1 1 1 0 -42dB 0 1 0 1 0 1 0 -15dB 0 0 0 1 1 1 1 -43dB 0 1 0 1 0 1 1 -16dB 0 0 1 0 0 0 0 -44dB 0 1 0 1 1 0 0 -17dB 0 0 1 0 0 0 1 -45dB 0 1 0 1 1 0 1 -18dB 0 0 1 0 0 1 0 -46dB 0 1 0 1 1 1 0 -19dB 0 0 1 0 0 1 1 -47dB 0 1 0 1 1 1 1 -20dB 0 0 1 0 1 0 0 -48dB 0 1 1 0 0 0 0 -21dB 0 0 1 0 1 0 1 -49dB 0 1 1 0 0 0 1 -22dB 0 0 1 0 1 1 0 -50dB 0 1 1 0 0 1 0 -23dB 0 0 1 0 1 1 1 -51dB 0 1 1 0 0 1 1 -24dB 0 0 1 1 0 0 0 -52dB 0 1 1 0 1 0 0 -25dB 0 0 1 1 0 0 1 -53dB 0 1 1 0 1 0 1 -26dB 0 0 1 1 0 1 0 -54dB 0 1 1 0 1 1 0 -27dB 0 0 1 1 0 1 1 -55dB 0 1 1 0 1 1 1 Rev.1.0, Sep.19.2003, page 10 of 17 M61522FP FLch SLch ATT FRch SRch Cch SBLch SWch SBRch -56dB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 ATT FLch SLch FRch SRch Cch SBLch SWch SBRch D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 1 1 1 0 0 0 -83dB 1 0 1 0 0 1 1 -57dB 0 1 1 1 0 0 1 -84dB 1 0 1 0 1 0 0 -58dB 0 1 1 1 0 1 0 -85dB 1 0 1 0 1 0 1 -59dB 0 1 1 1 0 1 1 -86dB 1 0 1 0 1 1 0 -60dB 0 1 1 1 1 0 0 -87dB 1 0 1 0 1 1 1 -61dB 0 1 1 1 1 0 1 -88dB 1 0 1 1 0 0 0 -62dB 0 1 1 1 1 1 0 -89dB 1 0 1 1 0 0 1 -63dB 0 1 1 1 1 1 1 -90dB 1 0 1 1 0 1 0 -64dB 1 0 0 0 0 0 0 -91dB 1 0 1 1 0 1 1 -65dB 1 0 0 0 0 0 1 -92dB 1 0 1 1 1 0 0 -66dB 1 0 0 0 0 1 0 -93dB 1 0 1 1 1 0 1 -67dB 1 0 0 0 0 1 1 -94dB 1 0 1 1 1 1 0 -68dB 1 0 0 0 1 0 0 -95dB 1 0 1 1 1 1 1 -69dB 1 0 0 0 1 0 1 -96dB 1 1 0 0 0 0 0 -70dB 1 0 0 0 1 1 0 -97dB 1 1 0 0 0 0 1 -71dB 1 0 0 0 1 1 1 -98dB 1 1 0 0 0 1 0 -72dB 1 0 0 1 0 0 0 -99dB 1 1 0 0 0 1 1 -73dB 1 0 0 1 0 0 1 -¥ dB 1 1 1 1 0 0 0 -74dB 1 0 0 1 0 1 0 -75dB 1 0 0 1 0 1 1 -76dB 1 0 0 1 1 0 0 -77dB 1 0 0 1 1 0 1 -78dB 1 0 0 1 1 1 0 -79dB 1 0 0 1 1 1 1 -80dB 1 0 1 0 0 0 0 -81dB 1 0 1 0 0 0 1 -82dB 1 0 1 0 0 1 0 Note : Please don't input except specification data. Rev.1.0, Sep.19.2003, page 11 of 17 M61522FP Electrical Characteristics Unless otherwise noted, Ta=25°C, AVCC=7V, AVEE=-7V, DVDD=3.3V, f=1kHz, Volume=0dB, Input ATT=0dB, Output Gain Control=0dB setting (1) Power supply characteristics Limits min typ max Unit With AVCC=7V and AVEE=-7V Pin30 pin current, no signal. — 40 60 mA With AVCC=7V and AVEE=-7V Pin72 pin current, no signal. With DVDD=5V, Pin25 pin current, no signal. — 40 60 mA — 3 6 mA Parameter Symbol Test condition Analog positive power circuit current AIcc Analog negative power Circuit current Digital power circuit current AIee DIdd Rev.1.0, Sep.19.2003, page 12 of 17 M61522FP (2) Input/Output characteristics (OVER ALL) Limits Parameter Symbol Test condition min typ max Unit Input resistance Rin 14~19, 45~50pin When each selector chooses a terminal concerned. 25 50 100 kΩ Maximum output voltage Pass gain VOM THD=1%, RL=10kohm Output Gain Contro=+10dB setting Vi=0.3Vrms, FLAT 3.6 4.2 — Vrms -2.0 0 2.0 dB BW: 400Hz~30kHz, f=1kHz, Vo=0.3Vrms, RL=10kΩ BW: 400Hz~30kHz, f=1kHz, Vo=2Vrms, RL=10kΩ — 0.005 0.05 % — 0.03 0.1 % Input Pin71,73/Output Pin39,32 Vi=0.3Vrms, JIS-A JIS-A, Rg=0ohm Volume=-∞dB setting -0.5 0 0.5 dB — 2 6 µVrms JIS-A, Rg=0ohm Volume=0dB setting Output Pin 7, 8, 10, 11 JIS-A, Rg=0Ω — 4 12 µVrms — 5 10 µVrms CS1 (Input selector) Pin73~80, Pin71~64 Vo=0.5Vrms, Rg=0Ω, RL=10kΩ, JIS-A — -80 -65 dB CS2 (Multi channel/external input selector) Pin51~44, Pin13~20, Pin54,55 Vo=0.5Vrms, Rg=0Ω, RL=10kΩ, JIS-A (Main line) Input Pin71,73/Output Pin32,39 Vo=0.5Vrms, Rg=0Ω, RL=10kΩ, JIS-A (Sub line) Input Pin71,73/Output Pin62,61 Vo=0.5Vrms, Rg=0Ω, RL=10kΩ, JIS-A — -80 -65 dB — -80 -65 dB — -80 -65 dB Total harmonic distortion Gv THD1 THD2 Channels balance CBAL Output noise voltage Vono (VOL=-∞dB) Vono (VOL=0dB) Vonobal (Balance out) Input selector channel separation Crosstalk of mutual channels CT1 CT2 Rev.1.0, Sep.19.2003, page 13 of 17 M61522FP (3) 8 channel Volume characteristics Unless otherwise noted, Output Gain Control=0dB setting Limits Parameter Symbol Test condition min typ max Unit Maximum attenuation ATTmax Vi=1Vrms, JIS-A, VOL=-∞ — -100 -95 dB Volume gain gang error of mutual channels Dvol Pin32,33,34,35,36,37,38,39 Output, Volume=0dB setting -0.5 0 +0.5 dB Cross talk of mutual channels CTvol Vo=0.5Vrms, RL=10k Ω, JIS-A, Rg=0 Ω — -80 -65 dB Rev.1.0, Sep.19.2003, page 14 of 17 73 74 75 76 77 78 79 80 71 70 69 68 67 66 65 64 INLA INLB INLC INLD INLE INLF INLG INLH INRA INRB INRC INRD INRE INRF INRG INRH 4 5 Rev.1.0, Sep.19.2003, page 15 of 17 63 ROUT 3 6 RECL4 RECL3 RECL2 RECL1 MAI N R RECR4 RECR3 RECR2 RECR1 SBRIN1 SBRIN2 FRIN1 FRIN2 SRIN1 SRIN2 23 44 20 45 19 FRch VolumeInputSelector 41 SBRch Volume InputSelector 18 SRch Volume InputSelector 46 42 22 SLch Volume InputSelector 50 14 47 17 55 49 15 54 48 16 51 13 FLch VolumeInputSelector SWch Volume InputSelector SLIN1 SLIN2 SWIN1 SWIN2 (External INB) SBLIN1 SBLIN2 SBLIN3 (External INA) FLIN1 FLIN2 CIN1 CIN2 CIN3 Input ATT 0/-3/-6/-9/-12dB SBLch Volume InputSelector 60 59 58 57 Input ATT 11 8 7 0/-3/-6/-9/-12dB R+ L- L+ 10 R- 0~-99dB 0~-99dB 0~-99dB 0~-99dB 0~-99dB 0~-99dB 0~-99dB 0~-99dB BALANCE OUTPUT Cch Volume InputSelector SUB R MAI N L SUB L 62 LOUT FLOUT MCU I/F 25 COUT SWOUT SLOUT SROUT SBROUT FROUT 0/+3/+6/+9/+10/+12dB Output Gain Control 39 0/+3/+6/+9/+10/+12dB Output Gain Control 38 0/+3/+6/+9/+10/+12dB Output Gain Control 37 0/+3/+6/+9/+10/+12dB Output Gain Control 33 0/+3/+6/+9/+10/+12dB Output Gain Control 36 30 SBLOUT 0/+3/+6/+9/+10/+12dB Output Gain Control 33 0/+3/+6/+9/+10/+12dB Output Gain Control 35 0/+3/+6/+9/+10/+12dB Output Gain Control 32 29 31 24 21 12 9 2 CLOCK 28 DATA 27 LA TCH 26 72 DVDD AV CC AV EE -7V DGND +3.3V +7V 63 56 53 52 43 40 1 NC GND M61522FP Internal Block Diagram M61522FP Application Example R SBRSR SW C SBL SL L MCU I/F 43 47k SBRIN2 26 27 DATA LATCH CLOCK Output Gain Control 42 RIN2 28 29 30 31 32 33 34 35 36 37 38 39 40 DGND 41 DVDD 3.3V MCU 25 AVCC 7V 24 23 22 Output Gain Control 21 44 FLchVOL 45 SRIN2 46 SWIN2 47 CIN2 20 FRchVOL RIN1 47k 19 SBRIN1 18 SRIN1 48 17 SWIN1 SBLIN2 49 16 CIN1 SLIN2 50 15 SBLIN1 51 14 SLIN1 52 13 53 12 LI N2 47k (External INA) SBLIN3 (External INB) FRch SBRchVOLSRchVOLSWchVOL CchVOL Output Gain Control Output Gain Control Output Gain Control Output Gain Control Output Gain Control SBLchVOL FLch SLchVOL 54 11 + 10 8 7 + Rch 55 56 RECR4 LI N1 47k - ADC - CIN3 Output Gain Control 9 Balance Out 57 InputATT Lch InputATT RECR3 58 RECR2 59 6 RECL4 RECR1 60 5 RECL3 ROUT 61 4 RECL2 LOUT 62 3 RECL1 INRH MAIN L SUB R MAIN R S UB L 63 2 64 1 NC 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 47k 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 47k 47k Rev.1.0, Sep.19.2003, page 16 of 17 INLH INLG INLF INLE INLD INLC INLB INLA INRA INRB INRC INRD INRE INRF INRG AVEE -7V y e b 40 x 41 24 65 64 25 HD D JEDEC Code — 1 80 EIAJ Package Code QFP80-P-1420-0.80 E M F Weight(g) 1.58 A Detail F Lead Material Alloy 42 L1 c L b2 I2 MD ME A A1 A2 b c D E e HD HE L L1 x y Dimension in Millimeters Min Nom Max — — 3.05 0.1 0.2 0 2.8 — — 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 — — 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 — — — — 0.2 0.1 — — 0˚ 10˚ — 0.5 — — 1.3 — — 14.6 — — — — 20.6 Recommended Mount Pad Symbol I2 MD Plastic 80pin 14✕20mm body QFP e b2 MMP A2 Rev.1.0, Sep.19.2003, page 17 of 17 A1 ME 80P6N-A M61522FP Package Dimensions HE Sales Strategic Planning Div. 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