BB501C Built in Biasing Circuit MOS FET IC UHF RF Amplifier REJ03G0830-0600 (Previous ADE-208-701D) Rev.6.00 Aug.10.2005 Features • Built in Biasing Circuit; To reduce using parts cost & PC board space. • High gain; PG = 21.5 dB typ. at f = 900 MHz • Low noise; NF = 1.85 dB typ. at f = 900 MHz • Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions. • Provide mini mold packages; CMPAK-4(SOT-343mod) Outline RENESAS Package code: PTSP0004ZA-A (Package name: CMPAK-4) 2 3 1 4 Notes: 1. Marking is “AS –”. 2. BB501C is individual type number of RENESAS BBFET. Rev.6.00 Aug 10, 2005 page 1 of 9 1. Source 2. Gate1 3. Gate2 4. Drain BB501C Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Symbol VDS VG1S Ratings 6 Unit V +6 –0 V Gate2 to source voltage VG2S V Drain current Channel power dissipation Channel temperature Storage temperature ID Pch Tch Tstg +6 –0 20 100 150 –55 to +150 mA mW °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) Min 6 +6 +6 — — 0.5 Typ — — — — — 0.7 Max — — — +100 +100 1.0 Unit V V V nA nA V VG2S(off) 0.5 0.7 1.0 V Drain current ID(op) 7 10 13 mA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 47 kΩ Forward transfer admittance |yfs| 19 24 29 mS Input capacitance Output capacitance Reverse transfer capacitance Power gain Noise figure Ciss Coss Crss PG NF 1.4 0.7 — 17 — 1.7 1.1 0.019 21.5 1.85 2.0 1.5 0.04 — 2.4 pF pF pF dB dB VDS = 5 V, VG1 = 5 V, VG2S =4 V RG = 47 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V VG2S =4 V, RG = 47 kΩ f = 1 MHz Gate2 to source cutoff voltage Rev.6.00 Aug 10, 2005 page 2 of 9 Test conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V ID = 100 µA VDS = 5 V, VG1S = 5 V ID = 100 µA VDS = 5 V, VG1 = 5 V VG2S =4 V, RG = 47 kΩ f = 900 MHz BB501C Main Characteristics 900MHz Power Gain, Noise Figure Test Circuit VD VG1 VG2 C6 C4 C5 R1 R2 C3 R3 RFC D G2 Output L3 L4 G1 Input S L1 L2 C1 C1, C2 : C3 : C4 to C6 : R1 : R2 : R3 : C2 Variable Capacitor (10pF MAX) Disk Capacitor (1000pF) Air Capacitor (1000pF) 47 kΩ 47 kΩ 4.7 kΩ L2 : L1 : 10 3 3 8 10 26 (φ1mm Copper wire) Unit : mm 21 L4 : 18 10 10 7 29 7 L3 : RFC : φ1mm Copper wire with enamel 4turns inside dia 6mm Rev.6.00 Aug 10, 2005 page 3 of 9 BB501C Typical Output Characteristics 20 200 VG2S = 4 V VG1 = VDS Drain Current ID (mA) Channel Power Dissipation Pch (mW) Maximum Channel Power Dissipation Curve 150 100 50 0 50 100 150 16 = 8 3 4 5 16 Drain Current ID (mA) Drain Current ID (mA) 2 VDS = 5 V RG = 47 kΩ 4V 3V 2V 8 4 VG2S = 1 V 1 2 3 2V 4 12 4V 3V 2V 4 VG2S = 1 V 3 4 Gate1 Voltage VG1 (V) Rev.6.00 Aug 10, 2005 page 4 of 9 5 Forward Transfer Admittance |yfs| (mS) VDS = 5 V RG = 68 kΩ 2 1 2 3 4 5 Forward Transfer Admittance vs. Gate1 Voltage 20 1 VG2S = 1 V Gate1 Voltage VG1 (V) Drain Current vs. Gate1 Voltage 8 4V 3V 8 0 5 4 12 Gate1 Voltage VG1 (V) Drain Current ID (mA) 1 kΩ 20 VDS = 5 V RG = 33 kΩ 12 0 100 Drain Current vs. Gate1 Voltage 20 16 kΩ 27 Ω k 33 k Ω 9 3 Ω k 47 k Ω 56 k Ω 68 k Ω 82 Drain to Source Voltage VDS (V) Drain Current vs. Gate1 Voltage 0 kΩ 4 Ambient Temperature Ta (°C) 16 RG 12 0 200 22 30 24 VDS = 5 V RG = 33 kΩ f = 1 kHz 4V 3V 18 2V 12 6 VG2S = 1 V 0 1 2 3 4 Gate1 Voltage VG1 (V) 5 BB501C Forward Transfer Admittance vs. Gate1 Voltage 30 VDS = 5 V RG = 47 kΩ f = 1 kHz 24 4V 3V 18 2V 12 6 VG2S = 1 V 0 1 2 3 4 5 Forward Transfer Admittance |yfs| (mS) Forward Transfer Admittance |yfs| (mS) Forward Transfer Admittance vs. Gate1 Voltage VDS = 5 V RG = 68 kΩ f = 1 kHz 24 4V 3V 18 2V 12 6 VG2S = 1 V 0 1 2 3 4 5 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Power Gain vs. Gate Resistance Noise Figure vs. Gate Resistance 30 4 25 Noise Figure NF (dB) Power Gain PG (dB) 30 20 15 10 5 VDS = VG1 = 5 V VG2S = 4 V f = 900 MHz 0 10 50 20 3 2 1 0 10 100 VDS = VG1 = 5 V VG2S = 4 V f = 900 MHz 20 50 100 Gate Resistance RG (kΩ) Gate Resistance RG (kΩ) Power Gain vs. Drain Current Noise Figure vs. Drain Current 4 30 Noise Figure NF (dB) Power Gain PG (dB) 25 20 15 10 5 0 0 VDS = VG1 = 5 V VG2S = 4 V RG = variable f = 900 MHz 3 2 0 5 10 15 Drain Current ID (mA) Rev.6.00 Aug 10, 2005 page 5 of 9 20 VDS = VG1 = 5 V VG2S = 4 V RG = variable f = 900 MHz 1 0 5 10 15 Drain Current ID (mA) 20 BB501C Power Gain vs. Gate2 to Source Voltage Drain Current vs. Gate Resistance 25 Power Gain PG (dB) Drain Current ID (mA) 20 15 10 VDS = VG1 = 5 V VG2S = 4 V 5 0 10 50 20 20 15 10 VDS = 5 V RG = 47 kΩ f = 900 MHz 5 0 1 100 Noise Figure vs. Gate2 to Source Voltage Input Capacitance vs. Gate2 to Source Voltage 4 Input Capacitance Ciss (pF) Noise Figure NF (dB) 5 VDS = 5 V RG = 47 kΩ f = 900 MHz 4 3 2 1 1 2 4 3 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage 0 Gain Reduction GR (dB) 4 3 Gate2 to Source Voltage VG2S (V) Gate Resistance RG (kΩ) 10 20 30 VDS = VG1 = 5 V VG2S = 4 V RG = 47 kΩ 40 50 2 4 3 2 1 Gate2 to Source Voltage VG2S (V) Rev.6.00 Aug 10, 2005 page 6 of 9 0 3 2 VDS = 5 V RG = 47 kΩ f = 1 MHz 1 0 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) BB501C S21 Parameter vs. Frequency S11 Parameter vs. Frequency .8 1 Scale: 1 / div. 90 1.5 .6 60° 120° 2 .4 3 30° 150° 4 5 .2 10 .2 0 .4 .6 .8 1 1.5 2 3 45 10 180° 0° –10 –5 –4 –.2 –.4 –30° –150° –3 –2 –.6 –.8 –1 –90° Test Condition: VDS = 5 V , VG1 = 5 V VG2S = 4 V , RG = 47 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) Test Condition: VDS = 5 V , VG1 = 5 V VG2S = 4 V , RG = 47 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) S12 Parameter vs. Frequency 90° S22 Parameter vs. Frequency Scale: 0.002 / div. .8 60° 120° –60° –120° –1.5 1 .6 1.5 2 .4 3 30° 150° 4 5 .2 10 180° 0° .2 0 .4 .6 .8 1 1.5 2 3 45 10 –10 –5 –4 –.2 –30° –150° –3 –.4 –60° –120° –90° Test Condition: VDS = 5 V , VG1 = 5 V VG2S = 4 V , RG = 47 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) Rev.6.00 Aug 10, 2005 page 7 of 9 –2 –.6 –.8 –1 –1.5 Test Condition: VDS = 5 V , VG1 = 5 V VG2S = 4 V , RG = 47 kΩ , Zo = 50Ω 50 to 1000 MHz (50 MHz step) BB501C S Parameter (VDS = VG1 = 5V, VG2S = 4V, RG = 47kΩ, Zo = 50Ω) S11 f(MHz) S21 S12 S22 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 MAG. 0.974 0.974 0.974 0.965 0.963 0.953 0.947 0.942 0.929 0.923 0.912 0.903 0.886 0.879 0.873 0.859 ANG. –2.8 –10.0 –13.6 –16.5 –20.0 –23.7 –26.8 –29.6 –32.8 –35.4 –38.5 –41.2 –44.2 –46.8 –49.2 –52.4 MAG. 2.40 2.38 2.38 2.37 2.35 2.32 2.30 2.28 2.26 2.21 2.19 2.15 2.12 2.08 2.06 2.03 ANG. 176.4 172.2 168.4 164.1 160.4 156.8 152.9 148.6 144.9 141.2 137.6 134.2 130.6 127.4 124.3 120.8 MAG. 0.00057 0.00144 0.00211 0.00316 0.00358 0.00431 0.00503 0.00545 0.00630 0.00646 0.00693 0.00732 0.00729 0.00733 0.00762 0.00756 ANG. 78.1 82.4 78.7 84.8 76.3 84.0 79.0 76.6 80.3 76.1 73.7 72.9 74.6 72.0 74.5 73.7 MAG. 0.997 0.998 0.997 0.995 0.994 0.992 0.990 0.987 0.984 0.981 0.977 0.974 0.971 0.967 0.962 0.959 ANG. –2.0 –4.2 –6.0 –8.1 –10.2 –12.2 –14.2 –16.2 –18.1 –20.2 –22.1 –24.1 –26.0 –27.8 –29.7 –31.7 850 900 950 1000 0.846 0.836 0.827 0.815 –55.4 –58.0 –60.4 –62.8 2.00 1.96 1.93 1.89 117.3 114.3 111.0 108.0 0.00772 0.00775 0.00801 0.00704 75.5 79.6 81.7 81.0 0.955 0.951 0.946 0.942 –33.6 –35.5 –37.3 –39.4 Rev.6.00 Aug 10, 2005 page 8 of 9 BB501C Package Dimensions JEITA Package Code RENESAS Code SC-82A Package Name PTSP0004ZA-A CMPAK-4(T) / CMPAK-4(T)V D MASS[Typ.] 0.006g A e2 e Q b1 c B B E HE LP Reference Symbol L A A x M L1 S A e2 A2 e l1 b5 S b c A A1 y S b2 A3 b e1 b1 b3 c1 c1 c A-A Section l1 b4 B-B Section Pattern of terminal position areas A A1 A2 A3 b b1 b2 b3 c c1 D E e e2 HE L L1 LP x y b4 b5 e1 l1 Q Dimension in Millimeters Min 0.8 0 0.8 0.25 0.35 0.1 1.8 1.15 1.8 0.3 0.1 0.2 Nom 0.9 0.25 0.32 0.42 0.3 0.4 0.13 0.11 2.0 1.25 0.65 0.6 2.1 Max 1.1 0.1 1.0 0.4 0.5 0.15 2.2 1.35 2.4 0.7 0.5 0.6 0.05 0.05 0.45 0.55 1.5 0.9 0.2 Ordering Information Part Name BB501CAS-TL-E Quantity 3000 Shipping Container φ 178 mm Reel, 8 mm Emboss Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.6.00 Aug 10, 2005 page 9 of 9 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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