APPLICATION NOTE - Skyworks Solutions, Inc.

APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Introduction
This application note details how to calculate a type III compensation network and investigates the relationship between
phase margin and load transient response for the Skyworks family of voltage mode control step-down converters. This
family includes the AAT1184, AAT1185, AAT1189, AAT2687, AAT2688, and AAT2689. Voltage mode control has become
a very popular topology for DC to DC converters, especially with low noise output systems including DSL and cable
modems, notebook computers, satellite set-top boxes, and wireless LAN systems.
Background
In order to reduce the DC-DC converter’s output voltage ripple, the equivalent series resistance (ESR) of the output
capacitor needs to be reduced. Ceramic output capacitors have a very small equivalent series resistance (ESR), low
cost, and small size, making them the ideal output filter solution for DC-to-DC converters. However, the use of low ESR
ceramic capacitors significantly affects the design of the error amplifier in the feedback loop. The power stage consists
of a double pole due to the L COUT filter and an ESR zero. The ESR zero is pushed far away from the double pole frequency which results in inadequate phase margin at the cross-over frequency. Therefore, type III compensation is used
to stabilize the loop and optimize the output transient response to dynamic load changes.
Voltage Mode Control Loop
As illustrated in Figure 1, a typical voltage mode control loop has three main stages: step-down power stage, compensation network, and PWM modulator. The Type III compensation network generates two zeros and two poles. The two
zeros are placed from 60% to 150% of double pole frequency to counter the 180° phase lag due to the L COUT output
filter. The two poles are set at the switching frequency of the converter to nullify the ESR zero and attenuate the high
frequency noise.
VIN
STEP-DOWN POWER STAGE
L
Driver
VOUT
RDCR
COUT
RESR
COMPENSATION NETWORK
PWM MODULATOR
Vreff
COMP
RAMP
COMPARATOR
ROUT
Error Amp
R1
C2
C1
Rfbh
Cff
Rff
Rfbl
Figure 1: Closed Loop Step-Down Converter with Type III Network Compensation.
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1
APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Step-Down Power Stage Transfer Function
The transfer function of the power stage of the step-down converter can be determined by the voltage division:
Eq. 1:
VOUT
ZOUT
=
VIN
ZL + ZOUT
Where ZL and ZOUT are the inductor impedance and output impedance of the power stage. The RDCR includes the DC
winding resistance, the turn-on resistance of the MOSFET, and the trace resistance. RESR is the equivalent series resistor of the output capacitor. ZL and ZOUT are calculated using Equations 2 and 3.
Eq. 2: ZOUT = RLOAD // RESR +
1
s · COUT · RLOAD · RESR + RLOAD
=
sCOUT
s · COUT · (RLOAD + RESR) + 1
Eq. 3: ZL = s · L + RDCR
Where the complex variable s = j · w and j =
-1
VIN
STEP-DOWN POWER STAGE
ZL
Driver
L
Z OUT
RDCR
VOUT
COUT
RESR
RLOAD
Figure 2: Step-Down Converter Power Stage.
The step-down power stage open loop gain is given by substituting Equations 2 and 3 into Equation 1. Algebraic
manipulation yields the following expression for the open-loop transfer function of the power stage:
Eq. 4: GP = VOUT =
VIN
RLOAD · (s · COUT · RESR + 1)
s2 · L · COUT · (RLOAD + RESR) + s{L + COUT · [RDCR(RLOAD + RESR) + RLOAD · RESR ]} + RLOAD + RDCR
A typical Bode plot of the step-down converter power stage is illustrated in Figure 3. A double pole at the cut-off frequency causes the gain to roll off with a -40dB/decade slope (blue) and the phase to exhibit a very sharp slope downward from 0 degree to -180 degree phase lag (red). The ESR zero is observed at a very high frequency due to the
ceramic output capacitor.
2
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APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Gain (dB) and Phase (degree)
Output Double Pole
at cut -off frequency
-40dB/dec
ESR zero at very
high frequency
-20dB/dec
-180 degree phase lag
due to double pole
Frequency (Hz)
Figure 3: The Bode Plot of the Output Stage.
Error Amplifier Transfer Function Calculation
The error amplifier transfer function with type III compensation as shown in Figure 4 is calculated from Equation 5:
Eq. 5: GE =
VCOMP
=
VOUT
1
1
// R1 +
s · C2
s · C1
Rfbh // Rff +
1
s · Cff
Z1
VREF
VCOMP
Rfbh
V OUT
Error Amp
R1
Cff
C1
P1
Rff
Z2
C2
Rfbl
P2
Figure 4: Error Amplifier With Type III Compensation Network.
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3
APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
By algebraic manipulation, GE can be explicitly expressed in terms of zeros and poles in Equation 6.
Eq. 6: GE =
Rfbh + Rff
·
Rfbh · Rff · C2
s+
1
1
· s+
R1 · C1
(Rfbh + Rff) · Cff
s· s+
(C1 + C2)
1
· s+
R1 · C1 · C2
Rff · Cff
Equation 6 gives two zeroes at frequencies FZ1 and FZ2 and two poles at frequencies FP1 and FP2 in the following expressions:
FZ1 =
1
1
and FZ2 =
2π · (Rfbh + Rff) · Cff
2π · R1 · C1
FP1 =
1
and FP2 =
2π · Rff · Cff
1
2π · R1 ·
C1 · C2
C1 + C2
Gain (dB) and Phase (degree)
180 degree phase boost
Placing the two zeros close
to the output double pole
frequency
Placing the two poles at
cross -over frequency
Figure 5: Error Amplifier With Type III Compensation Bode Plot.
Type III compensation provides two zeros and two poles which push the cross-over frequency as high as possible and
boosts the phase margin greater than 45 degree. A higher bandwidth yields a faster load transient response. The
faster transient response results in a smaller output voltage spike.
PWM Modulator Stage
The PWM modulator gain is inversely proportional to the peak-to-peak input ramp voltage of the oscillator and is derived
via Equation 7.
Eq. 7: GM =
4
VIN
VRAMP
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APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Step-Down Converter Loop Gain with Type III Compensation
The loop gain of the system is expressed in terms of GM, GE, and GP factors as shown in Equation 8.
Eq. 8: GLOOP = GM · GE · GP
The magnitude in dB and the phase in degree of the converter loop gain are derived from Equations 9 and 10.
Eq. 9: GLOOP (dB) = 20.log (GLOOP) = 20.log (GM · GE · GP)
Eq. 10: PLOOP = arg(GLOOP) ·
180
π
Gain (dB) and Phase (degree)
The magnitude and phase Bode plots of the converter loop gain with type III compensation are shown in Figure 5. By
placing the two zeros close to the output double pole and the two poles at switching frequency, the crossover frequency is pushed to 10% to 60% of switching frequency and in the vicinity of maximum phase boost in order to achieve
an optimum phase margin ΦM.
Placing the two zeros close
to the output double pole
frequency
ΦM
Output Double Pole
Cross-Over
Frequency at 1/10
Switching Frequency
Figure 6: Step-Down Converter Loop Gain With Type III Compensation Bode Plot .
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5
APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Type III Compensation Design Process
For Voltage Mode Control Step-Down Converter:
For example, assume the voltage mode step-down converter has the following specifications:
VIN = 6V to 24V
VOUT = 3.3V
RFBL = 6.04KΩ, RFBH = RFBL ·
VRAMP =
VOUT - VREF
3.3V - 0.6V
= 6.04K ·
= 27.4KΩ
VREF
0.6V
VIN
12
L = 4.7µH
COUT = 2x22µF, ESR = 2mΩ
IOUT = 2.5A
FSW = 490KHz
1. Set the crossover frequency in the range of 1/6 to 1/10 of switching frequency to avoid the Niquist pole:
Eq. 11: FC =
FSW
= 49KHz
10
2. Place the first zero from 60% to 150% of the double pole frequency of the L COUT filter:
Eq. 12: Cff =
L · COUT
4.7µH · 44µF
=
= 481pF
K · Rfbh
1.1 · 27.4KΩ
Where the value of factor K is within the range of 0.6 to 1.5.
3. Set the first pole at switching frequency and calculate Rff from:
Eq. 13: Rff =
1
1
=
= 675Ω
2π · Cff · FSW
2π · 481pF · 490KHz
4. At cross-over frequency (FC) the loop gain is unity. Setting |GLOOP|= 1 at s = jwc, the value of R1 is given by Equation
14.
Eq. 14: R1 =
(2π · FC)2 · L · COUT + 1 VRAMP
(2π · 49KHz)2 · 4.7µH · 44µF
·
=
= 11.6KΩ
VIN
2π · FC · Cff
2π · 49KHz · 481pF
5. Set the second zero to coincide with the first zero, and solve for C1:
Eq. 15: C1 =
L · COUT
4.7µH · 44µF
=
= 112pF
K · R1
1.1 · 11.6KΩ
6. Place the second pole from switching frequency to one decay higher for adequate phase margin, and solve for C2:
Eq. 16: C2 =
6
1
1
=
= 28pF
2π · R1 · FSW
2π · 11.6KΩ · 490KHz
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APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
The Relationship between Frequency Domain
and Time Domain in a Step-Down Converter
Knowing the relationship between the phase margin in the frequency domain and load transient response in time
domain is beneficial to achieving the best results. In this way, we can select either a slow output transient response
but without any overshoot or, a faster output transient response with a small amount of overshoot. Let’s concentrate
on the small area in the vicinity of the cross over frequency (see Figure 7). The curve has two different slopes (-20dB/
decade and -40dB/ decade) due to the location of the original pole w0 and the high frequency pole w2. Assuming the
other compensation pole w1 and the ESR zero are cancelled out. The open loop transfer function in this region can be
approximated by Equation 17:
1
Eq. 17: T(s) ≈
s
s
1+
ω0
ω2
The close loop transfer function can derive from T(s):
Eq. 18: GLOOP (s) =
1
=
1 + T(s)
1
s
s
+1
+
ω0 · ω 2 ω 0
2
=
1
s
s
+1
+
2
ωr
ωr · Q
2
Where the quality coefficient Q and the resonant frequency wr are defined using Equations 19 and 20.
Eq. 19: Q =
ω0
ω2
Eq. 20: ωr =
ω0ω2
The cross-over frequency wc can be solved by equating Equation 18 to unity at the crossover frequency:
1+4
2
-1
= ω2
2
Gain (dB) and Phase (degree)
Eq. 21: ωc = ω2
ω0
ω2
1 + 4(Q) 2 - 1
2
Placing the two zeros close
to the output double pole
frequency
ΦM
Output Double Pole
Cross-Over
Frequency at 1/10
Switching Frequency
Figure 7: The Gain Curve Has Two Different Slopes (-20dB/decade and -40dB/decade) at Crossover
Frequency due to the Location of the Original Pole ω0 and the High Frequency Pole ω2.
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7
APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
ωC
ωC
-1 ω0
Eq. 22: arg T(ωC) = - tan
+ tan-1
ω2
0
Eq. 23: ϕM = π + arg T(ωC) = tan
-1
= -tan-1
ω2
= tan-1
ωC
ωC π
ω2 2
2
1 + 4Q4 - 1
The relationship between the phase margin and the quality coefficient can be derived from Equation 23:
Eq. 24: Q =
1 + tan(ϕM)2
tan(ϕM)
cos(ϕM)
=
sin(ϕM)
The percent overshoot and quality factor in the second order system are given by Equation 25.
Eq. 25: %OS = 100 · e
-π
4Q2 - 1
= 100 · e
-π
4cosϕM
-1
sin2ϕM
Figure 8 plots the percent overshoot versus phase margin of a typical second order system.
Percent Overshoot vs. Phase Margin
80
Pecent Overshoot (%)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
Phase Margin (degree)
Figure 8: Percent Overshoot vs. Phase Margin for Second Order System.
The output transient response of a 3.3V output step-down converter with different phase margin is measured in Figure
9. The step load is generated from 200mA to 2.5A with 2A/µs slew rate. The red curve corresponding to 68° phase
margin has 160µs recovery time without overshoot and a transient voltage spike of 404mV. The black and green curves
experience very fast recovery time (40µs) with very small overshoot and a small transient voltage spike of 280mV.
Finally, the blue and pink curves reveal an unstable system due to the phase margin of less than 45°.
8
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APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
3.6V
PM=68º
PM=58º
PM=48º
PM=33º
PM=26º
Output Voltage (100mV/div)
3.5V
3.4V
3.3V
3.2V
3.1V
3.0V
Time (40µs/div)
Figure 9: The Relationship Between Phase Margin, Overshoot and Recovery Time
of the Output Transient Response of a 3.3V Output Buck Converter.
Phase Margin and Transient Response vs. DC Gain (FC = 50KHz)
Based on the discussion above of the frequency domain and time domain, the recovery time can be adjusted faster to
reduce the peak-to-peak output transient response of a step-down converter. This can be done by pushing the zeros a
bit above the double poles frequency (K = 1.1) in order to boost the DC gain from 65dB to 75dB. Figure 10 illustrates
the relationship between the phase margin and load transient response for K = 0.6 and K = 1.1 at the same crossover
frequency of 50KHz. A higher DC gain along with a smaller phase margin of 58° yields a faster recovery time of 60µs,
which results in a smaller peak-to-peak output transient response (280mV) for a 200mA to 2.5A dynamic load.
Frequency Domain
Time Domain
tr=140 us
K=0.6
= 1nF
VPP =404mV Cff
Rff = 365Ω
PM=68º
DC Gain = 65dB
R1 = 3.34kΩ
C1 = 3300pF
C2 = 47pF
2.5A
200mA
Fco =50KHz
Time (40μs/div)
Frequency (Hz)
tr=60us
K=1.1
DC Gain = 75dB
PM=58º
VPP =280mV
2.5A
Fco =50KHz
Frequency (Hz)
Cff = 470pF
Rff = 681Ω
R1 = 11.5kΩ
C1 = 1nF
C2 = 27pF
200 mA
Time (40μs/div)
Figure 10: Phase Margin and Transient Response For Differing K Factors (K = 0.6 and K = 1.1).
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APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Phase Margin and Transient Response vs. Bandwidth (K = 1.1)
As illustrated in Figure 11, the output voltage spike can be further improved by pushing the crossover frequency (FC)
to 80KHz if a small amount of overshoot is acceptable. However, further increasing the bandwidth reduces the phase
margin below 45°, resulting in an unstable system. In addition, increasing the bandwidth to exceed the effective control
bandwidth no longer reduces the output voltage spike due to the voltage drop across the ESR of the output capacitor
which dominates the transient voltage spike.
For a 3.3V output voltage buck converter using a 4.7µH inductor during a load transient step from 200mA to 2.5A, the
effective control bandwidth is derived from Equation 26.
Eq. 26: FCE =
VO
3.3V
=
= 76KHz
4 · ∆IO · L 4 · 2.5A · 4.7µH
Frequency Domain
Time Domain
K=1.1
K=1.1
PM=58º
VPP =280mV
2.5A
Fco =50KHz
Cff = 470pF
Rff = 681Ω
R1 = 11.5kΩ
C1 = 1nF
C2 = 27pF
200mA
Frequency (Hz)
Time (40μs/div)
K=1.1
K=1.1
VPP = 266mV
PM=55º
2.5A
Fco =80KHz
Frequency (Hz)
Cff = 470pF
Rff = 681Ω
R1 = 18.7kΩ
C1 = 680pF
C2 = 18pF
200mA
Time (40μs/div)
Figure 11: Frequency Domain vs. Time Domain For Different Bandwidth (FCO = 50KHz and FCO = 80KHz).
10
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APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Loop Gain Measurement
The following guidelines show the method used to measure the loop gain of a DC-DC converter:
1. Break the feedback loop and insert a 50Ω resistor between the broken original connection. Insert the secondary
winding terminal of the one-to-one isolation transformer between the 50Ω resistor. Configure the specified test
equipment as shown in Figure 11.
2. Inject a sinusoidal signal from SOURCE OUT of the network analyzer to the loop through the primary winding terminal of the transformer while monitoring the ratio of CHA and CHB on the network analyzer.
3. Set the converter output current to heavy load while monitoring the LX node of the converter on the oscilloscope
(to obtain a good result the converter must be in continuous PWM mode).
4. Sweep the frequency from SOURCE OUT of the network analyzer from 10Hz to 1MHz and adjust the magnitude of
the injected signal (around 10mV to 100mV) in order to have a clean PWM waveform at the LX node.
Analog Network Analyzer
Oscilloscope
SOURCE OUT
CHA
CHB
LOAD
Power Supply
12V
2A
5A
L1
4.7µH
50
Broken
Original
Connection
LX
VIN
VIN
CIN
Isolation
Transformer
Buck
Converter
Rfbh
VOUT
Rff
Cff
FB
COUT
Rfbl
PGND
Figure 12: Loop Gain Measurement Set-up.
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11
APPLICATION NOTE
Design Type III Compensation Network For Voltage Mode Step-down Converters
Conclusion
Using low ESR ceramic output capacitors for voltage mode controlled buck converters yields very low output voltage
ripple, but requires type III compensation for adequate phase margin. The type III compensation network provides two
zeros and two poles that push the crossover frequency to a possible maximum value with adequate phase margin for
the control loop. The trade-off between the stability and output transient response can be adjusted by using the factor
K, which represents the position of zeros in the vicinity frequency of the output double poles. In applications which
require no overshoot, the two zeros are placed at 60% (K = 0.6) of the output double poles frequency to achieve
approximately 70 degrees of phase margin. However, if the transient output voltage spike is critical, the two zeros can
be placed up to 150% (K = 1.5) of the output double pole frequency if a small amount of overshoot is acceptable. In
addition, a higher bandwidth yields a faster transient response. However, a bandwidth higher than the critical bandwidth
can no longer reduce the transient output voltage spike. A typical bandwidth for type III compensation is in the range
of 10% to 60% of switching frequency.
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