AS5263 Datasheet

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Datasheet
AS5263
1 2 - B i t R e d u n d a n t A u t o m o t iv e A n g l e P o s i t i o n S e n s o r
1 General Description
2 Key Features
360º contactless high resolution angular position encoding
The AS5263 is a contactless magnetic angle position sensor for
accurate angular measurement over a full turn of 360º. A sub range
can be programmed to achieve the best resolution for the
application. The AS5263 includes two AS5163 in one QFN package.
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User programmable start and end point of the application region
User programmable clamping levels and programming of the
transition point
It is a system-on-chip, combining integrated Hall elements, analog
front-end, digital signal processing and best in class automotive
protection features in a single device.
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Powerful analog output
- Short circuit monitor
- High driving capability for resistive and capacitive loads
Wide temperature range: -40ºC to +150ºC
To measure the angle, only a simple two-pole magnet, rotating over
the center of the chip, is required. The magnet may be placed above
or below the IC.
Small Pb-free package: 32-pin QFN (7x7mm)
The absolute angle measurement provides instant indication of the
magnet’s angular position with a resolution of 0.087º = 4096
positions per revolution. The start and end point of the sub segment
will be programmed with a resolution of 14-bit (0.022º= 16384 steps
per revolution). According to this resolution the adjustment of the
application specific mechanical positions are possible. The angular
output data is available over a 12-bit PWM signal or 12-bit ratiometric
analog output.
Broken GND and VDD detection over a wide range of different
load conditions
Simplified programming due to provided programming hardware
and software
Failure detection mode for magnet placement monitoring and
loss of power supply
Indication of high voltage condition
An internal voltage regulator with over voltage protection and reverse
polarity protection allows the AS5263 to operate in automotive
application up to a voltage to 27V. Programmability over the output
pin reduces the number of pins on the application connector. The
AS5263 is the ideal solution for safety critical applications due to the
redundant approach.
3 Applications
The AS5263 is ideal for automotive applications like transmission
gearbox position sensor, headlight position control, torque sensing,
valve position sensing, pedal position sensing, throttle position
sensing, and non-contact potentiometers.
Figure 1. AS5263 Block Diagram
VDD5_B
VDD_T
High voltage/
Reverse polarity
protection
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VDD_B
VDD3_T
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VDD5_T
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Hall Array
Frontend
Amplifier
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VDD3_B
OTP
Register
AS5263
Single pin
Interface
Zero
Position
Full Turn Output
Sin
Cos
CORDIC
Angle
14-bit
ADC
Output
DSP
12
M
U
X
12-bit
PWM
12-bit
DAC
OUT
Driver
Programmable
Angle
OUT_T
OUT_B
KDOWN_T
KDOWN_B
Top Silicon Die
Bottom Silicon Die
GND_T GND_B
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_T …… Pin of the Top Device
_B …… Pin of the Bottom Device
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AS5263
Datasheet - C o n t e n t s
Contents
1
2 Key Features.............................................................................................................................................................................
1
3 Applications...............................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
3
4.1 Pin Descriptions....................................................................................................................................................................................
3
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1 General Description ..................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
5
6 Electrical Characteristics...........................................................................................................................................................
6
6.1 Operating Conditions............................................................................................................................................................................
6
6.2 Magnetic Input Specification.................................................................................................................................................................
6
7
7
7 Detailed Description..................................................................................................................................................................
8
7.1 Operation..............................................................................................................................................................................................
9
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6.3 Electrical System Specifications...........................................................................................................................................................
6.4 Timing Characteristics ..........................................................................................................................................................................
7.1.1 VDD Voltage Monitor ................................................................................................................................................................... 9
7.2 Analog Output.....................................................................................................................................................................................
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
Programming Parameters..........................................................................................................................................................
Application Specific Angular Range Programming ....................................................................................................................
Application Specific Programming of the Break Point ...............................................................................................................
Full Scale Mode .........................................................................................................................................................................
Inverted Dual Channel Output ...................................................................................................................................................
Resolution of the Parameters ....................................................................................................................................................
Analog Output Diagnostic Mode ................................................................................................................................................
Analog Output Driver Parameters..............................................................................................................................................
10
10
10
11
11
12
12
14
14
7.3 Pulse Width Modulation (PWM) Output..............................................................................................................................................
15
7.4 Kick Down Function............................................................................................................................................................................
16
8 Application Information ...........................................................................................................................................................
8.1 Programming the AS5263 ..................................................................................................................................................................
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8.1.1 Hardware Setup.........................................................................................................................................................................
8.1.2 Protocol Timing and Commands of Single Pin Interface ...........................................................................................................
8.1.3 UNBLOCK .................................................................................................................................................................................
8.1.4 WRITE128 .................................................................................................................................................................................
8.1.5 READ128...................................................................................................................................................................................
8.1.6 DOWNLOAD..............................................................................................................................................................................
8.1.7 UPLOAD ....................................................................................................................................................................................
8.1.8 FUSE .........................................................................................................................................................................................
8.1.9 PASS2FUNC .............................................................................................................................................................................
8.1.10 READ.......................................................................................................................................................................................
8.1.11 WRITE .....................................................................................................................................................................................
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8.2 OTP Programming Data .....................................................................................................................................................................
8.2.1
8.2.2
8.2.3
8.2.4
Read / Write User Data..............................................................................................................................................................
Programming Procedure............................................................................................................................................................
Physical Placement of the Magnet ............................................................................................................................................
Magnet Placement.....................................................................................................................................................................
18
18
18
19
21
22
23
24
24
24
25
25
26
27
32
32
33
33
9 Package Drawings and Markings ...........................................................................................................................................
34
10 Ordering Information.............................................................................................................................................................
36
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AS5263
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
NC
2
NC_T
3
NC_B
4
VDD3_T
5
VDD3_B
6
GNDA_T
7
GNDA_B
8
VDD5_T
VDD_B
VDD_T
OUT_B
OUT_T
NC_B
NC_T
31
30
29
28
27
26
25
24
GNDP_B
23
GNDP_T
22
KDOWN_B
21
KDOWN_T
20
NC_B
19
NC_T
18
NC
17
NC
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32
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NC
VDD5_B
Figure 2. Pin Assignments (Top View)
9
10
11
12
13
14
15
16
NC_T
NC_B
NC
NC
GNDD_T
GNDD_B
NC_T
NC_B
AS5263
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number
Pin Name
Pin Type
Description
NC
-
Not bonded
NC
-
Not bonded
NC_T
DIO/AIO
multi purpose pin
3
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Table 1 provides the description of each pin of the standard 32-pin QFN (7x7mm) package. It is recommended to keep the electrical separation
as well on the printed circuit board (PCB) in the application (see Table 1).
4
NC_B
5
VDD3_T
6
VDD3_B
7
GNDA_T
Analog ground pin. Connected to GND for the top die in the application.
8
GNDA_B
Analog ground pin. Connected to GND intended for the bottom die in the
application.
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Test pin for fabrication. Connected to top ground in the application.
Test pin for fabrication. Connected to bottom ground in the application.
3.45V- Regulator output, internally regulated from VDD5. This pin
needs an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the top die.
Supply pin
3.45V- Regulator output, internally regulated from VDD5. This pin
needs an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the bottom die.
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AS5263
Datasheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Number
Pin Name
Pin Type
Description
9
NC_T
10
NC_B
11
NC
Test pin for fabrication. Open in the application.
12
NC
Test pin for fabrication. Open in the application.
13
GNDD_T
Test pin for fabrication. Connected to GND intended for the top die in
the application.
Supply pin
Test pin for fabrication. Connected to GND intended for the bottom die
in the application.
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DIO/AIO
multi purpose pin
Digital ground pin. Connected to GND intended for the top die in the
application.
Digital ground pin. Connected to GND intended for the bottom die in the
application.
GNDD_B
15
NC_T
16
NC_B
17
NC
-
Not bonded
NC
-
Not bonded
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14
18
19
NC_T
20
NC_B
21
KDOWN_T
22
KDOWN_B
23
GNDP_T
GNDP_B
25
NC_T
26
NC_B
DIO/AIO
multi purpose pin
Digital output open
drain
OUT_T
Test pin for fabrication. Connected to GND intended for the bottom die
in the application.
Test pin for fabrication. Connected to GND intended for the top die in
the application.
Test pin for fabrication. Connected to GND intended for the bottom die
in the application.
Kick down functionality. Open drain user pull-up resistor connected to
the intended VDD top supply.
Kick down functionality. Open drain user pull-up resistor connected to
the intended VDD bottom supply.
Analog ground pin. Connected to GND intended for the bottom die in the
application.
Test pin for fabrication. Connected to GND intended for the top die in
the application.
DIO/AIO
multi purpose pin
Test pin for fabrication. Connected to GND intended for the bottom die
in the application.
Output pin. Can be programmed as analog output or PWM output. Over
this pin the programming of the top die is possible.
29
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27
Test pin for fabrication. Connected to GND intended for the top die in
the application.
Analog ground pin. Connected to GND for the top die in the application.
Supply pin
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24
DIO/AIO
multi purpose pin
VDD_T
Positive supply pin. This pin is over voltage protected.
30
VDD_B
Positive supply pin. This pin is over voltage protected.
31
VDD5_T
4.5V- Regulator output, internally regulated from VDD. This pin needs
an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the top die.
OUT_B
Output pin. Can be programmed as analog output or PWM output. Over
this pin the programming of the bottom die is possible.
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32
VDD5_B
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Supply pin
4.5V- Regulator output, internally regulated from VDD. This pin needs
an external ceramic capacitor of 2.2μF. Connect second terminal of
capacitor to GND intended for the bottom die.
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AS5263
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
Comments
VDD
DC supply voltage at pin VDD
Overvoltage
-18
27
V
No operation
VOUT
Output voltage OUT
-0.3
27
V
VKDOWN
Output voltage KDOWN
-0.3
27
V
VDD3
DC supply voltage at pin VDD3
-0.3
5
V
VDD5
DC supply voltage at pin VDD5
-0.3
7
V
Iscr
Input current (latchup immunity)
-100
100
mA
Norm: JEDEC 78
±4
kV
Norm: MIL 883 E method 3015
This value is applicable to pins VDD, GND, OUT,
and KDOWN.
All other pins ±2 kV.
+150
ºC
Min -67ºF; Max +257ºF
260
ºC
t=20 to 40s,
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
85
%
Electrostatic Discharge
Electrostatic discharge
ESD
permanent
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Electrical Parameters
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Symbol
Temperature Ranges and Storage Conditions
Storage temperature
Tstrg
Body temperature (Lead-free package)
H
Humidity non-condensing
MSL
Moisture Sensitive Level
5
3
Represents a maximum floor life time of 168h
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TBody
-55
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AS5263
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
6.1 Operating Conditions
In this specification, all the defined tolerances for external components need to be assured over the whole operation conditions range and also
over lifetime.
Parameter
Conditions
Min
TAMB
Ambient temperature
-40ºF…+302ºF
-40
Isupp
Supply current
Lowest magnetic input field
Typ
Max
Units
+150
ºC
20
mA
Max
Units
70
mT
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Symbol
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TAMB = -40 to +150ºC, VDD = +4.5V to +5.5V, CLREG5 = 2.2µF, CLREG3 = 2.2µF, RPU = 1KΩ, RPD = 1KΩ to 5.6KΩ (Analog only),
CLOAD = 0 to 42nF, RPUKDWN = 1KΩ to 5.6KΩ, CLOAD_KDWN = 0 to 42nF, unless otherwise specified. A positive current is intended to flow into
the pin.
Table 3. Operating Conditions
6.2 Magnetic Input Specification
TAMB = -40 to +150ºC, VDD5 = 4.5 - 5.5V (5V operation), unless otherwise noted.
Two-pole cylindrical diametrically magnetized source:
Table 4. Magnetic Input Specification
Parameter
Conditions
Min
Typ
Bpk
Magnetic input field amplitude
Required vertical component of the
magnetic field strength on the die’s surface,
measured along a concentric circle with a
radius of 1.1mm
30
Boff
Magnetic offset
Constant magnetic stray field
±10
mT
Field non-linearity
Including offset gradient
5
%
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Symbol
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AS5263
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.3 Electrical System Specifications
TAMB = -40ºC to +150ºC, VDD = 4.5V - 5.5V (5V operation), Magnetic Input Specification; unless otherwise noted.
Table 5. Electrical System Specifications
Parameter
Conditions
RES
Resolution Analog and PWM Output
INLopt
INLtemp
Min
Typ
Max
Units
Angular operating range ≥ 90ºC
12
bit
Integral non-linearity (optimum)
360 degree full turn
Maximum error with respect to the best line fit.
Centered magnet without calibration,
TAMB=25ºC
±0.5
deg
Integral non-linearity (optimum)
360 degree full turn
Maximum error with respect to the best line fit.
Centered magnet without calibration,
TAMB = -40 to +150ºC
±0.9
deg
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Symbol
±1.4
deg
TN
Transition noise
1 sigma;
Note: The noise performance is dependent
on the programming of the output
characteristic.
0.06
Deg
RMS
VDD5LowTH
Undervoltage lower threshold
VDD5HighTH
Undervoltage higher threshold
INL
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Integral non-linearity
360 degree full turn
Best line fit = (Errmax – Errmin) / 2
Over displacement tolerance with 6mm
diameter magnet, without calibration,
TAMB = -40 to +150ºC
Note: This parameter is a system parameter
and is dependent on the selected magnet.
tPwrUp
Power-up time
tdelay
System propagation delay
absolute output: delay of ADC,
DSP and absolute interface
VDD5 = 5V
3.1
3.4
3.7
3.6
3.9
4.2
Fast mode, times 2 in slow mode
V
10
ms
100
µs
Note: The INL performance is specified over the full turn of 360 degrees. An operation in an angle segment increases the accuracy. A two
point linearization is recommended to achieve the best INL performance for the chosen angle segment.
6.4 Timing Characteristics
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Table 6. Timing Conditions
Symbol
Parameter
Internal Master Clock
TCLK
Interface Clock Time
TCLK = 1/ FRCOT
WatchDog error detection time
Min
Typ
Max
Units
4.05
4.5
4.95
MHz
202
222.2
247
ns
12
ms
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FRCOT
Conditions
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The AS5263 is manufactured in a CMOS process and uses a spinning current Hall technology for sensing the magnetic field distribution across
the surface of the chip.
The integrated Hall elements are placed around the center of the device and deliver a voltage representation of the magnetic field at the surface
of the IC.
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Through Sigma-Delta Analog / Digital Conversion and Digital Signal-Processing (DSP) algorithms, the AS5263 provides accurate high-resolution
absolute angular position information. For this purpose a Coordinate Rotation Digital Computer (CORDIC) calculates the angle and the
magnitude of the Hall array signals.
The DSP is also used to provide digital information at the outputs that indicate movements of the used magnet towards or away from the device’s
surface.
A small low cost diametrically magnetized (two-pole) standard magnet provides the angular position information (see Figure 26).
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The AS5263 senses the orientation of the magnetic field and calculates a 14-bit binary code. This code is mapped to a programmable output
characteristic. The type of output is programmable and can be selected as PWM or analog output. This signal is available at the pins 27, 28
(OUT_T, OUT_B).
The analog output and PWM output can be configured in many ways. The application angular region can be programmed in a user friendly way.
The starting angle T1 and the end point angle T2 can be set and programmed according the mechanical range of the application with a
resolution of 14 bits. In addition the T1Y and T2Y parameter can be set and programmed according the application. The transition point 0 to 360
degree can be shifted using the break point parameter BP. This point is programmable with a high resolution of 14 bits of 360 degrees. The
voltage for clamping level low CLL and clamping level high CLH can be programmed with a resolution of 7 bits. Both levels are individually
adjustable.
These parameters are also used to adjust the PWM duty cycle.
The AS5263 provides also a compare function. The internal angular code is compared to a programmable level using hysteresis. The function is
available over the output pins 21, 22 (KDOWN_T, KDOWN_B).
The output parameters can be programmed in an OTP register. No additional voltage is required to program the AS5263. The setting may be
overwritten at any time and will be reset to default when power is cycled. To make the setting permanent, the OTP register must be programmed
by using a lock bit the content could be frozen for ever.
The AS5263 is tolerant to magnet misalignment and unwanted external magnetic fields due to differential measurement technique and Hall
sensor conditioning circuitry.
It is also tolerant to air gap and temperature variations due to Sin-/Cos- signal evaluation.
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The AS5263 is tolerant to magnet misalignment and magnetic stray fields due to differential measurement technique and Hall sensor
conditioning circuitry.
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
7.1 Operation
The AS5263 operates at 5V ±10%, using two internal Low-Dropout (LDO) voltage regulators. For operation, the 5V supply is connected to pin
VDD. While VDD3 and VDD5 (LDO outputs) must be buffered by 2.2µF capacitors, the VDD requires a 1µF capacitor. All capacitors (low ESR
ceramic) are supposed to be placed close to the supply pins (see Figure 3).
The VDD3 and VDD5 outputs are intended for internal use only. It must not be loaded with an external load.
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Figure 3. External Circuitry for the AS5263 (figure shows only one sensor die)
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5V Operation
2.2µF
VDD5_T
2.2µF
VDD3_T
1µF
VDD_T
LDO
LDO
Internal
VDD4.5V
Internal
VDD3.45V
4.5 - 5.5V
GNDD_T
GNDA_T
GNDP_T
Notes:
VDD Voltage Monitor
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1. The pins VDD3 and VDD5 must always be buffered by a capacitor. These pins must not be left floating, as this may
cause unstable internal supply voltages, which may lead to larger output jitter of the measured angle.
2. Only VDD is overvoltage protected up to 27V. In addition, the VDD has a reverse polarity protection.
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VDD Overvoltage Management. If the voltage applied to the VDD pin exceeds the overvoltage upper threshold for longer than the detection
time, then the device enters a low power mode reducing the power consumption. When the overvoltage event has passed and the voltage
applied to the VDD pin falls below the overvoltage lower threshold for longer than the recovery time, then the device enters the normal mode.
VDD5 Undervoltage Management. When the voltage applied to the VDD5 pin falls below the undervoltage lower threshold for longer than
the VDD5_detection time, then the device stops the clock of the digital part and the output drivers are turned off to reduce the power
consumption. When the voltage applied to the VDD5 pin exceeds the VDD5 undervoltage upper threshold for longer than the VDD5_recovery
time, then the clock is restarted and the output drivers are turned on.
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
7.2 Analog Output
The reference voltage for the Digital-to-Analog converter (DAC) is taken internally from VDD. In this mode, the output voltage is ratiometric to the
supply voltage.
7.2.1
Programming Parameters
T1
Mechanical angle start point
T2
Mechanical angle end point
T1Y
Voltage level at the T1 position
T2Y
Voltage level at the T2 position
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The Analog output voltage modes are programmable by OTP. Depending on the application, the analog output can be adjusted. The user can
program the following application specific parameters:
Clamping Level Low
Clamping Level High
BP
Break point (transition point 0 to 360 degree)
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CLL
CLH
The above listed parameters are input parameters. Over the provided programming software and programmer, these parameters are converted
and finally written into the AS5263 128-bit OTP memory. More details about the conversion can be found in the AN_AS5163+AS5263_V1.0
application note.
7.2.2
Application Specific Angular Range Programming
The application range can be selected by programming T1 with a related T1Y and T2 with a related T2Y into the AS5263. The internal gain factor
is calculated automatically. The clamping levels CLL and CLH can be programmed independent from the T1 and T2 position and both levels can
be separately adjusted.
Figure 4. Programming of an Individual Application Range
Application range
90 degree
electrical range
T2
mechanical range
T1
100%VDD
clamping range
high
CLH
180 degree
ca
CLL
0 degree
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CLH
T1Y
BP
CLL
0
clamping range
low
T1
T2
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270 degree
T2Y
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Figure 4 shows a simple example of the selection of the range. The mechanical starting point T1 and the mechanical end point T2 define the
mechanical range. A sub range of the internal Cordic output range is used and mapped to the needed output characteristic. The analog output
signal has 12 bit, hence the level T1Y and T2Y can be adjusted with this resolution. As a result of this level and the calculated slope the clamping
region low is defined. The break point BP defines the transition between CLL and CLH. In this example, the BP is set to 0 degree. The BP is also
the end point of the clamping level high CLH. This range is defined by the level CLH and the calculated slope. Both clamping levels can be set
independently form each other. The minimum application range is 12 degrees.
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
7.2.3
Application Specific Programming of the Break Point
The break point BP can be programmed as well with a resolution of 14 bits. This is important when the default transition point is inside the
application range. In such a case, the default transition point must be shifted out of the application range. The parameter BP defines the new
position. The function can be used also for an on-off indication.
Application range
90 degree
electrical range
T2
mechanical range
CLH
100%VDD
CLH
0 degree
180 degree
T2Y
T1Y
CLL
CLL
BP
0
270 degree
7.2.4
clamping range
high
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T1
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Figure 5. Individual Programming of the Break Point BP
Full Scale Mode
clamping range
low
T1
T2
clamping range
low
The AS5263 can be programmed as well in the full scale mode. The BP parameter defines the position of the transition.
Figure 6. Full Scale Mode
0
360
Te
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Analog output Voltage
ca
100 % VDD
For simplification, Figure 6 describes a linear output voltage from rail to rail (0V to VDD) over the complete rotation range. In practice, this is not
feasible due to saturation effects of the output stage transistors. The actual curve will be rounded towards the supply rails (as indicated Figure 6).
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
7.2.5
Inverted Dual Channel Output
The AS5263 can be programmed as described in Figure 7.
electrical range
mechanical range
Analog Output at OUT_T
100%VDD
CLH
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CLH
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Figure 7. Inverted Slope Output
T2Y
T1Y
CLL
0
CLL
Analog Output at OUT_B
100%VDD
CLH
CLH
T1Y
T2Y
CLL
CLL
0
7.2.6
T2
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T1
Resolution of the Parameters
The programming parameters have a wide resolution of up to 14 bits.
ni
Table 7. Resolution of the Programming Parameters
Parameter
Resolution
T1
Mechanical angle start point
14 bits
T2
Mechanical angle stop point
14 bits
T1Y
Mechanical start voltage level
12 bits
T2Y
Mechanical stop voltage level
12 bits
CLL
Clamping level low
7 bits
4096 LSBs is the maximum level
CLH
Clamping level high
7 bits
31 LSBs is the minimum level
BP
Break point
14 bits
Te
ch
Symbol
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Note
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
100
96
Failure Band High
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Clamping Region High
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Figure 8. Overview of the Angular Output Voltage
Output Voltage in percent of VDD
CLH
T2Y
Application Region
T1Y
CLL
Clamping Region Low
4
Failure Band Low
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0
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Figure 8 gives an overview of the different ranges. The failure bands are used to indicate a wrong operation of the AS5263. This can be caused
due to a broken supply line. By using the specified load resistors, the output level will remain in these bands during a fail. It is recommended to
set the clamping level CLL above the lower failure band and the clamping level CLH below the higher failure band.
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Datasheet - D e t a i l e d D e s c r i p t i o n
7.2.7
Analog Output Diagnostic Mode
Due to the low pin count in the application, a wrong operation must be indicated by the output pin OUT_T, OUT_B. This could be realized using
the failure bands. The failure band is defined with a fixed level. The failure band low is specified from 0% to 4% of the supply range. The failure
band high is defined from 100% to 96%. Several failures can happen during operation. The output signal remains in these bands over the
specified operating and load conditions. All the different failures can be grouped into the internal alarms (failures) and the application related
failures.
CLOAD ≤ 42 nF, RPU= 2k…5.6kΩ
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RPD= 2k…5.6kΩ load pull-up
Table 8. Different Failure Cases of AS5263
Type
Failure Mode
Failure Band
Note
MAGRng
High/Low
Could be switched off by one OTP bit
EXT_RANGE.
Programmable by OTP bit DIAG_HIGH
Cordic overflow
COF
High/Low
Programmable by OTP bit DIAG_HIGH
Offset compensation finished
OCF
High/Low
Programmable by OTP bit DIAG_HIGH
Watchdog fail
WDF
High/Low
Programmable by OTP bit DIAG_HIGH
Oscillator fail
OF
High/Low
Programmable by OTP bit DIAG_HIGH
Overvoltage condition
OV
High/Low
Dependent on the load resistor
Pull up → failure band high
Pull down → failure band low
High/Low
Switch off → short circuit dependent
Internal alarms (failures)
Application related
failures
Symbol
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Out of magnetic range
(too less or too high magnetic
input)
Broken VDD
BVDD
Broken VSS
BVSS
Short circuit output
SCO
For efficient use of diagnostics it is recommended to program to clamping levels CLL and CLH.
7.2.8
Analog Output Driver Parameters
The output stage is configured in a push-pull output. Therefore it is possible to sink and source currents.
CLOAD ≤ 42 nF, RPU= 2k…5.6kΩ
RPD= 2k…5.6kΩ load pull-up
Symbol
Short circuit output current (low side driver)
8
32
mA
VOUT=27V
IOUTSCH
Short circuit output current (high side driver)
-8
-32
mA
VOUT=0V
Short circuit detection time
20
600
µs
output stage turned off
TSCDET
Short circuit recovery time
Typ
Max
Unit
Note
2
20
ms
output stage turned on
ILEAKOUT
Output Leakage current
-20
20
µA
VOUT=VDD=5V
BGNDPU
Output voltage broken GND with pull-up
96
100
%VDD
RPU = 2k…5.6k
BGNDPD
Output voltage broken GND with pull-down
0
4
%VDD
RPD = 2k…5.6k
BVDDPU
Output voltage broken VDD with pull-up
96
100
%VDD
RPU = 2k…5.6k
BVDDPD
Output voltage broken VDD with pull-down
0
4
%VDD
RPD = 2k…5.6k
Te
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TSCREC
Parameter
ni
Min
IOUTSCL
ca
Table 9. General Parameters for the Output Driver
Note: A Pull-Up/Down load is up to 1kΩ with increased diagnostic bands from 0%-6% and 94%-100%.
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AS5263
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 10. Electrical Parameters for the Analog Output Stage
Min
VOUT
Output Voltage Range
VOUTINL
Output Integral nonlinearity
VOUTDNL
Output Differential nonlinearity
VOUTOFF
Output Offset
VOUTUD
Update rate of the Output
VOUTSTEP
Output Step Response
Typ
Max
4
96
6
94
Unit
% VDD
Note
Valid when 1k ≤ RLOAD < 2k
10
LSB
-10
10
LSB
-50
50
mV
At 2048 LSB level
µs
Info parameter
550
µs
Between 10% and 90%, RPD
=1kΩ, CLOAD=1nF; VDD=5V
100
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Parameter
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Symbol
VOUTDRIFT
Output Voltage Temperature drift
2
2
%
Of value at mid code
VOUTRATE
Output ratiometricity error
-1.5
1.5
%VDD
0.04*VDD ≤ VOUT ≤ 0.96*VDD
VOUTNOISE
Noise
10
mVpp
1Hz…30kHz;
at 2048 LSB level
1
1. Not tested in production; characterization only.
7.3 Pulse Width Modulation (PWM) Output
The AS5263 provides a pulse width modulated output (PWM), whose duty cycle is proportional to the measured angle. This output format is
selectable over the OTP memory. If output pins OUT_T, OUT_B are configured as open drain configuration, then an external load resistor (pull
up) is required. The PWM frequency is internally trimmed to an accuracy of ±10% over full temperature range. This tolerance can be cancelled
by measuring the ratio between the on and off state. In addition, the programmed clamping levels CLL and CLH will also adjust the PWM signal
characteristic.
Figure 9. PWM Output Signal
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PWmax
PWmin
Position 0
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Position 1
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Position 4094
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Position 4095
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TPWM = 1/fPWM
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Datasheet - D e t a i l e d D e s c r i p t i o n
The PWM frequency can be programmed by the OTP bits PWM_frequency (1:0). Therefore, four different frequencies are possible.
Table 11. PWM Signal Parameters
Parameter
Min
Typ
Max
Unit
Note
fPWM1
PWM frequency1
123.60
137.33
151.06
Hz
PWM_frequency (1:0) = “00”
fPWM2
PWM frequency2
247.19
274.66
302.13
Hz
PWM_frequency (1:0) = “01”
fPWM3
PWM frequency3
494.39
549.32
604.25
Hz
PWM_frequency (1:0) = “10”
fPWM4
PWM frequency4
988.77
1098.63
1208.50
Hz
PWM_frequency (1:0) = “11”
PWMIN
MIN pulse width
(1+1)*1/
fPWM
µs
PWMAX
MAX pulse width
(1+4094)*1/
fPWM
ms
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Symbol
Taking into consideration the AC characteristic of the PWM output including load, it is recommended to use the clamping function. The
recommended range is 0% to 4% and 96% to 100%.
Table 12. Electrical Parameters for the PWM Output Mode
Symbol
Parameter
Min
PWMVOL
Output voltage low
ILEAK
Typ
Max
Unit
0
0.4
V
IOUT=8mA
Output leakage
-20
20
µA
VOUT=VDD=5V
PWMDC
PWM duty cycle range
4
96
%
PWMSRF
PWM slew rate
1
4
V/µs
2
Note
Between 75% and 25%
RPU/RPD = 1kΩ,
CLOAD = 1nF, VDD = 5V
7.4 Kick Down Function
The AS5263 provides a special compare function. This function is implemented using a programmable angle value with a programmable
hysteresis. It will be indicated over the open drain output pin KDOWN_T, KDOWN_B. If the actual angle is above the programmable value plus
the hysteresis, the output is switched to low. The output will remain at low level until the value KD is reached in the reverse direction.
ni
ca
Figure 10. Kick Down Hysteresis Implementation
KDHYS
Te
ch
KDOWN
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KD(5:0)+KDHYS
KD(5:0)
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Datasheet - D e t a i l e d D e s c r i p t i o n
Table 13. Programming Parameters for the Kick Down Function
Parameter
Resolution
KD
Kick Down angle
6 bits
KDHYS
Kick Down Hysteresis
2 bits
Note
KDHYS (1:0) = “00” → 8 LSB hysteresis
KDHYS (1:0) = “01” → 16 LSB hysteresis
KDHYS (1:0) = “10” → 32 LSB hysteresis
KDHYS (1:0) = “11” → 64 LSB hysteresis
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Symbol
Pull-up resistance 1k to 5.6K to VDD
CLOAD max 42nF
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Table 14. Electrical Parameters of the KDOWN Output
Symbol
Parameter
Min
IKDSC
Short circuit output current
(Low Side Driver)
TSCDET
Max
Unit
6
24
mA
VKDOWN = 27V
Short circuit detection time
20
600
µs
output stage turned off
TSCREC
Short circuit recovery time
2
20
ms
output stage turned on
KDVOL
Output voltage low
0
1.1
V
IKDOWN = 6mA
Output leakage
-20
20
µA
VKDOWN = 5V
KDILEAK
KDOWN slew rate (falling edge)
1
2
4
V/µs
Note
Between 75% and 25%,
RPUKDWN = 1kΩ, CLOAD_KDWN
= 1nF, VDD = 5V
Te
ch
ni
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KDSRF
Typ
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
The benefits of AS5263 are as follows:
Unique fully differential patented solution
Best protection for automotive applications
Flexible interface selection PWM, analog output
Ideal for applications in harsh environments due to contactless position sensing
Robust system, tolerant to magnet misalignment, airgap variations, temperature variations and external magnetic fields
No calibration required because of inherent accuracy
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High driving capability of analog output (including diagnostics)
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Easy to program
8.1 Programming the AS5263
The AS5263 programming is a one-time-programming (OTP) method, based on polysilicon fuses. The advantage of this method is that no
additional programming voltage is needed. The internal LDO provides the current for programming.
The OTP consists of 128 bits, wherein several bits are available for user programming. In addition, factory settings are stored in the OTP
memory. Both regions are independently lockable by built-in lock bits.
A single OTP cell can be programmed only once. By default, each cell is “0”; a programmed cell will contain a “1”. While it is not possible to reset
a programmed bit from “1” to “0”, multiple OTP writes are possible, as long as only unprogrammed “0”-bits are programmed to “1”.
Independent of the OTP programming, it is possible to overwrite the OTP register temporarily with an OTP write command. This is possible only
if the user lock bit is not programmed.
Due to the programming over the output pin, the device will initially start in the communication mode. In this mode, the digital angle value can be
read with a specific protocol format. It is a bidirectional communication possible. Parameters can be written into the device. A programming of the
device is triggered by a specific command. With another command (pass2funcion), the device can be switched into operation mode (analog or
PWM output). In case of a programmed user lock bit, the AS5263 automatically starts up in the functional operation mode. No communication of
the specific protocol is possible after this.
8.1.1
Hardware Setup
The pin OUT and the supply connection are required for OTP memory access. Without the programmed Mem_Lock_USER OTP bit, the device
will start up in the communication mode and will remain into an IDLE operation mode. The pull up resistor RCommunication is required during
startup. Figure 1 shows the configuration of an AS5263.
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Figure 11. Programming Schematic of the AS5263
SENSOR PCB
VDD_X
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VDD_X
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1uF
2.2uF
(low ESR)
2.2uF
(low ESR)
0.3 ohm
AS5263
VDD5_X
VDD3_X
VDD
Programmer
RCommunication
OUT_X
DIO
KDOWN_X
GNDA_X GNDD_X GNDP_X
GND
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GND
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.2
Protocol Timing and Commands of Single Pin Interface
During the communication mode, the output level is defined by the external pull up resistor RCommunication. The output driver of the device is in tristate. The bit coding (see Figure 18) has been chosen in order to allow the continuous synchronization during the communication, which can be
required due to the tolerance of the internal clock frequency. Figure 18 shows how the different logic states '0' and '1' are defined. The period of
the clock TCLK is defined with 222.2 ns.
The voltage levels VH and VL are CMOS typical.
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Each frame is composed by 20 bits. The 4 MSB (CMD) of the frame specifies the type of command that is passed to the AS5263. The 16 data
bits contain the communication data. There will be no operation when the ‘not specified’ CMD is used. The sequence is oriented in such a way
that the LSB of the data is followed by the command. The number of frames vary depending on the command. The single pin programming
interface block of the AS5263 can operate in slave communication or master communication mode. In the slave communication mode, the
AS5263 receives the data organized in frames. The programming tool is the driver of the single communication line and can pull down the level.
In case of the master communication mode, the AS5263 transmits data in the frame format. The single communication line can be pulled down
by the AS5263.
Figure 12. Bit Coding of the Single Pin Programming Interface
Bit “0”
Bit “1”
VH
VH
VL
VL
T1
T1
T2
T1 = 128 * TCLK
T2
TBIT = T1 + T2 = 512 * TCLK
T2 = 384 * TCLK
ch
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Figure 13. Protocol Definition
IDLE START
IDLE
PACKET
COMMAND
Te
DATA
START
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 15. OTP Commands and Communication Interface Modes
Description
AS5263
Communication Mode
Command
CMD
Number of
Frames
UNBLOCK
Resets the interface
SLAVE
0x0
1
WRITE128
Writes 128 bits (user + factory settings) into the device
SLAVE
0x9
(0x1)
8
READ128
Reads 128 bits (user + factory settings) from the device
SLAVE and MASTER
0xA
Transfers the register content into the OTP memory
SLAVE
0x6
Transfers the OTP content to the register content
SLAVE
0x5
FUSE
Command for permanent programming
SLAVE
0x4
9
1
1
1
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UPLOAD
DOWNLOAD
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Possible Interface
Commands
PASS2FUNC
Change operation mode from communication to operation
SLAVE
0x7
1
READ
Read related to address the user data
SLAVE and MASTER
0xB
2
Write related to address the user data
SLAVE
0xC
1
WRITE
Note: Other commands are reserved and shall not be used.
When single pin programming interface bus is in high impedance state, the logical level of the bus is held by the pull up resistor RCommunication.
Each communication begins by a condition of the bus level which is called START. This is done by forcing the bus in logical low level (done by
the programmer or AS5263 depending on the communication mode). Afterwards the bit information of the command is transmitted as shown in
Figure 14.
DATA14
MSB
LSB
DATA2
1 0 0 1
MSB
MSB
LSB
LSB
DATA3
MSB
LSB
MSB
DATA0
MSB
LSB
DATA1
LSB
LSB
START
IDLE
MSB
Figure 14. Bus Timing for the WRITE128 Command
1 0 0 0
1 0 0 0
ca
20*TBIT
Te
0 1 0 1
IDLE
0 0 0 P
DATA3
DATA14
MSB
LSB
DATA0
MSB
DATA1
MSB
LSB
LSB
DO NOT CARE
MSB
LSB
START
IDLE
DO NOT CARE
MSB
LSB
MSB
LSB
ch
ni
Figure 15. Bus Timing for the READ128 Command
0 0 0 P
20*TBIT
Slave Communication Mode
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Master Communication Mode
TSW
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
In case of READ or READ128 command (see Figure 15) the idle phase between the command and the answer is 10 TBIT (TSW).
DATA0
IDLE
0 0 0 P
al
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0 1 0 1
20*TBIT
Slave Communication Mode
MSB
LSB
DATA1
MSB
LSB
MSB
ADDR1
MSB
LSB
MSB
ADDR2
LSB
START
IDLE
LSB
Figure 16. Bus Timing for the READ Commands
Master Communication Mode
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TSW
In case of a WRITE command, the device stays in slave communication mode and will not switch to master communication mode.
When using other commands like DOWNLOAD, UPLOAD, etc. instead of READ or WRITE, it does not matter what is written in the address
fields (ADDR1, ADDR2).
8.1.3
UNBLOCK
The Unblock command can be used to reset only the one-wire interface of the AS5263 in order to recover the possibility to communicate again
without the need of a POR after a stacking event due to noise on the bus line or misalignment with the AS5263 protocol.
The command is composed by a not idle phase of at least 6 TBIT followed by a packet with all 20 bits at zero (see Figure 17).
Figure 17. Unblock Sequence
VH
NOT IDLE
IDLE
START
= 6 * TBIT => 3072* TCLK
= 512*TCLK
= 512*TCLK
PACKET[19:0] = 0x00000
20*TBIT => 10240*TCLK
IDLE
= 512*TCLK
ca
VL
Te
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COMMAND FROM EXT MASTER
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.4
WRITE128
Figure 18 illustrates the format of the frame and the command.
Figure 18. Frame Organization of the WRITE128 Command
DATA0
MSB
LSB
LSB
CMD
MSB
LSB
1
DATA3
DATA2
MSB
LSB
LSB
MSB
0
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DATA1
0
1
CMD
MSB
LSB
MSB
0
0
0
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1
DATA5
DATA4
MSB
LSB
LSB
CMD
MSB
LSB
1
DATA7
DATA6
MSB
LSB
LSB
LSB
1
DATA8
MSB
LSB
LSB
DATA10
MSB
LSB
DATA12
MSB
LSB
ca
MSB
DATA14
LSB
0
0
MSB
0
0
0
CMD
MSB
LSB
1
MSB
0
0
0
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0
MSB
0
LSB
1
LSB
0
CMD
MSB
DATA15
0
MSB
0
LSB
1
LSB
0
CMD
MSB
DATA13
MSB
0
LSB
1
LSB
0
CMD
MSB
DATA11
0
CMD
MSB
DATA9
MSB
0
Te
The command contains 8 frames. With this command, the AS5263 receives only frames. This command will transfer the data in the special
function registers (SFRs) of the device. The data is not permanent programmed using this command.
Table 16 describe the organization of the OTP data bits.
The access is performed with CMD field set to 0x9. The next 7 frames with CMD field set to 0x1. The 2 bytes of the first command will be written
at address 0 and 1 of the SFRs; the 2 bytes of the second command will be written at address 2 and 3; and so on, in order to cover all the 16
bytes of the 128 SFRs.
Note: It is important to always complete the command. All 8 frames are needed. In case of a wrong command or a communication error, a
power on reset must be performed. The device will be delivered with the programmed Mem_Lock_AMS OTP bit. This bit locks the
content of the factory settings. It is impossible to overwrite this particular region. The written information will be ignored.
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.5
READ128
Figure 19 illustrates the format of the frame and the command.
Figure 19. Frame Organization of the READ128 Command
DO NOT CARE
MSB
LSB
LSB
CMD
MSB
LSB
0
DATA1
DATA0
MSB
LSB
LSB
al
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DO NOT CARE
MSB
1
0
1
CMD DUMMY
MSB
0
0
P
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0
DATA3
DATA2
MSB
LSB
LSB
CMD DUMMY
MSB
0
DATA5
LSB
DATA7
DATA6
MSB
LSB
DATA8
LSB
ca
MSB
LSB
0
0
P
LSB
0
0
P
CMD DUMMY
DATA12
MSB
0
ni
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0
0
P
CMD DUMMY
DATA14
LSB
0
MSB
0
0
0
P
Te
LSB
P
MSB
DATA15
MSB
0
CMD DUMMY
DATA10
DATA13
LSB
0
MSB
DATA11
MSB
P
CMD DUMMY
0
LSB
0
MSB
DATA9
MSB
0
CMD DUMMY
0
LSB
P
MSB
0
LSB
0
CMD DUMMY
DATA4
MSB
LSB
0
The command is composed by a first frame transmitted to the AS5263. The device is in slave communication mode. The device remains for the
time TSWITCH in IDLE mode before changing into the master communication mode. The AS5263 starts to send 8 frames. This command will read
the SFRs. The numbering of the data bytes correlates with the address of the related SFR.
An even parity bit is used to guarantee a correct data transmission. Each parity (P) is related to the frame data content of the 16 bit word. The
MSB of the CMD dummy (P) is reserved for the parity information.
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.6
DOWNLOAD
Figure 20 shows the format of the frame.
Figure 20. Frame Organization of the DOWNLOAD Command
DO NOT CARE
MSB
LSB
LSB
CMD
MSB
LSB
MSB
0
1
0
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DO NOT CARE
The command consists of one frame received by the AS5263 (slave communication mode). The OTP cell fuse content will be downloaded into
the SFRs.
The access is performed with CMD field set to 0x5.
8.1.7
UPLOAD
Figure 21 shows the format of the frame.
Figure 21. Frame Organization of the UPLOAD Command
DO NOT CARE
DO NOT CARE
MSB
LSB
LSB
CMD
MSB
LSB
0
MSB
1
1
0
The command consists of one frame received by the AS5263 (slave communication mode) and transfers the data from the SFRs into the OTP
fuse cells. The OTP fuses are not permanent programmed using this command.
The access is performed with CMD field set to 0x6.
8.1.8
FUSE
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Figure 22 shows the format of the frame.
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Figure 22. Frame Organization of the FUSE Command
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DO NOT CARE
MSB
LSB
CMD
MSB
LSB
0
MSB
0
1
0
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LSB
DO NOT CARE
The command consists of one frame received by the AS5263 (slave communication mode) and it is giving the trigger to permanent program the
non volatile fuse elements.
The access is performed with CMD field set to 0x4.
Note: After this command, the device automatically starts to program the built-in programming procedure. It is not allowed to send other commands during this programming time. This time is specified to 4ms after the last CMD bit.
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.9
PASS2FUNC
Figure 23 shows the format of the frame.
DO NOT CARE
DO NOT CARE
MSB
LSB
LSB
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Figure 23. Frame Organization of the PASS2FUNCTION Command
CMD
MSB
LSB
MSB
1
1
0
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The command consists of one frame received by the AS5263 (slave communication mode). This command stops the communication receiving
mode, releases the reset of the DSP of the AS5263 device and starts to work in functional mode with the values of the SFR currently written.
The access is performed with CMD field set to 0x7.
8.1.10 READ
Figure 24 shows the format of the frame.
Figure 24. Frame Organization of the READ Command
ADDR2
ADDR1
MSB
LSB
LSB
CMD
MSB
LSB
1
DATA2
DATA1
MSB
LSB
0
1
CMD DUMMY
MSB
0
0
0
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LSB
MSB
1
The command is composed by a first frame sent to the AS5263. The device is in slave communication mode. The device remains for the time
TSWITCH in IDLE mode before changing into the master communication mode. The AS5263 starts to send the second frame transmitted by the
AS5263.
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The access is performed with CMD field set to 0xB.
When the AS5263 receives the first frame, it sends a frame with data value of the address specified in the field of the first frame.
Table 17 shows the possible readable data information for the AS5263 device.
An even parity bit is used to guarantee a correct data transmission. The parity bit (P) is generated by the 16 data bits. The MSB of the CMD
dummy (P) is reserved for the parity information.
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.11 WRITE
Figure 25 shows the format of the frame.
DATA
ADDR
MSB
LSB
LSB
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Figure 25. Frame Organization of the WRITE Command
CMD
MSB
LSB
MSB
0
1
1
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The command consists of one frame received by the AS5263 (slave communication mode). The data byte will be written to the address. The
access is performed with CMD field set to 0xC.
Table 17 shows the possible write data information for the AS5263 device.
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Note: It is not recommended to access OTP memory addresses using this command.
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.2 OTP Programming Data
Table 16. OTP Data Organization
Symbol
Default
0
AMS_Test
FS
1
AMS_Test
FS
2
AMS_Test
FS
3
AMS_Test
FS
4
AMS_Test
FS
5
AMS_Test
FS
6
AMS_Test
FS
DATA14
(0x0E)
AMS Test Area
AMS_Test
FS
0
AMS_Test
FS
1
AMS_Test
FS
2
AMS_Test
FS
3
AMS_Test
FS
4
ChipID<0>
FS
5
ChipID<1>
FS
6
ChipID<2>
FS
7
ChipID<3>
FS
0
ChipID<4>
FS
1
ChipID<5>
FS
2
ChipID<6>
FS
3
ChipID<7>
FS
4
ChipID<8>
FS
5
ChipID<9>
FS
6
ChipID<10>
FS
7
ChipID<11>
FS
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7
ChipID<12>
FS
1
ChipID<13>
FS
2
ChipID<14>
FS
3
ChipID<15>
FS
4
ChipID<16>
FS
5
ChipID<17>
FS
6
ChipID<18>
FS
7
ChipID<19>
FS
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Revision 1.4
Factory Settings
DATA13
(0x0D)
DATA12
(0x0C)
Description
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DATA15
(0x0F)
Bit Number
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Chip ID
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 16. OTP Data Organization
Symbol
Default
Description
0
ChipID<20>
FS
Chip ID
1
MemLock_AMS
1
Lock of the Factory Setting Area
2
KD<0>
0
3
KD<1>
0
4
KD<2>
0
5
KD<3>
0
6
KD<4>
0
7
KD<5>
0
DATA10
(0x0A)
ClampLow<0>
0
1
ClampLow<1>
0
2
ClampLow<2>
0
3
ClampLow<3>
0
4
ClampLow<4>
0
5
ClampLow<5>
0
6
ClampLow<6>
0
7
DAC_MODE
0
0
ClampHi<0>
0
1
ClampHi<1>
0
2
ClampHi<2>
0
3
ClampHi<3>
0
4
ClampHi<4>
0
5
ClampHi<5>
0
6
ClampHi<6>
0
7
DIAG_HIGH
0
0
OffsetIn<0>
0
1
OffsetIn<1>
0
2
OffsetIn<2>
0
3
OffsetIn<3>
0
4
OffsetIn<4>
0
5
OffsetIn<5>
0
6
OffsetIn<6>
0
7
OffsetIn<7>
0
Clamping Level Low
DAC12/DAC10 Mode
Clamping Level High
Diagnostic Mode, default=0 for
Failure Band Low
Offset
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0
Customer Settings
DATA9
(0x09)
DATA8
(0x08)
Kick Down Threshold
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DATA11
(0x0B)
Bit Number
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Data Byte
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 16. OTP Data Organization
DATA6
(0x06)
Default
0
OffsetIn<8>
0
1
OffsetIn<9>
0
2
OffsetIn<10>
0
3
OffsetIn<11>
0
4
OffsetIn<12>
0
5
OffsetIn<13>
0
6
OP_Mode<0>
0
7
OP_Mode<1>
0
Description
Offset
Selection of Analog=‘00’ or PWM
Mode=‘01’
OffsetOut<0>
0
1
OffsetOut<1>
0
2
OffsetOut<2>
0
3
OffsetOut<3>
0
4
OffsetOut<4>
0
5
OffsetOut<5>
0
6
OffsetOut<6>
0
7
OffsetOut<7>
0
0
OffsetOut<8>
0
1
OffsetOut<9>
0
2
OffsetOut<10>
0
3
OffsetOut<11>
0
4
KDHYS<0>
0
5
KDHYS<1>
0
6
PWM Frequency<0>
0
7
PWM Frequency<1>
0
0
BP<0>
0
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0
BP<1>
0
2
BP<2>
0
3
BP<3>
0
4
BP<4>
0
5
BP<5>
0
6
BP<6>
0
7
BP<7>
0
Kick Down Hysteresis
Select the PWM frequency (4
frequencies)
Break Point
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Output Offset
Customer Settings
DATA5
(0x05)
DATA4
(0x04)
Symbol
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DATA7
(0x07)
Bit Number
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Data Byte
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 16. OTP Data Organization
Symbol
Default
DATA2
(0x02)
0
BP<8>
0
1
BP<9>
0
2
BP<10>
0
3
BP<11>
0
4
BP<12>
0
5
BP<13>
0
6
FAST_SLOW
0
Output Data Rate
7
EXT_RANGE
0
Enables a wider z-Range
Break Point
Gain<0>
0
1
Gain<1>
0
2
Gain<2>
0
3
Gain<3>
0
4
Gain<4>
0
5
Gain<5>
0
6
Gain<6>
0
7
Gain<7>
0
0
Gain<8>
0
1
Gain<9>
0
2
Gain<10>
0
3
Gain<11>
0
4
Gain<12>
0
5
Gain<13>
0
6
Invert_Slope
0
Clockwise /Counterclockwise
rotation
7
Lock_OTPCUST
0
Customer Memory Lock
0
redundancy<0>
0
1
redundancy<1>
0
2
redundancy<2>
0
3
redundancy<3>
0
4
redundancy<4>
0
5
redundancy<5>
0
6
redundancy<6>
0
7
redundancy<7>
0
Gain
Gain
Redundancy Bits
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Customer Settings
DATA1
(0x01)
DATA0
(0x00)
Description
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DATA3
(0x03)
Bit Number
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Data Byte
Note: Factory settings (FS) are used for testing and programming at AMS. These settings are locked (only read access possbile).
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Data Content.
Redundancy (7:0): For a better programming yield, a redundancy is implemented. In case the programming of one bit fails, then this
function can be used. With an address (7:0) one bit can be selected and programmed.
Lock_OTPCUST = 1, locks the customer area in the OTP and the device, from hereon, starts in operating mode.
Redundancy Code
OTP Bit Selection
0
none
1
OP_Mode<1>
2
DIAG_HIGH
PWM Frequency<0>
ClampHi<6> - ClampHi<0>
11 - 17
ClampLow<6> - ClampLow<0>
18
OP_Mode<0>
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Redundancy <7:0>
in decimal
19 - 32
OffsetIn<13> - OffsetIn<0>
33 - 46
Gain<13> - Gain<0>
47 - 60
BP<13> - BP<0>
61 - 72
OffsetOut<11> - OffsetOut<0>
73
Invert_Slope
74
FAST_SLOW
75
EXT_RANGE
76
DAC_MODE
77
Lock_OTPCUST
78 - 83
KD<5> - KD<0>
84 - 85
KDHYS<1> - KDHYS<0>
86
PWM Frequency<1>
Invert_Slope = 1, inverts the output characteristic in analog output mode
Gain (7:0): With this value, the steepness of the output slope can be adjusted
EXT_RANGE = 1, provides a wider z-Range of the magnet by turning off the alarm function
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FAST_SLOW = 1, improves the noise performance due to internal filtering
BP (13:0): The breakpoint can be set with resolution of 14-bit
PWM Frequency (1:0): Four different frequency settings are possible. Please refer to Table 11.
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KDHYS (1:0): Avoids flickering at the KDOWN output (pin 11). For settings, refer to Table 12.
OffsetOut (11:0): Output characteristic parameter
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ANALOG_PWM = 1, selects the PWM output mode
OffsetIn (13:0): Output characteristic parameter
DIAG_HIGH = 1: In case of an error, the signal goes into high failure-band.
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ClampHI (6:0): Sets the clamping level high with respect to VDD.
DAC_MODE disables filter at DAC
ClampLow (6:0): Sets the clamping level low with respect to VDD
KD (5:0): Sets the kick-down level with respect to VDD
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.2.1
Read / Write User Data
Area
Region
Address
Address
R/W User Data
Table 17. Read / Write Data
0x10
16
0x11
17
0
0
0x12
18
OCF
COF
0x17
23
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
CORDIC_OUT[13:8]
0
0
0
AGC_VALUE[7:0]
DSP_RES R1K_10K
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Read and Write
Data only for read:
Bit0
CORDIC_OUT[7:0]
Read only
Data Content:
Bit1
CORDIC_OUT(13:0): 14-bit absolute angular position data
OCF (Offset Compensation Finished): logic high indicates the finished Offset Compensation Algorithm. As soon as this bit is set, the
AS5263 has completed the startup and the data is valid.
COF (Cordic Overflow): Logic high indicates an out of range error in the CORDIC part. When this bit is set, the CORDIC_OUT(13:0) data is
invalid. The absolute output maintains the last valid angular value. This alarm may be resolved by bringing the magnet within the X-Y-Z
tolerance limits.
AGC_VALUE (7:0): Magnetic field indication
Data for write and read:
DSP_RES resets the DSP part of the AS5263 the default value is 0. This is active low. The interface is not affected by this reset.
R1K_10K defines the threshold level for the OTP fuses. This bit can be changed for verification purpose. A verification of the programming
of the fuses is possible. The verification is mandatory after programming.
8.2.2
Programming Procedure
Note: After programming the OTP fuses, a verification is mandatory. The procedure described below must be strictly followed to ensure
properly programmed OTP fuses.
Pull-up on OUT pin
VDD=5V
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Wait startup time, device enters communication mode.
Write128 command: The trimming bits are written in the SFR memory.
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Read128 command: The trimming bits are read back.
Compare read data to previous written data. If the data matches, then proceed further.
Upload command: The SFR memory is transferred into the OTP RAM.
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Fuse command: The OTP RAM is written in the Poly Fuse cells.
Wait fuse time (6ms)
Write command (R1K_10K=1): Poly Fuse cells are transferred into the RAM cells compared with 10KΩ resistor.
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Download command: The OTP RAM is transferred into the SFR memory.
Read128 command: The fused bits are read back.
Compare read data to previous written and read data. If the data matches, then proceed further.
Write command (R1K_10K=0): Poly Fuse cells are transferred into the RAM cells compared with 1KΩ resistor.
Download command: The OTP RAM is transferred into the SFR memory.
Read128 command: The fused bits are read back.
Compare read data to previous written and two times read data. If the data matches, then proceed further.
Pass2Func command or POR: Go to Functional mode.
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Revision 1.4
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AS5263
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
An equal output of all read out data is sufficient to verify the OTP programming. If the data output is a mismatch, then the programming of the
OTP was not successful and can cause a change of the OTP register content during operation over temperature and life time.
8.2.3
Physical Placement of the Magnet
The best linearity can be achieved by placing the center of the magnet exactly over the defined center of the chip as shown in Figure 26.
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Figure 26. Defined Chip Center and Magnet Displacement Radius
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Defined
center
Rd
Area of recommended maximum
magnet misalignment
8.2.4
Magnet Placement
The magnet’s center axis should be aligned within a displacement radius Rd of 0.25mm (larger magnets allow more displacement) from the
defined center of the IC.
The magnet may be placed below or above the device. The distance should be chosen such that the magnetic field on the die surface is within
the specified limits (see Figure 26). The typical distance “z” between the magnet and the package surface is 0.5mm to 1.5mm, provided the
recommended magnet material and dimensions (6mm x 3mm) are used. Larger distances are possible, as long as, the required magnetic field
strength stays within the defined limits.
However, a magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be indicated by an
alarm forcing the output into the failure band.
z
N
Package surface
Die surface
Die 1
0.561mm
±0.075mm
0.850mm
nom.
Die 2
0.234mm
±0.060mm
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0.608mm
±0.050mm
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Figure 27. Vertical Placement of the Magnet
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AS5263
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The device is available in a 32-pin QFN (7x7mm) package.
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Figure 28. Package Drawings and Dimensions
YYWWIZZ
Min
0.80
0
0.50
0º
0.23
Typ
0.90
0.02
0.65
0.20 REF
0.60
Max
1.00
0.05
1.00
0.75
14º
0.35
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0.28
7.00 BSC
7.00 BSC
0.65 BSC
6.75 BSC
6.75 BSC
4.80
4.80
0.15
0.10
0.10
0.05
0.08
0.10
32
4.90
4.90
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4.70
4.70
-
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Symbol
A
A1
A2
A3
L
Θ
b
D
E
e
D1
E1
D2
E2
aaa
bbb
ccc
ddd
eee
fff
N
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AS5263
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M1994.
2. All dimensions are in miilimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well as the
terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
Marking: YYWWIZZ.
YY
WW
I
ZZ
Last two digits of the Manufacturing Year
Manufacturing Week
Plant Identifier
Traceability Code
Note: IC’s marked with a white dot or the letters “ES” denote Engineering samples.
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AS5263
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision
Date
Owner
Description
1.0
May 31, 2010
apg/rfu
Initial version
Oct 14, 2010
1.2
rfu
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1.1
Updated Absolute Maximum Ratings, Operating Conditions, Magnetic Input
Specification, Electrical System Specifications, Figure 3, Table 5, Table 6,
Table 9, Table 10, Table 14, Table 15, page 31, Programming Procedure,
Figure 26, Figure 27, Package Drawings and Markings.
Deleted chapter on “Choosing the Proper Magnet”.
Dec 14, 2010
Updated Absolute Maximum Ratings, Package Drawings and Markings.
Jan 12, 2011
Updated Figure 26 and Figure 28. Removed “AS5263 Stacked Die
Technology” diagram.
mub
Apr 08, 2011
Updated Electrical System Specifications, Application Specific Angular Range
Programming.
1.4
May 11, 2011
Updated Programming Procedure.
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Note: Typos may not be explicitly mentioned under revision history.
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AS5263
Datasheet - O r d e r i n g I n f o r m a t i o n
10 Ordering Information
The devices are available as the standard products shown in Table 18.
Table 18. Ordering Information
Description
AS5263-HQFT, -HQFM
Redundant 12-bit Magnetic Rotary Encoder
Delivery Form
Package
Tape & Reel
32-pin QFN (7x7mm)
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
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Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
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Ordering Code
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For further information and requests, please contact us mailto: [email protected]
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS5263
Datasheet - C o p y r i g h t s
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
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Headquarters
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austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
ch
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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http://www.austriamicrosystems.com/contact
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