TSL1401CS-LF

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The technical content of this TAOS datasheet is still valid.
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
r
r
128 × 1 Sensor-Element Organization
400 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 4000:1 (72 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 8 MHz
Single 3-V to 5-V Supply
Rail-to-Rail Output Swing (AO)
No External Load Resistor Required
Available in a Solder-Bump Linear Array
Package
Lead (Pb) Free and RoHS Compliant
Description
1 SI
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HOLD 2
3 CLK
GND 4
5 GND
AO 6
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D
(TOP VIEW)
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D
D
D
D
D
D
D
D
D
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TAOS072E − APRIL 2007
The TSL1401CS−LF linear sensor array consists
of a 128 × 1 array of photodiodes, associated
charge amplifier circuitry, and a pixel data-hold
function that provides simultaneous-integration
start and stop times for all pixels. The pixels
measure 63.5 μm (H) by 55.5 μm (W) with
63.5-μm center-to-center spacing and 8-μm
spacing between pixels. Operation is simplified by
internal control logic that requires only a
serial-input (SI) signal and a clock.
7 SO
VDD 8
Functional Block Diagram
Pixel 1
Pixel
2
1 Integrator
Reset
2
2
Pixel
128
_
1
Output
Buffer
3
+
S2
Sample/Hold/
Output
CLK
SI
VDD
AO
GND
Switch Control Logic
Q1
3
6
4, 5
ni
ch
2
Te
Hold
8
Analog
Bus
ca
S1
Pixel
3
Q2
Q3
Q128
Gain
Trim
7
SO
128-Bit Shift Register
1
The LUMENOLOGY r Company
Copyright E 2007, TAOS Inc.
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972)
r 673-0759
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1
TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
Terminal Functions
TERMINAL
AO
DESCRIPTION
NO.
6
Analog output
CLK
3
Clock. The clock controls charge transfer, pixel output, and reset.
GND
4, 5
Ground (substrate). All voltages are referenced to the substrate.
HOLD
2
Hold signal. HOLD freezes the result of a 128 pixel scan.
SI
1
Serial input. SI defines the start of the data-out sequence.
SO
7
Serial output. SO provides a signal to drive the SI input of another device
for cascading or as an end-of-data indication.
VDD
8
Supply voltage. Supply voltage for both analog and digital circuits.
lv
Detailed Description
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NAME
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The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. The signal called Hold is normally connected to SI. Then,
the rising edge of SI causes a HOLD condition. This causes all 128 sampling capacitors to be disconnected from
their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift
register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output
amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel
integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge,
the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note
that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to
a known state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum
delay of tqt (pixel charge transfer time) after the 129th clock pulse.
ca
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm2)
is the incident irradiance in μW/cm2
is integration time in seconds
Te
ch
where:
Vout
Vdrk
Re
Ee
tint
ni
Vout = Vdrk + (Re) (Ee)(tint)
A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device.
The TSL1401CS−LF is intended for use in a wide variety of applications, including: image scanning, mark and
code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and
optical linear and rotary encoding.
Copyright E 2007, TAOS Inc.
2
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
Available Options
DEVICE
TSL1401CS−LF
TA
−40°C to 100°C
PACKAGE − LEADS
PACKAGE DESIGNATOR
Solder Bump − Lead Free − 8
ORDERING NUMBER
TSL1401CS−LF
Absolute Maximum Ratings†
†
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Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . −0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 100°C
Solder reflow temperature, case exposed for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
Supply voltage, VDD
MIN
NOM
MAX
3
5
5.5
UNIT
V
Input voltage, VI
High-level input voltage, VIH
0
VDD
V
2
VDD
V
Low-level input voltage, VIL
0
0.8
400
1000
Wavelength of light source, λ
Clock frequency, fclock
5
Sensor integration time, tint (see Note 1)
Setup time, serial input, tsu(SI)
0.03375
8000
kHz
100
ms
ca
20
Hold time, serial input, th(SI) (see Note 2)
ns
0
Operating free-air temperature, TA
−40
V
nm
ns
85
°C
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NOTES: 1. Integration time is calculated as follows:
tint (min) = (128 − 18) clock period + 20 ms
where 128 is the number of pixels in series, 18 is the required logic setup clocks, and 20 ms is the pixel charge transfer time (tqt)
2. SI must go low before the rising edge of the next clock pulse.
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 11 μW/cm2 (unless otherwise noted) (see Note 3 and Note 4)
TEST CONDITIONS
MIN
TYP
MAX
1.6
2
2.4
V
0.1
0.2
V
± 4%
± 10%
Analog output voltage (white, average over 128 pixels)
See Note 4
Vdrk
Analog output voltage (dark, average over 128 pixels)
Ee = 0
PRNU
Pixel response nonuniformity
See Note 5
Nonlinearity of analog output voltage
See Note 6
± 0.4%
Output noise voltage
See Note 7
1
Re
Responsivity
See Note 8
25
35
Vsat
Analog output saturation voltage
VDD = 5 V, RL = 330 Ω
4.5
4.8
VDD = 3 V, RL = 330 Ω
2.5
2.8
SE
Saturation exposure
DSNU
Dark signal nonuniformity
All pixels, Ee = 0
IL
Image lag
See Note 11
IDD
Supply current
IIH
High-level input current
IIL
Low-level input current
Ci
Input capacitance
0
136
FS
mVrms
44
V/
(μJ/cm 2)
V
nJ/cm 2
lv
VDD = 5 V, See Note 9
UNIT
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PARAMETER
Vout
VDD = 3 V, See Note 9
78
See Note 10
0.02
0.05
V
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0.5%
VDD = 5 V, Ee = 0
2.8
4.5
VDD = 3 V, Ee = 0
2.6
4.5
VI = VDD
VI = 0
mA
1
μA
1
μA
5
pF
ca
NOTES: 3. All measurements made with a 0.1 μF capacitor connected between VDD and ground.
4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
8. Re(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint)
9. SE(min) = [Vsat(min) − Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) − Vdrk(min)]
10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V out (IL) * V drk
IL +
100
V out (white) * V drk
Timing Requirements (see Figure 1 and Figure 2)
Setup time, serial input (see Note 12)
th(SI)
Hold time, serial input (see Note 11 and Note 13)
tw
ch
tr, tf
tqt
MIN
ni
tsu(SI)
MAX
UNIT
ns
0
ns
Pulse duration, clock high or low
50
Input transition (rise and fall) time
0
Pixel charge transfer time
NOM
20
20
ns
500
ns
μs
Te
NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
13. SI must go low before the rising edge of the next clock pulse.
Copyright E 2007, TAOS Inc.
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figures 7 and 8)
Analog output settling time to ± 1%
tpd(SO)
Propagation delay time, SO1, SO2
TEST CONDITIONS
RL = 330 Ω,
MIN
CL = 10 pF
TYPICAL CHARACTERISTICS
tqt
UNIT
ns
50
ns
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SI
Integration
MAX
120
lv
CLK
Internal
Reset
TYP
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PARAMETER
ts
18 Clock Cycles
tint
Not Integrating
Integrating
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
129 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
CLK
2
128
ni
tsu(SI)
SI
1
129
ca
tw
2.5 V
0V
5V
50%
0V
th(SI)
ch
5V
tpd(SO)
tpd(SO)
Te
SO
AO
ts
Pixel 1
The LUMENOLOGY r Company
Pixel 128
Figure 2. Operational Waveforms
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
TYPICAL CHARACTERISTICS
IDLE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
PHOTODIODE SPECTRAL RESPONSIVITY
4.0
VDD = 5 V
TA = 25°C
0.6
0.4
0.2
3.0
2.5
2.0
1.5
1.0
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Relative Responsivity
0.8
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IDD — Idle Supply Current — mA
3.5
lv
1
0.5
0
300
400
500
600 700 800 900
λ − Wavelength − nm
0
−40
1000 1100
−15
10
AVERAGE ANALOG OUTPUT VOLTAGE, DARK
vs
FREE-AIR TEMPERATURE
Average Analog Output Voltage, Dark — V
ca
tint = 5 ms
1.00
0.50
ni
1.50
tint = 2.5 ms
tint = 0.5 ms
ch
Average Analog Output Voltage, White — V
2.00
tint = 1 ms
−15
10
35
60
TA − Free-Air Temperature − °C
Te
0
−40
Copyright E 2007, TAOS Inc.
6
0.12
tint = 10 ms
2.50
85
Figure 4
AVERAGE ANALOG OUTPUT VOLTAGE, WHITE
vs
FREE-AIR TEMPERATURE
3.00
60
TA − Free-Air Temperature − °C
Figure 3
3.50
35
0.10
tint = 5 ms
0.08
0.06
0.04
0.02
85
0
−40
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 6
Figure 5
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
TYPICAL CHARACTERISTICS
SETTLING TIME
vs.
LOAD
Vout = 1 V
Settling Time to 1% — ns
400
220 pF
300
200
470 pF
400
220 pF
300
200
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100 pF
100
100
10 pF
0
Vout = 1 V
500
470 pF
0
VDD = 5 V
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500
Settling Time to 1% — ns
600
VDD = 3 V
lv
600
SETTLING TIME
vs.
LOAD
200
400
600
800
RL — Load Resistance − W
1000
0
0
100 pF
10 pF
200
400
600
800
RL — Load Resistance − W
Figure 8
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Figure 7
1000
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
APPLICATION INFORMATION
Power Supply Considerations
A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device.
Connection Diagrams
VDD
8
1
2
3
AO
1
6
TSL1401CS−LF
HOLD
CLK
2
SO
GND
4
5
C3
0.1 mF
8
VDD
SI
C2
0.1 mF
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C1
0.1 mF
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The HOLD pin on the device is normally connected to the SI pin in single-die operation. In multi-die operation
of n die, the HOLD pin is used to provide a continuous scan across the n die. See Figure 9 for an example of
this wiring configuration. Note that there is a single AO signal when used in this mode. Alternately, the individual
die may be scanned all at once by connecting the individual SI and HOLD lines and reading the AO signals in
parallel. See Figure 10 for an example of this wiring configuration.
GND
CLK
SI
3
7
VDD
SI
AO
1
6
TSL1401CS−LF
2
HOLD
CLK
SO
GND
3
7
VDD
SI
AO
6
TSL1401CS−LF
HOLD
CLK
4
5
AO
8
SO
GND
7
4
5
Figure 9. Multi-Die Continuous Scan
VDD
8
VDD
AO
3
1
6
TSL1401CS−LF
2
HOLD
ch
2
SI
ni
1
C2
0.1 mF
ca
C1
0.1 mF
CLK
SO
GND
Te
5
3
7
4
C3
0.1 mF
AO1
AO2
8
8
VDD
SI
AO
1
6
TSL1401CS−LF
2
HOLD
CLK
SO
GND
5
3
7
4
VDD
SI
AO
6
AO3
TSL1401CS−LF
HOLD
CLK
SO
GND
5
7
4
GND
CLK
SI
Copyright E 2007, TAOS Inc.
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Figure 10. Multi-Die Individual Scan
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
APPLICATION INFORMATION
Integration Time
The integration time of the linear array is the period during which light is sampled and charge accumulates on
each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature
of the TAOS TSL14xx linear array family. By changing the integration time, a desired output voltage can be
obtained on the output pin while avoiding saturation for a wide range of light levels.
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The integration time is the time between the SI (Start Integration) positive pulse and the HOLD positive pulse
minus the 18 setup clocks. The TSL14xx linear array is normally configured with the SI and HOLD pins tied
together. This configuration will be assumed unless otherwise noted. Sending a high pulse to SI (observing
timing rules for setup and hold to clock edge) starts a new cycle of pixel output and integration setup. However,
a minimum of (n+1) clocks, where n is the number of pixels, must occur before the next high pulse is applied
to SI. It is not necessary to send SI immediately on/after the (n+1) clocks. A wait time adding up to a maximum
total of 100 ms between SI pulses can be added to increase the integration time creating a higher output voltage
in low light applications.
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Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity
to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the
Functional Block Diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing
switch S1 (position 2).
At SI input, all of the pixel voltages are simultaneously scanned and held by moving S2 to position 2 for all pixels.
During this event, S2 for pixel 1 is in position 3. This makes the voltage of pixel 1 available on the analog output.
On the next clock, S2 for pixel 1 is put into position 2 and S2 for pixel 2 is put into position 3 so that the voltage
of pixel 2 is available on the output.
Following the SI pulse and the next 17 clocks after the SI pulse is applied, the S1 switch for all pixels remains
in position 2 to reset (zero out) the integrating capacitor so that it is ready to begin the next integration cycle.
On the rising edge of the 19th clock, the S1 switch for all the pixels is put into position 1 and all of the pixels begin
a new integration cycle.
The first 18 pixel voltages are output during the time the integrating capacitor is being reset. On the 19th clock
following an SI pulse, pixels 1 through 18 have switch S2 in position 1 so that the sampling capacitor can begin
storing charge. For the period from the 19th clock through the nth clock, S2 is put into position 3 to read the output
voltage during the nth clock. On the next clock the previous pixel S2 switch is put into position 1 to start sampling
the integrating capacitor voltage. For example, S2 for pixel 19 moves to position 1 on the 20th clock. On the n+1
clock, the S2 switch for the last (nth) pixel is put into position 1 and the output goes to a high-impedance state.
ni
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If a SI was initiated on the n+1 clock, there would be no time for the sampling capacitor of pixel n to charge to
the voltage level of the integrating capacitor. The minimum time needed to guarantee the sampling capacitor
for pixel n will charge to the voltage level of the integrating capacitor is the charge transfer time of 20 μs.
Therefore, after n+1 clocks, an extra 20 μs wait must occur before the next SI pulse to start a new integration
and output cycle.
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The minimum integration time for any given array is determined by time required to clock out all the pixels
in the array and the time to discharge the pixels. The time required to discharge the pixels is a constant.
Therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels
in the array. A slower clock speed increases the minimum integration time and reduces the maximum light level
for saturation on the output. The minimum integration time shown in this data sheet is based on the maximum
clock frequency of 8 MHz.
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
APPLICATION INFORMATION
The minimum integration time can be calculated from the equation:
T int(min) +
1
ǒmaximum clock
Ǔ
frequency
(n * 18)pixels ) 20ms
where:
is the number of pixels
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n
In the case of the TSL1401CS−LF with the maximum clock frequency of 8 MHz, the minimum integration time
would be:
T int(min) + 0.125 ms
lv
(128 * 18) ) 20 ms + 33.75 ms
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It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
It should be noted that the data from the light sampled during one integration period is made available on the
analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock
period. In other words, at any given time, two groups of data are being handled by the linear array: the previous
measured light data is clocked out as the next light sample is being integrated.
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Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
Copyright E 2007, TAOS Inc.
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
APPLICATION INFORMATION
PCB Pad Layout
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Suggested PCB pad layout guidelines for the TSL1401CS−LF solder bump linear array package is shown in
Figure 11.
2
3
4
5
6
7
8
170
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1
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8 360
Diameter
Metal Pad
8 380
Diameter
Mask
8 110
Trace Width
7 1000
NOTES: A. All linear dimensions are in micrometers.
B. This drawing is subject to change without notice.
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Figure 11. Suggested PCB Layout
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11
TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
MECHANICAL INFORMATION
The TSL1401CS-LF is available in a solder bump linear array package, ready for surface mount manufacturing
processes.
SOLDER BUMP LINEAR ARRAY
8870 25
TOP VIEW
1000 25
A
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8120
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Pixel 1
Pixel 128
SIDE VIEW
645 55
BOTTOM
VIEW
4
170
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Alignment Marker (Pin 8)
8
145 30
935 30
300 30
7
4
B
415 30
1000
DETAIL B
SI
HOLD
CLK
GND
GND
AO
SO
VDD
128
63.5
430.4 25
Glass Cover Thickness
400 50
375 25
128
55.5
ni
1
2
3
4
5
6
7
8
ch
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
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DETAIL A
127
63.5
50 Typ
Pb
Lead Free
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NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is ± 10 μm unless otherwise noted.
B. Solder bumps are formed of Sn (96.5%), Ag (3%), and Cu (0.5%).
C. The top of the photodiode active area is 415 μm below the glass that forms the top surface of the package. The index of
refraction of the glass is 1.52.
D. This drawing is subject to change without notice.
Figure 12. TSL1401CS−LF Solder Bump Linear Array Package
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
MECHANICAL INFORMATION
1.24 0.100
0.300 0.200
SIDE VIEW
1.5 0.100 Typ
4 0.100 Typ
2 0.100
Pin 1
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1.75 0.100
4 0.100
TOP VIEW
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A
7.50
0.100
16
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CL
+ 0.300
− 0.100
A
R 0.58
B
DETAIL A
B
DETAIL B
Ko
9.17
0.82
Bo
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8 Max
1.29
Ao
1.17
5 Max
ch
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NOTES: A.
B.
C.
D.
E.
F.
G.
7.60
All linear dimensions are in millimeters.
The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001.
Each reel is 178 millimeters in diameter and contains 2800 parts.
TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
This drawing is subject to change without notice.
Figure 13. TSL1401CS−LF Solder Bump Linear Array Package Carrier Tape
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13
TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
MANUFACTURING INFORMATION
This product, in the solder bump linear array package, has been tested and has demonstrated an ability to be
reflow soldered to a PCB substrate. The process, equipment, and materials used in these tests are detailed
below.
Tooling Required
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D Solder stencil (round aperture size 0.36 mm, stencil thickness of 152.4 μm)
D 20 × 20 frame for solder stencil
Process
1. Apply solder paste using stencil
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2. Dispense adhesive dots
3. Place component
5. X-Ray verify
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4. Reflow solder/cure
Placement of the TSL1401CS−LF device onto the gold immersion substrate is accomplished using a standard
surface mount manufacturing process. First, using the stencil with 0.36 mm square aperture, print solder paste
onto the substrate. Next, dispense two 0.25 mm to 0.4 mm diameter dots of adhesive in opposing corners of
the TSL1401CS−LF mounting area. Machine place the TSL1401CS−LF from the JEDEC waffle carrier onto the
substrate. A suggested pick-up tool is the Siemens Vacuum Pickup tool nozzle number 912. This nozzle has
a rubber tip with a diameter of approximately 0.75 mm. The part is picked up from the center of the body. Reflow
the solder and cure the adhesive using the solder profile shown in Figure 14.
The reflow profiles specified here describe expected maximum heat exposure of components during the solder
reflow process of product on a PWB. Temperature is measured at the top of component. The components
should be limited to one pass through the solder reflow profile used.
Table 1. TSL1401CS−LF Solder Reflow Profile
PARAMETER
REFERENCE
TSL1401CS−LF
Average temperature gradient in preheating
tsoak
2 to 3 minutes
Time above T1, 217°C
t1
Max 60 sec
Time above T2, 230°C
t2
Max 50 sec
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Soak time
2.5°C/sec
Time above T3, (Tpeak −10°C)
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Peak temperature in reflow
t3
Max 10 sec
Tpeak
260°C (−0°C/+5°C)
Max −5°C/sec
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Temperature gradient in cooling
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
MANUFACTURING INFORMATION
Tpeak
Not to scale — for reference only
T3
T2
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Temperature (C)
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T1
Time (sec)
t3
t2
tsoak
t1
Figure 14. TSL1401CS−LF Solder Bump Linear Array Package Solder Profile
It is important to use a substrate that has an immersion plating surface. This may be immersion gold, silver, or
white tin. Hot air solder leveled substrates (HASL) are not coplanar and should not be used.
Qualified Equipment
D EKRA E5 — Stencil Printer
D ASYMTEC Century — Dispensing system
D SIEMENS F5 — Placement system
− SIEMENS 912 — Vacuum Pickup Tool Nozzle
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D VITRONICS 820 — Oven
D PHOENIX — Inspector X-Ray system
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Qualified Materials
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D OMG — Microbond solder paste
D Loctite 3621 — Adhesive
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15
TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
MANUFACTURING INFORMATION
Moisture Sensitivity
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Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package molding compound. To ensure the
package molding compound contains the smallest amount of absorbed moisture possible, each device is
dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica
gel to protect them from ambient moisture during shipping, handling, and storage before use.
Temperature Range
Relative Humidity
Floor Life
5°C to 50°C
60% maximum
1 year out of bag at ambient < 30°C / 60% RH
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This package has been assigned a moisture sensitivity level of MSL 2 and the devices should be stored under
the following conditions:
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Rebaking will be required if the aluminized envelope has been open for more than 1 year. If rebaking is required,
it should be done at 90°C for 3 hours.
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TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E − APRIL 2007
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
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Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
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Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
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TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
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LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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17
TSL1401CS−LF
128 × 1 LINEAR SENSOR ARRAY WITH HOLD
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TAOS072E − APRIL 2007
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