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is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
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Preliminary Datasheet AS3510
Analog
Audio
Front-End
Analog
Voice
Codec
AS3510
AS14889
DATA SHEET
PRELIMINARY DATA
SHEET
CONFIDENTIAL
General Description
Key Features
On chip DCDC Converter
This codec-chip contains a high performance 18 bit digital
to analog converter. The dynamic range exceeds 95dB for
best audio quality, for multi media applications (audio
playback) within battery or line operated equipment.
4 On-chip high performance voltage regulators
-
An additional audio power amplifier can directly drive
-
external headphones or small 4Ω speakers with a power of
up to half a watt. The power-up is click- and pop-less due to
a smooth start-up circuitry. The overall distortion level is
always below 0.02%.
18 Bit stereo DAC
-
-
Digital Supply, 2.9V
Analog Supply, 2.9V
Core Supply, 1.5 to 2.5V
USB Transceiver Supply, 3.2V
Dynamic range >95 dB
THD < -85dB
De-emphasis for 32 kHz, 44.1 kHz and 48 kHz
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1.0 to 5.5V input voltage range
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The AS3510 combines high flexibility and outstanding
performance for analog audio front-end solutions.
The microphone input amplifier contains an automatic gain
control (AGC) with a dynamic range of 40dB to generate an
amplified and compressed signal for the ADC, which
provides 14 Bit resolution at 8kHz sampling-rate.
Furthermore all necessary power management is included
such as bandgap reference and four voltage regulators. The
two 2.9V regulators are used internally (analog and digital
supply), but can also be used for external purposes as well.
The third output is designed to supply the peripheral cells
and an external digital core, and is programmable from 1.5V
to 2.5V in 5 steps (default is 2.5V). They are all powered
through a DCDC-Converter, which can work down to a
voltage of 1V. So the whole chip can work from a single
battery cell.
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The fourth regulator is only used for generating the supply
voltage for the analog USB 1.1 interface circuit. It is
supplied via the USB connector. The performance of the
regulators is excellent (noise, line- and load-regulation) and
allows the direct supply of sensitive analog circuits.
-
Stereo power audio amplifier
-
Max. 2x 0.5W @ 4Ω
Analog volume control –39dB to +3dB, 3dB steps
including mute)
Click- and pop-less startup and power down
Auxiliary inputs for additional audio sources
Microphone input
-
-
14 Bit Σ∆−ADC , 8kHz sampling rate
Automatic gain control (AGC)
Low power consumption
Wide battery supply range 1.0V – 5.5V
Standard I2S interface
Audio sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32,
44.1, and 48 kHz
I2C control interface
USB 1.1 front-end
49 Pin BGA Package
Applications
The current consumption is very low and makes the chip
ideally for battery powered devices.
-
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Because of the internal supply and signal filtering only few
small external capacitors are required for de-coupling and
stabilising and lead to very low output noise.
Rev. 1v2, June 2004
-
CONFIDENTIAL
Audio frontend for cellular phones
Stand alone MP3 player
CD and DVD player
PDAs
Page 1 of 19
-
SDA
-
SDI
-
-
SCLK
SCL
-
LRCK
Control
Interface
(I2C Slave)
Serial Audio
Interface (I2S)
&
Clock Generation
OEN
RCV
USB Connector
X
X
AUXL
Single Ended to
Differental
Converter
X
X
AUXR
DAC +
SC LPF
DAC +
SC LPF
-
UVDD
µP USB Interface
D+
VTRM
D-
USB 1.1 + LDO3.2V
-
-
Multibit SD Modulator
with DWA
VM
-
MCLK
Interpolator
*64
VP
-
Digital I2S
Synchronisation
VMO
-
-
VPO
-
SDO
Dither Generation
-
-
Multibit SD Modulator
with DWA
-
DVSS
Interpolator
*64
-
2nd Order
SD ADC
14Bit, 8kHz
+ Interpolator
-
Referenze Voltage &
Current Generation
-
VTRM
-
Microphon
Amplifier
AVSS2
-
BVDD
VSS
BVSS
DCDC Converter
Gain Control
+3...-39dB
Left Power
Amplifier
BVDD
BVSS
Right
Power Amplifier
Gain Control
+3...-39dB
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AVSS
-
-
VREF
-
-
AGND
10u
-
MICN
100n
-
MICP
10u
1 to 5.5V
Battery
VBAT1V SW
-
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100n
BVDD
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CONFIDENTIAL
LDO2
ENDCDC
AVSS
BVDD
Pop-less
Startup
AVSS
BVDD
ENLDO12
LDO3
BVSS
BVDD
LDO1
-
AVDD
PLDO3
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AVSS
BVDD
BGND Buffer
-
Rev. 1v2, June 2004
µP Digital Audio Interface
-
Figure 1
-
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BVDD
OUTR
BVSS
OUTL
-
-
-
-
2,2u / 6,3V
Z5U
V_REG3
2,2u with
RL=150 Ohm,
or 330u with
RL=8 Ohm
Headphone
Jack
c2,2u with
RL=150 Ohm,
or 330u with
RL=8 Ohm
QLDO3
PVDD
QLDO2
DVDD
-
-
2,2u / 6,3V
Z5U
2,9V, 50mA
@ BVDD=3V
V_REG2
2,2u / 6,3V
Z5U
1,75V to 2.5V, 200mA @ BVDD=3V
BGND
-
-
QLDO1
V_REG1
2,9V, 50mA @ BVDD=3V
Product Brief AS3510
Block Diagram
µP Control
Interface
Block Diagram of AS3510
Page 2 of 19
Product Brief AS3510
Modes of Operation
Inputs
LDO-Modes
ENLDO3
L
ON_12
H
L
ON_123
H
H
Outputs
DVDD, AVDD
PVDD
LDO1, LDO2 are OFF
LDO3 is OFF
2.8–3.6V supply fr. Ext.
1.75-3.6V supply fr. Ext.
LDO1, LDO2 are ON
LDO3 is OFF
Output is 2.9Vtyp
1.75-3.6V supply fr. Ext.
or connected to DVDD
LDO1, LDO2 are ON
LDO3 is ON
Output is 2.9Vtyp
Output 2.5Vtyp
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Table 1
OFF
ENLDO12
L
LDO Operating Modes
-
1.
2.
3.
4.
5.
6.
BVDD as input to the LDO regulators has to be >=3.0V.
DVDD - AVDD max. difference of 100mV.
PVDD has to be lower or equal to DVDD.
LDO1 is to be used for regulating AVDD (connect pin 25 to pin 26)
LDO2 output is internaly connected to DVDD (pos. digital supply)
LDO3 output is internaly connected to PVDD (pos. peripheral supply)
DAC-Modes
OFF
DAC_ON
Nodes:
-
Gain3:0
LLLL
LLLL
LLLH
.
.
HHHH
TriState
TriState
Stereo audio output
with PowerAmp gain adjusted
in 3dB steps by GAIN(3:0)
DAC Operating Modes
During supply voltages settling at system start-up GAIN(3:0) should be held “L”.
The MCLK frequency ratio to LRCK is permanently checked. If the ratio is different to 128, the DAC goes in Reset-Mode (no
audio will betransferred).
MCLK rising edge should not be within +/-10ns of LRCK edges.
Capacitors at VREF, AGND and BGND are needed for the DAC operation.
The SCLK has to have at least 34 or 38 cycles within one LRCK cycle
2*(16bit data + the leading empty bit) or 2*(18bit data + the leading empty bit)
There can be more SDI bits presented but just the first 18 bits are transferred.
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L
X
LRCK up to 50kHz
MCLK … 128*F(LRCK)
SCLK L=>H strobes SDI
SCLK … >=38*F(LRCK)
SDI left justified with MSB first
at 2 nd SCLK edge
LRCK up to 50kHz
MCLK … 128*F(LRCK)
SCLK L=>H strobes SDI
SCLK … >=38*F(LRCK)
SDI left justified with MSB first
at 2 nd SCLK edge
Outputs
OUTR, OUTL
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Table 2
DACPD
H
L
Inputs
I2S
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AUDIO_ON
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Nodes:
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Rev. 1v2, June 2004
CONFIDENTIAL
Page 3 of 19
Product Brief AS3510
ADC-Modes
Inputs
I2S-Clocks
ENADC
MICP/MICN
Output
SDO
LRCK, SCLK,MCLK
OFF
L
X
X
static L
ADC_ON
H
LRCK up to 50kHz
Differential analog
input
SDI serial data output
SCLK … >=34*F(LRCK)
Table 3
ADC Operating Modes
Nodes:
-
There are 16bit presented at SDO at each cycle but just the first 14 do have relevalt data.
The ADC is a single channel (mono) path. The same SDO bitstream is presented for left and right channel of one cycle.
The ADC sampling rate is equal to LRCK/4. This means that the SDO bitstream gets updated at each 4 th cycle of LRCK.
SCLK has to have at least 34 cycles within one LRCK cycle
2*(16bit data + the leading empty bit)
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Ieft justified to LRCK with
MSB first at 2 nd SCLK
edge
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to be converted to
digital output
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MCLK … 128*F(LRCK)
Rev. 1v2, June 2004
CONFIDENTIAL
Page 4 of 19
Product Brief AS3510
Functional Description
Audio DAC
Block Description
Signal Description
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Setting DACPD to ´1´ forces the analog section to powerdown. For Normal-Operation the I2S signals have to be
applied as shown below:
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MCLK
LRCK
SCLK
SDATA(16)
SDATA(18)
Figure 2
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sample rate. Optionally, a dither signal can be added that
may reduce eventual noise tones at the output. However,
the use of a multibit delta-sigma modulator already
provides extremely low noise tone energy.
This block is the complete audio DAC delivering 93dB
dynamic range. It is comprised of a multibit sigma-delta
modulator with dither option and a switched-capacitor
analog filter. This architecture provides a high insensitivity
to clock jitter. A digital interpolation filter increases the
sample rate by a factor of 8 using 3 linear phase, half-band
filters cascaded, followed by a first order SINC interpolator
with a factor of 8. This filter eliminates the images of
baseband audio remaining only the image at 64* the input
64 MCLK cycles
64 MCLK cycles
Left Channel
Right Channel
15
0
17
2
1
0
15
0
17
2
1
0
I2S Waveforms
The LRCK defines if the transferred data is for the left or
right channel (L=left).
If the dataword length is less than 18 bit, zeros have to be
added to avoid any offset value.
With the rising edge of the serial clock SCLK, the
inputdata gets strobed.
The frequency of master clock MCLK has to be 128 times
the input sample rate (F(LRCK)*128) with low jitter. The
rising edge of MCLK should be separated by >10ns from
LRCK edges.
hex value
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The data word at SDATA is max. 18 bit with MSB first and
2 nd complement coded. All I2S signals change state with
falling edge of SCLK.
Max. positive code
00000 (hex)
-1
3FFFF (hex)
Max. negative code:
20000 (hex)
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00001 (hex)
0
I2S Code Values
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Table 4
1FFFF (hex)
+1
Rev. 1v2, June 2004
There are 2 pins needed for the generation and decoupling
of reference-voltages for the DAC. AGND is AVDD/2 and
VREF is equal to AVDD. Both pins have high output
resistance which provides a suitable lowpass filter for
these reference voltages with external capacitors of 10uF
in parallel with 100nF.
The supply lines are separate for digital DVSS / DVDD and
analog AVSS / AVDD to minimise coupling influences.
The analog output is differential stereo signal at nodes
OUTRN, OUTRP and OUTLN, OUTLP respectively.
CONFIDENTIAL
Page 5 of 19
Product Brief AS3510
Byte 0 (default value: 0x80h)
Name
DITH
6..5
DacON
4
LP4/16
3..0
Gain
Description
dither enable
1: enable (default)
0: disable
11: Audio DAC is switched on
10: Audio DAC is switched on
01: Audio DAC is switched off
00: automatic mode, DAC is on only
when I2S interface is active
audio amplifier load switch
1: low power mode for speakers
with more than 16 Ohm.
0: normal mode, 4 Ohm loads
possible
gain settings for audio amplifier
from –39dB to +3dB in steps of 3dB
1111: full output swing: +3dB
1110: 0dB
.
0010: -36dB
0001: minimum output swing: -39dB
0000: mute
Bit
7..6
Name
Iaudio
5..4
Idac
3..1
0
MCLK#
Table 7 – Software I2C Byte 2
Byte 3 (default value: 0x11h)
Bit
7..4
3
1..2
0
Table 5 – Software I2C Byte 0
Byte 1 (default value: 0x10h)
5
USBspN
4
3
PwUphld
AUXen
2
ADCen
Description
not used
not used
not used, must be set to 000
1: only 18bit data are accepted
0: also less than 18 bit can be sent
to the I2S interface and are shifted
internal
Table 8 – Software I2C Byte 3
Description
not used
1: doubles the sampling ADC freq.
0: normal ADC sampling frequnecy
1: normal USB operation
0: suspend USB
0: switch off
1: enable AUX inputs
0: disable AUX inputs
1: ADC enable for microphone input
0: ADC disable
gain settings for microphone
amplifier
11: 40dB
10: 40dB
01: 34dB
00: 28dB
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Name
Fadc2
Name
Version
I2Sdir
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Bit
7
6
Description
audio amplifier supply current
11: 50%
10: 66%
01: 83%
00: 100% (default)
audio DAC supply current
11: 50%
10: 60%
01: 75%
00: 100% (default)
not used, must be set to 000
1: DAC uses inverted MCLK
0: DAC uses normal MCLK
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Bit
7
Byte 2 (default value: 0x01h)
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The interface is a standard I2C slave interface (write only).
The system uses address group 8 address 41h for audioprocessors. The following table shows the various control
options.
The PowerUp hold (PwUphld; Bit 4) is when an high pulse
on the PowerUp pin occures. To switch of the AS3520 the
PwUphld bit must be cleared.
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Control Interface
MicGain
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1..0
Table 6 – Software I2C Byte 1
Rev. 1v2, June 2004
CONFIDENTIAL
Page 6 of 19
Product Brief AS3510
Power Amplifier
Block Description
The Power Amplifier Block converts the differential output
signals from the AudioDAC into single ended signals with
With I2S data giving full-scale swing, clipping will occur with
the max. gain-step. With min. BVDD of 3.0V the same is
true for the two highest gain-steps.
When the control signals Gain(3:0) are all set to “L”, the
block is set to power-down.
With the conversion from differential to single ended, the
transformation of DC level from AGND (=AVDD/2) to BGND
(=BVDD/2) is done. The gain of this driver stage can be set
by 4 digital input signals in the range from –39dB to +3dB in
steps of 3dB. With the maximum gain of +3dB, full scale
gives 4.95Vpp at the single ended output.
There is a BGND generation, which needs an external
capacitor of 100nF for blocking of low frequency
components at BVDD. With this external capacitor, a so
called “Klickless On” is performed so that at power-up, the
output terminals have a smooth startup to avoid any
transient noise in the headphone.
Gain
difse
FS Swing
Gain
(3:0)
Gain
difse
FS
Swing
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Gain
(3:0)
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the drive capability for impedances ≥4 ohms.
H
H
H
+3dB
4.95Vpp
L
H
H
H
-21dB
309mVpp
H
H
H
L
0dB
3.50Vpp
L
H
H
L
-24dB
219mVpp
H
H
L
H
-3dB
2.47Vpp
L
H
L
H
-27dB
155mVpp
H
H
L
L
-6dB
1.75Vpp
L
H
L
L
-30dB
109mVpp
H
L
H
H
L
H
H
L
L
H
L
L
H
-9dB
1.24Vpp
L
L
H
H
-33dB
77mVpp
L
-12dB
0.87Vpp
L
L
H
L
-36dB
55mVpp
H
-15dB
0.62Vpp
L
L
L
H
-39dB
39mVpp
L
-18dB
0.44Vpp
L
L
L
L
OFF
-
Table of Gain Steps
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Table 9
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Rev. 1v2, June 2004
CONFIDENTIAL
Page 7 of 19
Product Brief AS3510
Supply Regulator
Block Description
This block can be used to provide three regulated supply
voltages for the
-
Vout is 2.9V for LDO1 and LDO2. The output Voltage for
LDO3 can be programmed via the PLDO3 pin.
on_chip digital section
on_chip analog section
external circuit (uP, DSP…)
from the battery supply BVDD which is directly used by the
power_amplifier.
The LDO1 and LDO2 do have the capability to drive 50mA
with a voltage drop of <=50mV (1Ohm). Since the nominal
output voltage for these LDOs is 2.9V (+/-50mV), a
regulation can be done with BVDD as low as 3.0V.
QLDO3 voltage
VSS
2.25V
150k to VSS
2.0V
open
2.5
150k to DVDD
1.5
DVDD
Table 10
1.75
LDO3 Programming
There are two pads at each LDO, one is the LDO output pad
and the second is the corresponding chip supply pad, which
are bonded to the same pin (LDO1 only), and have external
blocking caps (Cblock with low ESR).
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The LDO3 is used to generate a supply voltage PVDD for
the peripheral cells and external digital circuits, which are
controlling the inputs of the AS3510. The drive capability is
PLD3 pin
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(BVDD −(Vout +50mV )
1Ohm
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I max =
≥200mA with a BVDD≥3V.
If supply should not be generated from the on_chip LDOs,
these blocks can be disabled with control pin PowerUP.
AVDD, DVDD and PVDD can then be forced from external
regulators.
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The maximum output currents for these LDOs can be
calculated using the following equation:
Rev. 1v2, June 2004
CONFIDENTIAL
Page 8 of 19
Product Brief AS3510
Microphone Path
Block Description
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The fullscale ADC input range is 1.157Vp differential with
AVDD=2.9V.
The softclip references are +/-0.434V which gives a
useable ADC-range of 0.868Vp differential. This gives a
nominal mic input voltage range of 34.72 / 17.36 / 8.68mVp
or 24 /12 / 6mVrms for the three micamp gain settings.
SoftClip is done with 15 steps of –1dB.
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For LRCK=48kHz MCLK=6.144MHz, the ADC
conversion rate will be 12kHz. Due to this synchronisation
the transfer of the ADC data is possible with just one extra
digital output pin which makes the digital interface very
efficient.
The microphone amplifier can be programmed to three
different gain values 28dB/ 34dB/ 40dB to adjust the circuit
to the used microphone. The microphone amplifier includes
a softclip function that reduces the gain when the input
voltage range of the ADC is violated.
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This block converts a differential microphone signal into
digital and does a synchronisation to the DAC I2S input
clocks. The SigmaDelta converter clock gets derived from
MCLK. For LRCK=32kHz MCLK=4.096MHz, the
SD_CLK is 1.024MHz which gives with decimation to 14 bit
a sampling rate of 8kHz. Since the I2S signals for the DACpath is 4 times higher, each ADC-output-code will be
presented 4 times in both channels (left, right) the same.
Rev. 1v2, June 2004
CONFIDENTIAL
Page 9 of 19
Product Brief AS3510
Specifications
Electrical Characteristics
Absolute Maximum Ratings
MAX
5.0
7.0
7.0
5.0
5.0
5.0
0.5
UNIT
V
V
V
V
V
V
V
Vin
-0.5
AVDD+0.5
V
Input Current (latchup immunity)
Electrostatic Discharge
Storage Temperature
Soldering conditions
Vin
-0.5
5.0
V
Vin
-0.5
BVDD+0.5
V
Vin
-0.5
5.0
V
Vi
-0.5
DVDD+0.5
V
Iscr
-100
Tstrg
-55
100
1
125
240
mA
kV
OC
OC
85
%
T lead
Humidity non-condensing
Table 11
Note
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MIN
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
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SYMBOL
VBAT1.0
BVDD
UVDD
AVDD
PVDD
DVDD
xVSS
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PARAMETER
DCDC Input Supply Voltage
Battery Input Supply Voltage
USB Input Supply Voltage
AVDD Input Supply Voltage
PVDD Input Supply Voltage
DVDD Input Supply Voltage
Voltage between VSS-Terminals
VSS_DCDC, BVSS, AVSS, DVSS
Voltage at pins:
PowerUp, PLDO3, MICP, MICN,
VREF, AGND, BGND, QLDO3,
QLDO2, SW
Voltage at pins:
CSCL, CSDA
Voltage at pins:
AUXL, AUXR, OUTL, OUTR
Voltage at pins:
VTREM, DP, DM
All other digital input pins
5
no diode to DVDD
HBM, IEC61000-4-2
IEC61760-1
Table of Absolute Maximum Ratings
Operating Conditions
SYMBOL
AVDD
DVDD
PVDD
BVDD
VBAT1.0
UVDD
MIN
2.8
2.8
1.5
3.0
1.0
4.0
-20
TYP
2.9
2.9
3.2
1.5
5.0
25
MAX
3.6
3.6
2.5
5.5
3.6
5.5
85
UNIT
V
V
V
V
V
V
C
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PARAMETER
Analog Input Supply Voltage
Digital Input Supply Voltage
Digital Core Input Supply Voltage
Battery Input Supply Voltage
DCDC Input Supply Voltage
USB Input Supply Voltage
Ambient Temperature
Table of Operating Conditions
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Table 12
Rev. 1v2, June 2004
CONFIDENTIAL
Page 10 of 19
Product Brief AS3510
Block Characteristics
Overall
SUPPLY
AVDD (AVDD = 2.9 V)
DVDD analog (DVDD = 2.9V)
IDD in Power Down
TYP
2.6
4.5
<1
MAX
9
8.5
10
UNIT
mA
mA
uA
MIN
TYP
MAX
UNIT
-85
93
-75
90
dB
dB
dB
Table of Overall Block Characteristics
Table 14
Table of AudioDAC Block Characteristics
Power Amplifier
PARAMETER
ANALOG PERFORMANCE
R_Load at AOUTR and AOUTL differential
R_Load at AOUTR and AOUTL single ended
Gain Step Precision (RLmin-max,20Hz-20kHz)
MIN
THD @ 1kHz, BVDD=3-5V, Gain=8, no Load
PSRR (200Hz-20kHz)
IOUT_powerdown
Tpower_up (Cbgnd=100nF)
60
-20
TYP
MAX
UNIT
±0.5
±
Ohm
Ohm
dB
-
0.03%
20
8
4
200
%
dB
uA
ms
Table of Power Amplifier Block Characteristics
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Table 15
0.25
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PARAMETER
ANALOG PERFORMANCE
THD+Noise at –1dB_FS
Dynamic Range (20Hz-20kHz, -60dBFS)
Interchannel Mismatch
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AudioDAC
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Table 13
MIN
Rev. 1v2, June 2004
CONFIDENTIAL
Page 11 of 19
Product Brief AS3510
Supply Regulator
-
-
TYP
MAX
UNIT
2.15
2.0
100
-
V
V
mV
4.1
3.91
50
-
kHz
kHz
us
Table of Supply Regulator Block Characteristics
Microphone Path
TYP
30
28
34
40
15*1.0
39
80
24
12
6
128
14
71
tbd
MAX
UNIT
kohm
dB
dB
dB
dB
us/st
ms/st
mVrms
mVrms
mVrms
bit
dB
dB
Table of Microphone Path Block Characteristics
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Table 17
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PARAMETER
ANALOG PERFORMANCE
Rinp_dif (MICP, MICN)
Gain_MicAmp_0
Gain_MicAmp_1
Gain_MicAmp_2
SoftClip_AGC_Range
Attack_Time
Release_Time
MIC vin full scale_0 (AVDD=2.9V)
MIC vin full scale_1 (AVDD=2.9V)
MIC vin full scale_2 (AVDD=2.9V)
Decimation Rate
ENOB
SNR
PSRR
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Table 16
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PARAMETER
POR PERFORMANCE
DVDD_POR_OFF
DVDD_POR_ON
POR_ON/OFF_HYST
LRCK WATCHDOG with DVDD=2.9V
F(LRCK)_WD_OFF
F(LRCK)_WD_ON
ON_Delay
Rev. 1v2, June 2004
CONFIDENTIAL
Page 12 of 19
Product Brief AS3510
Measurements
The following measurement curves are the results from
noise measurements on the AS3510 DAC.
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TA.: 25C, Vdd: 2.9V, Signal: 1kHz, 0dB FS , Clk:128*48kHz
Figure 3
SINAD Measurement at 0dBFS
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TA.: 25C, Vdd: 2.9V, Signal: 1kHz, -20dB FS , Clk:128*48kHz
Figure 4
SINAD Measurement at -20dBFS
Rev. 1v2, June 2004
CONFIDENTIAL
Page 13 of 19
Product Brief AS3510
Package and Pinning
Pin Configuration for TQFP80
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Table 18
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Function
Neg. supply of digital circuit
Supply of peripheral levelshifter of digital inputs
Pos. supply of digital circuits
Master clock 128*FS / left open - enables PLL
I2S_Left/Right FrameClock = FS
I2S_Serial data clock >=38*FS
I2S_Serial data 18bit left oriented, first bit fix L
I2Ccomp_Serial clock to access control register
I2Ccomp_Serial data to access control register
I2S_Serial data 14bit left orieted, first bit fix L
USB_indication of usb supply present
USB_differential receiver output
USB_signle ended pos. receiver output
USB_signle ended neg. receiver output
USB_transmitter pos. input
USB_transmitter neg. input
USB_transmitter output enable (low active)
Neg. supply of digital circuit
USB_pos. I/O terminal
USB_neg. I/O terminal
USB_3.2V termination voltage regulator output
USB_external supply 4-5.5V
Analog aux input to audio amp Right channel
Analog aux input to audio amp Left channel
Enable LDO1 and 2 and DCDC
Selects one of 5 LDO3 states (L, 150kpd open, 150kpu, H)
Microphone pos. input (MIC-ADC path)
Microphone neg. input (MIC-ADC path)
Reference voltage of DAC (AVDD)
Reference voltage of DAC (AVDD/2)
Neg. supply terminal of analog circuit
2 nd Neg. supply terminal of analog circuit
Pos. supply of analog circuits, LDO1 output – 2.9V
Reference voltage of power-amp (BVDD/2)
Battery supply 3-5.5V
Speaker/Headphone output (4 ohm min.)
Neg. supply terminal of Power Amp.
Speaker/Headphone output (4 ohm min.)
Battery supply 3-5.5V
LDO2 output – 2.9V to be connected to DVDD
LDO3 output – 1.5…2.5V to be connected to PVDD
Power Ground for DCDC Converter
Power Ground for DCDC Converter
Switch Output for DCDC Converter
Switch Output for DCDC Converter
Battery Supply Input (1V-3V)
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Type
Supply
Supply
Supply
Din with pull down
Din with pull down
Din with pull down
Din with pull down
Din stt + spike supr
Di/od stt + spike supr
Dout_2mA
Dout_2mA
Dout_2mA
Dout_2mA
Dout_2mA
Din with pull down
Din with pull down
Din with pull up
Supply
Di/o with 1uA pd
Di/o with 1uA pd
Aout/Supply
Supply
Ain 40/200k to BGND
Ain 40/200k to BGND
Din 360k pull down
Din_5state
Ain 15k to agnd
Ain 15k to agnd
Ai/o 10uF decpl
Ai/o 10uF decpl
Supply
Supply
Aout/Supply
Ai/o 100nF decp
Supply
Aout
Supply
Aout
Supply
Aout
Aout
Supply
Supply
Aout
Aout
Supply
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PinName
DVSS
PVDD
DVDD
MCLK
LRCK
SCLK
SDI
CSCL
CSDA
SDO
USBon
RCV
VP
VM
VPO
VMO
OEN
DVSS
DP
DM
VTRM
UVDD
AUX_R
AUX_L
PWRUP
PLDO3
MICP
MICN
VREF
AGND
AVSS
AVSS2
AVDD
BGND
BVDD
OUTR
BVSS
OUTL
BVDD
QLDO2
QLDO3
VSSDCDC
VSSDCDC
SWDCDC
SWDCDC
VB1V
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Pin#
25
27
28
29
31
32
33
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
64
65
66
67
68
69
70
71
72
73
74
75
76
77
Table of Pin Configuration for TQFP80
Rev. 1v2, June 2004
CONFIDENTIAL
Page 14 of 19
Product Brief AS3510
Pin Configuration for CABGA 49
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Function
Neg. supply of digital circuit
Supply of peripheral levelshifter of digital inputs
Pos. supply of digital circuits
Master clock 128*FS / left open - enables PLL
I2S_Left/Right FrameClock = FS
I2S_Serial data clock >=38*FS
I2S_Serial data 18bit left oriented, first bit fix L
I2Ccomp_Serial clock to access control register
I2Ccomp_Serial data to access control register
I2S_Serial data 14bit left orieted, first bit fix L
USB_indication of usb supply present
USB_differential receiver output
USB_signle ended pos. receiver output
USB_signle ended neg. receiver output
USB_transmitter pos. input
USB_transmitter neg. input
USB_transmitter output enable (low active)
Neg. supply of digital circuit
USB_pos. I/O terminal
USB_neg. I/O terminal
USB_3.2V termination voltage regulator output
USB_external supply 4-5.5V
Analog aux input to audio amp Right channel
Analog aux input to audio amp Left channel
Enable LDO1 and 2 and DCDC
Selects one of 5 LDO3 states (L, 150kpd open, 150kpu, H)
Microphone pos. input (MIC-ADC path)
Microphone neg. input (MIC-ADC path)
Reference voltage of DAC (AVDD)
Reference voltage of DAC (AVDD/2)
Neg. supply terminal of analog circuit
Pos. supply of analog circuits, LDO1 output – 2.9V
Reference voltage of power-amp (BVDD/2)
Battery supply 3-5.5V
Speaker/Headphone output (4 ohm min.)
Neg. supply terminal of Power Amp.
Speaker/Headphone output (4 ohm min.)
Battery supply 3-5.5V
Power Ground for DCDC Converter
Power Ground for DCDC Converter
Switch Output for DCDC Converter
Switch Output for DCDC Converter
Battery Supply Input (1V-3V)
not connected
not connected
not connected
not connected
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Table 19
Type
Supply
Supply
Supply
Din with pull down
Din with pull down
Din with pull down
Din with pull down
Din stt + spike supr
Di/od stt + spike supr
Dout_2mA
Dout_2mA
Dout_2mA
Dout_2mA
Dout_2mA
Din with pull down
Din with pull down
Din with pull up
Supply
Di/o with 1uA pd
Di/o with 1uA pd
Aout/Supply
Supply
Ain 40/200k to BGND
Ain 40/200k to BGND
Din 360k pull down
Din_5state
Ain 15k to agnd
Ain 15k to agnd
Ai/o 10uF decpl
Ai/o 10uF decpl
Supply
Aout/Supply
Ai/o 100nF decp
Supply
Aout
Supply
Aout
Supply
Supply
Supply
Aout
Aout
Supply
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BallName
DVSS
PVDD
DVDD
MCLK
LRCK
SCLK
SDI
CSCL
CSDA
SDO
USBon
RCV
VP
VM
VPO
VMO
OEN
DVSS
DP
DM
VTRM
UVDD
AUX_R
AUX_L
PWRUP
PLDO3
MICP
MICN
VREF
AGND
AVSS
AVDD
BGND
BVDD
OUTR
BVSS
OUTL
BVDD
VSSDCDC
VSSDCDC
SWDCDC
SWDCDC
VB1V
n.c.
n.c.
n.c.
n.c.
ch
Ball#
F1
B2
A2
G1
D2
E2
F2
G2
G3
F3
E3
G4
F4
E4
E5
F5
D5
G5
G6
G7
F6
F7
D7
D6
E7
E6
C7
C6
C5
B6
B7
A7
A6
B5
A5
A4, B4
A3
B3
A1
B1
C1
D1
E1
C2
C3
C4
D4
Table of Pin Configuration for CABGA 49
Rev. 1v2, June 2004
CONFIDENTIAL
Page 15 of 19
Product Brief AS3510
2
3
4
5
6
7
A
VSSDCDC
DVDD
OUTL
BVSS
OUTR
BGND
AVDD
B
VSSDCDC
PVDD
BVDD
BVSS
BVDD
AGND
AVSS
C
SWDCDC
n.c.
(QPLL)
n.c.
(RESET)
n.c.
VREF
MICN
MICP
D
SWDCDC
LRCLK
DACPD
n.c.
OEN
AUXL
AUXR
E
VB1V
SCLK
USB_ON
VM
VPO
PLDO3
PWRUP
F
DVSDS
SDI
SDO
VP
VMO
VTRM
Figure 5
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UVDD
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1
MCLK
CSCL
CSDA
RCV
DVSS
DP
DM
Figure of Pin Configuration
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Mechanical Dimensions for CABGA 49
Mechanical Dimensions
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Figure 6
Rev. 1v2, June 2004
CONFIDENTIAL
Page 16 of 19
Product Brief AS3510
AGC
automatic gain control
DAC
digital to analog converter
dBFS
dB full scale
DSP
digital signalling processor
ENOB
effective number of bits
ESD
electrostatic discharge
I2S
inter IC sound
LDO
low drop regulator
PDA
personal digital assistance
PSRR
power supply rejection ratio
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analog to digital converter
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ADC
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Abbreviations
SFDR
spurious free dynamic range
SD
sigma delta
SNR
signal to noise ratio
SINAD
signal to noise and distortion (=THD+N)
TA
ambient temperature
THD
total harmonic distortion
uP
microprocessor
Σ∆
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sigma delta
Rev. 1v2, June 2004
CONFIDENTIAL
Page 17 of 19
Product Brief AS3510
Copyright
Package
Description
AS3510
LQFP 80
Thin Quad Flat Pack - 80
leads (evaluation only)
CABGA 49
ChipArray Ball Grid Array – 49
balls, 0.8mm pitch
The information furnished here by austriamicrosystems AG
is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or
any third party for any damages, including but not limited
to personal injury, property damage, loss of profits, loss of
use, interruption of business or indirect, special, incidental
or consequential damages, of any kind, in connection with
or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient
or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other
services.
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Devices sold by austriamicrosystems AG are covered by
the warranty and patent identification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no
warranty, express, statutory, implied, or by description
regarding the information set forth herein or regarding the
freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change
specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it
is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in
normal commercial applications. Applications requiring
extended temperature range, unusual environmental
requirements, or high reliability applications, such as
military, medical life-support or life-sustaining equipment
are specifically not recommended without additional
processing by austriamicrosystems AG for each
application.
Copyright © 2004, austriamicrosystems AG, Schloss
Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material
herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent
of the copyright owner.
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Ordering Information
Rev. 1v2, June 2004
CONFIDENTIAL
Page 18 of 19
Product Brief AS3510
Contact
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 5440
F. +43 (0) 3136 5692
[email protected]
www.austriamicrosystems.com
Sales Offices
austriamicrosystems USA, Inc.
Suite 400, 8601 Six Forks Road
Raleigh, NC 27615, USA
Phone: +1/919/676 5292
Fax: +1/919/676 5305
austriamicrosystems France S.a.r.l.
124, Avenue de Paris
F-94300 Vincennes, France
Phone: +33/1/43 74 00 90
Fax: +33/1/43 74 20 98
austriamicrosystems AG
AIOS Gotanda Annex 5th Fl.,
1-7-11,
Higashi-Gotanda, Shinagawa-ku,
Tokyo 141-0022 Japan
Phone: +81/3/5792 4975
Fax: +81/3/5792 4976
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austriamicrosystems Germany GmbH
Tegernseer Landstrasse 85
D-81539 München, Germany
Phone: +49/89/693643-0
Fax: +49/89/693643-66
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Headquarter
austriamicrosystems Italy S.r.l.
Via Leone Tolstoi, 64
I-20146 Milano, Italy
Phone: +39/0242/36713
Fax: +39/0242/290889
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austriamicrosystems Switzerland AG
Rietstrasse 4
CH-8640 Rapperswil, Switzerland
Phone: +41/55/220 9000
Fax: +41/55/220 9001
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austriamicrosystems UK, Ltd.
Coliseum Business Centre, Watchmoor Park
Camberley, Surrey, GU15 3YL, United Kindom
Phone: +44/1276/23 3 99
Fax: +44/1276/29 3 53
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austriamicrosystems USA, Inc.
Suite 116, 4030 Moorpark Ave,
San Jose, CA 95117, USA
Phone: +1/408/345 1790
Fax: +1/408/345 1795
Rev. 1v2, June 2004
austriamicrosystems AG
Suite 811, Tsimshatsui Centre,
East Wing, 66 Mody Road,
Tsim Sha Tsui East,
Kowloon, Hong Kong
Phone: +852/2268 6899
Fax: +852/2268 6799
austriamicrosystems AG
Singapore Representative Office
83 Clemenceau Avenue
#02-01 UE Square
Singapore 239920
Phone: +65 68 30 83 05
Fax: +65 62 34 31 20
austriamicrosystems AG
#805, Dong Kyung Bldg., 824-19,
Yeok Sam Dong,
Kang Nam Gu, Seoul
Korea 135-080
Phone: +82/2/557 8776
Fax: +82/2/569 9823
CONFIDENTIAL
Page 19 of 19