AS1118

austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: [email protected]
Please visit our website at www.ams.com
D atas he et
A S 111 8
64 L E D D r i v er fo r M o b i l e A p p l i ca ti on s w i th E r r or D e te ct i o n
2 Key Features
10MHz SPI-Compatible Interface
Open and Shorted LED Error Detection
- Global or Individual Error Detection
Hexadecimal- or BCD-Code for 7-Segment Displays
200nA Low-Power Shutdown Current (typ; data
retained)
Individual Digit Brightness Control
Digital and Analog Brightness Control
Display Blanked on Power-Up
Drive Common-Cathode LED Displays
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The AS1118 is a compact LED driver for 64 single LEDs
or 8 digits of 7-segments. The devices can be programmed via an SPI compatible 3-wire interface. Every
segment can be individually addressed and updated
separately. Only one external resistor (RSET) is required
to set the current. LED brightness can be controlled by
analog or digital means. The devices include an integrated BCD code-B/HEX decoder, multiplex scan circuitry, segment and display drivers, and a 64-bit
memory. Internal memory stores the shift register settings, eliminating the need for continuous device reprogramming.
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1 General Description
Table 1. Available Products
Devices
RESET Input
Interfaces
AS1115
no
I²C
no
SPI
yes
I²C
yes
SPI
AS1116
AS1117
AS1118
Supply Voltage Range: 2.7V to 5.5V
Software and Hardware Reset
Optional External Clock
Package: TQFN(4x4)-24
3 Applications
Additionally the AS1118 offers a detailed error diagnostic
mode for easy and fast production testing in critical
applications. The AS1118 features a low shutdown current of typically 200nA, and an operational current of
typically 350µA. The number of digits can be programmed, the devices can be reset by software, and an
external clock is also supported. The device is available
in a TQFN(4x4)-24 package.
The AS1118 is ideal for seven-segment or dot matrix dis,
plays in mobile applications, public information displays
at subway, train or bus stations, at airports and also at
displays in public transportation like buses or trains, personal electronic and toys.
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Figure 1. AS1118 - Typical Application Diagram
VDD
2.7V to 5.5V
8
SEGA-DP
VDD
DIG0 to
DIG7
8
Te
9.53kΩ
I/O
µP
I/O
I/O
I/O
I/O
ISET
8
8
8
GND
AS1118
SDO SDI
SDI
RESETN SCL
LD
AS1118
SDO
RESETN SCL LD
SDI
AS1118
SDO
RESETN SCL LD
Diagnostic readback: open & shorted LEDs
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Revision 1.01
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AS1118
Datasheet - P i n o u t
4 Pinout
Pin Assignments
18 SEG E
DIG3
2
17 SEGC
GND
3
DIG4
4
DIG5
5
14 SEGB
RESETN
6
13 SEGF
16 VDD
DIG7
9
10 11 12
ISET
8
15 SEGG
LD
7
DIG6
AS1118
SEGA
SCL
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Pin Descriptions
1
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24 23 22 21 20 19
DIG2
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SEGDP
SEGD
SDO
SDI
DIG0
DIG1
Figure 2. Pin Assignments (Top View)
Table 2. Pin Descriptions
TQFN(4x4)-24
Description
Serial-Data Input. Data is loaded into the internal 16-bit shift register on the
22
SDI
rising edge of pin SCL.
1, 2, 4, 5, 7, 8, 23, Digit Drive Lines. Eight digit drive lines that sink current from the display
DIG0:DIG7
24
cathode.
3
Ground.
GND
Load. Serial Data is loaded into the shift register while this pin is low. The last
9
LD
16 bits of serial data are latched on the rising edge of this pin.
Reset Input. Pull this pin to low to resest all registers (set to default values) and
6
RESETN
to put the device into shutdown.
Set Segment Current. Connect to VDD or a reference voltage through RSET to
10
set the peak segment current (see Selecting RSET Resistor Value and Using
ISET
External Drivers on page 15).
Serial-Clock Input. 10MHz maximum rate. Data is shifted into the internal shift
11
register on the rising edge of this pin. Data is clocked out of pin SDO on the
SCL
rising edge of this pin.
Seven Segment and Decimal Point Drive Lines. 8 seven-segment drives and
SEGA:SEGG,
12-15,
SEGDP
17-20
decimal point drive that source current to the display.
Positive Supply Voltage. Connect to +2.7V to +5.5V supply. Bypass this pin to
16
VDD
GND with a 10µF and a 0.1µF capacitor to avoid power supply ripple.
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Pin Name
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SDO
21
Exposed Pad
Serial-Data Output. The data into pin SDI is valid at pin SDO 16 clock cycles
later. This pin is used to daisy-chain several devices and is never highimpedance.
Exposed Pad. This pin also functions as a heat sink. Solder it to a large pad or
to the circuit-board ground plane to maximize power dissipation.
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Revision 1.01
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AS1118
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Min
Max
Units
VDD to GND
-0.3
7
V
All other pins to GND
-0.3
7 or
VDD + 0.3
V
DIG0:DIG7 Sink Current
500
mA
SEGA:SEGG, SEGDP
100
mA
Electrical Parameters
Input Voltage Range
Current
Electrostatic Discharge
Thermal Information
±100
mA
Norm: JEDEC 78
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Input Current (latch-up immunity)
Electrostatic Discharge
Notes
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Parameter
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Table 3. Absolute Maximum Ratings
Digital outputs
1000
V
All other pins
1000
V
30.5
ºC/W
+150
°C
+150
ºC
Thermal Resistance ΘJA
Norm: MIL 833 E method 3015
on PCB
Temperature Ranges and Storage Conditions
Junction Temperature
Storage Temperature
-55
Package Body Temperature
Humidity non-condensing
ºC
85
%
3
%
Represents a max. floor life time of 168h
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Moisture Sensitive Level
5
+260
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages
is matte tin (100% Sn).
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Revision 1.01
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AS1118
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 2.7V to 5.5V, RSET = 9.53kΩ, TAMB = -40°C to +85°C, typ. values @ TAMB = +25ºC and VDD = 5.0V (unless otherwise specified).
Table 4. Electrical Characteristics
Parameter
Conditions
Min
VDD
Operating Supply Voltage
IDDSD
Shutdown Supply Current
IDD
Operating Supply Current
fOSC
Display Scan Rate
8 digits scanned
0.6
IDIGIT
Digit Drive Sink Current
VOUT = 0.65V
320
ISEG
Segment Drive Source Current
∆ISEG
Segment Drive Current Matching
ISEG
Segment Drive Source Current
Typ
2.7
0.2
RSET = open circuit.
0.35
All segments and decimal
point on; ISEG = -40mA.
335
-37
5.5
V
2
µA
0.6
mA
0.8
1.2
kHz
mA
-42
-47
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VDD = 5.0V, VOUT = (VDD -1V)
Unit
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All digital inputs at VDD or
GND, TAMB = +25ºC
Max
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Symbol
3
Average Current
mA
%
47
mA
Max
1
Unit
µA
Table 5. Logic Inputs/Outputs Characteristics
Symbol
IIH, IIL
Parameter
Input Current SDI, SCL, LD
VIH
Logic High Input Voltage
SDI, SCL, LD, RESETN
Logic Low Input Voltage
SDI, SCL, LD, RESETN
VIL
Output High Voltage
VOH
Conditions
VIN = 0V or VDD
Min
-1
Typ
1.26
0.54
SDO, ISOURCE = -1mA,
VDD = 5.0V
VDD - 1
SDO, ISOURCE = -1mA,
VDD = 3.0V
VDD - 0.5
VOL
Output Low Voltage
SDO, ISINK = 1mA
∆VI
Hysteresis Voltage
SDI, SCL, LD
0.4
0.7x
VDD
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Open Detection Level Threshold
0.05x VDD
Short Detection Level Threshold
1
0.75x 0.8x
VDD
VDD
0.1x 0.15x
VDD
VDD
V
V
V
V
V
V
V
Parameter
SCL Clock Period
SCL Pulse Width High
SCL Pulse Width Low
LD to SCL Rise Setup Time
SCL Rise to LD Rise Hold Time
SDI Setup Time
SDI Hold Time
Output Data Propagation Delay
LD Rising Edge to SCL Rising Edge
Minimum LD Pulse High
Data-to-Segment Delay
Conditions
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Symbol
tCP
tCH
tCL
tCSS
tCSH
tDS
tDH
tDO
tLDCK
tCSW
tDSPD
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Table 6. SPI Timing Characteristics
Min
100
20
20
25
10
0
5
CLOAD = 50pF
Typ
Max
25
20
20
2.25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
See Figure 18 on page 8 for more information.
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Revision 1.01
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AS1118
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
RSET = 9.53kΩ, VRset = VDD;
980
960
960
940
940
900
880
920
900
880
Vdd = 2.7V
Tamb = - 40°C
860
Vdd = 4V
Tamb = + 25°C
Vdd = 5V
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860
Vdd = 5.5V
Tamb = + 85°C
840
2.7
3.1
3.5
3.9
4.3
4.7
5.1
840
-40
5.5
-15
10
Vdd (V)
Iseg (mA) .
20
Vseg = 1.7V; Vdd = 2.7V
Vseg = 1.7V; Vdd = 5V
10
Vseg
Vseg
Vseg
Vseg
30
20
10
0
-15
10
35
60
85
0
10
20
Tamb (°C)
30
40
50
60
70
80
90
Rset (kOhm)
Figure 8. Segment Current vs. VDD; VRset = 2.8V
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Figure 7. Segment Current vs. Supply Voltage;
50
Vseg
Vseg
Vseg
Vseg
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45
40
= 1.7V
= 2V
= 2.3V
= 3.1V
35
Iseg (mA) .
40
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Iseg (mA) .
= 4V; Vdd = 5V
= 3V; Vdd = 5V
= 2V; Vdd = 5V
= 1.7V; Vdd = 2.7V
Vseg = 3V; Vdd = 5V
Vseg = 4V; Vdd = 5V
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Iseg (mA) .
30
50
85
Figure 6. Segment Current vs. RSET;
40
40
60
60
50
50
0
-40
35
Tamb (°C)
Figure 5. Segment Current vs. Temperature;
60
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920
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Figure 4. Display Scan Rate vs. Temperature;
980
fosc (Hz) .
fosc (Hz) .
Figure 3. Display Scan Rate vs. Supply Voltage;
30
20
25
20
15
Vseg = 1.7V
10
Vseg = 3V
10
30
Vseg = 4V
5
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
Vdd (V)
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3
3.3
3.6
3.9
4.2
Vdd (V)
Revision 1.01
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AS1118
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 9. VDIGIT vs. IDIGIT
Figure 10. Input High Level vs. Supply Voltage
0.4
3.5
3
2.5
0.2
1.5
1
= 2.7V
= 3.3V
= 4V
= 5V
= 5.5V
0.5
0
0
0.05
0.1
0.15
0.2
0.25
Idig (A)
0.3
Figure 11. ISEG vs. VSEG; VDD = 5V
50
40
3.5
4.3
4.7
5.1
5.5
Vdd (V)
50
= 10k
= 13k
= 18k
= 30k
= 56k
Rext
Rext
Rext
Rext
Rext
45
40
= 8k2
= 10k
= 13k
= 18k
= 30k
Iseg (mA) .
30
30
25
25
20
20
15
15
10
10
5
5
0
0
2
2.5
3
3.5
4
4.5
5
1
1.5
2
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45
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40
3
3.5
4
Rext
Rext
Rext
Rext
Rext
Figure 14. ISEG vs. VSEG; VDD = 2.7V
= 6k8
= 8k2
= 10k
= 13k
= 18k
35
30
Te
25
20
50
Rext
Rext
Rext
Rext
Rext
45
40
= 4k7
= 5k6
= 6k8
= 10k
= 13k
35
Iseg (mA) .
Figure 13. ISEG vs. VSEG; VDD = 3.3V
50
2.5
Vseg (V)
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Vseg (V)
Iseg (mA) .
3.9
35
35
Iseg (mA) .
3.1
Figure 12. ISEG vs. VSEG; VDD = 4V
Rext
Rext
Rext
Rext
Rext
45
2.7
0.35
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Vdd
Vdd
Vdd
Vdd
Vdd
0.1
2
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Vih (V) .
Vdig (V) .
0.3
30
25
20
15
15
10
10
5
5
0
0
1
1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
1
Vseg (V)
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1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vseg (V)
Revision 1.01
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AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
Block Diagram
Open/Short
Detection
16
VDD
VDD
+
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Figure 15. AS1118 - Block Diagram
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100nF
–
RSET
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+
–
Oszillator
10
ISET
8
6
RESETN
9
LD
22
SDI
11
SCL
21
SEGA-G,
SEGDP
Digital Control
Logic
8
2-5, 7-10
DIG0 to DIG7
(PWM, Debounce,....)
Registers
SPI
Interface
Data - Registers
Control - Registers
Scan - Registers
3
GND
AS1118
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SDO
12-15, 17-20
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Figure 16. ESD Structure
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VDD
valid for the pins:
- SDI
- SCL
- SDO
- LD
- ISET
- SEGA-G, SEGDP
- RESETN
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VDD
valid for the pins:
- DIG0 to DIG7
Revision 1.01
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AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Serial-Addressing Format
The AS1118 contains a 16bit SPI interface to access the internal data and control registers of the device (see Digitand Control-Registers on page 9). The SPI interface is driven with the rising edge of SCL. A falling edge on LD signal
indicates the beginning of an access on the SPI interface, the rising edge on LD determines an access on SPI. An
access must consist of exactly 16bits for write operation and 8bits for read operation. Timing restrictions on the SPI
interface pins are defined in Figure 18.
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Table 7 shows the structure of the 16bit command word for writing data, Table 8 the 8bit command word for read operation.
D0 (write operation) / D8 (read operation) is the first bit to shift into the SPI interface after the falling edge of LD, is the
last bit to write to SPI before rising edge of LD.
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At a read operation an 8bit operation is executed. At the first rising edge of SCL after the rising edge of LD D7 of
addressed register is written to SDO pin. At the next rising edge of SCL D6 is written to SDO pin. LD must be kept high
during reading data from a internal data or control register of AS1118.
Table 7. 16-Bit Serial Data Format
D1
D2
D3
D4
Data
D5
D6
D7
MSB
D8
D9
D10
D11
D12
Register Address (see Table 8)
D13
0
D14
R/W
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D0
LSB
D15
X
Figure 17. Read operation
1
SCL
LD
SDO
8
9
D7
D6
16
10
D5
D4
D3
D2
D1
D0
Figure 18. Interface Timing
LD
tCSW
SCL
tCSH
tCP
tCSS
tCL
tLDCK
tCH
ca
tDH
tDS
ni
D0
D1
D14
D15
tDO
ch
SDI
Te
SDO
Initial Power-Up
On initial power-up, the AS1118 registers are reset to their default values, the display is blanked, and the device goes
into shutdown mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control
Register (see page 13) is set to the minimum values.
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AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Shutdown Mode
The AS1118 devices feature a shutdown mode, where they consume only 200nA (typ) current. Shutdown mode is
entered via a write to the Shutdown Register (see Table 9) or via pulling the pin RESTEN to logic low. When pin
RESETN is set to logic low an according write to the Shutdown Register is done internally.
For the AS1118, at that point, all segment current sources and digital drivers are switched off, so that all segments are
blanked. During shutdown mode the Digit-Registers maintain their data.
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Note: When pin RESETN is pulled to logic high again, a write to the Shutdown Register in necessary to leave the
shutdown mode.
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Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display
(repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should
be at GND or VDD (CMOS logic level).
When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown
Register bit D7 (page 10) = 0.
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Note: When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering or leaving shutdown mode. If the AS1118 is used with an external clock, Shutdown Register bit D7 should be set to 1 when
writing to the Shutdown Register.
Digit- and Control-Registers
The AS1118 devices contain 8 Digit-Registers,11 control-registers and 8 diagnostic-registers, which are listed in Table
8. All registers are selected using a 8-bit address word, and communication is done via the serial interface.
Digit Registers – These registers are realized with an on-chip 64-bit memory. Each digit can be controlled directly
without rewriting the whole register contents.
Control Registers – These registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and features selection registers.
Type
Table 8. Register Address Map
Address
Register
No-Op
Digit 0
Digit 3
Digit 4
D12
D11
D10
D9
D8
X
0
0
0
0
0
0
0
14
X
0
0
0
0
0
0
1
N/A
X
0
0
0
0
0
1
0
N/A
X
0
0
0
0
0
1
1
X
0
0
0
0
1
0
0
X
0
0
0
0
1
0
1
(see Table 11 on page 11,
Table 12 on page 11 and
Table 13 on page 11)
N/A
N/A
N/A
X
0
0
0
0
1
1
0
N/A
Digit 6
X
0
0
0
0
1
1
1
N/A
Digit 7
X
0
0
0
1
0
0
0
X
0
0
0
1
0
0
1
ni
Digit 5
D13
ca
Digit 2
D14
ch
Digit Register
Digit 1
D7:D0
Page
D15
N/A
(see Table 10 on page 10)
10
Global Intensity
X
0
0
0
1
0
1
0
(see Table 17 on page 13)
13
Scan Limit
X
0
0
0
1
0
1
1
(see Table 19 on page 13)
13
Shutdown
X
0
0
0
1
1
0
0
(see Table 9 on page 10)
Not Used
X
0
0
0
1
1
0
1
Feature
X
0/1
0
0
1
1
1
0
(see Table 20 on page 14)
14
Display Test Mode
X
0
0
0
1
1
1
1
(see Table 14 on page 12)
10
Te
Control Register
Decode-Mode
DIG0:DIG1 Intensity
X
0
0
1
0
0
0
0
(see Table 18 on page 13)
DIG2:DIG3 Intensity
X
0
0
1
0
0
0
1
(see Table 18 on page 13)
DIG4:DIG5 Intensity
X
0
0
1
0
0
1
0
(see Table 18 on page 13)
DIG6:DIG7 Intensity
X
0
0
1
0
0
1
1
(see Table 18 on page 13)
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Revision 1.01
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N/A
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AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Address
Register
Page
D14
D13
D12
D11
D10
D9
D8
D7:D0
Diagnostic Digit 0
X
1
0
1
0
1
0
0
N/A
Diagnostic Digit 1
X
1
0
1
0
1
0
1
N/A
Diagnostic Digit 2
X
1
0
1
0
1
1
0
N/A
Diagnostic Digit 3
X
1
0
1
0
1
1
1
N/A
Diagnostic Digit 4
X
1
0
1
1
0
0
0
Diagnostic Digit 5
X
1
0
1
1
0
0
1
Diagnostic Digit 6
X
1
0
1
1
0
1
0
Diagnostic Digit 7
X
1
0
1
1
0
1
1
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D15
N/A
N/A
N/A
N/A
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Diagnostic Register
Type
Table 8. Register Address Map
Note: Write operation: D14=0; Read operation: D14=1.
The Shutdown Register controls AS1118 shutdown mode.
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Table 9. Shutdown Register Format (Address (HEX) = 0x0C))
Mode
Shutdown Mode, Reset Feature Register to Default Settings
Shutdown Mode, Feature Register Unchanged
Normal Operation, Reset Feature Register to Default Settings
Normal Operation, Feature Register Unchanged
Register Data
HEX
Code D7 D6 D5 D4 D3 D2 D1 D0
0x00 0
X
X
X
X
X
X
0
0x80 1
X
X
X
X
X
X
0
0x01 0
X
X
X
X
X
X
1
0x81 1
X
X
X
X
X
X
1
Decode Enable Register (0x09)
The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code – characters 0:9, E, H, L,
P, and -, or HEX code – characters 0:9 and A:F) is selected by bit D2 (page 14) of the Feature Register. The Decode
Enable Register is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable Register corresponds to its respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so
on). Table 11 lists some examples of the possible settings for the Decode Enable Register bits.
Note: A logic high enables decoding and a logic low bypasses the decoder altogether.
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When decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers,
disregarding bits D6:D4. Bit D7 sets the decimal point (SEG DP) independent of the decoder and is positive logic (bit
D7 = 1 turns the decimal point on). Table 11 lists the code-B font; Table 12 lists the HEX font.
When no-decode mode is selected, data bits D7:D0 of the Digit-Registers correspond to the segment lines of the
AS1118. Table 13 shows the 1:1 pairing of each data bit to the appropriate segment line.
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Table 10. Decode Enable Register Format Examples
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Decode Mode
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No decode for digits 7:0
Code-B/HEX decode for digit 0. No decode for digits 7:1
Code-B/HEX decode for digit 0:2. No decode for digits 7:3
Code-B/HEX decode for digits 0:5. No decode for digits 7:6
Code-B/HEX decode for digits 0,2,5. No decode for digits 1, 3, 4, 6, 7
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Revision 1.01
Register Data
HEX
Code D7 D6 D5 D4 D3 D2 D1 D0
0x00 0
0
0
0
0
0
0
0
0x01 0
0
0
0
0
0
0
1
0x07 0
0
0
0
0
1
1
1
0x3F 0
0
1
1
1
1
1
1
0x25 0
0
1
0
0
1
0
1
10 - 20
AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 11. Code-B Font
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
X
1
1
1
1
X
0
1
0
0
X
1
0
1
0
X
X
X
X
X
X
0
*
1
0
1
X
1
0
1
*
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Register Data
Register Data
Register Data
CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
1
The decimal point can be enabled with every character by setting bit D7 = 1.
Table 12. HEX Font
Register Data
Register Data
Register Data
CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
X
1
1
1
1
X
X
X
X
X
X
1
0
0
X
1
0
1
0
0
1
0
1
X
1
0
1
1
1
*
The decimal point can be enabled with every character by setting bit D7 = 1.
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Table 13. No-Decode Mode Data Bits and Corresponding Segment Lines
Corresponding Segment Line
D7
DP
D6
A
D5
B
D4
C
D3
D
D2
E
D1
F
D0
G
Figure 19. Standard 7-Segment LED
F
E
www.austriamicrosystems.com/LED-Driver-ICs/AS1118
A
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D
B
C
DP
Revision 1.01
11 - 20
AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Display-Test Mode
The AS1118 can detect open or shorted LEDs. Readout of either open LEDs (D2=1) or short LEDs (D1=1) is possible,
as well as a OR relation of open and short (D1=D2=1). After a dignostic run bit D4 can be read to clearify if an error
occurred before reading out detailed diagnostic data.
Note: All settings of the digit- and control-registers are maintained.
Table 14. Testmode Register Summary
D6
REXT_short
D5
REXT_open
D4
LED_global
D3
LED_test
D2
LED_open
D1
LED_short
Table 15. Testmode Register Bit Description (Address (HEX) = 0x0F))
Addr: 0x0F
Address
Bit
Bit Name
Default
Access
D0
DISP_test
0
W
D1
LED_short
0
W
Starts a test for shorted LEDs. (Can be set together with D2)
0: Normal operation; 1: Activate testmode
D2
LED_open
0
W
Starts a test for open LEDs. (Can be set together with D1)
0: Normal operation; 1: Activate testmode
D3
LED_test
0
R
Indicates an ongoing open/short LED test
0: No ongoing LED test; 1: LED test in progress
D4
LED_global
0
R
Indicates that the last open/short LED test has detected an error
0: No error detected; 1: Error detected
D5
REXT_open
0
R
Checks if external resistor REXT is open
0: REXT correct; 1: REXT is open
D6
REXT_short
0
R
Checks if external resistor REXT is shorted
0: REXT correct; 1: REXT is shorted
0
-
Not used
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D7:D0
D0
DISP_test
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Optical display test. (Testmode for external visual test.)
0: Normal operation; 1: Run display test (All digits are tested
independently from scan limit & shutdown register.)
D7
LED Diagnostic Registers
These eight registers contain the result of the LED open/short test for the individual LED of each digit.
Table 16. LED Diagnostic Register Address
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Segment
Digit
D7
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DIG0
DIG1
DP
DIG2
DIG3
D6 D5 D4 D3 D2 D1 D0
A
B
C
D
E
F
G
Register
HEX
Address
0x18
0x19
0x1A
0x1B
Segment
Digit D7
DIG4
DIG5
DP
DIG6
DIG7
D6 D5 D4 D3 D2 D1 D0
A
B
C
D
E
F
G
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Register
HEX
Address
0x14
0x15
0x16
0x17
Note: If more than 2 shorts occure in the LED array, detection of individual LED fault could become limited to blocs.
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Intensity Control Register (0x0A)
The brightness of the display can be controlled by digital means using the Intensity Control Registers and by analog
means using RSET (see Selecting RSET Resistor Value and Using External Drivers on page 15). The intensity can be
controlled globally for all digits, or for each digit individually. The global intensity command will write intensity data to all
four individual brightness registers, while the individual intesity command will only write to the associated individual
intensity register.
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Revision 1.01
12 - 20
AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the
Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 15/16
down to 1/16 of the peak current set by RSET.
Table 17. Intensity Register Format
1/16 (min on)
2/16
3/16
4/16
5/16
6/16
7/16
8/16
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
MSB
0
0
0
0
0
0
0
0
Register Data
D2
D1 LSB
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Duty Cycle
HEX Code
9/16
10/16
11/16
12/16
13/16
14/16
15/16
15/16 (max on)
0xX8
0xX9
0xXA
0xXB
0xXC
0xXD
0xXE
0xXF
Register Data
Register HEX Address
0x0A
0x10
0x11
0x12
0x13
Register Data
D2
D1 LSB
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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Table 18. Intensity Register Address
MSB
1
1
1
1
1
1
1
1
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HEX Code
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Duty Cycle
Type
Global
Digit
Digit
Digit
Digit
D7:D4
X
Digit 1 Intensity
Digit 3 Intensity
Digit 5 Intensity
Digit 7 Intensity
D3:D0
Global Intensity
Digit 0 Intensity
Digit 2 Intensity
Digit 4 Intensity
Digit 6 Intensity
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of the digits are to be displayed. When all 8 digits are to be displayed, the
update frequency is typically 0.8kHz. If the number of digits displayed is reduced, the update frequency is increased.
The frequency can be calculated using 8fOSC/N, where N is the number of digits. Since the number of displayed digits
influences the brightness, RSET should be adjusted accordingly.
Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros).
Table 19. Scan-Limit Register Format (Address (HEX) = 0x0B))
Scan Limit
Scan Limit
Display digits 0:4
Display digits 0:5
Display digits 0:6
Display digits 0:7
Register Data
HEX
Code D7:D3 D2 D1 D0
0xX4
X
1
0
0
0xX5
X
1
0
1
0xX6
X
1
1
0
0xX7
X
1
1
1
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Display digit 0 only
Display digits 0:1
Display digits 0:2
Display digits 0:3
Register Data
HEX
Code D7:D3 D2 D1 D0
0xX0
X
0
0
0
0xX1
X
0
0
1
0xX2
X
0
1
0
0xX3
X
0
1
1
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Revision 1.01
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AS1118
Datasheet - D e t a i l e d D e s c r i p t i o n
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode,
applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the
SPI-compatible interface, setting the blinking rate, and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0.
D7
D6
D5
D4
D3
D2
D1
blink_
start
sync
blink_
freq_sel
blink_en
NU
decode_sel
reg_res
Table 21. Feature Register Bit Descriptions (Address (HEX) = 0xXE)
D2
D3
D4
D5
D6
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D1
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D0
D0
Feature Register
Enables and disables various device features.
Bit Name
Default
Access
Bit Description
External clock active.
clk_en
0
R/W
0 = Internal oscillator is used for system clock.
1 = Pin CLK of the serial interface operates as system clock input.
Resets all control registers except the Feature Register.
0 = Reset Disabled. Normal operation.
reg_res
0
R/W
1 = All control registers are reset to default state (except the Feature
Register) identically after power-up.
Note: The Digit Registers maintain their data.
Selects display decoding for the selected digits (Table 10 on page 10).
decode_sel
0 = Enable Code-B decoding (see Table 11 on page 11).
0
R/W
1 = Enable HEX decoding (see Table 12 on page 11).
NU
Not used
Enables blinking.
blink_en
0
R/W
0 = Disable blinking. 1 = Enable blinking.
Sets blink with low frequency (with the internal oscillator enabled):
blink_freq_sel
0 = Blink period typically is 1 second (0.5s on, 0.5s off).
0
R/W
1 = Blink period is 2 seconds (1s on, 1s off).
Synchronizes blinking on the rising edge of pin LD. The multiplex and
blink timing counter is cleared on the rising edge of pin LD. By setting
sync
0
R/W
this bit in multiple devices, the blink timing can be synchronized across
all the devices.
Start Blinking with display enabled phase. When bit D4 (blink_en) is set,
bit D7 determines how blinking starts.
blink_start
0
R/W
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
Addr: 0xXE
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Table 20. Feature Register Summary
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No-Op Register (0xX0)
The No-Op Register is used when multiple AS1118 devices are cascaded in order to support displays with more than 8
digits. The cascading must be done in such a way that all SDO pins are connected to SDI of the next AS1118 (see Figure 20 on page 16). The LD and SCL signals are connected to all devices.
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For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command
must be followed by four no-operation commands. When the LD signal goes high, all shift registers are latched. The
first four devices will receive no-operation commands and only the fifth device will receive the intended operation command, and subsequently update its register.
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Revision 1.01
14 - 20
AS1118
Datasheet - Ty p i c a l A p p l i c a t i o n
9 Typical Application
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows between VDD and ISET defines the
current that flows through the LEDs.
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Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operating voltages, and LED voltage drop (VLED) are given in Table 22 & Table 23. The maximum current the AS1118 can
drive is 47mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary
that the devices drive high currents.
Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page 12).
VLED
VLED
VLED
1.5V
2.0V
2.5V
1.5V
5kΩ
6.9kΩ
10.7kΩ
22.2kΩ
4.4kΩ
5.9kΩ
9.6kΩ
20.7kΩ
6.7kΩ
9.1kΩ
13.9kΩ
28.8kΩ
6.4kΩ
8.8kΩ
13.3kΩ
27.7kΩ
5.7kΩ
8.1kΩ
12.6kΩ
26kΩ
7.5kΩ
10.18kΩ
15.6kΩ
31.9kΩ
VDD = 3.6V
2.0V
VDD = 3.3V
1.5V
2.0V
2.5V
3.0V
7.2kΩ
9.8kΩ
15kΩ
31kΩ
6.6kΩ
9.2kΩ
14.3kΩ
29.5kΩ
5.5kΩ
7.5kΩ
13kΩ
27.3kΩ
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40
30
20
10
VDD = 2.7V
ISEG (mA)
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Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V
Table 23. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V & 5.0V
VLED
VDD = 4.0V
40
30
20
10
1.5V
2.0V
8.6kΩ
8.3kΩ
11.6kΩ 11.2kΩ
17.7kΩ 17.3kΩ
36.89kΩ 35.7kΩ
2.5V
7.9kΩ
10.8kΩ
16.6kΩ
34.5kΩ
VLED
3.0V
3.5V
7.6kΩ 5.2kΩ
9.9kΩ 7.8kΩ
15.6kΩ 13.6kΩ
32.5kΩ 29.1kΩ
VDD = 5.0V
ISEG
(mA)
1.5V
2.0V
11.35kΩ
15.4kΩ
23.6kΩ
48.9kΩ
11.12kΩ
15.1kΩ
23.1kΩ
47.8kΩ
2.5V
3.0V
3.5V
4.0V
10.84kΩ 10.49kΩ 10.2kΩ 9.9kΩ
14.7kΩ 14.4kΩ 13.6kΩ 13.1kΩ
22.6kΩ
22kΩ 21.1kΩ 20.2kΩ
46.9kΩ 45.4kΩ 43.8kΩ 42kΩ
Calculating Power Dissipation
The upper limit for power dissipation (PD) for the AS1118 is determined from the following equation:
PD = (VDD x 5mA) + (VDD - VLED)(DUTY x ISEG x N)
Where:
(EQ 1)
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VDD is the supply voltage.
DUTY is the duty cycle set by intensity register (page 13).
N is the number of segments driven (worst case is 8)
VLED is the LED forward voltage
ISEG = segment current set by RSET
Dissipation Example:
(EQ 2)
PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W
(EQ 3)
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ISEG = 40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V
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Thus, for a QSOP-24 package ΘJA = +88°C/W, the maximum allowed T AMB is given by:
TJ,MAX = TAMB + PD x ΘJA = 150°C = T AMB + 0.865W x 88°C/W
(EQ 4)
In this example the maximum ambient temperature must stay below 73.88°C.
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Revision 1.01
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AS1118
Datasheet - Ty p i c a l A p p l i c a t i o n
8x8 Dot Matrix Mode
The application example in Figure 20 shows the AS1118 in the 8x8 LED dot matrix mode.
The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the
segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed
in Table 8 on page 9.
Figure 20. Application Example as LED Dot Matrix Driver
VDD
2.7V to 5V
VDD
DIG0 to
DIG7
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9.53kΩ
SEG A to G
SEP DP
ISET
I/O
I/O
µP
I/O
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Note: For a multiple-digit dot matrix, multiple AS1118 devices can be cascaded easily.
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The Decode Enable Register (see page 10) must be set to ‘00000000’ as described in Table 10 on page 10. Single
LEDs in a column can be addressed as described in Table 13 on page 11, where bit D0 corresponds to segment G and
bit D7 corresponds to segment DP.
SDI
AS1118
SCL
Diode Arrangement
LD
SDO
I/O
Diagnostic
readback: open
& shorted LEDs
GND
RESETN
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1118 should be placed very close to the LED display to minimize effects
of electromagnetic interference and wiring inductance.
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Furthermore, it is recommended to connect a 10µF electrolytic and a 0.1µF ceramic capacitor between pins VDD and
GND to avoid power supply ripple (see Figure 15 on page 7).
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Revision 1.01
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AS1118
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
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Figure 21. TQFN(4x4)-24 Marking
Table 24. Packaging Code YYWWIZZ
YY
X
ZZ
manufacturing week
plant identifier
free choice / traceability code
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last two digits of the current year
WW
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Revision 1.01
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AS1118
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
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Figure 22. TQFN(4x4)-24 Package
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Revision 1.01
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AS1118
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 25.
Table 25. Ordering Information
Marking
AS1118-BQFT
ASSX
Desciption
64 LED Driver for Mobile
Applications with Error Detection
Delivery Form
Package
Tape and Reel
TQFN(4x4)-24
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Ordering Code
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
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Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
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For further information and requests, please contact us mailto:[email protected]
or find your local distributor at http://www.austriamicrosystems.com/distributor
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Revision 1.01
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AS1118
Datasheet
Copyrights
Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show
deviations from the standard production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
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Contact Information
Headquarters
Te
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com/LED-Driver-ICs/AS1118
Revision 1.01
20 - 20