TSL202R

TAOS Inc.
is now
ams AG
The technical content of this TAOS datasheet is still valid.
Contact information:
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Tel: +43 (0) 3136 500 0
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
r
r
128 × 1 Sensor-Element Organization
200 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 2000:1 (66 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 5 MHz
Single 5-V Supply
Replacement for TSL202
É
É
É
É
Ç
É
Ç
Ç
Ç
Ç
(TOP VIEW)
VDD 1
SI1 2
CLK 3
AO1 4
GND 5
SO2 6
NC 7
14 NC
13 SO1
12 GND
11 NC
10 SI2
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D
D
D
D
D
D
D
D
TAOS032F − JANUARY 2012
9 NC
8 AO2
lv
NC − No internal connection
Description
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The TSL202R linear sensor array consists of two sections of 64 photodiodes and associated charge amplifier
circuitry arranged to form a contiguous 128 × 1 array. The pixels measure 120 μm (H) by 70 μm (W) with 125-μm
center-to-center spacing and 55-μm spacing between pixels. Operation is simplified by internal control logic that
requires only a serial-input (SI) signal and a clock.
The TSL202R is intended for use in a wide variety of applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear
and rotary encoding.
Functional Block Diagram (each section — pin numbers apply to section 1)
Pixel 1
S1
_
Pixel
3
Pixel
64
Analog
Bus
2
1
3
5
GND
RL
(External
330 W
Load)
Q3
Q64
ch
ni
Q2
4
AO
Gain
Trim
Switch Control Logic
Q1
1
VDD
Output
Amplifier
S2
Sample/
Output
ca
+
Pixel
2
1 Integrator
Reset
2
CLK
64-Bit Shift Register
2
Te
SI
3
The LUMENOLOGY r Company
Copyright E 2012, TAOS Inc.
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972)
r 673-0759
www.taosinc.com
1
TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
AO1
4
Analog output of section 1
AO2
8
Analog output of section 2
CLK
3
Clock. Clk controls charge transfer, pixel output, and reset.
GND
5,12
Ground (substrate). All voltages are referenced to GND.
7, 9, 11, 14
SI1
2
Serial input (section 1). SI1 defines the start of the data-out sequence.
SI2
10
Serial input (section 2). SI2 defines the start of the data-out sequence.
SO1
13
Serial output (section 1). SO1 provides a signal to drive the SI2 input.
SO2
6
Serial output (section 2). SO2 provides a signal to drive the SI input of another device for
cascading or as an end-of-data indication.
VDD
1
Supply voltage. Supply voltage for both analog and digital circuitry.
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Detailed Description
No internal connection
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NC
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2) †. As the SI pulse
is clocked through the 128-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 129th clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 129th clock pulse is required to terminate the
output of the 128th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
as early as the 130th clock pulse, thereby initiating another pixel output cycle.
The voltage developed at analog output (AO) is given by:
ni
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm2)
is the incident irradiance in μW/cm2
is integration time in seconds
ch
where:
Vout
Vdrk
Re
Ee
tint
ca
Vout = Vdrk + (Re) (Ee) (tint)
Te
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device.
†
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
Copyright E 2012, TAOS Inc.
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
Absolute Maximum Ratings†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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†
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Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Voltage range applied to any output in the high impedance or
power-off state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Recommended Operating Conditions (see Figure 1 and Figure 2)
Supply voltage, VDD
Input voltage, VI
High-level input voltage, VIH
Low-level input voltage, VIL
Wavelength of light source, λ
Clock frequency, fclock
Sensor integration time, serial, tint
MIN
NOM
4.5
5
MAX
UNIT
5.5
V
0
VDD
V
2
VDD
V
0
0.8
400
1000
nm
V
5
5000
kHz
0.026
100
ms
Sensor integration time, parallel, tint
Operating free-air temperature, TA
0.013
100
ms
0
70
°C
Load resistance, RL
300
4700
Ω
420
pF
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Load capacitance, CL
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 16.5 μW/cm2 (unless otherwise noted)
TEST CONDITIONS
MIN
See Note 1
TYP
Vout
Analog output voltage (white, average over 128 pixels)
Vdrk
Analog output voltage (dark, average over 128 pixels)
PRNU
Pixel response nonuniformity
See Notes 2 & 3
Nonlinearity of analog output voltage
See Note 3
± 0.4%
Output noise voltage
See Note 4
1
Re
Responsivity
SE
Saturation exposure
Vsat
Analog output saturation voltage
DSNU
Dark signal nonuniformity
All pixels
IL
Image lag
See Note 7
IDD
Supply current, output idle
IIH
High-level input current
IIL
Low-level input current
MAX
1.6
2
2.4
V
0
50
150
mV
± 4%
± 10%
18
See Note 5
23
142
2.5
25
30
High level output voltage,
High-level
voltage SO1 and SO2
VOL
O
Low level output voltage,
Low-level
voltage SO1 and SO2
Ci(SI)
Input capacitance, SI
Ci(CLK)
Input capacitance, CLK
V/
(μJ/cm 2)
nJ/cm 2
V
120
mV
10
mA
10
μA
10
μA
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See Note 6
3.4
FS
mVrms
0.5%
7
VI = VDD
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VOH
O
UNIT
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PARAMETER
VI = 0
IO = 50 μA
4.5
4.95
IO = 4 mA
4.6
IO = 50 μA
0.01
IO = 4 mA
0.4
V
0.1
V
5
pF
10
pF
NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
V out (IL) * V drk
V out (white) * V drk
100
ni
ca
IL +
Timing Requirements (see Figure 1 and Figure 2)
th(SI)
tw
Setup time, serial input (see Note 8)
Hold time, serial input (see Note 8 and Note 9)
NOM
MAX
UNIT
20
ns
0
ns
Pulse duration, clock high or low
50
Input transition (rise and fall) time
0
Te
tr, tf
ch
tsu(SI)
MIN
ns
500
ns
NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
9. SI must go low before the rising edge of the next clock pulse.
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
Analog output settling time to ± 1%
tpd(SO)
Propagation delay time, SO1, SO2
TEST CONDITIONS
RL = 330 Ω,
MIN
CL = 10 pF
TYP
MAX
UNIT
185
ns
50
ns
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PARAMETER
ts
TYPICAL CHARACTERISTICS
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CLK
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SI
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
129 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
tw
CLK
2.5 V
tsu(SI)
SI1 (SI2) 2.5 V
1 (65)
2 (66)
64 (128)
65 (129)
2.5 V
5V
2.5 V
0V
5V
ca
2.5 V
th(SI)
ni
SO1 (SO2)
tpd(SO)
ts
ch
ts
tpd(SO)
0V
AO1 (A02)
Te
Pixel 1 (65)
The LUMENOLOGY r Company
Pixel 64 (128)
Figure 2. Operational Waveforms (each section)
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
TYPICAL CHARACTERISTICS
ANALOG OUTPUT SETTLING TIME
vs
LOAD CAPACITANCE AND RESISTANCE
PHOTODIODE SPECTRAL RESPONSIVITY
1
600
500
0.6
0.2
400
100 pF
300
10 pF
200
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0.4
220 pF
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ts — Settling Time to 1% — ns
0.8
Normalized Responsivity
470 pF
VDD = 5 V
Vout = 1 V
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TA = 25°C
100
0
300
0
400
500
600
700
800
900
1000 1100
λ − Wavelength − nm
0
200
400
600
800
1000
1200
RL − Load Resistance − Ω
Figure 4
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Figure 3
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
APPLICATION INFORMATION
Power Supply Considerations
For optimum device performance, power-supply lines should be decoupled by a 0.01-μF to 0.1-μF capacitor
with short leads mounted close to the device package (see Figure 5 and Figure 6).
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Integration Time
The integration time of the linear array is the period during which light is sampled and charge accumulates on
each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature
of the TAOS TSL2xx linear array family. By changing the integration time, a desired output voltage can be
obtained on the output pin while avoiding saturation for a wide range of light levels.
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Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity
to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the
functional block diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing
switch S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this event, S2 moves from position 1 (sampling) to
position 3 (holding). This holds the sampled voltage for pixel 1. Switch S1 for pixel 1 is then moved to position
2. This resets (clears) the voltage previously integrated for that pixel so that pixel 1 is now ready to start a new
integration cycle. When the next clock period starts, the S1 switch is returned to position 1 to be ready to
start integrating again. S2 is returned to position 1 to start sampling the next light integration. Then the next pixel
starts the same procedure. The integration time is the time from a specific pixel read to the next time that pixel
is read again. If either the clock speed or the time between successive SI pulses is changed, the integration time
will vary. After the final (nth) pixel in the array is read on the output, the output goes into a high-impedance mode.
A new SI pulse can occur on the (n+1) clock causing a new cycle of integration/output to begin. Note that the
time between successive SI pulses must not exceed the maximum integration time of 100 msec.
The minimum integration time for any given array is determined by time required to clock out all the pixels in
the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore,
the minimum integration period is simply a function of the clock frequency and the number of pixels in the array.
A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation
on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency
of 5 MHz.
The minimum integration time can be calculated from the equation:
where:
n
is the number of pixels
ni
n
1
ǒmaximum clock
Ǔ
frequency
ca
T int(min) +
ch
In the case of the TSL202R, the minimum integration time would be:
T int(min) + 200 ns
128 + 25.6 ms
Te
It is important to note that not all pixels will have the same integration time if the clock frequency is varied while
data is being output.
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
APPLICATION INFORMATION
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
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The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
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If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
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Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 5 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
APPLICATION INFORMATION
Connection Diagrams
VDD
0.1 μF
TSL202R
NC
SO1
GND
NC
SI2
NC
AO2
14
13
12
11
10
9
8
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SI
CLK
VDD
SI1
CLK
AO1
GND
SO2
VDD
lv
1
2
3
4
5
6
7
AO
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RL
Figure 5. Serial Connection
VDD
TSL202R
0.1 μF
1
2
3
4
5
6
7
Si
CLK
AO1 (Pixels 1− 64)
RL
VDD
SI1
CLK
AO1
GND
SO2
VDD
NC
SO1
GND
NC
SI2
NC
AO2
14
13
12
11
10
9
8
AO2 (Pixels 65 −128)
ca
RL
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Figure 6. Parallel Connection
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
MECHANICAL INFORMATION
This assembly consists of 2 sensor chips mounted on a printed-circuit board in a clear molded plastic package.
TOP VIEW
19.30
18.29
CL
Sensors 3.62
to Pin 1 3.92
Pixel 1 0.53
to Pin 1 0.28
10.67
9.65
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ÉÉÉÉÉ
ÇÇÇÇÇÇ
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Sensors
Pin 1
Indicator
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END VIEW
SIDE VIEW
3.18
2.79
Top of Die to 0.89
Top of Package 1.29
ÏÏÏÏÏÏÏÏÏÏÏ
14 y 4.60 MIN
14
14
BOTTOM
VIEW
1.90
0.76
2
14
13
3
0.50
0.00
0.508
0.406
4
12
y
5
6
11
10
9
7
8
ni
2.16
1.42
ch
y
yj
ca
1
7.87
7.37
2
ÏÏÏÏÏÏ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
12 y 2.54
Nonaccumulative
See Note B
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NOTES: A. All linear dimensions are in millimeters.
B. The true-position spacing is 2.54 mm between lead centerlines. Each pin centerline is located within 0.25 mm of its true
longitudinal positions.
C. Index of refraction of clear plastic is 1.52.
D. This drawing is subject to change without notice.
Copyright E 2012, TAOS Inc.
Figure 7. Packaging Configuration
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
SOLDERING INFORMATION
TSL202 128 y 1 linear array 14-lead gold pin package soldering instructions:
D The TSL202R has been designed to withstand a lead temperature during soldering of 260°C for 10 seconds
at a distance of 1.6 mm from the package body.
D In most applications, these through-hole parts will be sufficiently protected by the combination of the PCB
or flex plus the standoff provided by the package.
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D If lead clipping is required, this should be performed after solder attach to prevent the pulling of the lead from
the package body.
D As in all board manufacturing, care should be taken to prevent part bending during board singulation or final
assembly.
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D If the process includes both surface-mount parts and the TSL202R, the surface mount operations should
be completed first with the through-hole parts afterward.
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These parts can be washed as a part of the flux cleanup operation. A final top-surface cleanup may be required
with water or alcohol to remove any remaining particles.
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TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032F − JANUARY 2012
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
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Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
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TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
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TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
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LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
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