Datasheet

AS8202B
TTP-C2NF Communication Controller
1 General Description
40 MHz oscillator clock support
16 MHz bus guardian clock with support for 16 MHz crystal or
The AS8202B communication controller is an integrated device
supporting serial communication according to the TTP specification
version 1.1. It performs all communication tasks such as reception
and transmission of messages in a TTP cluster without interaction of
the host CPU. TTP provides mechanisms that allow the deployment
in high-dependability distributed real-time systems. It provides the
following services:
16 MHz oscillator
Single power supply 3.3V, 0.35µm CMOS process
Full automotive temperature range (-40ºC to 125ºC)
16k x 16 SRAM for message, status, control area
(communication network interface) and for scheduling
information (MEDL)
Predictable transmission of messages with minimal jitter
4k x 16 (plus parity) instruction code RAM for protocol execution
Fault-tolerant distributed clock synchronization
code
Consistent membership service with small delay
Datasheet conforms to protocol revision 2.05
Masking of single faults
16k x 16 instruction code ROM containing startup execution
code and deprecated protocol code revision 1.00
16-bit non-multiplexed asynchronous host CPU interface
2 Key Features
16-bit RISC architecture
Dual-channel controller for redundant data transfers
Software tools, design support, development boards available
Dedicated controller supporting TTP (time-triggered protocol
Visit www.tttech.com
class C standardized in SAE 6003)
Certification support package according to RTCA/DO-254 DAL
Suited for dependable distributed real-time systems with
A available – Visit www.tttech.com
guaranteed response time
RoHS conform
Asynchronous data rate up to 4 Mbit/s (MFM/Manchester)
3 Applications
Synchronous data rate 20 to 25 Mbit/s
Bus interface (speed, encoding) for each channel selectable
The device is ideal for application fields such as, aerospace
according to DO-254 level A (e.g. flight control, power distribution,
engine control), industrial systems, and railway systems.
independently
Figure 1. Block Diagram
D[15:0]
TTP Bus Unit
Host Processor Interface
Asynchronous
Bus Interface
(MFM/
Manchester)
CEB
OEB
WEB
READYB
INTB
LED[2:0]
Communication
Network
Interface
(CNI)
TTP Protocol
Processor Core
TxCLK[1:0]
Synchronous
Bus Interface
(MII)
RAM_CLK_TESTSE
USE_RAM_CLK
Bus
Guardi
Bus
Guardian
an
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XIN0
Instruction Memory
RAM & ROM
RESETB
Revision 1.0
Test Interface
TxD[1:0]
CTS[1:0]
XIN1
XOUT1
RAM_CLK_TESTSE
FTEST
STEST
FIDIS
TTEST
Test Interface
40 MHz Clock
AS8202B
TTP Bus Media Drivers
RxD[1:0]
RxCLK[1:0]
RxDV[1:0]
RxER[1:0]
A[11:0]
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AS8202B
Datasheet - A p p l i c a t i o n s
Contents
1 General Description
.................................................................................................................................................................. 1
2 Key Features
............................................................................................................................................................................ 1
3 Applications
.............................................................................................................................................................................. 1
4 Pin Assignments
....................................................................................................................................................................... 3
4.1 Pin Descriptions
................................................................................................................................................................................... 3
5 Absolute Maximum Ratings
6 Electrical Characteristics
7 Detailed Description
...................................................................................................................................................... 6
.......................................................................................................................................................... 7
................................................................................................................................................................. 9
7.1 Host CPU Interface
.............................................................................................................................................................................. 9
7.1.1 Synchronous READYB Generation ........................................................................................................................................... 12
7.2 Reset and Oscillator
7.2.1
7.2.2
7.2.3
7.2.4
........................................................................................................................................................................... 13
External Reset Signal ................................................................................................................................................................ 13
Integrated Power-On Reset ....................................................................................................................................................... 13
Oscillator Circuitry ...................................................................................................................................................................... 13
Built-in Characteristics ............................................................................................................................................................... 14
7.3 TTP Bus Interface
.............................................................................................................................................................................. 14
7.4 TTP Asynchronous Bus Interface
...................................................................................................................................................... 15
7.5 TTP Synchronous Bus Interface
........................................................................................................................................................ 15
7.6 Test Interface
...................................................................................................................................................................................... 16
7.7 LED Signals
....................................................................................................................................................................................... 16
8 Package Drawings and Markings
9 Ordering Information
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........................................................................................................................................... 17
............................................................................................................................................................... 19
Revision 1.0
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AS8202B
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
VSS
READYB
WEB
OEB
CEB
VSS
VDD
VSSBG
XIN1
XOUT1
VDDBG
D15
D14
D13
D12
D11
D10
D9
D8
TTEST
Figure 2. Pin Assignments (Top View)
80
61
60
1
NC
XIN0
CTEST
VDD
TXD0
CTS0
TXCLK0
RXER0
RXCLK0
RXDV0
RXD0
VDD
VSS
TXD1
CTS1
TXCLK1
RXER1
RXCLK1
RXDV1
RXD1
VSS
VDD
D7
D6
D5
D4
D3
D2
D1
D0
VSS
VDD
A11
A10
A9
A8
A7
A6
A5
VSS
AS8202B
TTP
Communications
Controller
(TOP VIEW)
20
40
USE_RAM_CLK
A0
A1
A2
A3
A4
NC
21
RAM_CLK_TESTSE
STEST
OSCMODE
FTEST
FIDIS
RESETB
NC
INTB
VDD
VSS
LED0
LED1
LED2
41
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
Pin Number
VDD
4, 12, 29, 49, 59, 74
VSS
13, 30, 41, 50, 60,
75, 80
VDDBG
70
Positive Power Supply for Bus Guardian (connect to VDD)
VSSBG
73
Negative Power Supply for Bus Guardian (connect to VSS)
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Dir
Description
Positive Power Supply
Power pin
Revision 1.0
Negative Power Supply
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AS8202B
Datasheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
Pin Number
Dir
Description
RAM_CLK when STEST=0 and USE_RAM_CLK=1, else
Test Input, connect to VSS if not used
RAM_CLK_TESTSE
21
STEST
22
FTEST
24
TTL Input with internal weak Test Input, connect to VSS
pull-down
Test Input, connect to VSS
FIDIS
25
Test Input, connect to VSS
TTEST
61
TTL Input with internal weak Test Input, connect to VDD
pull-up
USE_RAM_CLK
34
TTL Input with internal weak RAM_CLK Pin Enable, connect to VSS if not used
pull-down
XIN0
2
CTEST
3
OSCMODE
23
XIN1
72
XOUT1
71
RESETB
26
TTL Input with internal weak Main Reset Input, active low
pull-up
TxD0
5
TTL output with internal weak TTP Bus Channel 0: Transmit Data
pull-up at tristate
CTS0
6
TTL output with internal weak TTP Bus Channel 0: Transmit Enable
pull-down at tristate
RxD0
11
TTL Input with internal weak TTP Bus Channel 0: Receive Data
pull-up
TxCLK0
7
TTL Input with internal weak TTP Bus Channel 0: Transmit Clock (MII mode)
pull-down
RxER0
8
TTL Input with internal weak TTP Bus Channel 0: Receive Error (MII mode)
pull-up
RxCLK0
9
TTL Input with internal weak TTP Bus Channel 0: Receive Clock (MII mode)
pull-down
RxDV0
10
TTL Input with internal weak TTP Bus Channel 0: Receive Data Valid (MII mode)
pull-up
TxD1
14
TTL output with internal weak TTP Bus Channel 1: Transmit Data
pull-up at tristate
CTS1
15
TTL output with internal weak TTP Bus Channel 1: Transmit Enable
pull-down at tristate
RxD1
20
TTL Input with internal weak TTP Bus Channel 1: Receive Data
pull-up
TxCLK1
16
TTL Input with internal weak TTP Bus Channel 1: Transmit Clock (MII mode)
pull-down
RXER1
17
TTL Input with internal weak TTP Bus Channel 1: Receive Error (MII mode)
pull-up
RXCLK1
18
TTL Input with internal weak TTP Bus Channel 1: Receive Clock (MII mode)
pull-down
RxDV1
19
TTL Input with internal weak TTP Bus Channel 1: Receive Data Valid (MII mode)
pull-up
Analog CMOS pin
Test input, to be unconnected
TTL Input with internal weak
1
Connect to VDD
pull-down
Analog CMOS pin
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Main Clock: 40MHz external clock input
Revision 1.0
Bus Guardian Clock: Analog CMOS Oscillator Input, use as
input when providing external clock
Bus Guardian Clock: Analog CMOS Oscillator Output,
leave open when providing external clock
4 - 20
AS8202B
Datasheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
Pin Number
Dir
A[11:0]
48-42, 39-35
TTL Input
D[15:0]
69-62, 58-51
CEB
76
OEB
77
WEB
78
READYB
79
INTB
28
LED[2:0]
33-31
NC
1, 27, 40
Description
Host Interface (CNI) Address Bus
2
TTL input/output with tristate Host Interface (CNI) Data Bus, tristate
Host Interface (CNI) chip enable, active low
TTL Input with internal weak Host interface (CNI) output enable, active low
pull-up
Host interface (CNI) write enable, active low
Host interface (CNI) transfer finish signal, active low, open
3
TTL output with internal weak drain
pull-up at tristate
Host interface (CNI) time signal (interrupt), active low, open
drain
TTL output with internal weak Configurable generic output port
pull-down at tristate
Not connected, leave open
1. This pin selects a clock multiplier of 1. This is the only supported operation mode.
2. The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-granular address bus, remember that A[11:0] of the AS8202B device has to be connected to A[12:1] of the CPU (considering a little endian CPU address bus)
3. At de-assertion READYB is driven to the inactive value (high) for a configurable time.
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Revision 1.0
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AS8202B
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only. Functional operation of the
device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
VDD
DC Supply voltage
-0.3
5.0
V
VIN
Input voltage
-0.3
VDD+0.3
V
any pin
IIN
Input current
-100
100
mA
any pin, TAMB=25ºC
Electrostatic discharge
1000
V
HBM: 1KV Mil.std.883, Method 3015.7
Electrical Parameters
Electrostatic Discharge
ESD
Temperature Ranges and Storage Conditions
TSTRG
Storage temperature
TBODY
Package body temperature
H
Humidity non-condensing
MSL
Moisture sensitivity level
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-55
+150
5
ºC
260
ºC
85
%
3
Revision 1.0
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
Represents a maximum floor life time of 168h
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AS8202B
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
TAMB = -40 to +125 ºC, VDD = 3V to +3.6V, VSS = 0V unless otherwise specified.
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Static Supply Current
All inputs tied to VDD/VSS,
clocks stopped, exclusive of I/O
drive requirements, VDD=3.6V
5
Typ
Max
Unit
900
µA
100
mA
Operating Conditions
IDDs
IDD
CLK1
Operating Supply Current
(see note 1)
VDD=3.3V,
exclusive of I/O drive requirements
Clock Period of Bus Guardian Clock
62.5
(see note 1)
ns
TTL Input Pins and TTL Bidirectional Pins in Input/Tristate Model
VIL
Input Low Voltage
VIH
Input High Voltage
IINleak
Input Leakage Current
IIL
IIH
CIN
Input Low Current
Input High Current
0.8
2.0
Pins without pad resistors,
VDD=3.6V
Pins with pull-down
resistors, VDD=3.0V
VIN=0.4V
VIN=0.8V
V
-1
1
4.9
8.8
µA
(see note 2)
VDD=3.6V
VIN=0V
-15
-75
Pins with pull-down
resistors
VDD=3.6V
VIN=3.6V
15
75
VIN=2.0V
VIN=2.5V
µA
(see note 2)
Pins with pull-up
resistors
Pins with pull-up
resistors, VDD=3.0V
V
-10.7
µA
(see note 2)
-6
(see note 2)
4.5
Input Capacitance
pF
(see note
2)
RxD Pin
tASYM_Rx
t(VIN=0.5*VDD)
Asymmetric Receiver Delay RxD
T=125ºC, VDD=3.0V,
CLOAD=35pF
RxD[1,0]
-2
2
(see note 3)
(see note 3)
ns
CMOS Inputs (XIN), drive from external clock generator
Drive at XIN
CXIN
Input Capacitance
IXIN
Input Current
VIL_XIN
Input Low Voltage
0
0.3* VDD
V
VIH_XIN
Input High Voltage
0.7* VDD
VDD
V
1.9
2.5
±1
(see note 3)
pF
µA
Outputs and TTL Bi-directional Pins in Output Mode
IOL
Output Low Current
VDD=3.0V, Vo = 0.4V
-4
mA
IOH
Output High Current
VDD=3.0V, Vo = 2.5V
4
mA
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AS8202B
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
IOZ
Output Tristate Current
VDD=3.6V
tRISE
t(VOUT=0.1*VDD)
to
t(VOUT=0.9*VDD)
tFALL
t(VOUT=0.9*VDD)
to
t(VOUT=0.1*VDD)
Transition Time – Rise
Transition Time – Fall
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
Min
Typ
Max
±10
(see note 3)
CTS[1,0],
LED[2:0],
INTB
Unit
µA
8.1
(see note 2)
ns
8.9
D[15:0],
READYB
(see note 2)
CTS[1,0],
LED[2:0],
INTB
6
(see note 2)
ns
7
D[15:0],
READYB
(see note 2)
TxD Pins
tRISE
t(VOUT=0.3*VDD)
to
t(VOUT=0.7*VDD)
Transition Time – Rise TxD
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
TxD[1,0]
tFALL
t(VOUT=0.7*VDD)
to
t(VOUT=0.3*VDD)
Transition Time – Fall TxD
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
TxD[1,0]
tASYM_Rx
t(VOUT=0.5*VDD)
Asymmetric Driver Delay TxD
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
TxD[1,0]
4.5
(see note 3)
3
(see note 3)
-3
3
(see note 3)
(see note 3)
ns
ns
ns
Notes:
1. Typical values: CLK0=40 MHz (duty cycle 45-55%), CLK1=16 MHz.
2. Implicitly tested.
3. Guaranteed by design; not tested during production.
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AS8202B
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The AS8202B is the first TTP controller to support both MFM and Manchester coding. Manchester coding is important for DC-free data
transmission, which allows the use of transformers in the data stream. The AS8202B is pin-compatible with its predecessor, the AS8202. The
AS8202B provides support for fault-tolerant, high-speed bus systems in a single device. The communication controller is qualified for the full
temperature range required for automotive applications and is certifiable according to RTCA standards. It offers superior reliability and supports
data transfer rates of 25 Mbit/s with MII and up to 4 Mbit/s with MFM/Manchester.
The CNI (communication network interface) forms a temporal firewall. It de-couples the controller network from the host subsystem by use of a
dual ported RAM (CNI). This prevents the propagation of control errors. The interface to the host CPU is implemented as a 16-bit wide nonmultiplexed asynchronous bus interface.
The TTP follows a conflict-free media access strategy called time division multiple access (TDMA). This means, TTP deploys a time slot
technique based on a global time that is permanently synchronized. Each node is assigned a time slot in which it is allowed to perform transmit
operation. The sequence of time slots is called TDMA round, a set of TDMA rounds forms a cluster cycle. The operation of the network is
repeated after one cluster cycle. The sequence of interactions forming the cluster cycle is defined in a static time schedule, called message
descriptor list (MEDL). The definition of the MEDL in conjunction with the global time determines the response time for a service request.
The membership of all nodes in the network is evaluated by the communications controller. This information is presented to all correct cluster
members in a consistent fashion. During operation, the status of all other nodes is propagated within one TDMA round. Please read more about
TTP and request the TTP specification at www.tttech.com.
7.1 Host CPU Interface
The host CPU interface, also referred to as CNI (Communication Network Interface), connects the application circuitry to the AS8202B TTP
controller. All related signal pins provide an asynchronous read/write access to a dual ported RAM located in the AS8202B. There are no setup/
hold constraints referring to the microtick (main clock “CLK0”).
All accesses have to be executed on a granularity of 16-bit (2 byte), the device does not support byte-wide accesses. The pin A0 (LSB) of the
device differentiates even and odd 16-bit word addresses and is typically connected to A1 of a little-endian host CPU. The A0 of host CPU is not
connected to the device, and the application/driver on the host CPU should force all accesses to be 16-bit. For efficiency reasons, the host CPU
application/driver may access some memory locations of the AS8202B using wider accesses (e.g. 32-bit), and the bus interface of the host CPU
will automatically split the access into two consecutive 16-bit wide accesses to the TTP controller. Note that particularly in such a setup all timing
parameters of the host CPU interface must be met, especially the inactivity timeouts described as symbols 16–19.
The host interface features an interrupt or time signal INTB to notify the application circuitry of programmed and protocol-specific, synchronous
and asynchronous events.
The host CPU interface allows access to the internal instruction code memory. This is required for proper loading of the protocol execution code
into the internal instruction code RAM, for extensive testing of the instruction code RAM and for verifying the instruction code ROM contents.
INTB is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pull-up resistors or transistors
may be necessary depending on the application.
READYB is also an open-drain output, but with a possibility to be driven to ‘1’ for a defined time (selectable by register) before weak-pull-up at
any other time.
The LED port is software-configurable to automatically show some protocol-related states and events, see below for the LED port configuration.
Table 4. Host Interface Ports
Pin Name
Mode
Width
Comment
A[11:0]
in
12
CNI address bus, 12-bit (A0 is LSB)
D[15:0]
inout (tri)
16
CNI data bus, 16-bit (D0 is LSB)
CEB
in
1
CNI chip enable, active low
WEB
in
1
CNI write enable, active low
OEB
In
1
CNI output enable, active low
READYB
out (open drain)
1
CNI ready, active low
INTB
out (open drain)
1
CNI interrupt, time signal, active low
RAM_CLK_TESTSE
in
1
HOST clock
USE_RAM_CLK
in
1
HOST clock pin enable
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AS8202B
Datasheet - D e t a i l e d D e s c r i p t i o n
Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal synchronization in the application. Connect
USE_RAM_CLK to VSS to enable this mode of operation.
Synchronous READYB uses an external clock (usually the host processor’s bus clock) for synchronization of the signal, eliminating external
synchronization logic. Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of
operation.
Note: Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.
Table 5. Asynchronous DPRAM Interface
Symbol
Parameter
Tc
Controller Cycle Time
1a
2a
1b
2b
Input Valid to CEB, WEB (Setup Time)
CEB, WEB to Input Invalid (Hold Time)
Conditions
Min
Typ
Max
25
A[11:0]
ns
5
D[15:0]
A[11:0]
3
D[15:0]
4
Units
ns
ns
5
ns
3
Input Rising to CEB, WEB Falling
CEB, WEB, OEB
4
CEB, WEB Rising to Input Falling
CEB, WEB, OEB
5
(see note 1,2)
5
Write Access Time (CEB, WEB to
READYB)
Min = 1 Tc, Max = 4 Tc
25
6
CEB, WEB de-asserted to READYB
de-asserted
7a
Input Valid to CEB, OEB (Setup Time)
A[11:0]
5
ns
7b
CEB, OEB to Input Invalid (Hold Time)
A[11:0]
2
ns
8
Input Rising to CEB, OEB Falling
CEB, WEB, OEB
9
CEB, OEB Rising to Input Falling
CEB, WEB, OEB
10
Read Access Time (CEB, OEB to
READYB)
Min = 1.5 Tc, Max = 8 Tc
37.5
200
ns
11a
CEB, OEB asserted to signal asserted
D[15:0]
4.0
8.4
ns
11b
CEB, OEB de-asserted to signal deasserted
D[15:0]
3.8
11c
READYB
12
READYB, D skew
13
RAM_CLK_TESTSE Rising to
READYB Falling
USE_RAM_CLK=1
14
RAM_CLK_TESTSE Rising to
READYB Rising
USE_RAM_CLK=1
15
16
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RAM_CLK_TESTSE Rising to
READYB Deactivated 1->Z
Read to Read Access Inactivity Time
(CEB, OEB low to CEB, OEB low)
USE_RAM_CLK
=1
Min = 1.5 Tc
Revision 1.0
(see note 1)
ns
100
ns
9.4
ns
5
ns
(see note 1)
5
ns
(see note 1)
8
8.8
ns
±2
ns
3.7
13.5
ns
3
9.7
ns
Ready
delay=00
3.6
12.9
Ready
delay=01
4.5
15.4
Ready
delay=10
5.4
18.8
Ready
delay=11
6.4
22.2
ns
37.5
(see note 1)
ns
10 - 20
AS8202B
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 5. Asynchronous DPRAM Interface
Symbol
Parameter
Conditions
Min
Typ
Max
17
Read to Write Access Inactivity Time
(CEB, OEB low to CEB, WEB low)
(see note 1)
18
Write to Write Access Inactivity Time
(CEB, WEB low to CEB, WEB low)
5
(see note 1,2)
ns
19
Write to Read Access Inactivity Time
(CEB, WEB low to CEB, OEB low)
5
(see note 1,2)
ns
5
Units
ns
Notes:
1. Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). In addition the
designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19. For more information on the inactivity times
(see Figure 3).
2. To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal CONTROLLER_ON register,
CEB OEB and WEB have to be stable high within 200 ns (min = 8 Tc).
3. All values not tested during production, guaranteed by design.
Figure 3. Read/Write Access Inactivity Time
Read
16
Read
17
Write
18
Write
19
Read
CEB
OEB
WEB
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AS8202B
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 4. Write Access Timing (CEB Controlled)
1a
A
1a
A
Valid
2a
D
2a
2b
D
Valid
3
4
5
2b
Valid
3
OEB
4
5
6
6
READYB
READYB
Figure 6. Read Access Timing (CEB Controlled)
7a
Figure 7. Read Access Timing (OEB Controlled)
7b
7a
A
Valid
CEB
7b
Valid
CEB
WEB
WEB
11a
12
Invalid
D
11a
11b
12
Valid
8
Invalid
D
9
11b
Valid
8
9
OEB
OEB
10
10
11c
READYB
7.1.1
Valid
WEB
WEB
A
1b
CEB
CEB
OEB
Figure 5. Write Access Timing (WEB Controlled)
1b
11c
READYB
Synchronous READYB Generation
Figure 8. Synchronous READYB Timing
asynchronous READYB
RAM_CLK_TESTSE
15
synchronous READYB
13
14
Synchronous READYB is aligned to host clock (with pulse duration of one host clock cycle) to fulfill the required host timing constraints for input
setup and input hold time to/after host clock rising edge.
Note: Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of operation. Due to
possible metastability occurrence, it is not recommended to be used in safety critical systems.
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Datasheet - D e t a i l e d D e s c r i p t i o n
7.2 Reset and Oscillator
Table 6. Pin Mode
7.2.1
Pin Name
Mode
Comment
XIN1
analog
Bus guardian oscillator input (external clock input)
RESETB
in
External reset
External Reset Signal
To issue a reset of the chip the RESETB port has to be driven low for at least 1µs. Pulses under 50ns duration are discarded. At power-up the
reset must overlap the build-up time of the power supply. This reset may only be used if a proper power-on reset can be ensured (refer to Section
7.2.2 Integrated Power-On Reset).
7.2.2
Integrated Power-On Reset
The device has an internal Power-On-Reset generator. When supply voltage ramps up, the internal reset signal is kept active (low) for 33µs
typical.
Table 7. Parameters
Symbol
Parameter
Min
Typ
Max
Unit
dV/dt
supply voltage slope
551
-
-
V/ms
tpores
power on reset active time after VDD > 1,0V
25
33
49
µs
Note: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid and main clock is stable.
7.2.3
Oscillator Circuitry
The main clock requires an external oscillator. The bus guardian requires an external oscillator or an external quartz.
Figure 9. Main Clock Setup
External oscillator
XINO
40MHz
square
wave
XIN0 of the main clock shall be supplied by a 40MHz clock provided by an oscillator IC.
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Figure 10. Bus Guardian Clock Setup
External quartz
External oscillator
C ext
16 M H z
XIN1
XOUT1
XIN1
Rd
Rf
XOUT1
C ext
16 M H z
s q u a re
w ave
The bus guardian clock (XIN1/XOUT1) supports driving a quartz crystal oscillation, as well as a clock input by an external oscillator.
7.2.4
Built-in Characteristics
Table 8. Characteristics
Symbol
Pin
Parameter
Tosc_startup1
XIN1/XOUT1
Oscillator startup time
(Bus Guardian clock)
Min
Typ
Max
Unit
Note
20
ms
Frequency: 16MHz
7.3 TTP Bus Interface
The AS8202B contains two TTP bus units, one for each TTP channel, building the TTP bus interface. Each TTP bus channel contains a
transmitter and a receiver and can be configured to be either in the asynchronous or synchronous mode of operation. Note that the two channels
(channel 0 and channel 1) can be configured independently for either of these modes.
The drivers of the TxD and CTS pins are actively driven only during a transmission window, all the other time the drivers are switched off and the
weak pull resistors are active. External pull resistors must be used to define the signal levels during idle phases.
Note: The transmission window may be different for each channel.
Table 9. Bus Interface Connections
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Pin Name
Tx inactive
TxD[0]
weak pull-up
CTS[0]
weak pull-down
TxD[1]
weak pull-up
CTS[1]
weak pull-down
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7.4 TTP Asynchronous Bus Interface
When in asynchronous mode of operation the channel's bus unit uses a self-clocking transmission encoding which can be either MFM or
Manchester at a maximum data rate of 4 Mbit/s on a shared media (physical bus). The pins can either be connected to drivers using recessive/
dominant states on the wire as well as drivers using active push/pull functionality.
The RxD signal uses '1' as the inactivity level. In the so-called RS485 compatible mode longer periods of '0' are treated as inactivity. If the RS485
compatible mode is not used, the application must care to drive RxD to '1' during inactivity on the bus.
Table 10. Asynchronous Bus Interface Connections
Pin Name
Mode
Connect to PHY
Note
TxD[0]
out
TxD
Transmit data channel 0
CTS[0]
out
CTS
Transmit enable channel 0
TxCLK[0]
in
No function (do not connect)
RXER[0]
in
No function (do not connect)
RXCLK[0]
in
No function (do not connect)
RxDV[0]
in
No function (do not connect)
RxD[0]
in
RxD
Receive data channel 0
TxD[1]
out
TxD
Transmit data channel 1
CTS[1]
out
CTS
Transmit enable channel 1
TxCLK[1]
in
No function (do not connect)
RXER[1]
in
No function (do not connect)
RXCLK[1]
in
No function (do not connect)
RxDV[1]
in
No function (do not connect)
RxD[1]
in
RxD
Receive data channel 1
7.5 TTP Synchronous Bus Interface
When in synchronous mode of operation, the bus unit uses a synchronous transfer method to transfer data at a rate between 20 and 25 Mbit/s.
The interface is designed to run at 25 Mbit/s and to be fully compatible with the commercial 100 Mbit/s Ethernet MII (Media Independent
Interface) according to IEEE standard 802.3 (Ethernet CSMA/CD).
Connecting the synchronous TTP bus unit to a 100 Mbit/s Ethernet PHY is done by connecting TxD, CTS, TxCLK, RXER, RXCLK, RxDV and
RxD of any channel to TxD0TxD0, TxEN, TxCLK, RXER, RXCLK, RxDV and RxD0 of the PHY's MII. The pins TxD1, TxD2 and TxD3 of the
PHY's MII should be linked to VSS. The signals RxD1, RxD2, RxD3, COL and CRS as well as the MMII (Management Interface) should be left
open or can be used for diagnostic purposes by the application.
Note that the frames sent by the AS8202B are not Ethernet compatible and that an Ethernet Hub (not a Switch) can be used as a 'star coupler'
for proper operation. Also note that the Ethernet PHY must be configured for Full Duplex operation (even though the Hub does not support full
duplex), because TTP has its own collision management that should not interfere with the PHY's Half-Duplex collision management. In general,
the PHY must not be configured for automatic configuration ('Auto negotiation') but be hard-configured for 100 Mbit/s, Full Duplex operation.
Note: To run the interface at a rate other than 25 Mbit/s other transceiver PHY components have to be used.
Table 11. Synchronous Bus Interface Connections
Pin Name
Mode
Connect to PHY
Note
TxD[0]
out
TxD0TxD0
Transmit data channel 0
CTS[0]
out
TxEN
Transmit enable channel 0
TxCLK[0]
in
TxCLK
Transmit clock channel 0
RXER[0]
in
RXER
Receive error channel 0
RXCLK[0]
in
RXCLK
Receive clock channel 0
RxDV[0]
in
RxDV
Receive data valid channel 0
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Table 11. Synchronous Bus Interface Connections
Pin Name
Mode
Connect to PHY
Note
RxD[0]
in
RxD0
Receive data channel 0
TxD[1]
out
TxD0
Transmit data channel 1
CTS[1]
out
TxEN
Transmit enable channel 1
TxCLK[1]
in
TxCLK
Transmit clock channel 1
RXER[1]
in
RXER
Receive error channel 1
RXCLK[1]
in
RXCLK
Receive clock channel 1
RxDV[1]
in
RxDV
Receive data valid channel 1
RxD[1]
in
RxD0
Receive data channel 1
7.6 Test Interface
The Test Interface supports the manufacturing test and characterization of the chip. In the application environment test pins have to be
connected as following:
STEST, FTEST, FIDIS: connect to VSS
TTEST: connect to VDD
Caution: Any other connection of these pins may cause permanent damage to the device and to additional devices of the application.
7.7 LED Signals
The LED port consists of three pins. Via the MEDL each of these pins can be independently configured for any of the three modes of operation.
At Power-Up and after Reset the LED port is inactive and only weak pull-down resistors are connected. After the controller is switched on by the
host and when it is processing its initialization, the LED port is initialized to the selected mode of operation.
Table 12. LED Signals
Pin Name
Protocol Mode
LED2
RPV or
7
Protocol activity
LED1
Sync Valid
LED0
Protocol activity or RPV
Timing Mode
1
6
Time Overflow
4
Time Tick
7
Microtick
2
8
Bus Guardian Mode
2
Action Time
BDE1
BDE0
3
5
5
1. RPV is Remote Pin Voting. RPV is a network-wide agreed signal used typically for agreed power-up or power-down of the application's
external drivers.
2. Time Overflow is active for one clock cycle at the event of an overflow of the internal 16-bit time counter. Time Tick is active for one clock
cycle when the internal time is counted up. Time Overflow and Time Tick can be used to externally clone the internal time control unit
(TCU). With this information the application can precisely sample and trigger events, for example.
3. Action Time signals the start of a bus access cycle.
4. The controller sets this output when cluster synchronization is achieved (after integration from the LISTEN state, after acknowledge in
the COLDSTART state).
5. BDE0 and BDE1 show the Bus Guardian's activity, '1' signals an activated transmitter gate on the respective channel.
6. Protocol activity is typically connected to an optical LED. The flashing frequency and rhythm give a simple view to the internal TTP protocol state.
7. LED2's RPV mode and LED0's Protocol activity mode can be swapped with a MEDL parameter.
8. Microtick is the internal main clock signal.
Each LED pin can be configured to be either a push/pull driver (drives both LOW and HIGH) or to be only an open-drain output (drives only
LOW).
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Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
8 Package Drawings and Markings
The product is available in a 80-pin LQFP package.
Figure 11. Drawings and Dimensions
AS8202NFB TTP
YYWWGZZ @@
licensed by
Marking: YYWWGZZ.
YY
WW
G
ZZ
@@
Manufacturing year
Manufacturing week
Plant identifier
Traceability code
Sublot identifier
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Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Revision History
Revision
Date
Owner
1.0
26 Mar, 2013
hgl
Description
Release of datasheet
Note: Typos may not be explicitly mentioned under revision history.
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Datasheet - O r d e r i n g I n f o r m a t i o n
9 Ordering Information
Table 13. Ordering Information
Ordering Code
AS8202B-ALQR
Marking
AS8202NFB
Description
TTP communication controller
Delivery Form
Tray
Package
80-pin LQFP
Note: All products are RoHS compliant and ams green
Technical Support is available at www.ams.com/Technical-Support
For further information and requests, email us at sales@ams.com
(or) find your local distributor at www.ams.com/distributor
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Copyrights
Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing
by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
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Fax
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