AS3606/AS3607 Preliminary Datasheet

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Data Sheet
AS3606 AS3607
System PMU with HV Back Light Driver
1 General Description
HV Backlight Driver
Step up for 30V backlight with internal transistor
The AS3606/07 is an ultra compact System PMU with integrated
battery charger and HV back light driver.
2 programmable current sink (max. 38mA)
The device offers advanced power management functions. All
necessary ICs and peripherals in a battery powered mobile device
are supplied by the AS3606/07. It features 3 DCDC converters as
well as 5 low noise LDOs. The different regulated supply voltages
are programmable via the serial control interface.
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Voltage control mode and over-voltage protection
Max. [email protected] (with ext. transistor) or [email protected]
Possible external PWM dimming input
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Battery Charger
The step-up converter for the backlight can operate up to 30V. Both
constant voltage (OLED supply) as well as constant current (white
LED backlight) operations with 2 current sinks are possible. An
internal voltage protection is limiting the output voltage in the case of
external component failures.
Prog. trickle charging (25-265mA)
AS3606/07 also contains a Li-Ion battery charger with constant
current and constant voltage. The maximum charging current is 1A.
An integrated battery switch and an optional external switch are
separating the battery during charging or whenever an external
power supply is present. With this switch it is also possible to operate
with no or deeply discharged batteries. A programmable current limit
can be used to control the maximum current used from a USB
supply.
Selectable current limitation for USB mode
Prog. constant current charging (94-1060mA)
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Prog. constant voltage charging (3.9V-4.25V)
The single supply voltage may vary from 2.7V to 5.5V.
Charger time-out and temperature supervision
Integrated battery switch & ideal diode
External battery switch control output
General
Battery and Temperature Supervisor
2 or 4 General Purpose IOs
10bit general purpose ADC input
2 Key Features
Power Management
Voltage Generation
Status output for: charger, low battery, power good and powerup key
OTP Programmable BOOT Sequence
3 DCDC step down regulators
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DVM (0.61V-3.3V, 700mA)
50µA quiescent current
Selectable switching frequency (2 or 1MHz)
1.4A with combined DCDC 2 & 3
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PWM dimming input or wake-up input
Programmable regulator default voltages
Programmable start-up sequence
Applicable for LDO 1-4 and DCDC 1-3
Control Interface
I2C control lines, including watchdog
Power-Up input
3 or 4 LDOs low noise
Interrupt output
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1 LDO low noise 2.7V (2.3-3.5V), 100mA
- 1.2-3.5V; 150/250mA
- 30µA quiescent current (low power mode)
Power supply supervision (LDO5)
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4sec and 8sec emergency shut-down
Hibernation function
Bidirectional reset, with selectable delay
Low power standby mode, 160µA with LDO5 on
Power-On Reset Circuit
Packaging
QFN32 5x5mm or QFN36 6x6mm, 0.5mm pitch
3 Application
The devices are ideal for Portable Media Players and Portable
Navigation Devices, e-Books, Tablet PCs, etc
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AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n
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Figure 1. AS3606 Block Diagram
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Figure 2. AS3607 Block Diagram
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AS3606 AS3607 2v2
Data Sheet - C o n t e n t s
Contents
1
2 Key Features.............................................................................................................................................................................
1
3 Application ................................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
5
4.1 Pin Descriptions....................................................................................................................................................................................
6
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1 General Description ..................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
8
6 Electrical Characteristics...........................................................................................................................................................
9
7 Typical Operating Characteristics ...........................................................................................................................................
11
8 Detailed Description - Power Management Functions............................................................................................................
12
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8.1 Low Drop Out Regulators ...................................................................................................................................................................
12
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8.1.1 LDO5 ......................................................................................................................................................................................... 12
8.1.2 LDO 1, LDO2, LDO3 & LDO4.................................................................................................................................................... 13
8.1.3 Parameter .................................................................................................................................................................................. 13
8.2 DCDC Step-Down Converter..............................................................................................................................................................
15
8.2.1 Functional Description ............................................................................................................................................................... 16
8.2.2 Parameter .................................................................................................................................................................................. 17
8.3 30V Step-Up DCDC Converter...........................................................................................................................................................
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Voltage Feedback and OV Protection .......................................................................................................................................
Voltage Feedback......................................................................................................................................................................
DLS & Dimming .........................................................................................................................................................................
Current Sinks .............................................................................................................................................................................
Parameter ..................................................................................................................................................................................
8.4 Charger...............................................................................................................................................................................................
22
Soft Charge/Trickle Charge ....................................................................................................................................................... 23
End of Charge Detection ........................................................................................................................................................... 23
VSUPSW and Temperature Supervision................................................................................................................................... 23
Battery Temperature Supervision .............................................................................................................................................. 23
No Battery Detection.................................................................................................................................................................. 23
Charger Modes .......................................................................................................................................................................... 24
Parameter .................................................................................................................................................................................. 24
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8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
19
19
19
20
20
20
9 Detailed Description - SYSTEM Functions
9.1 SYSTEM
............................................................................................................................. 26
............................................................................................................................................................................................ 26
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9.1.1 Power Up/Down Conditions ....................................................................................................................................................... 26
9.1.2 Start-up Sequence ..................................................................................................................................................................... 26
......................................................................................................................................................................................... 27
9.3 Supervisor
.......................................................................................................................................................................................... 27
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9.2 Hibernation
VSUP Supervision ..................................................................................................................................................................... 27
VDD27 Supervision ................................................................................................................................................................... 27
Junction Temperature Supervision ............................................................................................................................................ 27
Power Rail Monitoring ................................................................................................................................................................ 27
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9.3.1
9.3.2
9.3.3
9.3.4
9.4 Interrupt Generation
........................................................................................................................................................................... 28
9.4.1 IRQ Source Interpretation .......................................................................................................................................................... 28
9.4.2 Interrupt Sources ....................................................................................................................................................................... 28
9.5 10-Bit ADC
......................................................................................................................................................................................... 29
9.5.1 Input Sources ............................................................................................................................................................................. 29
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AS3606 AS3607 2v2
Data Sheet - C o n t e n t s
9.5.2 Parameter .................................................................................................................................................................................. 29
9.6 GPIO Pins
.......................................................................................................................................................................................... 30
9.7 2-Wire-Serial Control Interface
........................................................................................................................................................... 31
9.7.1 Protocol ...................................................................................................................................................................................... 31
9.7.2 Parameter .................................................................................................................................................................................. 34
................................................................................................................................................................ 35
11 Application Information
11.1 Pad Cells
......................................................................................................................................................... 62
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10 Register Definition
.......................................................................................................................................................................................... 62
11.2 Application Schematics
.................................................................................................................................................................... 63
12 Package Drawings and Markings
............................................................................................................................................................. 69
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13 Ordering Information
......................................................................................................................................... 65
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AS3606 AS3607 2v2
Data Sheet - P i n A s s i g n m e n t s
4 Pin Assignments
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Figure 3. Pin Assignments (Top View)
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AS3606 AS3607 2v2
Data Sheet - P i n A s s i g n m e n t s
4.1 Pin Descriptions
Note: Pin description may change in preliminary data sheets.
Table 1. Pin Description for AS3606/07
Pin Number
AS3606 AS3607
Type
Description
if not used
VBATSW
-
1
SUP IO
Battery Switch Terminal to be connected to the Li-Ion battery
VSUPSW
1
2
SUP IO
Battery Switch Terminal to be connected to system supplies VSUPx
VUSB
2
3
SUP IN
Charger or USB Bus Power Input
BATTEMP
4
4
ANA IO
Li-Ion Charger Battery Temp. Sensor Input
External Battery Switch Gate Driver Output
open
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Pin Name
always needed
open
open
3
5
ANA OUT
VDD27
5
6
SUP IO
PVDD4
-
7
ANA OUT
VSUP5
6
8
SUP IN
PVDD3
7
9
ANA OUT
LDO3 Output
open
PVDD2
8
10
ANA OUT
LDO2 Output
open
PVDD1
9
11
ANA OUT
LDO1 Output
open
VSUP4
10
12
SUP IN
LDO1/2 Pos. Supply Terminal
always needed
SUP IN
CVDD1 Step Down Pos. Supply Terminal
always needed
14
DIG OUT
CVDD1 Step Down Switch Output to Coil
open
15
ANA IN
CVDD1 and Feedback Pin
open
16
ANA IO
Load Current Sink2 Terminal
open
17
ANA IO
Load Current Sink1 Terminal
open
18
DIG OUT
DCDC Step-Up Switch Output to Coil
open
19
ANA IN
DCDC Step-Up Feed-Back
open
20
ANA IO
General Purpose IO 4
open
21
ANA IO
General Purpose IO 2
open
open
LXC1
12
CVDD1
13
CURR2
14
CURR1
15
LXSU
16
FBSU
17
GPIO4
-
GPIO2
18
13
22
ANA IO
ANA IO
General Purpose IO 3
open
24
DIG IN
2-wire SERIF Clock Input
open
25
DIG IO
2-wire SERIF Data I/O
open
26
DIG IN
Power Up Input
open
23
27
DIG OUT
Interrupt Request Output
open
24
28
DIG IO
Reset Output
open
25
29
SUP IN
Digital Periphery Pos. Supply Terminal
VSUPx
CSCL
20
CSDA
21
PWRUP
22
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DVDD
always needed
23
19
GPIO3
XRES
LDO3/4 & LDO5 Pos. Supply Terminal, connect to VSUPSW
open
General Purpose IO 1
GPIO1
XIRQ
open
always needed
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LDO4 Output
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VSUP1
LDO5 Output default 2.7V
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EXTBATSW
always needed
26
30
SUP IN
LXC3
27
31
DIG OUT
CVDD3 Step Down Switch Output to Coil
open
CVDD3
28
32
ANA IN
CVDD3 and Feedback Pin
open
CVDD2
29
33
ANA IN
CVDD2 and Feedback Pin
open
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VSUP3
CVDD3 Step Down Pos. Supply Terminal
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AS3606 AS3607 2v2
Data Sheet - P i n A s s i g n m e n t s
Table 1. Pin Description for AS3606/07
Pin Name
Pin Number
AS3606 AS3607
Type
Description
if not used
LXC2
30
34
DIG OUT
CVDD2 Step Down Switch Output to Coil
open
VSUP2
31
35
SUP IN
CVDD2 Step Down Pos. Supply Terminal
always needed
VBATSW
32
36
SUP IO
Battery Switch Terminal to be connected to the Li-Ion battery
VSS
33
37
SUP IO
Exposed Pad: Neg. Supply Terminal for all blocks
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open
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always needed
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AS3606 AS3607 2v2
Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 9 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating
conditions.
Table 2. Absolute Maximum Ratings
Min
Max
Units
Comments
5V pins
-0.5
7.0
V
Applicable for pins VBATSW, VSUPSW, VSUP1/
2/3/4/5, PWRUP, GPIO1/2/3/4, VBUS
3V pins
-0.5
5.0
V
Applicable for pins DVDD
30V pins
-0.5
32
V
Applicable for pin LXSU, CURR1/2
5V pins with protection to VSUPx
-0.5
7.0
VSUPx+0.5
V
Applicable for pins EXTBATSW, FBSU
3V pins with protection to VDD27
-0.5
5.0
VDD27
V
Applicable for pins BATTEMP
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Parameter
3V pins with protection to DVDD
-0.5
5.0
DVDD+0.5
V
Applicable for pins XIRQ, XRES, CSCL, CSDA
3V pins with protection to VSUPx
-0.5
5.0
VSUPx+0.5
V
Applicable for pins PVDD1/2/3/4, VDD27,
CVDD1/2/3, LXC1,/2/3
Input Current (latch-up immunity)
-100
100
mA
Norm: JEDEC 78
1
W
PT for QFN32/36 package (RTH ~ 30K/W)
±1.5
kV
Norm: JEDEC JESD22-A114C
Continuous Power Dissipation (TA = +85ºC)
Continuous power dissipation
Electrostatic Discharge
Electrostatic Discharge HBM
1
Temperature Ranges and Storage Conditions
Junction Temperature
+110
ºC
Storage Temperature Range
-55
+125
ºC
Humidity non-condensing
5
85
%
260
ºC
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Temperature (soldering)
Package Body Temperature
3
Represents a max. floor live time of 168h
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Moisture Sensitive Level
2
Norm IPC/JEDEC J-STD-020
The lead finish for Pb-free leaded packages is
matte tin (100% Sn)
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1. Depending on actual PCB layout and PCB used
2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”
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AS3606 AS3607 2v2
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VSUPx=+2.7V...+5.5V, TA =-40ºC...+85ºC. Typical values are at VSUPx=+3.6V, TA=+25ºC, unless otherwise specified.
Table 3. Electrical Characteristics
Parameter
VBATSW
Battery Supply Voltage
VSUPx
Supply Voltage
VSUPSW, VSUP1/2/3/4/5
VBUS
USB VBUS Voltage
DVDD
Digital Periphery Supply Voltage
1.8
VDD27
Analog Supply Voltage
2.6
VDELTA+
Difference of Positive Supplies
TAMB
Operating Temperature Range
ISD
Shut-down current
@ VBATSW = 4.2V
600
nA
Iq
Quiescent current
All regulators off
reference & LDO5 on
160
µA
Min
Typ
Max
Unit
operation, VBUS > 2.7V
0
3.6
5.5
V
operation from battery
2.7
3.6
5.5
V
2.7
3.6
5.5
V
operating, VSUP5 > 2.7V
0
5.0
5.5
V
charging
4.5
5.0
5.5
V
3.6
V
3.5
V
0
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VDD27-VSUPx
2.7
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IO Pins
Condition
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Symbol
-40
+85
ºC
3V digital input pins
XRES, CSCL, CSDA
0
3.6V or
DVDD
+0.5
V
VIA3V
3V input pin
BATTEMP
0
3.6V or
VDD27
+0.5
V
VI5V
5V input pins
GPIO1/2/3/4
0
5.5V
V
VI5V
5V input pin
FBSU
0
5.5V or
VSUP5
+0.5
V
VI30V
20V analiog input pins
LXSU, CURR1/2
0
30
V
POR & Watchdog
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VID3V
Power-on Reset Activation Level
Power-on Reset activation level when
VDD27 decreases
2.15
V
VPOR_OFF
Power-on Reset Release Level
Power-on Reset release when VDD27
increases
2.0
V
100
mV
VPOR_HY
Power-on Hysteresis
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PWRUP
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VPOR_ON
Delay Time of pin PWRUP
Minimum key press time
VPWRUP_L
Input Level LOW
Pin PWRUP, VSUP5>3V
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VPWRUP_H
Input Level HIGH
IPWRUP
Internal Pull-down Current Source
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60
ms
0.5
V
Pin PWRUP, VSUP5>3V
VSUP5/3
V
Pin PWRUP, VSUP5<=3V
1
V
Pin PWRUP; @2.7V
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AS3606 AS3607 2v2
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
VDO_DL
Digital Output Driver Capability
(drive LOW)
Pins XRES, XIRQ, GPIOx @ 6mA, open
drain mode
IPU
Internal Pull-up Current Source
IPD
Internal Pull-down Current Source
Pins GPIOx @ 2.7V
VDI_L
Digital Input Level LOW
Pin GPIOx
30%
DVDD
VDI_H
Digital Input Level HIGH
Pin GPIOx
70%
DVDD
Max
Unit
20%
DVDD
V
Digital Inputs/Outputs
13
µA
Pins CSDA, CSCL @ 0V
100
µA
13
20
µA
V
V
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Pins XIRQ @ 0V
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AS3606 AS3607 2v2
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
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VSUPx = +3.6V, TA = +25ºC, unless otherwise specified.
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8 Detailed Description - Power Management Functions
8.1 Low Drop Out Regulators
These LDOs are designed to supply sensitive analog circuits, audio devices, AD and DA converters, micro-controller and other peripheral
devices. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered
devices.
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Stability is guaranteed with ceramic output capacitors of 1µF ±20% (X5R) or 2.2µF +100/-50% (Z5U). The low ESR of these caps ensures low
output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to
operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance
allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the
device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
8.1.1
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Figure 4. LDO Block Diagram
LDO5
This LDO generates the digital supply voltage used for the PMU itself.
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Input Voltage is VSUP5
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Output Voltage is VDD27 (typ. 2.7V), this LDO always starts at the beginning of the start-up sequence as it is needed for all further
operation. The default voltage cannot be changed in the boot ROM.
Driver strength: 100mA, can be programmed to 200mA
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It is set to a default output voltage of 2.7V, 100mAmax. It supplies the analog and digital part of the PMU. Additional external loads are possible
but must not exceed the supply ratings in total together with the operating internal blocks. Further, the external load must not induce noise to the
VDD27.
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.1.2
LDO 1, LDO2, LDO3 & LDO4
These LDOs can be used to generate the periphery voltage for the digital processor or other external components (e.g. ext. DAC, USB-PHY, SDCards, NAND-Flashes, FM-Tuner …). LDO4 is only available on AS3607.
Input Voltage VSUP5 for LDO3 and LDO4, and VSUP4 for LDO2 and LDO1
Output Voltage is PVDD1, PVDD2, PVDD3 & PVDD4 (1.2V to 3.5V)
Driver strength: 150mA, can be programmed to 250mA
8.1.3
Parameter
VSUPx=3.6V, TA= 25ºC, unless otherwise specified.
Table 4. LDO Parameter
Parameter
RON
On resistance
Power supply rejection ratio
IOFF
Shut down current
IVDD
Supply current
Noise
Output noise
tstart
Startup time
Vout_tol
Output voltage tolerance
f=1kHz
f=100kHz
Min
Typ
Max
Unit
1
Ω
70
dB
40
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PSRR
Condition
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Default value at start-up is defined by the boot ROM, when the boot ROM is not programmed the LDOs will not start-up
Line regulation
VLoadReg
Load regulation
ILIMIT
Current limitation
nA
without load
50
μA
low power enabled, without load
32
μA
10Hz < f < 100kHz
50
µV rms
200
µs
minimum ±50mV
-2.5%
2.5%
Static
<1
Transient; Slope: tr=10µs
<10
Static
<1
Transient; Slope: tr=10µs
<10
default
190
has to be enabled via register
350
mV
mV
mV
mA
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VLineReg
100
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
Figure 5. LDO Characteristics
Output Noise
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Load Regulation
transient load: 1mA – 100mA slope: 1µs
Output load: 150mA
Load Regulation
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Load Regulation
output load: 150mA
transient input voltage ripple: 500mV
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output load: 10mA
transient input voltage ripple: 500mV
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.2 DCDC Step-Down Converter
These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for
microprocessors.
Input Voltage VSUP1/2/3 (usually connected to VSUPSW)
Output Voltage CVDD1 & CVDD2 & CVDD3
The default value at start-up is defined by the boot ROM
DVM for all three outputs with selectable timings
Driver strength 700mA, DCDC2 & 3 can be combined together to double the output current
Under- and over-voltage detection
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High efficiency current force mode
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Output voltage levels can be programmed independently form 0.61V to 3.35V
1MHz or 2MHz switching frequency
Fast regulation mode
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Figure 6. DCDC Step-Down Block Diagram
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.2.1
Functional Description
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches
efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The
unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current
of 700mA, with an output capacitor of only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition.
To achieve optimized performance in different applications, adjustable settings allow to compromise between high efficiency and low input,
output ripple:
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Low Ripple, Low Noise Operation (current force mode = OFF). In this mode there is no minimum coil current necessary before
switching off the PMOS. As result, the ON time of the PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil
current is very small or the coil current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at
low input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip mode.
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Figure 7. DCDC Buck with Disabled Current Force / Pulse Skip Mode
1: LXC1 voltage
2: Coil current (1mV=1mA)
3: Output voltage
High Efficiency Operation (current force mode = ON). In this mode, there is a minimum coil current necessary before switching off the
PMOS. As result, fewer pulses at low output loads are necessary, and therefore the efficiency at low output load is increased. On the other hand
the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current.
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Figure 8. DCDC Buck with Enabled Current Force / Pulse Skip Mode
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1: LXC1 voltage
2: Coil current (1mV=1mA)
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3: Output voltage
It’s also possible to switch between these two modes dynamically during operation.
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DVM (Dynamic Voltage Management). To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled.
With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew
rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current.
Fast Regulation Mode. This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output
voltage. FRM needs an 22uF output capacitor instead the 10uF one to guarantee the stability of the regulator.
Low Frequency Operation. Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be
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reduced to achieve a higher efficiency.
100% PMOS ON Mode for Low Dropout Regulation. For low input to output voltage difference the DCDC converter can use 100% duty
cycle for the PMOS transistor, which is than in LDO mode.
Parameter
VSUP=3.6, TA= 25ºC, unless otherwise specified.
Table 5. DCDC Parameter
Parameter
Condition
Min
VIN
Input voltage
VSUPx
2.7
VOUT
Regulated output voltage
VOUT_tol
Output voltage tolerance
Iload
Maximum Load current
600
ILIMIT
Current limit
1000
RPSW
P-Switch ON resistance
VSUPx=3.0V
0.5
0.7
Ω
RNSW
N-Switch ON resistance
VSUPx=3.0V
0.5
0.7
Ω
fSW
Switching frequency
depending on DCDC_Cntr settings
1/2
MHz
fSWsc
Switching frequency
in shortcut case
0.6
MHz
Cout
Output capacitor
Ceramic, ±10% tolerance
10
µF
Lx
Inductor
±10% tolerance
2.2
µH
ηeff
Efficiency
Iout=150mA, Vout=3.0V
97
%
IVDD
Current consumption
Operating current without load
Shutdown current
65
0.1
µA
tMIN_ON
Minimum on time
80
ns
tMIN_OFF
Minimum off time
40
ns
Static
2
mV
VLineReg
Line regulation
Transient; Slope: tr=10µs, 100mV step, 200mA
load
10
minimum ±50mV
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Load regulation
Max
Unit
5.5
V
0.6125
3.35
V
-3%
3%
mV
700
mA
Static
5
Transient; Slope: tr=10µs,
100mA step
50
mA
mV
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VLoadReg
Typ
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Symbol
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8.2.2
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Figure 9. DCDC Step-down Performance Characteristics
DCDC buck Efficiency @2MHz, 3.6V VSUPx
100,00
95,00
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85,00
80,00
75,00
70,00
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Efficiency [%]
90,00
CVDD1 @ 1,2V Vout
CVDD1 @ 1,8V Vout
65,00
CVDD1 @ 3V Vout
1
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60,00
10
100
1000
Output Current [mA]
Output voltage vs. Output Current
1,225
Line Regulation
1,215
1,215
OUTPUT VOLTAGE [V] OUTPUT VOLTAGE [V] 1,21
1,205
1,195
IOUT=0mA
1,205
IOUT=125mA
IOUT=250mA
1,2
1,185
VOUT=1.2V
VIN=3.6V
1,175
1,195
0
50
100
150
200
250
3
OUTPUT CURRENT [mA]
3,4
3,8
4,2
4,6
5
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INPUT VOLTAGE [V]
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8.3 30V Step-Up DCDC Converter
The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 30V. A constant
switching-frequency results in a low noise on supply and output voltages.
It has two programmable high voltage current sinks (0 to 38.25mA) for driving e.g. white LEDs as back-light. It can drive also unbalanced strings
due to the internal automatic feedback selection.
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A voltage feedback mode allows generating constant supply voltages for e.g. OLEDs. The output voltage is set by an external resistor divider
and an internal current sink.
An internal protection circuit will shut down the regulator if the voltage on FBSU exceeds the over voltage threshold. No more external protection
has to be used to avoid an exceeding of the operation conditions in a no load situation.
Voltage Feedback
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8.3.1
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Figure 10. DCDC15 Block Diagram
Setting bit SU_CURR_FB = 0 enables voltage feedback at pin FBSU.
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The output voltage is regulated to a constant value, given by (Bit SU_GAIN should be set to 1 in this configuration)
UStep up_out = (R1+R2)/R2 *1.25 + IFB * R1
(EQ 1)
If R2 is not used, the output voltage is by (Bit SU_GAIN should be set to 0 in this configuration)
UStep up_out = 1.25 + IFB * R1
(EQ 2)
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Where:
UStep up_out = Step Up DC/DC Converter output voltage
R1 = Feedback resistor R1
R2 = Feedback resistor R2
IFB = Tuning current at pin FBSU; 0 to 31µA
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Table 6. Voltage Feedback Example Values
UStep up_out
UStep up_out
µA
R1 = 1MΩ, R2 not used
R1 = 500kΩ, R2 = 50kΩ
0
-
13.75
1
-
14.25
2
-
14.75
3
-
15.25
4
-
15.75
5
6.25
16.25
6
7.25
7
8.25
8
9.25
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IDCDC_FB
16.75
17.25
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17.75
9
10
11
12
13
14
15
…
30
31
10.25
18.25
11.25
18.75
12.25
19.25
13.25
19.75
14.25
20.25
15.25
20.75
16.25
21.25
…
…
31.25
28.75
32.25
29.25
Note: The voltage on CURR1 and CURR2 must not exceed 30V.
8.3.2
Over Voltage Protection (OVP)
DLS & Dimming
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8.3.3
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Setting bit SU_CURR_FB = 1 enables feedback via the current sink pins. The voltage on the current sink pin is regulated to VCURR. The
selection of the current sink with the larger load is done automatically. The pin FBSU acts as an overvoltage protection in this mode. Please be
sure to set the voltage to a higher level than needed to drive the longer LED string. the calculation of the resistor can be done the same as
described in the chapter above.
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AS3606/07 feature external dimming inputs via CURR1, CURR2, GPIO1 or GPIO2 by directly connecting a PWM output of e.g. the display
controller for DLS (dynamic luminance scaling). Manual dimming can be done at any time by setting the sink current via I2C commands.
8.3.4
Current Sinks
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The current sinks work independent from each other and can also be used without the booster, or can act as a dimming input if they are not
needed as a sink.
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8.3.5
Parameter
VSUPx=3.6V, TA= 25ºC, unless otherwise specified.
Table 7. DCDC Parameter
Symbol
Parameter
Condition
Min
VSW
High Voltage Pin
Pin FBSU
0
IVDD
Quiescent Current
Pulse Skipping mode
VFB
Feedback Voltage, Transientt
VFBSU
Typ
Unit
30
V
140
0
Feedback Voltage, for voltage
regulation
Pin FBSU
1.2
1.25
VCURR
Feedback Voltage, for current sink
regulation
Pin CURR1 or CURR2
0.4
0.5
IDCDC_FB
Additional Tuning Current at Pin
DCDC_FB and over voltage
protection
Adjustable by software using Register DCDC
control1
1µA step size (0-31µA)
VPROTECT = 1.25V +
IDCDC_FB * R1
V
5
V
1.3
V
0.6
V
31
µA
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30
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0
Pin FBSU
µA
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Pin CURR1 or CURR2
Accuracy of Feedback Current at
full scale
Max
RSW
Switch Resistance
ILOAD
Load Current
@ 30V output voltage
FSW
Fixed Switching Frequency
SU_FREQU = 0
COUT
Output Capacitor
Ceramic, ±20%. Use nominal 4.7µF capacitors
to obtain at least 0.7µF under all conditions
(voltage dependence of capacitors)
L
Inductor
Use inductors with small CPARASITIC (<100pF)
for high efficiency
tMIN_ON
Minimum On-Time
Guaranteed per design
MDC
Maximum Duty Cycle
Guaranteed per design
-6
0
6
%
1
Ω
50
mA
1
MHz
0.7
4.7
µF
7
10
13
µH
100
190
ns
84
90
%
Figure 11. 30V Step-Up Performance Characteristics
DCDC Boost 6 LEDs
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90,00
85,00
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Efficiency (%)
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80,00
75,00
70,00
65,00
60,00
55,00
1
10
100
Output Current [mA]
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8.4 Charger
This block can be used to charge a 4V Li-Ion accumulator. It supports constant current and constant voltage charging modes with adjustable
charging currents (94 to 1000mA) and maximum charging voltage (3.9 to 4.25V).
The charger consists basically of a pre-regulator, which limits the current from e.g. the USB input and provides a constant VSUP after reaching
EOC (end of charge) and the battery switch, which is controlling the current into the battery.
Input Voltage of the pre-regulator: VUSB
CVM (constant voltage), CCM (constant current) and trickle charging
Adjustable EOC voltage and EOC current limit
Selectable input -, trickle- and charging-current limit
Auto-resume with selectable resume voltage level
Charger time-out supervision with selectable time-out setting
No battery detection
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Battery temperature supervision supporting two levels (45 or 50ºC) and 100k or 10k NTC types
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Output of the battery switch and battery terminal: VBATSW
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Output of the pre-regulator and input for the battery switch and system supply: VSUPSW
Status register and interrupt generation
Per default the USB current limit is set to 470mA and the charger is switched off.
The current battery and charger input voltage can be measured with the general purpose ADC.
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Figure 12. Charger Block Diagram
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8.4.1
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Figure 13. Charger States
Soft Charge/Trickle Charge
If the battery and therefore VBATSW is below 3V the charger is working in a fixed soft charge mode with a smaller trickle charging current of 24265mA. After reaching the 3V level the charger switches to the constant current mode with the programmed charging current.
8.4.2
End of Charge Detection
For the EOC level 4 presets can be selected. This makes it possible to monitor the charging progress also during constant voltage mode. If the
EOC level is reached an interrupt can be generated, but it is also possible to poll the charger status bits at any time.
8.4.3
VSUPSW and Temperature Supervision
Battery Temperature Supervision
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8.4.4
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The charger will automatically reduce the charging current if VSUPSW drops below the selected level. It will automatically stop charging when
the chip temperature gets too to hot. The charger will return to normal operation as defined in the charger registers if VSUPSW and the chip
temperature return to their normal operating range.
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This charger block also features a supply for an external NTC resistor to measure the battery temperature while charging. If the temperature is
too high (voltage on BATTEMP pin is below VBATTEMP_ON) the charger will stop operation. If needed an interrupt can be generated based on
this event. When the battery temperature drops the charger the voltage on BATTEMP pin will rise above VBATTEMP_OFF and the charger will
start charging again. This is forming a temperature hysteresis of about 3 to 5°C to avoid an oscillation of the charger.
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The levels for switching off the charger (45ºC or 55ºC) as well as the type of NTC (10k or 100k) can be selected via register settings. The battery
temperature supervision via the NTC can be switched off (NTC_ON = 0).
The supply for the NTC will be only on when a charger is detected and NTC_ON bit is set.
8.4.5
No Battery Detection
If the charger state machine reaches EOC 2 times within a very short period it assumes that there is no battery connected to the VBATSW
terminal.
After this a sensing current of 1uA is applied to the BATTEMP pin to detect if a battery is reconnected.
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8.4.6
Charger Modes
8.4.7
Parameter
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Figure 14. Charger Modes
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VDD27=2.7, TA= 25ºC, unless otherwise specified.
Table 8. Charger Parameter
Parameter
ch
Symbol
Condition
Min
Typ
Max
Unit
Charging Current
@ 470mA
INOM
-8%
INOM
INOM
+8%
mA
VCHG (0-7)
Charging Voltage
end of charge is true
VNOM
-50mV
VNOM
VNOM
+33mV
V
0.8
V
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ICHG (0-7)
rising edge on VUSB start
VON_ABS
VON_REL
Charger On Voltage Detection
VOFF_REL
VBATTEMP_ON
Battery Temp. high level
(45 or 55ºC)
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rising edge on VUSB end
3.5V
V
VUSB-VBATSW
170
VUSB-VBATSW
50
mV
VSUP >3V
NTCbeta=4200
610 or
400
mV
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Table 8. Charger Parameter
Parameter
Condition
VBATTEMP_OFF
Battery Temp. low level
(42 or 50ºC)
VSUP >3V
NTCbeta=4200
Min
Typ
700 or
500
mV
IBATTEMP
NTC Bias Current
100k
10k
15
150
µA
ICHG_OFF
End Of Charge current level
VSUP >3V
8%
10%
15%
20%
INOM
IREV_OFF
Reverse current shut down
VSUPSW = 5V, VUSB open
<1
RON_BATSW
Battery Switch On-resistance
Unit
mA
µA
Ω
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0.15
Max
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Symbol
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9 Detailed Description - SYSTEM Functions
9.1 SYSTEM
The system block handles the power up, power down and regulator voltage settings of the PMU.
Power Up/Down Conditions
The chip powers up when one of the following conditions is true:
Table 9. Power UP Conditions
Source
Description
1
PWRUP PwUp
2
VBUS PwUp
ON_KEY High Level at PWRUP pin of >= 1/3 VBATSW
USB Plug-In …. High level at VBUS pin of >= 4.5V and >2.7V on VSUP5
The chip automatically shuts off if one of the following conditions arises:
Table 10. Power DOWN Conditions
Source
1
SERIF MAJOR PwDn
2
Emergency PwDn
3
SERIF Watch-Dog PwDn
4
Junction-Temp PwDn
Power-Down if junction temperature rises up to 140degC.
This threshold can be lowered with bits <4:0> in reg 21h.
This supervisor can be disabled with bit 2 in reg. 20h.
5
VDD27 LOW PwDn
Power-Down if VDD27 LDO5 has 10% under-voltage for more than 680µs.
This supervisor can get disabled with bit 6 in reg. 21h.
6
CVDD1 LOW PwDn
Power-Down if enabled with bit 7 in reg. 23h and
CVDD1 DCDC has 10% under-voltage for more than 680µs.
7
CVDD2 LOW PwDn
Power-Down if enabled with bit 5 in reg. 23h and
CVDD2 DCDC has 10% under-voltage for more than 680µs.
8
CVDD3 LOW PwDn
Power-Down if enabled with bit 3 in reg. 23h and
CVDD3 DCDC has 10% under-voltage for more than 680µs.
9
VSUP LOW PwDn
Power-Down if VSUPx goes below the defined level in Reg22h (bits <3:1>)
This supervisor has to be enabled with bit 4 in reg. 22h.
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Power-Down by SERIF writing 0h to register 20h
Power-Down if PWRUP pin is HIGH for 8sec.
This has to be enabled in register 21h, per default a reset cycle is initiated. It can also be changed to 4s.
write 3h to reg. 20h … enable SERIF watch-dog
Power-Down if no SERIF read is seen for 500ms.
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9.1.2
Description
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9.1.1
Start-up Sequence
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The start-up sequence is defined in the boot ROM and will be fixed during the production test.
The sequence and voltage of the regulators can be freely chosen for the start-up sequence with the following limitations:
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VDD27 will always start-up, after a ~5ms delay the sequencer will start-up the other chosen regulators with either 0, 1 or 4ms delay each.
A maximum of 6 regulators (no matter of DCDC or LDO) or 5 regulators and a changed GPIO configuration can be chosen for the start-up.
On a 7th time-slot PVDD2 can be started-up, but has reduced setting on the output voltage
Te
PWRGOOD will be activated ~3ms after the last regulator.
XRES will be released 10ms to 110ms (set in the boot ROM) after the last regulator started up.
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9.2 Hibernation
Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible interrupt of the PMU. The
interrupt has to be enabled before going to hibernation.
Table 11. Hibernation
Description
Enter via GPIO
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
- Set the GPIO to input
- Select the GPIO for hibernation control (GPIO_DIMM_HBN_SEL <1:0>)
- Enable hibernation via GPIO (GPIO_HBN_ON)
- Define which regulators should be kept powered and enter hibernation by writing to Reg 1Ch_0x04 + Reg
17h-4. This register MUST NOT be read back!!!
- Drive the selected GPIO to LOW.
Note that hibernation will shutdown regulators which are not in the keep list of the mentioned Reg 17h-4 writing and
are part of the power-up sequence.
Enter via SW
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
- Set a delay for entering hibernation if needed (HBN_DELAY<1:0>)
- Define which regulators should be kept powered and enter hibernation by writing to Reg 1Ch_0x04 + Reg
17h-4. This register MUST NOT be read back.!!!
Note that hibernation will shutdown regulators which are not in the keep list of the mentioned Reg 17h-4 writing and
are part of the power-up sequence.
Hibernation
VDD27 chip supply is kept ON
All other regulators are switched OFF dependent on the KEEP-Bits
XRES goes active (can be disabled in the boot ROM) and PWRGOOD goes inactive
Leave
9.3 Supervisor
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State
The chip will come out of Hibernation with
- IRQ activation or
- GPIO control
Start-Up sequence is provided defined by the boot ROM.
9.3.1
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This supervisor function can be used for automatic detection of VSUP brown out or junction over-temperature condition.
VSUP Supervision
The VSUP supervision has a selectable level. If the shutdown is not enabled an interrupt can be generated.
VDD27 Supervision
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9.3.2
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If VDD27 reaches the “programmed level of VDD27” -10% for typ. 3ms, the PMU shuts down automatically. If the shutdown is not enabled an
interrupt can be generated.
9.3.3
Junction Temperature Supervision
Te
The temperature supervision level can also be set by 5 bits (120 to –15ºC). If the temperature reaches this level, an interrupt can be generated.
The over-temperature shutdown level is always 20ºC higher. This shutdown can be disabled in Reg. 20h.
9.3.4
Power Rail Monitoring
The 3 DCDC regulators have an extra monitor which observes the output voltage of the regulators. This power rail monitors are independent
from the 10bit ADC. To activate these please see related registers. For a shut down the voltage of the regulator has to be 10% or more below the
programmed value for more than 3ms.
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9.4 Interrupt Generation
All interrupt sources can get enabled or disabled by corresponding bits in the 4 IRQ-bytes. By default no interrupt source is enabled.
The XIRQ pin can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tri-state. The signal polarity can
be defined as active-low or active-high. Default state is open-drain active-low.
9.4.1
IRQ Source Interpretation
LEVEL. The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled.
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There are 3 different modules to process interrupt sources:
EDGE. The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.
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STATUS CHANGE. The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt
was the source. The IRQ stays active until the corresponding interrupt register gets read.De-bouncer
There is a de-bounce function implemented, a de-bounce time of 3ms is selected per default in the IRQ_ENRD_3 register (26h).
9.4.2
Interrupt Sources
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These IRQ events will activate the XIRQ pin:
10bit ADC end of conversion
Charger end of charge, connect/disconnect, no battery
Battery temperature high (at 45ºC or 50ºC with 100/10kΩ NTC)
Junction temperature high
Battery low (Brown-out voltage reached)
Power-up key (pin PWRUP) pressed
Current sink low voltage
Power rail monitor: over-voltage CVDD1, CVDD2, CVDD3
Te
ch
ni
ca
Power rail monitor: under-voltage CVDD1, CVDD2, CVDD3, VDD27
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Revision 1.03
28 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.5 10-Bit ADC
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature
supervision, button press detection, etc.
9.5.1
Input Sources
Table 12. ADC10 Input Sources
Source
Range
LSB
Description
0
VSUP
5.120V
5mV
check main system supply voltage
1
GPIO3
5.120V
5mV
2
GPIO4
5.120V
5mV
3
VBATSW
5.120V
5mV
4
VUSB
5.120V
5mV
check USB/charger input voltage
5.120V
5mV
Source defined by DC_TEST in register 18h
check battery charging temperature
BATTEMP
2.048V
2mV
7
GPIO1
5.120V
5mV
8
GPIO2
5.120V
5mV
9
PWRUP
5.120V
5mV
B
C
VBE_1µA
D
VBE_2µA
E
F
9.5.2
Parameter
am
lc s
on A
te G
nt
st
il
6
A
check battery voltage of 4V Li-Ion accumulator
lv
5
al
id
#
2mV
reserved
2mV
reserved
1.024
1mV
measuring basis-emitter voltage of temperature sense transistor;
Tj = (674 - ADC10<9:0>) / 2
1.024
1mV
measuring basis-emitter voltage of temperature sense transistor;
Tj = (694 - ADC10<9:0>) / 2
1mV
reserved
1mV
reserved
VDD27=2.7, TA= 25ºC, unless otherwise specified.
Table 13. ADC10 Parameter
Symbol
Parameter
ADC Full Scale Range
TCON
Conversion Time
Min
Typ
Max
2.16
ca
ADCFS
Condition
34
50
V
µs
Te
ch
ni
-
Unit
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.6 GPIO Pins
AS3607 features 4 GPIO pins, AS3606 has 2 GPIO pins.
If not re-configured in the start-up sequence GPIO1, GPIO3 and GPIO4 are input per default.GPIO2 is set to output and the pin is driven to low
right at the beginning of the startup sequence. GPIO3/4 have one state defined as input and three states as output. The following table shows
the different input/output options.
Table 14. GPIO Configuration
GPIO2
GPIO4/3
00
xCharging (1Hz pulses)
LOW
HiZ / HiZ (input)
01
xVSUP_low
xVSUP_low
xVSUP_low / xCharging (1Hz pulses)
10
xPWRUP
HIGH
xPWRUP / PWRGOOD
11
PWRGOOD
xCharging (1Hz pulses)
xEOC / xCharger_active
lv
al
id
GPIO1
When configured as input the following functionality is available:
ADC input, to measure external voltage sources
am
lc s
on A
te G
nt
st
il
Wake-up input to return from hibernation
Hibernation enable input (GPIO1/2/3 only)
PWM dimming input (GPIO1/2/3 only)
GPIO pins have a 200kOhm pull-down resistor activated when they are used as an input. (HiZ-mode).
Table 15. GPIO Output Functions
Function
Description
xCharging (1Hz pulses)
The output will be high when the charger is no active. The output toggles between high and low as
long as the charging is on going. If EOC, a timeout or overtempertur event stops the charger the
output stops toggling.
xCharger_active
The output will be high when the charger is no active or in EOC; it will be low if the charger is active.
The output will be high when the charger active; it will be low if the charger is has reached EOC.
The output will return back to high if the charger enters resume state.
xEOC
The output will get low if the PWRUP pin is high.
xPWRUP
PWRGOOD
HIGH
The output will be high.
The output will be low.
ni
LOW
The output will get low if the VSUP undervoltage level is reached.
ca
xVSUP_low
The output will be high about 3ms after the start-up seuence is finished. It will be low during the
sequence. Please be sure to configure the GPIO before the pull-up voltage, otherwise the output
will be high as long as the GPIOs are default inputs.
Te
ch
Please note that all GPIO pins are open-drain outputs. They can only output a logic “high” if a pull-up and the corresponding pull-up voltage is
present.
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.7 2-Wire-Serial Control Interface
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audio processors
8Ch_write
8Dh_read
Protocol
al
id
9.7.1
Table 16. 2-Wire Serial Symbol Definition
Definition
RW
Note
S
Start condition after stop
R
1 bit
Sr
Repeated start
R
1 bit
DW
Device address for write
R
1000 1100b (8Ch)
DR
Device address for read
R
WA
Word address
R
Acknowledge
N
reg_data
data (n)
P
WA++
1000 1101b (8Dh)
8 bit
am
lc s
on A
te G
nt
st
il
A
lv
Symbol
W
1 bit
No Acknowledge
R
1 bit
Register data/write
R
8 bit
Register data/read
W
8 bit
Stop condition
R
1 bit
Increment word address internally
R
during acknowledge
AS3606 AS3607 (=slave) receives data
AS3606 AS3607 (=slave) transmits data
Figure 15. Byte Write
DW
A
WA
A
ca
S
reg_data
A P
Te
ch
ni
write register
WA++
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
Figure 16. Page Write
DW
A
WA
A
reg_data 1
A
reg_data 2
...
reg_data n
write register
WA++
A
P
write register
WA++
lv
write register
WA++
A
al
id
S
am
lc s
on A
te G
nt
st
il
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The devicewrite address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is
incremented internally, in order to write subsequent data bytes on subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition
followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE
state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent
register bytes can be read from the slave. The word address is incremented internally.
Figure 17. Random Read
S
DW
A
WA
A Sr
DR
A
data
N P
ca
read register
WA++
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer
from the master.
ni
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the
device-write address and the word address.
Te
ch
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address
transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located
by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on
the bus.
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
Figure 18. Sequential Read
DW
A
WA
A Sr
DR
A
data
read register
WA++
A
reg_data 2
read register
WA++
A
...
reg_data n
read register
WA++
N P
al
id
S
lv
Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the
Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data
bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master
has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
S
am
lc s
on A
te G
nt
st
il
Figure 19. Current Address Read
DR
A
data
read register
WA++
A
reg_data 2
read register
WA++
A
...
reg_data n
N P
read register
WA++
Te
ch
ni
ca
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer.
The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte
transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can
be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master
sends a not-acknowledge following the last data byte and a subsequent STOP condition.
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.7.2
Parameter
TS
TSU
TH
THD
TL
al
id
Figure 20. 2-Wire Serial Timing
TPD
CSDA
1-7
9
1-7
R/W
ACK
8
Data
9
ACK
1-7
8
9
Data
ACK
Stop
Condition
am
lc s
on A
te G
nt
st
il
Start
Address
Condition
8
lv
CSCL
DVDD =2.9V, Tamb=25ºC, unless otherwise specified.
Table 17. 2-Wire Serial Parameter
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VCSL
CSCL, CSDA Low Input Level
(max 30%DVDD)
0
-
0.87
V
VCSH
CSCL, CSDA High Input Level
CSCL, CSDA (min 70%DVDD)
2.03
-
5.5
V
HYST
CSCL, CSDA Input Hysteresis
200
450
800
mV
VOL
CSDA Low Output Level
-
-
0.4
V
Tsp
Spike insensitivity
50
100
-
ns
TH
Clock high time
max. 400kHz clock speed
500
ns
TL
Clock low time
max. 400kHz clock speed
500
ns
CSDA has to change Tsetup before rising edge
of CSCL
250
-
-
ns
No hold time needed for CSDA relative to rising
edge of CSCL
0
-
-
ns
CSDA H hold time relative to CSDA edge for
start/stop/rep_start
200
-
-
ns
ca
TSU
CSDA prop delay relative to lowgoing edge of
CSCL
50
ns
Te
ch
TPD
ni
THD
TS
at 3mA
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Revision 1.03
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10 Register Definition
b7
b6
b5
b4
b3
b2
PMU Register
17h-3
CVDD3
17h-4
Hibernation
17h-5
DCDC_Cntr
17h-7
GPIO_Cntr
18h-1
PVDD1
18h-2
PVDD2
18h-3
PVDD3
b0
lv
CVDD2
b1
am
lc s
on A
te G
nt
st
il
17h-2
ni
ca
CVDD1
ch
35 - 70
17h-1
Te
Revision 1.03
VSEL_CVDD1<6:0>
0 … OFF
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
VSEL_CVDD2<6:0>
0 … OFF
CVDD2_fast
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0: Cext=10µF
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
1: Cext=22µF
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
VSEL_CVDD3<6:0>
0 … OFF
CVDD3_fast
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0: Cext=10µF
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
1: Cext=22µF
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
KEEP_PVDD4
KEEP_PVDD3
KEEP_PVDD2
KEEP_PVDD1
KEEP_CVDD3
DVM_CVDD23<1:0>
CFM_CVDD23_OF
0: immediate;
CVDD1_FREQ
CFM_CVDD1_OFF CVDD23_FREQ
F
1: 42µs/step;
0: 2MHz
0: 2MHz
0: pulse skip on
0: pulse skip on
2: 166µs/step;
1: 1MHz
1: 1MHz
1: pulse skip off
1: pulse skip off
3: 666µs/step
MUX_GPIO43<1:0>
DRIVE_GPIO1
MUX_GPIO2<1:0>
DRIVE_GPIO2
0: HiZ/HiZ; 1: xVSUP_low/xCharging;
0: HiZ
0: LOW; 1: xVSUP_low;
0: opend drain
2: xPWRUP/PWRGOOD;
1: opend drain
2: HIGH; 3: xCharging
1: HiZ
3: xEOC/xCharger_active
VSEL_PVDD1<4:0>
LP_PVDD1
ILIM_H_PVDD1
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
0: normal mode
PVDD1_ON
0: 150mA
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
1: 250mA
VSEL_PVDD2<4:0>
LP_PVDD2
ILIM_H_PVDD2
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
0: normal mode
PVDD2_ON
0: 150mA
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
1: 250mA
VSEL_PVDD3<4:0>
LP_PVDD3
ILIM_H_PVDD3
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
0: normal mode
PVDD3_ON
0: 150mA
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
1: 250mA
CVDD1_fast
0: Cext=10µF
1: Cext=22µF
al
id
Name
KEEP_CVDD2
KEEP_CVDD1
DVM_CVDD1<1:0>
0: immediate;
1: 42µs/step;
2: 166µs/step;
3: 666µs/step
MUX_GPIO1<1:0>
0: xCharging; 1: xVSUP_low;
2: xPWRUP; 3: PWRGOOD
Data Sheet - R e g i s t e r D e f i n i t i o n
Addr
AS3606 AS3607 2v2
www.austriamicrosystems.com
Table 18. I2C Register Overview
Table 18. I2C Register Overview
18h-5
VDD27
PRG_VDD27
0: boot ROM
1:register defined
19h-0
CHG_Cntr
BAT_DET_OFF
AUTO_RESUME
19h-1
CHG_VCntr
19h-2
CHG_ICntr
19h-3
CHG_Conf
19h-4
CHG_NTC
19h-5
CHG_TIME
19h-6
19h-7
CHG_STAT1
CHG_STAT2
1Ah-1
Out_Cntr
1Ah-2
Clk_Cntr
1Bh-1
Boost_Cntr1
1Bh-2
Boost_Cntr2
b5
b4
b3
b2
b1
VSEL_PVDD4<4:0>
LP_PVDD4
0x00 – 0x0F: 1.2V + VSEL * 50mV → (1.2V – 1.95V)
0: normal mode
1: low power mode 0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV → (2.0V – 3.5V)
VSEL_VDD27<3:0>
LP_VDD27
0x0 – 0x2: 2.3V
0x3 – 0xF: 2.0V + VSEL* 100mV → (2.3V – 3.5V)
USB_CURRLIM <3:0>
0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380mA; 7:
BAT_CHARGE_ON
428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA;
E-F: not defined
CHG_V_EOC <2:0>
VSUP_MIN<1:0>
0: 3.9V; 1: 3.95V; 2: 4.0V; 3: 4.05V;
0: 3.9V; 1: 3.6V;
4: 4.1V; 5: 4.15V; 6: 4.2V; 7: 4.25V
2: 4.2V; 3: 4.5V
b0
al
id
PVDD4_ON
USB_PREREG_ON
ni
ca
am
lc s
on A
te G
nt
st
il
CHG_V_RESUME <2:0>
0: 3.85V; 1: 3.9V; 2: 3.95V; 3: 4.0V;
4: 4.05V; 5: 4.1V; 6:4.15V; 7: 4.2V
CHG_I_CONSTANT <3:0>
CHG_I_TRICKLE <3:0>
0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380mA; 7:
0: 25mA; 1: 35mA; 2: 47mA; 3: 59mA; 4: 71mA; 5: 83mA; 6: 95mA; 7: 107mA;
428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA;
8: 118mA; 9: 129mA; A: 150mA; B: 190mA; C: 221mA; D: 265mA; E-F: not defined
E-F: not defined
VSUP_EOC <2:0>
CHG_I_EOC<1:0>
0: 4.3V; 1: 4.4V; 2: 4.5V; 3: 4.6V;
0: 8%; 1: 15%;
4: 4.7V; 5: 4.8V; 6: 4.9V; 7: 5.0V
2: 10%; 3: 20%
NTC_MODE
NTC_10K
NTC_ON
0: 55°C; 1: 45°C 0: 100k; 1: 10K;
CHG_TIMEOUT <3:0>
TMAX_TIMER
0:disabled; 1: 0.5h; 2: 1h; 3: 1,5h; 4: 2h; 5: 2.5h; 6: 3h; 7: 3.5h;
8: 4h; 9: 4.5h; A: 5h; B: 5.5h; C: 6h; D: 6.5h; E: 7h; F:7.5h
NO_BAT
BATTEMP_HIGH EOC
CV
TRICKLE
RESUME
CC
CHG_DET
BATSW_MODE <1:0>
MUX_XIRQ<1:0>
DRIVE_XIRQ<1:0>
HBN_DELAY<1:0>
0: XIRQ; 1: CLKINT1;
0: 6mA OD; 1: 6mA PP;
DCDC23_1.4A
GPIO_HBN_ON
0: 0ms; 1: 8ms;
2: CLKINT2; 3: IRQ
2: 1mA PP; 3: HiZ
2: 16ms; 3: 32ms
GPIO_DIMM_HBN_SEL <1:0>
CLKINT1<1:0>
CLKINT2<1:0>
0: LOW; 1: GPIO1;
0: 2MHz; 1: 1MHz;
0: LOW; 1: CLK1Hz (charger);
2: GPIO2; 3: GPIO3
2: 1kHz; 3: 125Hz
2: do not use; 3: HIGH
SU_EXTDIM<1:0>
SU_SLOWDIM
0: no dimm; 1: CURR1;
SU_OVP_OFF
SU_CURR_FB
SU_FASTSKIP
SU_ON
0: tbd
2: CURR2; 3: GPIO1/2/3
1: tbd
SU_IFB<4:0>
SU_CURRLIM
SU_GAIN
SU_FREQ
0x00 - 0x1F: 1µA * SU_IFB;
ch
36 - 70
PVDD4
Te
Revision 1.03
18h-4
b6
ILIM_H_PVDD4
0: 150mA
1: 250mA
ILIM_H_VDD27
0: 100mA
1: 200mA
lv
b7
Data Sheet - R e g i s t e r D e f i n i t i o n
Name
AS3606 AS3607 2v2
www.austriamicrosystems.com
Addr
Table 18. I2C Register Overview
CURR2
1Ch
PMU_Enable
System Register
20h
SYSTEM
SUPERVISOR1
22h
SUPERVISOR2
23h
IRQENRD_0
24h
IRQENRD_1
25h
IRQENRD_2
26h
IRQENRD_3
ADC10_0
2Fh
ADC10_1
-
-
CVDD1_SD
CVDD1_under
PWRUP_IRQ
CVDD1_IRQ
CVDD1_over
GPIO1_IRQ
CHG_TEMP_IRQ
CHG_TEMP
CHG_EOC_IRQ
CHG_EOC
SD_XRES_TIME
0: 8s;
1: 4s
VDD27low_SD_OF
F
CVDD2_SD
CVDD2_under
GPIO2_IRQ
b1
37 - 70
ch
b0
PMU_ENABLE <2:0>
SubRegister addresses for registers:
0x17: DCDC regulators
0x18: LDOs regulators
0x19: Charger
0x1A: IO_clock_control
0x1B: BackLight_DCDC
PWR_HOLD
VSUPlow_SD_ON VSUPlow_SUP<2:0>
VSUPlow_SUP_OFF
CVDD2_IRQ
CVDD2_over
GPIO3_IRQ
ADC10_MUX<3:0>
0: VSUP; 1: GPIO3; 2: GPIO4; 3: VSUPSW; 4: VUSB
5: DC_TEST; 6: BATTEMP; 7: GPIO1; 8: GPIO2; 9: PWRUP; A,B: -;
C: VBE_1µA; D: VBE_2µA; E,F: ADC10<7:0>
Te
b2
JTEMP_SUP_OFF I2C_WD_ON
JTEMP_SUP<4:0>
Temp_ShutDown = 140ºC - JTEMP_SUP*5ºC → (140ºC...5ºC)
Temp_IRQ = 120ºC - JTEMP_SUP*5ºC → (120ºC...-15ºC)
CHG_NoBAT_IRQ CHG_DET_IRQ
CHG_NoBat
CHG_DET
T_DEB<1:0>
0: 3ms; 1: off;
ca
2Eh
PMU_GATE
ni
Revision 1.03
21h
DC_TEST_MUX <3:0>
0: open; 1: PVDD1; 2: PVDD2;
3: PVDD3; 4: PVDD4; 5: VDD27;
6: CVDD1; 7: CVDD2; 8: CVDD3;
9-F: not defined
Design_Version<3:0>
PWRUP_SD_XRES <1:0>
0: XRES; 1: -;
2: SD; 3: SD
b3
al
id
1Bh-4
b4
lv
CURR1
b5
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1Bh-3
b7
b6
ICURR1<7:0>
0x00 - 0xFF: 150µA * ICURR;
ICURR2<7:0>
0x00 - 0xFF: 150µA * ICURR;
CVDD3_SD
CVDD3_under
GPIO4_IRQ
CVDD3_IRQ
CVDD3_over
-
-
ICURR_LV_IRQ
VSUP_LOW_IRQ
VDD27_LOW_IRQ
JTEMP_HIGH
-
ADC_EOC
-
ADC10<9:8>
-
Data Sheet - R e g i s t e r D e f i n i t i o n
Name
AS3606 AS3607 2v2
www.austriamicrosystems.com
Addr
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 19. CVDD1 Register
Name
Base
Default
CVDD1
2-wire serial
00h
CVDD1 DC/DC Buck Regulator Control Register
Offset: 17h-1
al
id
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
Bit Description
7
CVDD1_fast
0
R/W
Selects a faster regulation mode for CVDD1 suitable for larger load changes.
0: normal mode, Cext=10µF
1: fast mode, Cext=22µF required
6:0
VSEL_CVDD1<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
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Table 20. CVDD2 Register
lv
Bit
Name
Base
Default
CVDD2
2-wire serial
00h
CVDD2 DC/DC Buck Regulator Control Register
Offset: 17h-2
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
7
CVDD2_fast
6:0
VSEL_CVDD2<6:0>
Default
Access
Bit Description
0
R/W
Selects a faster regulation mode for CVDD2 suitable for larger load changes.
0: normal mode, Cext=10µF
1: fast mode, Cext=22µF required
000000
R/W
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Te
ch
ni
ca
Bit
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 21. CVDD3 Register
Name
Base
Default
CVDD3
2-wire serial
00h
CVDD3 DC/DC Buck Regulator Control Register
Offset: 17h-3
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
Bit Description
7
CVDD3_fast
0
R/W
Selects a faster regulation mode for CVDD3 suitable for larger load changes.
0: normal mode, Cext=10uF
1: fast mode, Cext=22uF required
6:0
VSEL_CVDD3<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
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al
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Bit
Table 22. Hibernation Register
Name
Base
Default
Hibernation
2-wire serial
00h
PMU Hibernation Control Register
Hibernation starts when writing this register, except hibernation via GPIO is selected.
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input. This register MUST NOT be read back!!!
Offset: 17h-4
Bit Name
Default
Access
7
-
0
n/a
6
KEEP_PVDD4
0
W
Keeps the programmed PVDD4 level during hibernation.
0: power down PVDD4
1: keep PVDD4
5
KEEP_PVDD3
0
W
Keeps the programmed PVDD3 level during hibernation.
0: power down PVDD3
1: keep PVDD3
4
KEEP_PVDD2
0
W
Keeps the programmed PVDD2 level during hibernation.
0: power down PVDD2
1: keep PVDD2
3
KEEP_PVDD1
0
W
Keeps the programmed PVDD1 level during hibernation.
0: power down PVDD1
1: keep PVDD1
2
KEEP_CVDD3
0
W
Keeps the programmed CVDD3 level during hibernation.
0: power down CVDD3
1: keep CVDD3
0
W
Keeps the programmed CVDD2 level during hibernation.
0: power down CVDD2
1: keep CVDD2
0
W
Keeps the programmed CVDD1 level during hibernation.
0: power down CVDD1
1: keep CVDD1
ch
ni
ca
Bit
KEEP_CVDD2
Te
1
0
KEEP_CVDD1
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Bit Description
Revision 1.03
39 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 23. DCDC_Cntr Register
Name
Base
Default
DCDC_Cntr
2-wire serial
00h
DC/DC Step Down Control Register
Offset: 17h-5
Bit
Bit Name
Default
Access
7
CFM_CVDD23_OFF
0
R/W
Disables pulse skip mode for DCDC2 and DCDC3
0: current force mode / pulse skip enabled
1: current force mode / pulse skip disable
6
CFM_CVDD1_OFF
0
R/W
Disables pulse skip mode for DCDC1
0: current force mode / pulse skip enabled
1: current force mode / pulse skip disable
5
CVDD23_FREQ
0
R/W
Selects the switching frequency for DCDC2 and DCDC 3
0: 2MHz
1: 1MHz
4
CVDD1_FREQ
0
R/W
Selects the switching frequency for DCDC1
0: 2MHz
1: 1MHz
3:2
DVM_CVDD23<1:0>
00
R/W
Configures the dynamic voltage management (output voltage slope) for
CVDD2 and CVDD3
00: immediate change of the output voltage
01: 32µs/step
10: 128µs/step
11: 512µs/step
1:0
DVM_CVDD1<1:0>
00
R/W
Configures the dynamic voltage management (output voltage slope) for
CVDD1
00: immediate change of the output voltage
01: 32µs/step
10: 128µs/step
11: 512µs/step
Te
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lv
Bit Description
al
id
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 24. GPIO_Cntr Register
Name
Base
Default
GPIO_Cntr
2-wire serial
00h
GPIO Control Register
Offset: 17h-7
Default
Access
7:6
MUX_GPIO43<1:0>
00
R/W
Configures GPIO4 and GPIO3
00: HiZ / HiZ (GPIOs are inputs)
01: xVSUP_low / xCharging
10: xPWRUP / PWRGOOD
11: xEOC / xCharger_active
5
DRIVE_GPIO2
0
R/W
Configures GPIO2 as input or output
0: open drain (output)
1: HiZ (input)
4:3
MUX_GPIO2<1:0>
00
R/W
Configures GPIO2 output mode
00: LOW
01: xVSUP_low
10: HIGH
11: xCharging
2
DRIVE_GPIO1
0
R/W
Configures GPIO1 as input or output
0: HiZ (input)
1: open drain (output)
1:0
MUX_GPIO1<1:0>
00
R/W
Configures GPIO1 output mode
00: xCharging
01: xVSUP_low
10: xPWRUP
11: PWRGOOD
Table 25. PVDD1 Register
Base
Default
PVDD1
2-wire serial
00h
Access
PVDD1_ON
0
R/W
Enables PVDD1 regulator
0: PVDD1 switched off
1: PVDD1 switched on
0
R/W
Selects the higher current limit for PVDD1
0: default mode, 150mA
1: 250mA mode
ni
Default
ILIM_H_PVDD1
Te
6
PVDD1 Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
ch
7
ca
Name
Offset: 18h-1
Bit
Bit Description
lv
Bit Name
am
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Bit
al
id
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Description
5
LP_PVDD1
0
R/W
Selects the low power mode for PVDD1
0: PVDD1 is in normal operation
1: PVDD1 supply current is reduced
4:0
VSEL_PVDD1<4:0>
00000
R/W
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by boot ROM
0x00-0x0F: 1.2V+VSEL*50mV → (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V)
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 26. PVDD2 Register
Name
Base
Default
PVDD2
2-wire serial
00h
PVDD2 Control Register
Offset: 18h-2
al
id
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
7
PVDD2_ON
0
R/W
Enables PVDD2 regulator
0: PVDD2 switched off
1: PVDD2 switched on
6
ILIM_H_PVDD2
0
R/W
Selects the higher current limit for PVDD2
0: default mode, 150mA
1: 250mA mode
5
LP_PVDD2
0
R/W
Selects the low power mode for PVDD2
0: PVDD2 is in normal operation
1: PVDD2 supply current is reduced
4:0
VSEL_PVDD2<4:0>
00000
R/W
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by the boot ROM
0x00-0x0F: 1.2V+VSEL*50mV → (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V)
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Table 27. PVDD3 Register
Bit Description
lv
Bit
Name
Base
Default
PVDD3
2-wire serial
00h
PVDD3 Control Register
Offset: 18h-3
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
7
PVDD3_ON
6
5
Access
0
R/W
Enables PVDD3 regulator
0: PVDD1 switched off
1: PVDD1 switched on
ILIM_H_PVDD3
0
R/W
Selects the higher current limit for PVDD3
0: default mode, 150mA
1: 250mA mode
LP_PVDD3
0
R/W
Selects the low power mode for PVDD3
0: PVDD3 is in normal operation
1: PVDD3 supply current is reduced
VSEL_PVDD3<4:0>
00000
R/W
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by the boot ROM
0x00-0x0F: 1.2V+VSEL*50mV → (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V)
ni
Bit Description
Te
ch
4:0
Default
ca
Bit
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 28. PVDD4 Register
Name
Base
Default
PVDD4
2-wire serial
00h
PVDD4 Control Register
Offset: 18h-4
al
id
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
7
PVDD4_ON
0
R/W
Enables PVDD4 regulator
0: PVDD4 switched off
1: PVDD4 switched on
6
ILIM_H_PVDD4
0
R/W
Selects the higher current limit for PVDD4
0: default mode, 150mA
1: 250mA mode
5
LP_PVDD4
0
R/W
Selects the low power mode for PVDD4
0: PVDD4 is in normal operation
1: PVDD4 supply current is reduced
4:0
VSEL_PVDD4<4:0>
00000
R/W
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by the boot ROM
0x00-0x0F: 1.2V+VSEL*50mV → (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V)
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Table 29. VDD27 Register
Bit Description
lv
Bit
Name
Base
Default
VDD27
2-wire serial
00h
VDD27 Control Register
Offset: 18h-5
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
7
PRG_VDD27
0
n/a
Selects the output voltage control mode for VDD27
0:VDD27 is in default mode
1: VDD27 is register controlled (Reg. 18-5h)
6
ILIM_H_VDD27
0
R/W
Selects the higher current limit for VDD27
0: default mode, 100mA
1: 200mA mode
5
LP_VDD27
0
R/W
Selects the low power mode for VDD27
0: VDD27 is in normal operation
1: VDD27 supply current is reduced
ni
-
0
n/a
VSEL_VDD27<3:0>
0000
R/W
ch
5
ca
Bit
Te
3:0
www.austriamicrosystems.com
Bit Description
Sets the LDO output voltage in register control mode (default voltage of the
regulator is 2.7V)
0x0-0x2: 2.3V
0x3-0xF: 2.0V + VSEL*100mV → (2.3V-3.5V)
Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 30. CHG_Cntr Register
Name
Base
Default
CHG_Cntr
2-wire serial
C9h
Charger Control Register
Offset: 19h-0
Bit
Bit Name
Default
Access
7
BAT_DET_OFF
1
R/W
Disables the battery detection
0: Battery detection switched on
1: Battery detection switched off
6
AUTO_RESUME
1
R/W
Defines the behavior after end of charge (EOC)
0: auto resume is disabled
1: auto resume enabled, charger will start charging when VBATSW
drops below the resume level
5
BAT_CHARGE_ON
0
R/W
Enables the battery charging
0: VSUP is supplied via USB pre-regulator, but the battery switch is
open
1: normal battery charging operation from USB pre-regulator
4:1
USB_CURRLIM
<3:0>
1000
R/W
Sets the USB pre-regulator current limit
0x0: 94mA (USB low current)
0x1: 141mA
0x2: 189mA
0x3: 237mA
0x4: 285mA
0x5: 332mA
0x6: 380mA
0x7: 428mA
0x8: 470mA (USB high current)
0x9: 517mA
0xA: 599mA
0xB: 760mA
0xC: 882mA
0xD: 1060mA
0xE, 0xF: do not use
0
USB_PREREG_ON
ca
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lv
Bit Description
al
id
This is an extended register but does not need to be enabled as Reg. 1Ch is 000b per default.
This register is reset at a VDD27-POR or XRES input.
R/W
Enables the USB pre-regulator and current limiter
0: USB pre-regulator is switched off
1: USB pre-regulator supplies VSUP from VUSB input
Te
ch
ni
1
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 31. CHG_VCntr Register
Name
Base
Default
CHG_VCntr
2-wire serial
36h
Charger Voltage Control Register
Offset: 19h-1
Bit Description
al
id
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
7:5
CHG_V_RESUME
<2:0>
001
R/W
4:3
VSUP_MIN<1:0>
10
R/W
Defines the minimum VSUP voltage during trickle or constant current
charging. The charging current will be reduced if VSUP would drop below
this threshold.
00: 3.9V
01: 3.6V
10: 4.2V
11: 4.5V
2:0
CHG_V_EOC
<2:0>
110
R/W
Sets the charger end of charge voltage threshold
000: 3.90V
001: 3.95V
010: 4.00V
011: 4.05V
100: 4.10V
101: 4.15V
110: 4.20V
111: 4.25V
Te
ch
ni
ca
am
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lv
Sets the charger auto resume voltage threshold
000: 3.85V
001: 3.90V
010: 3.95V
011: 4.00V
100: 4.05V
101: 4.10V
110: 4.15V
111: 4.20V
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 32. CHG_ICntr Register
Name
Base
Default
CHG_VCntr
2-wire serial
21h
Charger Current Control Register
Offset: 19h-2
Bit Name
Default
Access
7:4
CHG_I_CONSTANT
<3:0>
0010
R/W
3:0
CHG_I_TRICKLE
<3:0>
Bit Description
Sets the current during constant current charging
0x0: 94mA
0x1: 141mA
0x2: 189mA
0x3: 237mA
0x4: 285mA
0x5: 332mA
0x6: 380mA
0x7: 428mA
0x8: 470mA
0x9: 517mA
0xA: 599mA
0xB: 760mA
0xC: 882mA
0xD: 1060mA
0xE, 0xF: do not use
am
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lv
Bit
al
id
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
R/W
Sets the current during constant current charging
0x0: 24mA
0x1: 35mA
0x2: 47mA
0x3: 59mA
0x4: 71mA
0x5: 83mA
0x6: 95mA
0x7: 107mA
0x8: 118mA
0x9: 129mA
0xA: 150mA
0xB: 190mA
0xC: 221mA
0xD: 265mA
0xE, 0xF: do not use
Te
ch
ni
ca
0001
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 33. CHG_Config Register
Name
Base
Default
CHG_Config
2-wire serial
15h
Charger Configuration Register
Offset: 19h-3
Default
Access
7:5
-
000
n/a
4:3
CHG_I_EOC<1:0>
10
R/W
2:0
VSUP_EOC
<2:0>
al
id
Bit Name
Bit Description
Configures the end of charge current threshold. Charging will be stopped if
the current drops below the threshold.
00: 8% of constant current setting
01: 15%
10: 10%
11: 20%
am
lc s
on A
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st
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lv
Bit
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
101
R/W
Defines VSUP voltage after EOC and isolated battery.
000: 4.3V
001: 4.4V
010: 4.5V
011: 4.6V
100: 4.7V
101: 4.8V
110: 4.9V
111: 5.0V
Table 34. CHG_NTC Register
Name
Base
Default
CHG_NTC
2-wire serial
01h
Charger NTC Control Register
Offset: 19h-4
Bit Name
Default
-
2
NTC_MODE
1
ch
NTC_10K
NTC_ON
Bit Description
0000 0
n/a
0
R/W
Defines the temperature level for the battery temperature supervisor to stop
charging. (for beta of NTC = 4250)
0: 55ºC
1: 45ºC
0
R/W
Defines the type of NTC used for battery temperature supervisor.
0: 100kΩ
1: 10kΩ
1
R/W
Enables the battery temperature supervisor via NTC resistor.
0: NTC battery temp supervision disabled
1: NTC battery temp supervision enabled
Te
0
Access
ca
7:3
ni
Bit
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
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Data Sheet - R e g i s t e r D e f i n i t i o n
Table 35. CHG_TIME Register
Name
Base
Default
CHG_TIME
2-wire serial
07h
Charger Time Control Register
Offset: 19h-5
Access
7:5
-
0000 0
n/a
4
TMAX_TIMER
0
R
Returns the time-out supervision status
0: no time-out reached
1: charger time-out reached, charging stopped
W
Resets the charger time supervision
0: 1: resets time-out counter
3:0
al
id
Default
Bit Description
lv
Bit Name
am
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st
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Bit
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
CHG_TIMEOUT
<3:0>
0111
R/W
Sets the current during constant current charging
0x0: charger timer disabled
0x1: 0.5h
0x2: 1h
0x3: 1.5h
0x4: 2h
0x5: 2.5h
0x6: 3h
0x7: 3.5h
0x8: 4h
0x9: 4.5h
0xA: 5h
0xB: 5.5h
0xC: 6h
0xD: 6.5h
0xE: 7h
0xF: 7.5h
Table 36. CHG_STAT1 Register
Base
Default
CHG_STAT1
2-wire serial
xxh
Bit Name
Default
Access
Bit Description
NO_BAT
x
R
Status if a battery is detected to the system, by measuring the NTC value on
BATTEMP pin.
0: battery detected
1: no battery detected
ch
Bit
Te
7
Charger Status Register 1
This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
ni
Offset: 19h-6
ca
Name
6
BATTEMP_HIGH
x
R
Only valid if a charger is deducted.
0: battery temperature o.k.
1: battery temperature higher 55ºC/45ºC (seed NTC_MODE)
5
EOC
x
R
0: end of charge not reached. Bit is cleared automatically if
USB_PREREG_ON or BAT_CHARGE_ON is cleared or resume state is
entered
1: end of charge reached
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Revision 1.03
48 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 36. CHG_STAT1 Register
Name
Base
Default
CHG_STAT1
2-wire serial
xxh
Charger Status Register 1
Offset: 19h-6
Bit Name
Default
Access
Bit Description
4
CV
x
R
1: if charger is in constant voltage (top-off charge) mode
3
TRICKLE
x
R
1: if charger is in trickle charging mode
2
RESUME
x
R
1: if VBATSW dropped below resume threshold
1
CC
x
R
1: if charger is in constant current charging mode
0
CHG_DET
x
R
1: if a charger adapter is detected on VUSB pin
lv
Bit
al
id
This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
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Table 37. CHG_STAT2 Register
Name
Base
Default
CHG_STAT2
2-wire serial
xxh
Charger Status Register 2
Offset: 19h-7
Bit
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
-
1:0
BATSW_MODE
<1:0>
Access
xxxx xx
n/a
x
R
Bit Description
Shows the battery switch operation mode
00: battery switch open, no ideal diode operation (just for charger start-up)
01: battery switch open, ideal diode operation (charger connected but EOC
reached)
10: battery switch acting as a voltage limited current source (charging)
11: battery switch closed (charger disconnected)
Te
ch
ni
ca
7:3
Default
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Revision 1.03
49 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 38. Out_Cntr Register
Name
Base
Default
Out_Cntr
2-wire serial
00h
DCDC mode and XIRQ Output Control Register
Offset: 1Ah-1
al
id
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
7
DCDC23_1.4A
0
R/W
Combines DCDC2 and DCDC3 to one regulator for 1.4A output currents
0: DCDC2 and DCDC3 working independent
1: DCDC2 & DCDC3 combined for 1.4A (DCDC3 registers have no effect)
6
GPIO_HBN_ON
0
R/W
0: Hibernation enable via GPIOs disabled
1: Hibernation enalbe via GPIOs enabled
GPIO selected via GPIO_DIMM_HBN_SEL <1:0>
5:4
HBN_DELAY<1:0>
00
R/W
Sets the delay time for going into hibernation after writing to register 17-4h
00: 0ms
01: 8ms
10: 16ms
11: 32ms
3:2
DRIVE_XIRQ<1:0>
00
R/W
Sets the XIRQ output pin to open-drain, push-pull or tri-state and sets
various driving strengths
00: 6mA open-drain output
01: 6mA push-pull output
10: 1mA push-pull output
11: HiZ, tri-state
1:0
MUX_XIRQ<1:0>
00
R/W
Multiplexes various digital signals to the XIRQ output pin
00: XIRQ, active low interrupt request signal
01: CLKINT1, internal clock signal, see Clk_Cntr register
10: CLKINT2, internal clock signal, see Clk_Cntr register
11: IRQ, active low reset signal
Base
Default
2-wire serial
00h
ni
Bit Name
Default
Access
Bit Description
CLKINT2<1:0>
00
R/W
Selects the CLKINT2 input source. Note, this is an internal clock, which can
be multiplexed to the XRES output.
00: LOW, drives the signal to logic “0”
01: CLK1Hz charger
10: do not use
11: HIGH, drives the signal to logic “1”
00
R/W
Selects the CLKINT1 frequency. Note, this is an internal clock, which can be
multiplexed to XIRQ output.
00: 2MHz
01: 1MHz
10: 1kHz
11: 125Hz
Te
5:4
Clock Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
ch
7:6
ca
Name
Clk_Cntr
Offset: 1Ah-2
Bit
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Table 39. Clk_Cntr Register
Bit Description
lv
Bit
CLKINT1<1:0>
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Revision 1.03
50 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 39. Clk_Cntr Register
Name
Base
Default
Clk_Cntr
2-wire serial
00h
Clock Control Register
Offset: 1Ah-2
Bit Name
Default
Access
3:2
GPIO_DIMM_HBN_SEL
<1:0>
00
R/W
1:0
-
00
n/a
Bit Description
Selects input for external dimming or hibernation control
00: disable dimming or hibernation via GPIO
01: GPIO1
10: GPIO2
11: GPIO3
lv
Bit
al
id
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
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Table 40. BOOST_Cntr1 Register
Name
Base
Default
BOOST_Cntr1
2-wire serial
00h
DCDC step-up Control Register 1
Offset: 1Bh-1
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
7
SU_ON
0
R/W
6
-
0
n/a
5
SU_SLOWDIM
0
R/W
Selects the DCDC step-up regulator external dimming mode
0: for dimming frequencies <1kHz
1: for dimming frequencies >1kHz
4:3
SU_EXTDIM<1:0>
00
R/W
Selects the DCDC step-up external PWM dimming input
00: no ext. dimming
01: CURR1 controlled
10: CURR2 controlled
11: GPIO1/2/3 controlled (selected via GPIO_DIMM_HBN_SEL <1:0>)
2
SU_OVP_OFF
1
SU_CURR_FB
0
SU_FASTSKIP
ca
Bit
ch
Te
www.austriamicrosystems.com
Enables the DCDC step-up regulator
0: SU switched off
1: SU switched on (will be reset if VFB exceeds the maximum and the
current drops to zero)
R/W
Disables the DCDC step-up over-voltage protection
0: SU OVP switched on
1: SU OVP switched off
0
R/W
Selects the DCDC step-up feedback mode
0: voltage FB via pin FBSU
1: current feedback via CURR1 or CURR2 (automatic select)
0
R/W
Defines the DCDC step-up regulator output voltage at low loads, when pulse
skipping is active
0: Accurate output voltage, more ripple
1: Elevated output voltage, less ripple
ni
0
Bit Description
Revision 1.03
51 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 41. BOOST_Cntr2 Register
Name
Base
Default
BOOST_Cntr2
2-wire serial
00h
DCDC step-up Control Register 2
Offset: 1Bh-2
al
id
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
7:3
SU_IFB<4:0>
0 0000
R/W
Defines the tuning current at pin FBSU.
0x00: 0µA
0x01: 1µA
0x02: 2µA
...
0x1F: 31µA
2
SU_CURRLIM
0
R/W
Selects the DCDC step-up converter coil current limit
0: normal current limit
1: current limit increased by about 50%
1
SU_GAIN
0
R/W
DCDC step-up converter feedback gain is selected automatically depending
on current or voltage feedback mode. Setting this bit to “1” will choose the
alternative feedback gain setting.
0
SU_FREQ
00
R/W
Defines the DCDC step-up switching frequency
0: 1MHz
1: 500kHz
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Table 42. CURR1 Register
Bit Description
lv
Bit
Name
Base
Default
CURR1
2-wire serial
00h
Current Sink 1 Register
Offset: 1Bh-3
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
7:0
ICURR1<7:0>
Default
Access
ca
Bit
R/W
Sets the current for current sink 1 in 255 steps with 140.626µA stepsize
0x00: Current sink 1 switched off
0x01: 0.15 mA
0x02: 0.30 mA
0x03: 0.45 mA
..
0xFE: 38,10 mA
0xFF: 38.25 mA
Te
ch
ni
0x00
Bit Description
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Revision 1.03
52 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 43. CURR2 Register
Name
Base
Default
CURR2
2-wire serial
00h
Current Sink 2 Register
Offset: 1Bh-4
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
Access
7:0
ICURR2<7:0>
0x00
R/W
Bit Description
al
id
Bit Name
Sets the current for current sink 2 in 255 steps with 140.626µA stepsize
0x00: Current sink 2 switched off
0x01: 0.141 mA
0x02: 0.281 mA
0x03: 0.422 mA
..
0xFE: 35,72 mA
0xFF: 35.86 mA
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lv
Bit
Table 44. PMU_Enable Register
Name
Base
Default
PMU_Enable
2-wire serial
00h
PMU_Enable Register
Selects the extended register on address 17h to 1Bh and enables writing to these PMU register. It also
sets the ADC10 multiplexer to measure various regulator voltages
This register is reset at a VDD27-POR or XRES input.
Offset: 1Ch
Bit Name
7:4
DC_TEST_MUX
<3:0>
Default
Access
Bit Description
0000
R/W
Allows multiplexing internal and external supply voltages to one DC test
node which can be further multiplexed to the ADC10. The accuracy is 5mV/
LSB (see reg. 2Eh)
0x0: open
0x1: PVDD1
0x2: PVDD2
0x3: PVDD3
0x4: PVDD4
0x5: VDD27
0x6: CVDD1
0x7: CVDD2
0x8: CVDD3
0x9-0xF: n/a
PMU_GATE
ch
3
ni
ca
Bit
PMU_ENABLE
<2:0>
Te
2:0
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0
R/W
Enables all settings made in registers 17h to 1Bh at once. If this bit is set,
changes are activated as soon as they are written to the related register.
0: no change
1: change at once
000
R/W
Selects extended registers 17h to 1Bh for the next read or write. This register
has to be set before every read or write even if the selection is not changing.
0: 19h-0 selected
1: 17h-1 to 1Bh-1 selected
2: 17h-2 to 1Bh-2 selected
...
7: 17h-7 to 1Bh-7 selected
Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 45. SYSTEM Register
Name
Base
Default
SYSTEM
2-wire serial
51h
SYSTEM Register
Offset: 20h
al
id
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7:4
Design_Version<3:0>
0101
R
3
-
0
n/a
2
JTEMP_SUP_OFF
0
R/W
Junction temperature supervision (level can be set in register 21h)
0: temperature supervision enabled
1: temperature supervision disabled
1
I2C_WD_ON
0
R/W
2-wire serial interface watchdog
To reset the watchdog counter a 2-wire serial read operation has to be
performed at least every 500ms. If the watchdog counter is not reset, the
PMU will be powered down.
0: watchdog is disabled
1: watchdog is enabled
0
PWR_HOLD
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lv
Number to identify the design version
0101: for chip version 2v2
1
R/W
0: power up hold is cleared and PMU will power down
1: is automatically set to on after power on
Table 46. SUPERVISOR1 Register
Name
Base
Default
SUPERVISOR1
2-wire serial
00h
SUPERVISOR Register 1
Offset: 21h
This register is reset at a VDD27-POR or XRES input.
Bit Name
7:6
PWRUP_SD_XRES
<1:0>
5
SD_XRES_TIME
4:0
JTEMP_SUP<4:0>
Default
Access
00
R/W
Applying a high signal on PWRUP pin for about 8s will
00: perform a reset cycle
01: have no effect
10: initiate a shut-down
11: initiate a shut-down
R/W
Halfs the time from pulling PWRUP high to XRES or SD
0: 8s
1: 4s
R/W
Sets the threshold for junction temperature emergency shutdown and
junction temperature interrupt
Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5ºC
Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5ºC
ca
Bit
Te
ch
ni
0
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0
Bit Description
JT_Sup
00000
00001
.
.
11110
11111
Revision 1.03
IRQ Shutdown
120°C
115°C
.
.
-30°C
-35°C
140°C
135°C
.
.
-10°C
-15°C
54 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 47. SUPERVISOR2 Register
Name
Base
Default
SUPERVISOR2
2-wire serial
00h
SUPERVISOR Register 2
Offset: 22h
Bit Description
7:6
-
00
n/a
5
VDD27low_SD_OFF
0
R/W
0: VDD27low (VDD27 -10%) shut down enabled
1: VDD27low shut down disabled
4
VSUPlow_SD_ON
0
R/W
0: VSUPlow shut down enabled
1: VSUPlow shut down disabled
3:1
VSUPlow_SUP<2:0>
000
R/W
Sets the threshold for VSUP supervisor
000: 2.7V
001: 2.9V
010: 3.1V
011: 3.2V
100: 3.3V
101: 3.4V
110: 3.5V
111: 3.6V
0
VSUPlow_SUP_OFF
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Access
al
id
Default
lv
Bit Name
0
R/W
0: VSUPlow supervision enabled
1: VSUPlow supervision disabled
Te
ch
ni
ca
Bit
This register is reset at a VDD27-POR or XRES input.
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 48. First Interrupt Register
Name
Base
Default
IRQENRD_0
2-wire serial
00h
First Interrupt Register
Offset: 23h
al
id
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Bit Name
Default
Access
Bit Description
7
CVDD1_SD
0
W
Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD1
occurs
0: disable
1: enable
CVDD1_under
x
R
This bit is set when a –5% under-voltage at CVDD1 occurs
3
2
W
Enables interrupt for over-voltage/under-voltage supervision of CVDD1
0: disable
1: enable
CVDD1_over
x
R
This bit is set when a +8% over-voltage at CVDD1 occurs
CVDD2_SD
0
W
Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD2
occurs
0: disable
1: enable
CVDD2_under
x
R
This bit is set when a –5% under-voltage at CVDD2 occurs
CVDD2_IRQ
0
W
Enables interrupt for over-voltage/under-voltage supervision of CVDD2
0: disable
1: enable
CVDD2_over
x
R
This bit is set when a +8% over-voltage at CVDD2 occurs
CVDD3_SD
0
W
Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD3
occurs
0: disable
1: enable
CVDD3_under
x
R
This bit is set when a –5% under-voltage at CVDD3 occurs
CVDD3_IRQ
0
W
Enables interrupt for over-voltage/under-voltage supervision of CVDD3
0: disable
1: enable
CVDD3_over
x
R
This bit is set when a +8% over-voltage at CVDD3 occurs
-
00
n/a
Te
ch
1:0
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4
0
ca
5
CVDD1_IRQ
ni
6
lv
Bit
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 49. Second Interrupt Register
Name
Base
Default
IRQENRD_1
2-wire serial
00h
Second Interrupt Register
Offset: 24h
Bit Name
Default
Access
7
PWRUP_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at the PWRUP
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. VSUP/3 at the PWRUP input pin
occurs (PWRUP pin is commonly connected to the power-up button)
-
Enables interrupt which is invoked whenever a high signal at the GPIO1
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO1 input pin
occurs
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO2
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO2 input pin
occurs
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO3
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO3 input pin
occurs
0
W
Enables interrupt which is invoked whenever a high signal at the GPIO4
input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. tbd at the GPIO4 input pin
occurs
000
n/a
Te
ch
2:0
GPIO4_IRQ
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3
GPIO3_IRQ
W
ca
4
GPIO2_IRQ
0
ni
5
GPIO1_IRQ
lv
Bit
6
Bit Description
al
id
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 50. Third Interrupt Register
Name
Base
Default
IRQENRD_2
2-wire serial
00h
Third Interrupt Register
Offset: 25h
Bit Name
Default
Access
7
CHG_TEMP_IRQ
(status change)
0
W
Battery over-temperature interrupt setting
0: disable
1: enable interrupt if CHG_TEMP status bit changes
CHG_TEMP
x
R
Battery over-temperature status reading
0: battery temperature below off-threshold
1: battery temperature was too high and the charger was turned off. The
charger will be turned on again, when the temperature gets below the onthreshold
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4
CHG_EOC_IRQ
(status change)
0
W
Charger end of charge interrupt setting.
0: disable
1: enable interrupt if CHG_EOC status bit changes
CHG_EOC
x
R
Charger end of charge status reading
0: battery charging in progress
1: charging is complete, charging current is below selected level of nominal
current, charger was turned off.
CHG_NoBAT_IRQ
(status change)
0
W
Charger no battery interrupt setting
0: disable
1: enable interrupt if CHG_NoBat status bit changes
CHG_NoBat
x
R
Charger no battery status reading
0: battery connected
1: no battery detected at VBATSW pin
CHG_DET_IRQ
(status change)
0
W
Charger detect interrupt setting.
0: disable
1: enable interrupt if CHG_DET status bit changes
CHG_DET
x
R
Charger detect status reading
0:charger disconnected
1: charger connected
0
n/a
ca
5
lv
Bit
6
Bit Description
al
id
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
-
2
ICURR_LV_IRQ
(level)
Te
ch
ni
3
www.austriamicrosystems.com
0
W
Current sink undervoltage interrupt setting.
0: disable
1: enable interrupt if the outputvoltage of one of the current sinks gets below
the target regulation voltage
x
R
Current sink undervoltage status reading
0: normal voltage on ICURR1 and ICURR2
1: voltage at ICURR1 or ICURR2 dropped below target voltage
Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 50. Third Interrupt Register
Name
Base
Default
IRQENRD_2
2-wire serial
00h
Third Interrupt Register
Bit Name
Default
Access
1
VSUP_LOW_IRQ
(level)
0
W
VSUP under-voltage supervisor interrupt setting
0: disable
1: enable
x
R
VSUP supervisor interrupt reading
0: VSUP is above brown out level
1: VSUP has reached brown out level
The threshold can be set with VSUPlow_SUP<2:0> in SUPERVISOR2
register (22h). If the shutdown is enabled the interrupt will not occur.
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lv
Bit
VDD27_LOW_IRQ
(level)
0
W
VDD27 undervoltage supervisor interrupt setting
0: disable
1: enable
x
R
VDD27 supervisor interrupt reading
0: VDD27 is above threshold out level
1: VDD27 has reached threshold level (VDD27-10%).
If the shutdown is enabled the interrupt will not occur.
Te
ch
ni
ca
0
Bit Description
al
id
Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
Offset: 25h
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Revision 1.03
59 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 51. Fourth Interrupt Register
Name
Base
Default
IRQENRD_3
2-wire serial
00h
Fourth Interrupt Register
Offset: 26h
Bit
Bit Name
Default
Access
7:6
-
00
R/W
5
T_DEB<1:0>
0
R/W
4:3
-
00
R/W
2
JTEMP_HIGH
(level)
0
W
Supervisor junction over-temperature interrupt setting
0: disable
1: enable
x
R
Supervisor junction over-temperature interrupt reading
0: chip temperature below threshold
1: chip temperature has reached the threshold
The threshold can be set in the SUPERVISOR register (21h)
0
R/W
0
W
ADC end of conversion interrupt setting
0: disable
1: enable
x
R
ADC end of conversion interrupt reading
0: ADC conversion not finished
1: ADC conversion finished. Read out ADC10_0 and ADC10_1 register to
get the result (2Eh & 2Fh)
0
ADC_EOC
(edge)
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Sets the de-bounce time all interrupt inputs:
0: 3ms
1: off
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Bit Description
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Please be aware that writing to this register will enable/disable the corresponding
interrupts, while reading gets the actual interrupt status and will clear the register at the
same time. It is not possible to read back the interrupt enable/disable settings. This register is
reset at a VDD27-POR or XRES input.
www.austriamicrosystems.com
Revision 1.03
60 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 52. ADC10_0 Register
Name
Base
Default
ADC10_0
2-wire serial
0000 00xxb
First 10-bit ADC Register
Offset: 2Eh
Bit Name
Default
Access
7:4
ADC10_MUX<3:0>
0000
R/W
Bit Description
Selects ADC input source
0000: VSUP
0001: GPIO3
0010: GPIO4
0011: VBATSW
0100: VUSB
0101: defined by DC_TEST in register 0x1C
0110: BATTEMP
0111: GPIO1
1000: GPIO2
1001:PWRUP
1010: reserved
1011: reserved
1100: VBE_1uA
1101: VBE_2uA
1110: reserved
1101: reserved
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Writing to this register will start the measurement of the selected source.
This register is reset at a VDD27-POR, exception are bit 0 and 1
3:2
-
1:0
ADC10<9:8>
Table 53. ADC10_1 Register
00
n/a
xx
R
ADC result bit 9 to 8
Name
Base
Default
ADC10_1
2-wire serial
xxh
Second 10-bit ADC Register
Offset: 2Fh
This register is reset at a VDD27-POR.
Bit Name
ADC10<7:0>
Default
Access
00h
R
Bit Description
ADC results bits 7 to 0
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Bit
7:0
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Revision 1.03
61 - 70
AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
11 Application Information
11.1 Pad Cells
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Figure 21. Pad Cells Equivalant Circuit
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Revision 1.03
62 - 70
D
C
B
A
VSUP
Power ON
GND
Reset
Vbat-
BU13
Vbat+
BU12
ON
S1
ON
S2
Shield
BUS_GND
D+
D-
USB Mini
1
3
5
2
4
6
D16
1
PWRUP
XRES
C8
10uF
GND
GND
5
4
3
2
1
USB - Box Interface
BUS_PWR
U2
GND
1
3
5
GND
2.2uF
C9
VSUP
Vbat
10uH
L4
GND
D14
D11
D10
D8
D5
D3
GND
C16
2.2uF
C5
2.2uF
R17
0R
C17
1.5nF
GND
2
C18
R7
100k 15nF
R5
910k
1
2
GND
FB_SU
17
16
4
EXTBATSW3
Q1
FDC602P
32
GND
Q2
NDT014L
Q2 optional: for 50V only
D1
GND
10uF
C20
C7 VSUP
10uF
GND
C4
2.2uF
C6
2.2uF
FBSU
LXSU
BATTEMP
VBATSW
EXTBATSW
VSUPSW
VUSB
L1
2.2uH
CVDD1
GND
L2
2.2uH
C1
10uF
GND
with HV BL driver
System PMU
AS3606
DCDC SD 1-3
L3
2.2uH
C2
10uF
3
GND
C3
10uF
U1
AS3606_QFN32
Interface / GPIOs / VSS
GND
3
VDD27
VSUP5
PVDD3
PVDD2
VSUP4
PVDD1
A4
2.2uF
C19
10uF
0R
0R
GND
J11
LX3
VDD27
PVDD3
PVDD2
PVDD1
4
Sheet 3
of
4
Revision
V1.1
D6
ON LED
R6
100R
GND
GND
2.2uF
C15
GND
R14
R13
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Project Title
AS3606 Eval Board
GND
2.2uF
LX2
C13
CVDD2
CVDD3
C12
Date 17.02.2010
Originator DGM
Size
Title
4
combine DCDC SD 2 and 3 to 1.2A mode
remove L3 in this application
GND
4.7uF
2.2uF
GND
C11
C10
GND
DVDD
5
6
7
8
10
9
VSUP
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VSUP
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VDCDC_SU
BATTEMP
XRES
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XRIQ
CSCL
CSDA
CVDD2
LX2
J3
10k
10k
10k
10k
11
VSUP1
CURR1
15
DVDD
13
CVDD1
12
LXC1
Charger
DCDC
SU 30V
CURR2
14
31
VSUP2
30
ch
CSCL
20
CSCL
33
R1
R2
R3
R15
2
4
6
2
CVDD3
LX3
1
29
CVDD2
26
VSUP3
VSS
USB - Box Interface / I2C Interface
28
CVDD3
PRG LDOs
LXC2
XRES
24
XRES
XIRQ
23
XRIQ
CSDA
21
CSDA
PWRUP
22
PWRUP
DVDD
27
LXC3
GPIO1
19
GPIO1
GPIO2
18
GPIO2
Revision 1.03
25
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ON
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AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
11.2 Application Schematics
Figure 22. Typical AS3606 Application Schematic
63 - 70
D
C
B
GND
Reset
VSUP
Power ON
Vbat-
BU13
Vbat+
BU12
USB Mini
Shield
BUS_GND
D+
D-
BUS_PWR
U2
GND
PWRUP
Vbat
ON
S2
ON
S1
GND
C8
1uF
1
XRES
GND
2.2uF
C9
VSUP
10uH
L4
D14
D11
D10
D8
D5
D3
C7
10uF
GND
D1
R17
0R
EXTBATSW
Q1
FDC602P
Q1: optional
GND
GND
C4
2.2uF
C5
2.2uF
4
36
1
5
2
3
C6
2.2uF
C17
1.5nF
GND
2
C18
R7
100k 15nF
R5
910k
FB_SU
L1
2.2uH
FBSU
LXSU
BATTEMP
VBATSW
VBATSW
EXTBATSW
VSUPSW
VUSB
GND
Q2
NDT014L
18
Q2 optional: for 50V only
19
GND
C16
2.2uF
VDCDC_SU
BATTEMP
GND
10uF
5
VSUP
VSUP
GND
L2
2.2uH
GND
Interface / GPIOs / VSS
with HV BL driver
System PMU
AS3607
DCDC SD 1-3
L3
2.2uH
C2
10uF
GND
C3
10uF
11
DVDD
VDD27
VSUP5
PVDD4
PVDD3
PVDD2
VSUP4
PVDD1
GND
3
A4
Project Title
GND
GND
R14
R13
GND
Sheet 3
4
4
Revision
*
of
VDD27
PVDD4
PVDD3
PVDD2
PVDD1
D6
ON LED
R6
100R
GND
2.2uF
C24
GND
2.2uF
GND
2.2uF
C15
LX3
GND
C14
C19
10uF
0R
0R
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GND
2.2uF
C12
LX2
AS3607 Application circuit
GND
2.2uF
4.7uF
CVDD2
CVDD3
C11
Date 17.02.2010
Originator DGM
Size
Title
29
DVDD
6
8
7
9
10
12
4
combine DCDC SD 2 and 3 to 1.2A mode
remove L3 in this application
C10
*
AS3607_QFN36
VSUP
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C20
GND
D16
XRES
4
3
2
1
CPU - IF
ni
VSUP1
16
XRIQ
CSCL
CSDA
CVDD1
14
LXC1
2
4
6
15
CVDD1
1
3
5
C1
10uF
CSDA
25
Charger
DCDC
CURR2
SU 30V
VSUP2
28
1
3
5
CVDD2
LXC2
J3
26
A
10k
10k
10k
10k
13
CURR1
17
CURR1
CSCL
24
CSCL
VSS
37
DVDD
33
CVDD2
LX2
34
XRES
XRES
XIRQ
27
XRIQ
PWRUP
PWRUP
ch
R1
R2
R3
R15
2
4
6
3
GPIO1
GPIO1 22
Interface
2
CVDD3
GPIO2
GPIO2 21
35
CSDA
30
VSUP3
GPIO3
1
32
CVDD3
LX3
31
LXC3
PRG LDOs
GPIO4
Revision 1.03
GPIO3 23
www.austriamicrosystems.com
GPIO4 20
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AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 23. Typical AS3607 Application Schematic
64 - 70
AS3606 AS3607 2v2
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
12 Package Drawings and Markings
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Figure 24. AS3606 QFN32, 0.5mm Pitch
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Revision 1.03
65 - 70
AS3606 AS3607 2v2
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
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Figure 25. AS3607 QFN36, 0.5mm Pitch
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Revision 1.03
66 - 70
AS3606 AS3607 2v2
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
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Figure 26. QFN Marking
Table 54. Package Code YYWWZZZ
YY
year
WW
X
ZZ
working week assembly / packaging
plant identifier
free choice
Table 55. Start-up Revision Code
xx
FF
00
engineering samples, no sequence programmed or sequence programmed on request
default sequence (no sequence programmed)
customer specified sequence programmed during production test
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Sequence
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Revision 1.03
67 - 70
AS3606 AS3607 2v2
Data Sheet - R e v i s i o n H i s t o r y
Revision History
Date
Owner
Description
1.00
7.2010
pkm
first official release
1.01
9.2010
pkm
corrected GPIO2 bit description & GPIO hibernation description
updated package drawings
1.02
11.2010
pkm
corrected charger block diagram, updated package drawings
1.03
3.2011
pkm
added NTC supply description, added USB rising edge specification
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Note: Typos may not be explicitly mentioned under revision history.
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - O r d e r i n g I n f o r m a t i o n
13 Ordering Information
The devices are available as the standard products shown in Table 56.
Table 56. Ordering Information
Marking
Sequence
Description
Delivery Form
Package
R2v2-FF
sequence
programmable on
request
System PMU with HV Backlight
Tape & Reel
dry pack
QFN32 5x5 0.5mm pitch
AS3606-BQFP-00
R2v2-00
default sequence
System PMU with HV Backlight
Tape & Reel
dry pack
QFN32 5x5 0.5mm pitch
AS3606-BQFP-xx
R2v2-xx
customer specified
System PMU with HV Backlight
Tape & Reel
dry pack
QFN32 5x5 0.5mm pitch
AS3607-BQFP-FF
R2v2-FF
sequence
programmable on
request
System PMU with HV Backlight
Tape & Reel
dry pack
QFN36 6x6 0.5mm pitch
AS3607-BQFP-00
R2v2-00
default sequence
System PMU with HV Backlight
Tape & Reel
dry pack
QFN36 6x6 0.5mm pitch
AS3607-BQFP-xx
R2v2-xx
customer specified
System PMU with HV Backlight
Tape & Reel
dry pack
QFN36 6x6 0.5mm pitch
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Ordering Code
AS3606-BQFP-FF
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
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For further information and requests, please contact us mailto:[email protected]
or find your local distributor at http://www.austriamicrosystems.com/distributor
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Revision 1.03
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AS3606 AS3607 2v2
Data Sheet - C o p y r i g h t
Copyright
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
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Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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Revision 1.03
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