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AS3688
Datasheet, Confidential
austriamicrosystems
Datasheet, Confidential
AS3688
Flexible Lighting Management Unit (Charge Pump, DCDC Step Up,
Current Sink, ADC, LDO)
1 General Description
Three Programmable (8-bit) from: 0.15mA
to 38.25mA for RGB LEDs
− Three (AS3688B only; AS3688: One)
Programmable (8-bit) from: 0.15mA to
38.25mA for General Purpose
− Programmable Hardware Control (Strobe,
and Preview or PWM)
− Selectively Enable/Disable Current Sinks
Internal PWM Generation
− 8 Bit resolution
− Logarithmic up/down dimming
Led Pattern Generator
− Autonomous driving for any LED
10-bit Successive Approximation ADC
− 27µs Conversion Time
− Four Selectable Inputs: GPIO0-3
− Internal Temp. Measurement
− Support for Light Sensor, inluding a
adjustable current source (0-15uA)
Support for automatic LED function testing
(open and shorted LEDs can be identified)
Support for external Temperature Sensor
for high current LED protection (CURR3x)
Strobe Timeout protection
− Up to 1600ms
− Three different timing modes
TXMask function (reduce current during
Strobe) selectable on pin GPIO1
Four General Purpose Inputs/Outputs
− GPIO0-2 Input/Output, GPI only Input
− Digital Input, Digital Output, and Tristate
− Programmable Pull-Up, and Pull-Down
− GPI can be used as Flash Strobe
− GPIO2 can be used for Preview Mode
− GPIO0/2 can used for PWM input
Negative or High-Voltage Charge Pump
− Regulated Output Voltage, Programmable
by Dual Resistors e.g. -6V, 10mA for
OLED or ±15V, 5mA for TFT
− ±5% Accuracy
Standby LDO always on
− Regulated 2.5V max. output 10mA
− 3µA Quiescent Current
Wide Battery Supply Range: 3.0 to 5.5V
Two Wire Serial Interface Control
Overcurrent and Thermal Protection
Package QFN32 5x5mm
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The AS3688 is a highly-integrated CMOS Power
and Lighting Management Unit to supply power to
LCD-and cameramodules in mobile telephones, and
other 1-cell Li+ or 3-cell NiMH powered devices.
The AS3688 incorporates one low-power, lowdropout regulator (LDO), one Step Up DC/DC
Converter for white backlight LEDs, one high-power
Charge Pump for camera flash LEDs, one Analogto-Digital Converter, support for up to 11 current
sinks, a two wire serial interface, and control logic
all onto a single device. Fully programmable.
The
AS3688
is
a
successor
to
the
austrimicrosystems AS3681 with several additional
features (Charge Pump Automatic Up Switching,
Extended timer features, autonomous logarithmic
PWM dimming, LED pattern generator, DCDC step
up overvoltage protection, improved Charge Pump
and a fourth high current sink).
New features of the AS3688 compared to the
AS3681 are written in boldface italics.
Programmable High-Performance Regulator
− Low-Noise LDO (1.85 to 3.4V, 150mA)
− Default off after Power-up
− 3µA Quiescent Current in Standby
− Programmable via Serial Interface
High-Efficiency Step Up DC/DC Converter
− Up to 25V/50mA for White LEDs
− Programmable Output Voltage with
External Resistors and Serial Interface
− Overvoltage Protection
− 0.1Ohm Shunt Resistor
High-Efficiency High-Power Charge Pump
− 1:1, 1:1.5, and 1:2 Mode
− Automatic Up Switching (can be
disabled and 1:2 mode can be blocked)
− Output Current up to 400mA / 900mA
pulsed
− Efficiency up to 95%
− Very Low effective Resistance (0.5Ω typ.
1Ω max. in 1:1 mode, 1.4Ω typ. 2Ω max.
in 1:1.5)
− Only 4 External Capacitors Required:
2 x 1µF Flying Capacitors, 2 x 2.2µF
− Supports LCD White Backlight LEDs,
− Camera Flash White LEDs, and Keypad
Backlight LEDs
Supports up to 12 Current Sinks
− Four Programmable (8+1Bit) from: 0.6mA
to 300mA
− Two High Voltage Programmable (8-bit)
from: 0.15mA to 38.25mA
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2 Key Features
www.austriamicrosystems.com (ptr,tje)
3 Application
Power- and lighting-management for mobile
telephones and other 1-cell Li+ or 3-cell NiMH
powered devices.
Revision 1.1.1 / 20060707
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AS3688
Datasheet, Confidential
austriamicrosystems
4 Block Diagram
Figure 1 – Application Diagram of the AS3688: Option shown: Step up DCDC converter, RGB Current Sinks
Battery
R2
AS3688 Lighting
Management
Unit
LED
Test
VBAT3
LDO VANA1
e.g. 2.8V
Step Up DC/DC
Converter
Q1
DCDC_FB
(CURR41)
R4
100k
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LDO VANA2
1.85-3.4V
150mA
(Alternative Function)
VBAT2
C5
2.2µF
C2_P
V2_5
C4
1µF
RBIAS
R1
220k
CREF
C1
100nF
C11
15nF
Battery
VBAT1
C3
2.2µF
C9
4.7µF
C10
1.5nF
R3
1M
DCDC_GATE
LDO VANA1
1.85-3.4V
150mA
VANA1
D1
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Battery
L1
10µH
3 x 0.15-38.25mA
Current Sinks
(Alternative Function
only in AS3688B)
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SENSE_N
(CURR43)
SENSE_P
(CURR42)
C2
1µF
D7
Charge Pump
References
and
Temperature
Supervision
1:1, 1:1.5, 1:2
C2_N
400mA / 900mA
C1_P
C6
2.2µF
D8
D9
C7
2.2µF
C1_N
D10
D11
D12
White LEDs,
Backlight
CPOUT
C8
2.2µF
OLED
Charge Pump
(Alternative Function)
Battery or CPOUT
Current Sinks
each 0.6-300mA
D3
D4
D5
D6
CURR30
Current Sinks
0.15-38.25mA
RGB1
CURR31
CURR32
RGB2
CURR33
D13,D14,D15
LDO VANA2
e.g. 2.8V
8Bit PWM
Generator
Automatic Dimming
and LED Pattern
Generator
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C12
2.2µF
Current Sinks
each 0.15-38.25mA
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RGB3 (VANA2)
CURR1
CURR2
V2_5
GPIO/
ADC
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Vtemp
Strobe
Preview
Timer
CLK
Serial
Interface
GPIO0 GPIO1
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GPIO2
GPI
DATA
CLK
VDD_GPIO
R5
1-10k
DATA
VDD_GPIO
R6
Revision 1.1.1 / 20060707
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AS3688
Datasheet, Confidential
austriamicrosystems
Revision History
Date
Owner
Description
tje,ptr
- Fixed typo for vtuning range
- Corrected full scale value for current sinks from 38.5mA
to 38.25mA (blockdiagram and one overview)
- Typical CP power consumption updated
- Reduced CP effective resistance in 1:2 mode, efficiency,
Vcpout updated, quiescent current consumption
- Efficiency diagram of CP added
- Changed charge pump output capacitor to
1.5uF minimum
- Changed default state for curr_3x_on_cp to 0
- Updated ASIC ID1 and ID2 register position
- Updated LED Testing procedure
- Updated Mode Switching Diagram (and->or)
- Register Map Table updated
- slow LED pattern (bit pattern_slow added)
- GPIO2 current source modified
- polarity control of external overtemp comparator added
- Increased standby current consumption by 2uA
- Added comment to avoid current source on and
0mA setting
- Added comment for preview_off_after strobe
- Removed cp_start_debounce
- Added comment not to use softdim_pattern
for CURR1,CURR2 and CURR3x mode ‘Other’
- Added comment for order of setting of pattern_data
- Changed to ‘Datasheet’ from ‘Preliminary Datasheet’
30.3.2006
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1.0
23.6.2006
tje,ptr
- Update Application Diagram
- Included AS3688B version (for CURR42, CURR43)
- Improved Current Sink Matching to 8%; added comment
for current sink voltage compliance for accuracy spec
- Updated minimum value C6,C7
- Updated Vrsense* (DCDC step up)
- Replaced ‘FuseReg*’ by their actual default value
- TTOL +/-5° move from min/max to typical value and
removed comment ‘Design Target’
- Added comment about ADC Reference (V2_5)
- Improved voltage compliance of RGB current sinks to
V(CPOUT)
- Removed CSP Version (use austriamicrosystems
AS3689)
- Added ADC Temperature measurement coefficients
- Removed fuse I2C_Add (replace by comment about
factory programmability)
- Added comment in LED test for reduced settling time
for the DCDC step up converter
- Added DCDC efficiency curve
- Added ICP1_1.5 and ICP1_2 max.
- Added VPGIO rising max; and comment for VPOR_VBAT
- Added comment for LDO startup
tje,ptr
- Added maximum value for IACTIVE
- Added maximum value for ILIMIT
- Reduced ICP1_1.5
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1.1
1.1.1
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Revision
7.7.2006
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Revision 1.1.1 / 20060707
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AS3688
Datasheet, Confidential
austriamicrosystems
Table of Contents
General Description ......................................................................................................................................... 1
Key Features.................................................................................................................................................... 1
Application ....................................................................................................................................................... 1
Block Diagram.................................................................................................................................................. 2
Characteristics ................................................................................................................................................. 5
5.1
Absolute Maximum Ratings ...................................................................................................................... 5
5.2
Operating Conditions ................................................................................................................................ 5
6 Typical Operating Characteristics .................................................................................................................... 6
7 Detailed Functional Description ....................................................................................................................... 8
7.1
Analog LDO .............................................................................................................................................. 8
7.1.1
LDO Registers............................................................................................................................... 10
7.2
Step Up DC/DC Converter...................................................................................................................... 12
7.2.1
Feedback Selection....................................................................................................................... 13
7.2.2
Overvoltage Protection in Current Feedback Mode....................................................................... 14
7.2.3
Voltage Feedback ......................................................................................................................... 14
7.2.4
PCB Layout Tips ........................................................................................................................... 15
7.2.5
Step up Registers.......................................................................................................................... 16
7.3
Charge Pump.......................................................................................................................................... 17
7.3.1
Charge Pump Mode Switching...................................................................................................... 19
7.3.2
Soft Start ....................................................................................................................................... 20
7.3.3
Charge Pump Registers ................................................................................................................ 20
7.3.4
Usage of PCB Wire Inductance..................................................................................................... 23
7.4
Current Sinks .......................................................................................................................................... 24
7.4.1
High Voltage Current Sinks CURR1, CURR2 ............................................................................... 24
7.4.2
High Current Sinks CURR30, CURR31, CURR32, CURR33 ........................................................ 26
7.4.3
RGB Current Sinks RGB1, RGB2, RGB3 (VANA2,cpext) ............................................................. 31
7.4.4
General Purpose Current Sinks CURR41, CURR42, CURR43..................................................... 34
7.4.5
LED Pattern Generator.................................................................................................................. 35
7.4.6
Overtemp comparator ................................................................................................................... 39
7.4.7
External chargepump .................................................................................................................... 40
7.4.8
PWM Generator ............................................................................................................................ 41
7.5
General Purpose Input / Outputs ............................................................................................................ 46
7.5.1
GPIO Characteristics..................................................................................................................... 47
7.5.2
GPIO Registers ............................................................................................................................. 48
7.6
LED Test................................................................................................................................................. 50
7.6.1
Function Testing for single LEDs connected to the Charge Pump ................................................ 50
7.6.2
Function Testing for LEDs connected to the Step Up DCDC Converter........................................ 51
7.7
Analog-To-Digital Converter ................................................................................................................... 52
ADC Registers............................................................................................................................... 53
7.7.1
53
7.8
Power-On Reset ..................................................................................................................................... 55
7.9
Temperature Supervision........................................................................................................................ 55
7.9.1
Temperature Supervision Registers .............................................................................................. 56
7.10 Serial Interface........................................................................................................................................ 56
7.10.1
Serial Interface Features ............................................................................................................... 56
7.10.2
Device Address Selection ............................................................................................................. 56
7.11 Operating Modes .................................................................................................................................... 59
8 Registermap................................................................................................................................................... 60
9 External Components..................................................................................................................................... 62
10
Pinout and Packaging............................................................................................................................. 64
10.1 Pin Description........................................................................................................................................ 64
10.2 Package Drawings and Markings ........................................................................................................... 66
11
Ordering Information............................................................................................................................... 68
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1
2
3
4
5
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AS3688
Datasheet, Confidential
austriamicrosystems
5 Characteristics
5.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in Section 5
Electrical Characteristics is not implied.
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Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 1 – Absolute Maximum Ratings
Min
Max
Unit
VIN_HV
15V Pins
-0.3
17
V
VIN_MV
5V Pins
-0.3
7.0
V
Note
Applicable for high-voltage current
sink pins CURR1 and CURR2.
Applicable for 5V pins
VBAT1:VBAT3, VANA1,
CURR30:CURR33; C1_N, C2_N,
C1_P, C2_P, CPOUT; SENSE_N,
SENSE_P, DCDC_FB,
DCDC_GATE; CURR41:CURR43,
RGB1,RGB2,RGB3(VANA2).
Applicable for 3.3V pins
VDD_GPIO; GPIO0:GPIO2; GPI;
serial interface pins CLK, DATA;
V2_5; RBIAS, CREF
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Symbol
VIN_LV
3.3V Pins
-0.3
5.0
IIN
Input Pin Current
-25
+25
mA At 25ºC, Norm: JEDEC 17
Tstrg
Storage Temperature Range
-55
125
ºC
Humidity
5
85
%
Non-condensing
Electrostatic Discharge
-1000
1000
V
Norm: MIL 883 E Method 3015
1
W
2.5
W
260
ºC
VESD
Total Power Dissipation
QFN32 5x5
Pt
TBODY
TA = 70 degrees, Tjunction max =
125deg
TA = 70 degrees, Tjunction max =
125deg; for 800ms
T = 20 to 40s, in accordance with
IPC/JEDEC J-STD 020C.
Operating Conditions
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5.2
Peak Body Temperature
V
Table 2 – Operating Conditions
VHV
Min
High Voltage
0.0
Battery Voltage
3.0
ch
VBAT
Parameter
ni
Symbol
Periphery Supply Voltage
1.5
V2_5
Voltage on Pin V2_5
2.4
TAMB
Operating Temperature
Range
-30
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VGPIO
IACTIVE
Battery current
www.austriamicrosystems.com (ptr,tje)
Typ
3.6
Max
Unit
15.0
V
5.5
Note
Applicable for high-voltage current
sink pins CURR1 and CURR2.
VBAT1:VBAT3
3.3
V
For GPIO and serial interface pins.
2.5
2.6
V
Internally generated
25
85
°C
64
130
Revision 1.1.1 / 20060707
µA
Normal Operating current – see
section ‘Operating Modes’
(excluding current of the enabled
blocks, e.g. LDOs, DCDC);
interface active
5 - 70
AS3688
Datasheet, Confidential
austriamicrosystems
Parameter
ILOWPOWER
Typ
Max
Unit
Low-Power Mode Current
10
18
µA
ISTANDBY
Standby Mode Current
8
13
µA
ISHUTDOWN
Shutdown Mode Current
0.1
3
µA
Notes:
1.
Min
Note
Current consumption in low-power
mode; ldo_ana1_lpo= 1,
ldo_ana1_on=1 and V2_5 on,
maximum LDO load current on
ldo_ana1 = 5mA; interface active
Current consumption in standby
mode. Only 2.5V regulator on
VDD_GPIO > 1.5V; interface active
VDD_GPIO < 0.3V; interface
disabled and register are reset
All device parameters are valid under all operating conditions unless otherwise specified
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Figure 2 – DCDC Step Up Converter: Efficiency at VBAT = 3.8V
90
VOUT=14.2V
VOUT=17.2V
Efficiency [%]
85
80
VOUT=22.3V
VOUT=14.2V
500kHz
75
70
65
0,0
20,0
40,0
60,0
80,0
Load Current [mA]
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Figure 3 – Charge Pump: Efficiency vs. VBAT
100
90
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80
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Efficiency [%]
70
60
50
ILED=80mA,
VLED=3.26V
40
ILED=160mA,
VLED=3.65V
ILED=320mA,
VLED=4.6V
30
20
10
0
2,8
3,0
3,2
3,4
3,6
3,8
4,0
4,2
Vbat [V]
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Revision 1.1.1 / 20060707
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AS3688
Datasheet, Confidential
austriamicrosystems
Figure 4 – Charge Pump: Battery Current vs. VBAT
700
600
ILED=320mA,
VLED=4.6V
400
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IBAT [mA]
500
ILED=160mA,
VLED=3.65V
300
200
100
0
2,8
3,0
3,2
3,4
3,6
3,8
4,0
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ILED=80mA,
VLED=3.26V
4,2
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Vbat [V]
Figure 5 – Current Sink CURR1 vs. V(CURR1)
Figure 6 – Current Sink CURR1 Protection Current vs. Voltage (I(CURR1)=0mA)
45
40
Current [mA]
35
CURR1=38.25mA
30
25
20
15
10
5
CURR1=4.8mA
0
0,0
0,5
1,0
1,5
2,0
2,5
3,0
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V(CURR1) [V]
Figure 7 – Current Sink CURR30 vs. V(CURR30)
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3,0
curr_prot1_on=1
Current [mA]
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2,5
2,0
1,5
1,0
4.5uA
0,5
curr_prot1_on=0
0,0
0,0
5,0
10,0
15,0
20,0
V(CURR1) [V]
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Revision 1.1.1 / 20060707
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AS3688
Datasheet, Confidential
austriamicrosystems
90
CURR1=76.8mA, curr3x_strobe_high=0
80
CURR1=76.8mA, curr3x_strobe_high=1
60
50
40
30
20
CURR1=10.2mA, curr3x_strobe_high=0
10
0
0,0
0,5
1,0
1,5
2,0
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V(CURR1) [V]
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Current [mA]
70
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Figure 8 – RGB Current Sinks RGB1 vs. V(RGB1)
45
40
Current [mA]
35
RGB1=38.25mA
30
25
20
15
10
5
RGB1=4.8mA
0
0,0
0,5
1,0
1,5
2,0
V(RGB1) [V]
7.1
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7 Detailed Functional Description
Analog LDO
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The Analog LDOs (VANA1, VANA2) is designed to supply power to sensitive analog circuits like camera supply,
LNAs, Transceivers, VCOs, and other critical RF components of cellular radios. Additionally, the Analog LDO is
suitable for supplying power to audio devices or as a reference for A/D and D/A converters.
The design is optimized to deliver the best compromise between quiescent current and regulator performance for
battery powered devices.
Stability is guaranteed with ceramic output capacitors (see Figure 3) of 1µF ±20% (X5R) or 2.2µF +100/-50%
(Z5U). The low ESR of these capacitors ensures low output impedance at high frequencies. Regulation
performance is excellent even under low dropout conditions, when the power transistor has to operate in linear
mode. Power supply rejection is high enough to suppress ripple on the battery caused by the PA in TDMA
systems. The low noise performance allows direct connection of noise sensitive circuits without additional filtering
networks. The low impedance of the power transistor enables the device to deliver up to 150mA even at nearly
discharged batteries without any decrease in performance.
The LDO is off by default after startup (apply voltage on VDD_GPIO)
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AS3688
Datasheet, Confidential
austriamicrosystems
Figure 9 – Analog LDO Block Diagram
High-Gain
Low-Bandwidth Amplifier
VREF1.8V Low-Noise
DC Reference
Low-Gain Ultra HighBandwidth Amplifier
+
VBAT3 3 - 5.5V
PMOS
Power Device
1Ω Max
–
–
+
C1
1µF
C2
2.2µF
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GND
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VOUT 1.85 - 3.4V
150mA Load
Table 3 – Analog LDOs Characteristics
Symbol
Parameter
VBAT
Supply Voltage Range
RON
On Resistance
Min
Typ
3.0
VDROPOUT Dropout Voltage
PSRR
Power Supply Rejection Ratio
Max
Unit
5.5
V
1.0
Ω
mV @150mA, ldo_ana1_lpo= 0
50
mV @50mA, ldo_ana1_lpo= 0
500
mV @5mA, ldo_ana1_lpo= 1
70
dB
55
dB
40
dB
tstart
VLineReg
50
Startup Time
200
µs
-2
+2
%
ldo_ana1_lpo= 0
1.85
2.85
V
VBAT > 3.0V
1.85
3.4
V
Full Programmable Range
-1
+1
mV Static (1)
-10
+10
-3
+3
mV Transient; Slope: tr = 10µs (1)
Transient; Slope: tr = 30µs
mV
(VBAT-VANA1,2) >500mV, Iout=1mA
Output Voltage Tolerance
Output Voltage
Line Regulation
ldo_ana1_lpo= 0
VLoadReg_H Load Regulation
P
With 150mA load
Output noise
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Vout
150
100
ch
Vout_tol
Without load
Without load, ldo_ana1_lpo= 1
ldo_ana1 only
3
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Noise
µA
f = 1kHz,
Iout=10mA,VBAT-VANA1,2=0.2V
f = 10kHz
Iout=10mA,VBAT-VANA1,2=0.2V
f = 100kHz
Iout=10mA,VBAT-VANA1,2=0.2V
Shutdown Current
ni
IOFF
Supply Current
@150mA, full operating
temperature range
150
50
IOn
Note
ldo_ana1_lpo= 0
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nA
Without load
µVrm
10Hz < f < 100kHz
s
-1
+1
mV Static (2)
-20
+20
mV Transient; Slope: tr = 10µs (3)
-8
+8
mV Transient; Slope: tr = 30µs (3)
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Datasheet, Confidential
ILIMIT
(8)
Parameter
Min
LDO Current Limit
ldo_ana1_lpo= 0
LDO Current Limit
ldo_ana1_lpo= 1
P
ldo_ana1_lpo= 1
Max
Unit
Note
300
450
(7)
520
(7)
mA
Pin VANA1. LDO acts as current
source if the output current
exceeds ILIMIT. (6)
300
450
(7)
520
(7)
mA
Pin VANA2
4
VLoadReg_L Load Regulation
Typ
8
mA VBAT3-VANA>=0.2V
-10
10
mV Static (4)
-50
50
mV Transient; Slope: tr = 10µs (5)
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Symbol
austriamicrosystems
am
lc s
on A
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nt
st
il
lv
Notes:
1. The Line Regulation in Table 3 is valid for whole output voltage (1.8 to 3.3V), if (VBAT-VANA1,2) >200mV.
2. The static Load Regulation in Table 3 is valid for whole output voltage (1.8 to 3.3V) and current range (0
to 100mA), if (VBAT-VANA1,2) >200mV.
3. The load condition for this value is a 1 to 100mA and 100 to 1mA steps.
4. The static load regulation in Table 3 is valid for the whole output voltage range (1.8 to 3.3V) and current
range (0 to 5mA), if (VBAT-VANA1,2) >500mV.
5. The load condition for this value is a 0.05 to 5mA and 5 to 0.05mA steps.
6. The duration of operation in current limit is only dependent on the total power dissipation of the device.
If this limit exceeded, the overtemperature detection might disable the device temporarily.
7. During startup of the LDO the current limit is half the value of ILIMIT
8. Not production tested – guaranteed by design and laboratory verification
7.1.1 LDO Registers
Table 4 – Register definition for Analog LDO
Reg. Control
Addr: 00
This register enables/disables the LDOs, Charge Pumps, Charge Pump
LEDs, current sinks, the Step Up DC/DC Converter, and low-power mode.
Bit Name
Default
Access
0
ldo_ana1_on
0
R/W
0 = Analog LDO is switched off
1 = Analog LDO is switched on
1
ldo_ana2_on
0
R/W
0 = Analog LDO is switched off
1 = Analog LDO is switched on
R/W
0 = Normal Operation
1 = Low-power mode; (ldo_ana1 only),current
consumption is reduced by about 75µA. Reduced
performance of LDO: max 5mA load, internal oscillator is
switched off. The device will exit low-power mode
automatically, if blocks requiring the oscillator are
enabled.
ni
ldo_ana1_lpo
0
Description
Te
ch
7
ca
Bit
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Table 5 – Register definition for Analog LDO
Ldo ana1 voltage
Addr: 07h
This register sets the output voltage (VANA) for the LDO.
4:0
Bit Name
ldo_ana1_voltage
Default
00000b
Access
R/W
Description
Controls LDO voltage selection.
00000b = 1.85V.
... LSB = 50mV
11111b = 3.4V
Table 6 – Register definition for Analog LDO
Ldo ana2 voltage
Addr: 08h
Bit
00000b
Access
Description
R/W
Controls LDO voltage selection.
00000b = 1.85V.
... LSB = 50mV
11111b = 3.4V
R/W
Enable a pulldown for LDO ANA2 (pin RGB3). If RGB3
current sink or the external charge pump is used, leave
this bit at default 0; if the LDO ANA2 is used in a system,
set this bit always to 1
0 = pulldown is disabled
1 = pulldown is enabled; has only effect if LDO ANA2 is
off (ldo_ana2_on = 0)
ldo_ana2_pulld
0
Te
ch
ni
ca
5
ldo_ana2_voltage
Default
am
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st
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4:0
Bit Name
lv
This register sets the output voltage (VANA) for the LDO.
al
id
Bit
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7.2
austriamicrosystems
Step Up DC/DC Converter
The DCDC step up converter is only available in the AS3688 version (not available for the AS3688B – marking
‘AS3688B’).
The Step Up DC/DC Converter is a high-efficiency current mode PWM regulator, providing output voltage up to
25V and a load current up to 50mA. A constant switching-frequency results in a low noise on the supply and
output voltages.
al
id
Figure 10 – Step Up DCDC Converter Block Diagrammö Option: Current Feedback with Overvoltage protection
Battery
R2
D1
C9
4.7µF
am
lc s
on A
te G
nt
st
il
L1
10µH
lv
SENSE_N
C2
1µF
Step Up DC/DC
Converter
DCDC_GATE
R3
1M
C10
1.5nF
Q1
DCDC_FB
R4
100k
C11
D7
15nF
D11
D8
D12
D9
D10
White LEDs,
Backlight
Current Sinks
each 0.625-40mA
CURR1
ni
ca
CURR2
Te
ch
TBD: Final Datasheet: Add internal logic with overvoltage detection.
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Table 7 – Step Up DC/DC Converter Parameters
IVDD
Quiescent Current
VFB1
Feedback Voltage for
External Resistor Divider
1.20
1.25
1.30
V
VFB2
Feedback Voltage for Current
Sink Regulation
0.4
0.5
0.6
V
Additional Tuning Current at
Pin DCDC_FB and
overvoltage protection
0
30
µA
Accuracy of Feedback
Current
-4
4
%
IDCDC_FB
Vrsense_max
RSW
Iload
fIN
Cout
L
tMIN_ON
MDC
Vripple
72
Unit
µA
Note
Pulse skipping mode.
For constant voltage control.
step_up_res=1
on CURR1 or CURR2 in
regulation.
step_up_res=0
Adjustable by software using
Register DCDC control1
1µA step size
VPROTECT = 1.25V +
IDCDC_FB * R3
Design Target
e.g., 0.66A for 0.1Ω sense
resistor.
93
27
36
47
33
47
61
Load Current
0
Switching Frequency
0.9
1
Output Capacitor
0.7
4.7
Inductor
7
10
Minimum on Time
90
140
Maximum Duty Cycle
88
91
mV
If stepup_lowcur=1
Ω
ON-resistance of external
switching transistor.
50
mA
At 15V output voltage.
45
mA
At 17V output voltage.
1.1
MHz Internally trimmed.
µF
Ceramic, ±20%. Use nominal
2.2µF capacitors to obtain at least
0.7µF under all conditions (voltage
dependance of capacitors)
13
µH
Use inductors with small Cparasitic
(<100pF) to get high efficiency.
190
ns
%
Voltage ripple >20kHz
160
mV
Voltage ripple <20kHz
40
mV
Efficiency
For fixed startup time of
500us
1
Switch Resistance
ni
Efficiency
Max
am
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nt
st
il
Vrsense_max_lc
Current Limit Voltage at
RSENSE (R2)
TYP
140
55
ca
Vrsense_max_st
art
Min
al
id
Parameter
lv
Symbol
85
%
Cout=2.2uF,Iout=0..45mA,
Vbat=3.0...4.2V
Iout=20mA,Vout=17V,Vbat=3.8V
ch
To ensure soft startup of the dcdc converter, the overcurrent limits are reduced for a fixed time after enabling the
dcdc converter. The total startup time for an output voltage of e.g. 25V is less than 2ms.
7.2.1 Feedback Selection
Te
Register 12 (DCDC Control) selects the type of feedback for the Step Up DC/DC Converter.
The feedback for the DC/DC converter can be selected either by current sinks CURR1 or CURR2 or by a voltage
feedback at pin DCDC_FB. If the register bit step_up_fb_auto is set, the feedback path is automatically selected
between CURR1 and CURR2 (the lowest voltage of these current sinks is used).
Setting step_up_fb = 01 enables feedback at pin 19 (CURR1); setting step_up_fb = 10 enables feedback at pin
20 (CURR2). The Step Up DC/DC Converter is regulated such that the required current at the feedback path can
be supported. (Bit step_up_res should be set to 0 in this configuration)
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Note: Always choose the path with the higher voltage drop as feedback to guarantee adequate supply for the
other (unregulated) path or enable the register bit step_up_fb_auto.
7.2.2 Overvoltage Protection in Current Feedback Mode
The overvoltage protection in current feedback mode (step_up_fb = 01 or 10) works as follows: Only resistor R3
and C10 is soldered and R4 and C11 is omitted. An internal current source (sink) is used to generate a voltage
drop across the resistor R3. If then the voltage on DCDC_FB is above 1.25V, the DCDC is momentarily disabled
to avoid too high voltages on the output of the DCDC converter.
The protection voltage can be calculated according to the following formula:
al
id
VPROTECT = 1.25V + IDCDC_FB * R3
Notes:
1.
lv
2.
The voltage on the pin DCDC_FB is limited by an internal protection diode to VBAT + one diode
forward voltage (typ. 0.6V).
If the overvoltage protection is not used in current feedback mode, connect DCDC_FB to ground.
Figure 11 –Step Up DC/DC Converter Block Diagram; Option: Regulated Output Voltage, Feedback is at Pin DCDC_FB
am
lc s
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st
il
Battery
24 SENSE_P
Current
Sense +
R2 (RSENSE)
0.1 Ω/5%
C2
1µF
-
23 SENSE_N
L1
CLK
PWM
Logic
Comparator
Q1
Si1304
SOT-323
Driver
28 DCDC_GATE
D1
R3
1MΩ
C10
1.5nF
R4
100kΩ
C11
15nF
C9
2.2µF
+ –
+
Ramp
Generation
10µH, 5x5x1.2mm
Coiltronics SD12-100
Pulse Skip
Comparator
+
MUX
White
LEDs
MUX
29 DCDC_FB
0.5V
+
Error Amplifier
19 CURR 1
0.5V
+
Error Amplifier
20 CURR 2
ca
1.25V
+
Error Amplifier
ni
V SS
7.2.3 Voltage Feedback
ch
Setting bit step_up_fb = 00 enables voltage feedback at pin DCDC_FB..
Te
The output voltage is regulated to a constant value, given by (Bit step_up_res should be set to 1 in this
configuration)
Ustepup_out = (R3+R4)/R4 x 1.25 + IDCDC_FB x R3
If R4 is not used, the output voltage is by (Bit step_up_res should be set to 0 in this configuration):
Ustepup_out = 1.25 + IDCDC_FB x R3
Where:
Ustepup_out = Step Up DC/DC Converter output voltage.
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R3 = Feedback resistor R3.
R4 = Feedback resistor R4.
IDCDC_FB = Tuning current at pin 29 (DCDC_FB); 0 to 31µA.
Ustepup_out
µA
R3 = 1MΩ, R4 not used
R3 = 500kΩ, R4 = 50kΩ
0
-
13.75
1
-
14.25
2
-
14.75
3
-
15.25
4
-
15.75
5
6.25
16.25
6
7.25
16.75
7
8.25
17.25
8
9
10
11
12
13
14
15
…
30
31
lv
Ustepup_out
am
lc s
on A
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nt
st
il
Ivtuning
al
id
Table 8 – Voltage Feedback Example Values
9.25
17.75
10.25
18.25
11.25
18.75
12.25
19.25
13.25
19.75
14.25
20.25
15.25
20.75
16.25
21.25
…
…
31.25
28.75
32.25
29.25
Caution: The voltage on CURR1 and CURR2 must not exceed 15V – see also section ‘High Voltage Current
Sinks’.
ca
7.2.4 PCB Layout Tips
Te
ch
ni
To ensure good EMC performance of the DCDC converter, keep its external power components C2, R2, L1, Q1,
D1 and C9 close together. Connect the ground of C2, Q1 and C9 locally together and connect this path with a
single via to the main ground plane. This ensures that local high-frequency currents will not flow to the battery.
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7.2.5 Step up Registers
Reg. Control
Bit
Bit Name
3
step_up_on
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs, current
sinks, the Step Up DC/DC Converter
Default
Access Description
Enable the step up converter
0b = Disable the Step Up DC/DC Converter.
0
R/W
1b = Enable the Step Up DC/DC Converter.
al
id
Addr: 00
Bit Name
0
step_up_frequ
2:1
step_up_fb
7:3
step_up_vtuning
This register controls the Step Up DC/DC Converter.
Default
Access Description
Defines the clock frequency of the Step Up DC/DC
Converter.
0
R/W
0 = 1 MHz
1 = 500 kHz
Controls the feedback source if step_up_fb_auto = 0
00 = DCDC_FB enabled (external resistor divider).
Set step_up_fb=00 (DCDC_FB), if external
PWM is enabled for CURR1 or CURR2
00
R/W
01 = CURR1 feedback enabled (feedback via white LEDs.
10 = CURR2 feedback enabled (feedback via white LEDs.
11 = Reserved.
Defines the tuning current at pin DCDC_FB.
00000 = 0 µA
00001 = 1 µA
00010 = 2 µA
00000
R/W
…
10000 = 15 µA
…
11111 = 31 µA
am
lc s
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nt
st
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Bit
lv
DCDC Control 1
Addr: 21h
ca
DCDC Control 2
Addr: 22h
This register controls the Step Up DC/DC Converter and low-voltage current sinks
CURR3x.
Bit Name
0
step_up_res
Default
Te
ch
ni
Bit
Access
0
R/W
1
skip_fast
0
R/W
2
stepup_prot
1
R/W
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Description
Gain selection for Step Up DC/DC Converter.
0 = Select 0 if Step Up DC/DC Converter is used with
current feedback (CURR1, CURR2) or if DCDC_FB is
used with current feedback only – only R1, C1
connected
1 = Select 1 if DCDC_FB is used with external resistor
divider (2 resistors).
Step Up DC/DC Converter output voltage at low loads, when
pulse skipping is active.
0 = Accurate output voltage, more ripple.
1 = Elevated output voltage, less ripple.
Step Up DC/DC Converter protection.
0 = No overvoltage protection.
1 = Overvoltage protection on pin DCDC_FB enabled
voltage limitation =1.25V on DCDC_FB
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DCDC Control 2
This register controls the Step Up DC/DC Converter and low-voltage current sinks
CURR3x.
Default
Access Description
Step Up DC/DC Converter coil current limit.
0 = .Normal current limit
1
R/W
1 = Current limit reduced by approx. 33%
3
stepup_lowcur
4
curr1_prot_on
0
R/W
5
curr2_prot_on
0
R/W
7
step_up_fb_auto
0
R/W
7.3
0 = No overvoltage protection
1 = Pull down current on CURR1 switched on, if voltage on
CURR1 exceeds 13.75V, and step_up_on=1
0 = No overvoltage protection
1 = Pull down current on CURR1 switched on, if voltage on
CURR1 exceeds 13.75V, and step_up_on=1
0 = step_up_fb select the feedback of the DCDC converter
1 = The feedback is automatically chosen within the current
sinks CURR1and CURR2 (never DCDC_FB). Only those are
used for this selection, which are enabled (currX_mode must
not be 00) and not connected to the charge pump
(currX_on_cp must be 0). Don’t use automatic feedback
selection together with external PWM for CURR1 or CURR2.
al
id
Bit Name
am
lc s
on A
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nt
st
il
Bit
lv
Addr: 22h
Charge Pump
The Charge Pump uses two external flying capacitors C6, C7 to generate output voltages higher than the battery
voltage.
There are three different operating modes of the charge pump itself:
ca
1:1 Bypass Mode
− Battery input and output are connected by a low-impedance switch (0.5Ω );
− battery current = output current.
1:1.5 Mode
− The output voltage is up to 1.5 times the battery voltage (without load), but is limited to VCPOUTmax all
the time
− battery current = 1.5 times output current.
1:2 Mode
− The output voltage is up to 2 times the battery voltage (without load), but is limited to VCPOUTmax all
the time
−
− battery current = 2 times output current
ch
Examples:
ni
As the battery voltage decreases, the Charge Pump must be switched from 1:1 mode to 1:1.5 mode and
eventually in 1:2 mode in order to provide enough supply for the current sinks. Depending on the actual current
the mode with best overall efficiency can be automatically or manually selected:
Battery voltage = 3.7V, LED dropout voltage = 3.5V. The 1:1 mode will be selected and there is 100mV drop
on the current sink and on the Charge Pump switch. Efficiency 95%.
Battery voltage = 3.5V, LED dropout voltage = 3.5V. The 1:1.5 mode will be selected and there is 1.5V drop
on the current sink and 250mV on the Charge Pump. Efficiency 66%.
Te
Battery voltage = 3.8V, LED dropout voltage = 4.5V (Camera Flash). The 1:2 mode can be selected and there
is 600mV drop on the current sink and 2.5V on the Charge Pump. Efficiency 60%.
The efficiency is dependent on the LED forward voltage given by:
Eff=(V_LED*Iout)/(Uin*Iin)
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The charge pump mode switching can be done manually or automatically with the following possible software
settings:
Automatic up all modes allowed (1:1, 1:1.5, 1:2)
− Start with 1:1 mode
− Switch up automatically 1:1 to 1:1.5 to 1:2
Automatic up, but only 1:1 and 1:1.5 allowed
− Start with 1:1 mode
− Switch up automatically only from 1:1 to 1:1.5 mode; 1:2 mode is not used
Manual
− Set modes 1:1, 1:1.5, 1:2 by software
Figure 12 – Charge Pump Pin Connections
3.0 - 5.5V
VBAT1
lv
C5
2.2µF
al
id
am
lc s
on A
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nt
st
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VBAT2
Charge Pump
1:1, 1:1.5, 1:2
C2_P
C6
2.2µF
F
C2_N
C1_P
C7
2.2µF
C1_N
CP_OUT
To Camera
Flash LEDs
C8
2.2µF
The Charge Pump requires the external components listed in the following table:
Table 9 – Charge Pump External Components
External Flying
Capacitor (2x)
0.65
(@3.2V,
1MHz)
2.2
µF
1.0
(@3.3V)
2.2
µF
1.5
2.2 or
4.7
µF
Supply Buffer Capacitor
ch
C5
Min
ni
C6, C7
Parameter
ca
Symbol
Te
C8
External Storage
Capacitor
Typ
Max
Unit
Note
Ceramic low-ESR capacitor between
pins C1_P and C1_N, and between
pins C2_P and C2_N. Use nominal
2.2µF capacitors (size 0603)
Ceramic low-ESR capacitor between
pins CP_OUT and VSS, pins VBAT
and VBAT2 (in parallel) and VSS.
Use nominal 2.2µF capacitors (size
0603)
Ceramic low-ESR capacitor between
pins CP_OUT and VSS, pins VBAT
and VBAT2 (in parallel) and VSS.
Use nominal 2.2µF or 4.7µF
capacitors (size 0603)
Note:
1.) The connections of the external capacitors C5, C6, C7 and C8 should be kept as short as possible.
2.) The maximum voltage on the flying capacitors C6 and C7 is VBAT
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Table 10 – Charge Pump Characteristics
ICPOUT_Pulsed Output Current Pulsed
Min
Typ
Max
Unit
0.0
900
mA
0.0
400
mA
5.6
V
90
%
ICPOUT
Output Current
Continuous
VCPOUTmax
Output Voltage
η
Efficiency
ICP1_1.5
Power Consumption
without Load
fclk = 1 MHz
8.4
13
9.5
18
Effective Charge Pump
Output Resistance
(Open Loop, fclk =
1MHz)
0.4
1.0
1.4
2.0
Rcp1_1
Rcp1_1.5
Rcp1_2
fclk Accuracy
currlv_switch
currhv_switch
curr3x_switch
Ω
Internally limited, Including output
ripple
Including current sink loss;
ICPOUT < 400mA.
1:1.5 Mode
1:2 Mode
1:1 Mode; VBAT >= 3.5V
1:1.5 Mode; VBAT >= 3.3V ;
TJUNCTION<85°C
1:1.2 Mode; VBAT >= 3.1V
Accuracy of Clock
Frequency
RGB1:RGB3 and
CURR41:CURR42
minumum voltage
CURR1, CURR2
minumum voltage
CURR30:CURR33
minumum voltage
0-160mA range
CURR30:CURR33
minumum voltage
>160mA range
CP automatic upswitching debounce
time
1.8
-10
2.5
10
%
0.2
V
0.45
V
0.2
V
0.4
V
240
If the voltage drops below this
threshold, the charge pump will use
the next available mode
(1:1 -> 1:1.5 or 1:1.5 -> 1:2)
µsec
ca
tdeb
mA
300ms pulse width,
10% duty cycle max.
am
lc s
on A
te G
nt
st
il
ICP1_2
55
Note
al
id
Parameter
lv
Symbol
7.3.1 Charge Pump Mode Switching
Te
ch
ni
If automatic mode switching is enabled (cp_mode_switching = 00 or cp_mode_switching = 01) the charge pump
monitors the current sinks, which are connected via a led to the output CP_OUT. To identify these current
sources (sinks), the registers cp_mode_switch1 and cp_mode_switch2 (register bits curr30_on_cp …
curr33_on_cp, rgb1_on_cp … rgb3_on_cp, curr1_on_cp, curr2_on_cp, curr41_on_cp … curr43_on_cp) should
be setup before starting the charge pump (cp _on = 1). If any of the voltage on these current sources drops
below the threshold (currlv_switch, currhv_switch, curr3x_switch), the next higher mode is selected after the
debounce time.
To avoid switching into 1:2 mode (battery current = 2 times output current), set cp_mode_switching = 10.
If the currX_on_cp=0 and the according current sink is connected to the chargepump, the current sink will be
functional, but there is no up switching of the chargepump, if the voltage compliance is too low for the current sink
to supply the specified current.
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Figure 13 – Automatic Mode Switching
Battery
VBAT1
VBAT2
Charge Pump
Mode Switching
cp_mode<1:0>
1:1 -> 1:1.5
1:1.5 -> 1:2
1:1, 1:1.5, 1:2
C2_N
400mA / 900mA
C1_P
C1_N
C5
2.2µF
C6
2.2µF
al
id
C2_P
C7
2.2µF
...
curr30_on_cp
CURR30
200/400mV
(curr3x_switch)
CURR31
C8
2.2µF
am
lc s
on A
te G
nt
st
il
curr31_on_cp
lv
CPOUT
curr32_on_cp
CURR32
curr33_on_cp
CURR33
rgb3_on_cp
200mV
(currlv_switch)
RGB3
...
CURR41
curr43_on_cp
...
...
curr41_on_cp
cp_start_debounce
...
RGB1
...
...
rgb1_on_cp
Debounce
CURR43
curr1_on_cp
curr2_on_cp
CURR1
450mV
(currhv_switch)
CURR2
7.3.2 Soft Start
ca
An implemented soft start mechanism reduces the inrush current. Battery current is smoothed when switching the
charge pump on and also at each switching condition. This precaution reduces electromagnetic radiation
significantly.
ni
7.3.3 Charge Pump Registers
Reg. Control
ch
Addr: 00h
Bit Name
2
cp _on
Te
Bit
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs, current
sinks, the Step Up DC/DC Converter.
Default
Access Description
0 = Set Charge Pump into 1:1 mode (off state) unless
cp_auto_on is set
0
R/W
1 = Enable manual or automatic mode switching – see
register CP Control for actual settings
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CP Control
Addr: 23h
0
cp_clk
2:1
cp_mode
This register controls the Charge Pump.
Default
Access Description
Clock frequency selection.
0
R/W
0 = 1 MHz
1 = 500 kHz
Charge Pump mode (in manual mode sets this mode, in
automatic mode reports the actual mode used)
00 = 1:1 mode
01 = 1:1.5 mode
10 = 1:2 mode
00b
R/W
11 = NA
Note:Direct switching from 1:1.5 mode into 1:2 in manual
mode and vice versa is not allowed. Always switch over
1:1 mode.
al
id
Bit Name
cp_auto_on
Note :
1.
00b
R/W
0
R/W
Set the mode switching algorithm:
1
00 = Automatic Mode switching; 1:1, 1:1.5 and 1:2 allowed
1
01 = Automatic Mode switching; only 1:1 and 1:1.5 allowed
10 = Manual Mode switching; register cp_mode defines the
actual charge pump mode used
11 = reserved
0 = Charge Pump is switched on/off with cp _on
1 = Charge Pump is automatically switched on if a current
sink, which is connected to the charge pump (defined by
registers CP Mode Switch 1 & 2) is switched on
am
lc s
on A
te G
nt
st
il
4:3 cp_mode_switching
lv
Bit
6
austriamicrosystems
Don’t use automatic mode switching together with external PWM for the current sources connceted
to the charge pump with less than 500us high time.
Addr: 24h
Bit Name
0
curr30_on_cp
1
curr31_on_cp
2
curr32_on_cp
3
curr33_on_cp
R/W
0 = current Sink CURR30 is not connected to charge pump
1 = current sink CURR30 is connected to charge pump
0
R/W
0 = current Sink CURR31 is not connected to charge pump
1 = current sink CURR31 is connected to charge pump
0
R/W
0 = current Sink CURR32 is not connected to charge pump
1 = current sink CURR32 is connected to charge pump
0
R/W
0 = current Sink CURR33 is not connected to charge pump
1 = current sink CURR33 is connected to charge pump
0
ni
ca
Bit
CP Mode Switch 1
Setup which current sinks are connected (via leds) to the charge pump; if set to ‘1’ the
correspond current source (sink) is used for automatic mode selection of the charge
pump
Default
Access Description
rgb1_on_cp
0
R/W
0 = current Sink RGB1 is not connected to charge pump
1 = current sink RGB1 is connected to charge pump
5
rgb2_on_cp
0
R/W
0 = current Sink RGB2 is not connected to charge pump
1 = current sink RGB2 is connected to charge pump
0
R/W
Te
ch
4
6
rgb3_on_cp
7
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0 = current Sink RGB3 is not connected to charge pump
1 = current sink RGB3 is connected to charge pump
NA
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CP Mode Switch 2
Setup which current sinks are connected (via leds) to the charge pump; if set to ‘1’ the
correspond current source (sink) is used for automatic mode selection of the charge
pump
Default
Access Description
Addr: 25h
Bit Name
0
curr1_on_cp
0
R/W
0 = current Sink CURR1 is not connected to charge pump
1 = current sink CURR1 is connected to charge pump
1
curr2_on_cp
0
R/W
0 = current Sink CURR2 is not connected to charge pump
1 = current sink CURR2 is connected to charge pump
2
curr41_on_cp
0
R/W
0 = current Sink CURR41 is not connected to charge pump
1 = current sink CURR41 is connected to charge pump
3
curr42_on_cp
0
R/W
0 = current Sink CURR42 is not connected to charge pump
1 = current sink CURR42 is connected to charge pump
4
curr43_on_cp
0
R/W
0 = current Sink CURR43 is not connected to charge pump
1 = current sink CURR43 is connected to charge pump
lv
al
id
Bit
Curr low voltage status 1
Indicates the low voltage status of the current sinks. If the currX_low_v bit is set, the
voltage on the current sink is too low, to drive the selected output current
Default
Access Description
am
lc s
on A
te G
nt
st
il
Addr: 2Ah
Bit
Bit Name
0
curr30_low_v
NA
R
0 = voltage of current Sink CURR30 >curr3x_switch
1 = voltage of current Sink CURR30 <curr3x_switch
1
curr31_low_v
NA
R
0 = voltage of current Sink CURR31 >curr3x_switch
1 = voltage of current Sink CURR31 <curr3x_switch
2
curr32_low_v
NA
R
0 = voltage of current Sink CURR32 >curr3x_switch
1 = voltage of current Sink CURR32 <curr3x_switch
3
curr33_low_v
NA
R
0 = voltage of current Sink CURR33 >curr3x_switch
1 = voltage of current Sink CURR33 <curr3x_switch
4
rgb1_low_v
NA
R
0 = voltage of current Sink RGB1 >currlv_switch
1 = voltage of current Sink RGB1 <currlv_switch
5
rgb2_low_v
NA
R
0 = voltage of current Sink RGB2 >currlv_switch
1 = voltage of current Sink RGB2 <currlv_switch
6
rgb3_low_v
NA
R
Te
ch
ni
ca
7
0 = voltage of current Sink RGB3 >currlv_switch
1 = voltage of current Sink RGB31 <currlv_switch
NA
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Curr low voltage status 2
Addr: 2Bh
Indicates the low voltage status of the current sinks. If the currX_low_v bit is set, the
voltage on the current sink is too low, to drive the selected output current
Default
Access Description
Bit Name
0
curr1_low_v
NA
R
0 = voltage of current Sink CURR1 >currhv_switch
1 = voltage of current Sink CURR1 <currhv_switch
1
curr2_low_v
NA
R
0 = voltage of current Sink CURR2 >currhv_switch
1 = voltage of current Sink CURR2 <currhv_switch
2
curr41_low_v
NA
R
0 = voltage of current Sink CURR41 >currlv_switch
1 = voltage of current Sink CURR41 <currlv_switch
3
curr42_low_v
NA
R
0 = voltage of current Sink CURR42 >currlv_switch
1 = voltage of current Sink CURR42 <currlv_switch
4
curr43_low_v
NA
R
0 = voltage of current Sink CURR43 >currlv_switch
1 = voltage of current Sink CURR43 <currlv_switch
lv
am
lc s
on A
te G
nt
st
il
7.3.4 Usage of PCB Wire Inductance
al
id
Bit
The inductance between the battery and pins VBAT1 and VBAT2 can be used as a filter to reduce disturbance on
the battery. Instead of using one capacitor (C5) it is recommended to split C5 into C51 and C52 with the
capacitance equal:
C51 = C52 = 1/2 x C5
It is recommended to apply a minimum of 20nH (maximum 200nH) with low impedance. This inductance can be
realized on the PCB without any discrete coil. Assuming that a 1mm signal line corresponds to approximately
1nH (valid if the length (L) is significantly bigger than the width (W) of the line (L/W <10)), a line length of:
20mm < L < 200mm
is recommended. The shape of the line is not important.
ca
Figure 14 – PCB Wire Inductance Example 1 (TBD: TODO: replace C1 by C5)
Te
ch
ni
Figure 15 – PCB Wire Inductance Example 2 (TBD: TODO: replace C1 by C5)
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7.4
austriamicrosystems
Current Sinks
The AS3688 contains general purpose current sinks intended to control backlights, buzzers, and vibrators. All
current sinks have an integrated protection against overvoltage.
CURR1 and CURR2 is also used as feedback for the Step Up DC/DC Converter (regulated to 0.5V in this
configuration).
Current sinks CURR1 and CURR2 are high-voltage compliant (15V) current sinks, used e.g., for series of
white LEDs
Current sinks CURR3x (CURR30, CURR31, CURR32 and CURR33) are parallel 5V, high-current current
sinks, used e.g., for a photocamera flash LED.
Current sinks RGB1, RGB2, and RGB3 are general purpose current sinks e.g. for a fun LED (the pins for
these current sinks are shared with the OLED charge pump)
Current sinks CURR4x (CURR41, CURR42, and CURR43) are general purpose current sinks optionally used
in place of the Step Up DC/DC Converter, e.g. for white LEDs.
lv
al
id
am
lc s
on A
te G
nt
st
il
As the current sinks consume current whenever enabled (currX_mode not equal ‘off’), do always disable the
current sinks by setting their currX_mode register to ‘off’ (and not by setting currX_current to 0 and not by setting
pwm_code to 0 if currX_mode = ‘PWM controlled’).
Table 11 – Current Sink Function Overview
Pin
CURR1 TBD
CURR2 TBD
CURR30 TBD
CURR31 TBD
CURR32 TBD
Max.
Current
(mA)
Resolution
(Bits)
(mA)
Software
Current
Control
Hardware On/Off
Control
15.0
38.25
8
0.15
Separate
PWM at GPIO0/2;
Internal PWM
Flash LED Strobe
(GPI) & Preview
(GPIO2);
153
(300 for
strobe)
8
(+1 for
strobe)
0.6
VBAT
(5.5V)
RGB1
TBD
RGB2
TBD
RGB3
38.25
8
Combined in TXMask (GPIO1);
Strobe/Preview
PWM at GPIO0/2;
or
Internal PWM;
Separated
Ext-Overtemp on
GPIO2
0.15
Separate
PWM at GPIO0/2;
Internal PWM
CURR41 TBD
LED Pattern;
ch
38.25
8
N/A
LED Pattern
LED Pattern;
TBD
CURR42 TBD
Alternate Function
LED Pattern;
ni
CURR33 TBD
Max.
Voltage
(V)
ca
Current
Sink
0.15
Separate
CURR43 TBD
OLED Charge Pump
RGB3: LDO VANA2
Step Up DC/DC
PWM at GPIO0/2; Converter (feedback at
CURR1 or CURR2)
Internal PWM
Te
7.4.1 High Voltage Current Sinks CURR1, CURR2
The high voltage current sinks have a resolution of 8 bits. Additionally an internal protection circuit monitors with
a voltage divider (max 3µA @ 13V) the voltage on CURR1 and CURR2 and increases the current in off state in
case of overvoltage. See section ‘Typical Operating Characteristics’ Figure ‘Current Sink CURR1 and CURR2
Protection Current’. This shows the protection current versus applied voltage depending on the register setting
currX_prot_on (X=1 or 2).
External PWM control of these current sinks is possible and can be enabled by software (Input pin GPIO0).
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Table 12 – HV - Current Sinks Characteristics
Parameter
IBIT7
Current sink if Bit7 = 1
19.2
IBIT6
Current sink if Bit6 = 1
9.6
IBIT5
Current sink if Bit5 = 1
4.8
IBIT4
Current sink if Bit4 = 1
2.4
IBIT3
Current sink if Bit3 = 1
1.2
IBIT2
Current sink if Bit2 = 1
0.6
IBIT1
Current sink if Bit1 = 1
0.3
IBIT0
Current sink if Bit0 = 1
0.15
∆m
matching Accuracy
∆
absolute Accuracy
-15
+15
%
Curr1 –
Curr2
Voltage compliance
0.45
15
V
Ov_prot_
13V
Overvoltage Protection of
current sink CURR1,2
3.0
µA
At 13V, independent of
curr1_prot_on or curr2_prot_on
Ov_prot_
15V
Overvoltage Protection of
current sink CURR1,2
4.0
mA
At 15V, step_up_on=1,
curr1_prot_on=1 for CURR1,
curr2_prot_on=1 for CURR2
Max
+8
Unit
Note
mA
For V(CURRx) > 0.45V
%
CURR1,CURR2; full scale
am
lc s
on A
te G
nt
st
il
-8
Typ
lv
Min
al
id
Symbol
0.8
7.4.1.1 High Voltage Current Sinks CURR1, CURR2 Registers
Curr1 current
Addr: 09h
Bit Name
7:0
curr1_current
This register controls the High voltage current sink current.
Default
Access Description
Defines current into Current sink curr1
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
ch
ni
ca
Bit
Addr: 0Ah
Bit Name
Te
Bit
7:0
curr2_current
Curr2 current
This register controls the High voltage current sink current.
Default
Access Description
Defines current into Current sink curr1
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
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Bit
Bit Name
1:0
curr1_mode
3:2
curr2_mode
curr12 control
This register select the mode of the current sinkscontrols High voltage current sink
current.
Default
Access Description
Select the mode of the current sink curr1
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled; do not use softdim_pattern=1
Select the mode of the current sink curr2
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled; do not use softdim_pattern=1
al
id
Addr: 01h
austriamicrosystems
lv
DCDC Control 2
Addr: 22h
This register controls the Step Up DC/DC Converter and low-voltage current sinks
CURR3x.
Default
Access Description
Gain selection for Step Up DC/DC Converter.
0 = Select 0 if Step Up DC/DC Converter is used with
current feedback (CURR1, CURR2) or if DCDC_FB is
0
R/W
used with current feedback only – only R1, C1
connected
1 = Select 1 if DCDC_FB is used with external resistor
divider (2 resistors).
Step Up DC/DC Converter output voltage at low loads, when
pulse skipping is active.
0
R/W
0 = Accurate output voltage, more ripple.
1 = Elevated output voltage, less ripple.
Step Up DC/DC Converter protection.
0 = No overvoltage protection.
1
R/W
1 = Overvoltage protection on pin DCDC_FB enabled
voltage limitation =1.25V on DCDC_FB
Step Up DC/DC Converter coil current limit.
0 = .Normal current limit
1
R/W
1 = Current limit reduced by approx. 33%
Bit Name
0
step_up_res
1
skip_fast
2
stepup_prot
3
stepup_lowcur
4
curr1_prot_on
0
R/W
5
curr2_prot_on
0
R/W
0
R/W
ch
ni
ca
am
lc s
on A
te G
nt
st
il
Bit
step_up_fb_auto
Te
7
0 = No overvoltage protection
1 = Pull down current on CURR1 switched on, if voltage on
CURR1 exceeds 13.75V, and step_up_on=1
0 = No overvoltage protection
1 = Pull down current on CURR2 switched on, if voltage
exceeds on CURR2 13.75V, and step_up_on=1
0 = step_up_fb select the feedback of the DCDC converter
1 = The feedback is automatically chosen within the current
sinks CURR1and CURR2 (never DCDC_FB). Only those are
used for this selection, which are enabled (currX_mode must
not be 00) and not connected to the charge pump
(currX_on_cp must be 0).
7.4.2 High Current Sinks CURR30, CURR31, CURR32, CURR33
These current sinks have a preview and strobe setting. The preview and strobe can be controlled by software
(register bit) or GPIO2 can be programmed to enter preview mode (polarity programmable) and GPI can be
programmed to enter strobe mode (polarity programmable).
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In strobe mode, a timeout timer protects the flash leds with a settable timeout of 100ms to 1600ms. This timer
has the following modes:
Flash time defined by timeout timer (Ts) independent of strobe signal (Mode 1)
Flash time limited to timeout or end of strobe pulse (Mode 2)
Flash time identical to strobe pulse time (Mode 3)
Figure 16 – Flash Mode 1 – Flash time defined by timeout timer (Ts) independent of strobe signal (Strobe on)
Strobe Current Level
(defined by curr3x_strobe
and curr3x_strobe_high)
Preview on
(Software trigger or GPIO2)
Strobe on
(Software trigger or GPI3)
am
lc s
on A
te G
nt
st
il
TX Masking-function
reduce current during flash
(GPIO1 if txmask_on=1)
lv
Preview Current Level
(defined by curr3x_preview)
al
id
GPIO1 can be programmed to be used as TXMasking function. This function quickly reduces the current during
strobing from strobe levels to preview levels. The timeout counter is not affected by this input.
Strobe Current Level
(defined by curr3x_strobe
and curr3x_strobe_high)
Preview Current Level
(defined by curr3x_preview)
TX Masking-function
reduce current during flash
(GPIO1 if txmask_on=1)
Preview on
(Software trigger or GPIO2)
Te
ch
ni
Strobe on
(Software trigger or GPI3)
ca
Figure 17 – Flash Mode 2 – Flash time limited to timeout or end of strobe pulse
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Figure 18 – Flash Mode 3 – Flash time identical to strobe pulse time
Strobe Current Level
(defined by curr3x_strobe
and curr3x_strobe_high)
Preview Current Level
(defined by curr3x_preview)
al
id
TX Masking-function
reduce current during flash
(GPIO1 if txmask_on=1)
Preview on
(Software trigger or GPIO2)
lv
Strobe on
(Software trigger or GPI3)
am
lc s
on A
te G
nt
st
il
Table 13 – High Current Sinks CURR30,31,32,33 Parameters
Symbol
Parameter
Min
Typ
IBIT7
Current sink if Bit7 = 1
76.8
IBIT6
Current sink if Bit6 = 1
38.4
IBIT5
Current sink if Bit5 = 1
19.2
IBIT4
Current sink if Bit4 = 1
9.6
IBIT3
Current sink if Bit3 = 1
4.8
IBIT2
Current sink if Bit2 = 1
2.4
IBIT1
Current sink if Bit1 = 1
1.2
IBIT0
Current sink if Bit0 = 1
0.6
∆
absolute Accuracy
VCURR3X_H
CURR30,31,32,33 Voltage
Compliance Range
P
ca
VCURR3X
Max
Unit
Note
mA
For V(CURRx) > 0.2 / 0.4V
All Current sinks;
V(CURR3x) < VBAT-1.0V
-15
+15
%
0.2
CPOUT
V
0.4
CPOUT
V
0-150mA range
150mA-300mA range
ch
ni
7.4.2.1 High Current Sinks CURR3x Registers
Addr: 12h
Bit Name
Te
Bit
0
preview_off_after
strobe
2:1
preview_ctrl
Curr3 control1
This register select the modes of the current sinks30..33 current.
Default Access Description
Select the switch off mode after strobe pulse
0=normal preview/strobe mode,
0b
R/W 1=switch off preview after strobe duration has expired
To reinitiate the torch mode the preview_ctrl has to be set off
and on again
Preview is triggered by
00b = off
00b
R/W 01b = software trigger (setting this bit automatically triggers preview)
10b = GPIO2 active high
11b = GPIO2 active low
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Curr3 control1
Addr: 12h
5
6
txmask_invert
0b
R/W
Inverts the GPIO1 input for txmask function
0b = GPIO1 not inverted
1b = GPIO1 inverted
Curr3 strobe control
Addr: 11h
al
id
4
lv
3
This register select the modes of the current sinks30..33 current.
Bit Name
Default Access Description
Enables the txmask operation
txmask_on
0b
R/W 0b = disabled
1b = During Strobe current is reduced to Preview levels if GPIO1 =1
Selects overtemperature switch off of flash LED
0b = normal operation of CURR3x
curr3x_ext_ovtemp
0b
R/W 1b = if the voltage on GPIO2 drops below 1.25V, CURR3x is
switched from strobe to preview current levels
(can be used to monitor the temperature of the flash led)
Doubles curr3x current during strobe
curr3x_strobe_high
0b
R/W 0b = normal operation of CURR3x (0..153 mA)
1b = Doubles current during strobe (0..300mA)
am
lc s
on A
te G
nt
st
il
Bit
austriamicrosystems
Bit Name
1:0
strobe_ctrl
3:2
strobe_mode
7:4
strobe_timing
Te
ch
ni
ca
Bit
This register select the modes of the current sinks30..33 current.
Default Access Description
Strobe is triggered by
00b = off
00b
R/W 01b = software trigger (setting this bit automatically triggers strobe)
10b = GPI active high
11b = GPI active low
Selects strobe mode
00b = Mode 1 (Tstrobe=Ts; strobe trigger signal >= 10µs)
00b
R/W 01b = Mode 2 (Tstrobe=max Ts)
10b = Mode 3 (Tstrobe = strobe signal)
11b = not used
Selects strobe time (Ts)
0000b = 100 msec
0001b = 200 msec
0010b = 300 msec
0011b = 400 msec
0100b = 500 msec
0101b = 600 msec
0110b = 700 msec
0000b
R/W 0111b = 800 msec
1000b = 900 msec
1001b = 1000 msec
1010b = 1100 msec
1011b = 1200 msec
1100b = 1300 msec
1101b = 1400 msec
1110b = 1500 msec
1111b = 1600 msec
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Curr3x strobe
Bit
Bit Name
7:0
curr3x_strobe
This register select the strobe current of the current sinks30..33
Default Access Description
Selects strobe current (curr3x_strobe_high can double the current
setting)
00h = 0 mA
01h = 0.6mA (1.25mA if curr3x_strobe_high = 1)
00
R/W
...
F0h = 150mA (300mA if curr3x_strobe_high = 1)
…
FFh = 153mA
Note: Do not exceed 300mA for curr3x_strobe.
Curr3x preview
Bit Name
7:0
curr3x_preview
Curr3x other
Addr: 10h
Bit
Bit Name
7:0
curr3x_other
Bit Name
1:0
curr30_mode
3:2
curr31_mode
This register select the mode of the current sinks30 - 33
Default
Access Description
Select the mode of the current sink curr30
00b = off
0
R/W
01b = strobe/preview
10b = curr3x_other PWM controlled
11b = curr3x_other; do not use softdim_pattern=1
Select the mode of the current sink curr31
00b = off
0
R/W
01b = strobe/preview
10b = curr3x_other PWM controlled
11b = curr3x_other; do not use softdim_pattern=1
Select the mode of the current sink curr32
00b = off
0
R/W
01b = strobe/preview
10b = curr3x_other PWM controlled
11b = curr3x_other; do not use softdim_pattern=1
Select the mode of the current sink curr33
00b = off
0
R/W
01b = strobe/preview
10b = curr3x_other PWM controlled
11b = curr3x_other; do not use softdim_pattern=1
ch
ni
ca
Bit
curr32_mode
Te
7:6
This register selects the current of the current sinks30..33
Default Access Description
Selects curr3x current, if curr30, curr31, curr32 or curr33 are not
used for strobe/preview (CurX_mode=11b)
00h = 0 mA
00
R/W
01h = 0.6mA
...
FFh = 153mA
curr3 control
Addr: 03h
5:4
This register select the preview current of the current sinks30..33
Default Access Description
Selects peview current
00h = 0 mA
00
R/W 01h = 0.6mA
...
FFh = 153mA
am
lc s
on A
te G
nt
st
il
Bit
lv
Addr: 0Fh
al
id
Addr: 0Eh
curr33_mode
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Pattern control
0
pattern_color
2:1
pattern_delay
3
softdim_pattern
4
curr30_pattern
5
curr31_pattern
al
id
Bit Name
0b
R/W
Additional CURR33 LED pattern control bit
0b = CURR31 controlled according curr31_mode register
1b = CURR31 controlled by LED pattern generator
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Bit
This register controls the LED pattern
Default
Access Description
Defines the pattern type for the RGBx current sinks
0b = single 32 bit pattern (also set rgbx_mode = 11)
0
R/W
1b = RGB pattern with each 10 bits (set all rgbx_mode = 11)
Delay between pattern
00b = 0 sec
01b = 1 sec
0
R/W
10b = 2 sec
11b = 3 sec
Enable the ‘soft’ dimming feature for the pattern generator
0 = Pattern generator directly control current sources
0b
R/W
1 = ‘Soft Dimming’ is performed – see section ’Soft Dimming
for pattern’
Additional CURR33 LED pattern control bit
0b = CURR30 controlled according curr30_mode register
0b
R/W
1b = CURR30 controlled by LED pattern generator
lv
Addr: 18h
6
curr32_pattern
0b
R/W
Additional CURR33 LED pattern control bit
0b = CURR32 controlled according curr32_mode register
1b = CURR32 controlled by LED pattern generator
7
curr33_pattern
0b
R/W
Additional CURR33 LED pattern control bit
0b = CURR33 controlled according curr33_mode register
1b = CURR33 controlled by LED pattern generator
7.4.3 RGB Current Sinks RGB1, RGB2, RGB3 (VANA2,cpext)
Te
ch
ni
ca
The RGB1,RGB2, RGB3 are pins with different functionality. These pins can act as current sinks or as external
chargepump. In addition RGB3 can be programmed as Analog LDO supplied by VBAT3
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Figure 19 – RGB pin functionality
OLED
Charge Pump
(Alternative Function)
Vref
FB
al
id
VBAT3
CLK1
VBAT3
CLK2
lv
Battery or CPOUT
Current Sinks
0.15-38.5mA
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st
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RGB1
RGB2
RGB3 (VANA2)
D13,D14,D15
RGB3
VANA2
Battery
LDO VANA2
1.85-3.4V
150mA
VBAT3
Table 14 – RGB pins Function Overview
Bit settings
Pin Function / Name
rgb1_
mode
rgb2_
mode
rgb3_ cp_ext ldo_an
RGB1
mode _on a2_on
00b
00b
00b
0b
0b
01b
01b
01b
0b
10b
10b
10b
0b
xxb
open
open
open
all functions off
0b
RGB1
RGB2
RGB3
Normal current sink operation
0b
RGB1
RGB2
RGB3
PWM current sink operation
CP_FB
External chargepump operation
LDO_ANA2
current sink operation on RGB1 and
RGB2, LDO_ANA2 on RGB3 pin
1b
ni
xb
ch
ca
RGB3
xxb
xxb
0b
1b
xxb
xxb
xxb
Function
RGB2
CP_CLK1 CP_CLK2
open or
RGB1
open or
RGB2
Te
These low voltage current sinks have a resolution of 8 bits. They can be controlled individually by the LED
pattern generator (on/off).
External PWM control of these current sinks is also possible and can be enabled by software (Input pin GPIO0).
If the current sink RGB3 (VANA2) is not used, its alternative function is ldo VANA2.
Symbol
Parameter
IBIT7
Current sink if Bit7 = 1
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Min
Typ
Max
19.2
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Unit
Note
mA
For V(CURRx) > 0.2V
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Typ
Max
Unit
Note
IBIT6
Current sink if Bit6 = 1
9.6
IBIT5
Current sink if Bit5 = 1
4.8
IBIT4
Current sink if Bit4 = 1
2.4
IBIT3
Current sink if Bit3 = 1
1.2
IBIT2
Current sink if Bit2 = 1
0.6
IBIT1
Current sink if Bit1 = 1
0.3
IBIT0
Current sink if Bit0 = 1
0.15
∆m
matching Accuracy
-8
+8
%
RGB1,2,3; full scale
∆
absolute Accuracy
-15
+15
%
V(RGBx) < VBAT-1.0V
RGB1 –
RGB3
Voltage compliance
0.2
V(CP
OUT)
V
al
id
Min
lv
Parameter
am
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Symbol
7.4.3.1 RGB Current Sinks Registers
curr rgb control
Addr: 02h
Bit Name
1:0
rgb1_mode
3:2
rgb2_mode
5:4
rgb3_mode
Rgb1 current
ch
Addr: 0Bh
ni
ca
Bit
This register select the mode of the current sinks RGB1, RGB2, RGB3
Default
Access Description
Select the mode of the current sink RGB1
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled
Select the mode of the current sink RGB2
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled
Select the mode of the current sink RGB3
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled
Bit Name
7:0
rgb1_current
Te
Bit
This register controls the RGB current sink current.
Default
Access Description
Defines current into Current sink RGB1
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
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Rgb2 current
Bit
Bit Name
7:0
rgb2_current
This register controls the RGB current sink current.
Default
Access Description
Defines current into Current sink RGB2
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
Rgb3 current
Bit Name
7:0
rgb3_current
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Bit
This register controls the RGB current sink current.
Default
Access Description
Defines current into Current sink RGB3
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
lv
Addr: 0Dh
al
id
Addr: 0Ch
7.4.4 General Purpose Current Sinks CURR41, CURR42, CURR43
Symbol
Parameter
Note
IBIT7
Current sink if Bit7 = 1
19.2
IBIT6
Current sink if Bit6 = 1
9.6
IBIT5
Current sink if Bit5 = 1
4.8
IBIT4
Current sink if Bit4 = 1
2.4
IBIT3
Current sink if Bit3 = 1
1.2
mA
For V(CURRx) > 0.2V
IBIT2
Current sink if Bit2 = 1
0.6
IBIT1
Current sink if Bit1 = 1
0.3
IBIT0
Current sink if Bit0 = 1
0.15
∆m
matching Accuracy
-8
+8
%
CURR41,42,43; full scale
absolute Accuracy
-15
+15
%
V(CURR4x) < VBAT-1.0V
0.2
VBAT
V
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Voltage compliance
Min
Typ
Max
Te
Curr41,42
,43
ni
∆
ca
Unit
ch
The current sinks CURR42 and CURR43 are only available in the device version AS3688B. In the AS3688B
version , the dcdc step up converter is not available.
The general purpose current sink can only be used if the DCDC step up converter is not required. The current
sink on the pin DCDC_FB can even be used together with the dcdc converter in current feedback mode without
overvoltage protection. These low voltage current sinks have a resolution of 8 bits and can sink up to 40mA.
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7.4.4.1 General Purpose Current Sinks CURR41, CURR42, CURR43 Registers
curr4 control
1:0
curr41_mode
3:2
curr42_mode
5:4
curr43_mode
This register selects the mode of the current sinks CURR41, CURR42, CURR43
Default
Access Description
Select the mode of the current sink CURR41
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled
Select the mode of the current sink CURR42
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled
Select the mode of the current sink CURR43
00b = off
0
R/W
01b = on
10b = PWM controlled
11b = LED pattern controlled
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Bit Name
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Bit
lv
Addr: 04h
Curr41 current
Addr: 13h
Bit
Bit Name
7:0
curr41_current
This register controls the curr41 current sink current.
Default
Access Description
Defines current into Current sink CURR41
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
Curr42 current
Addr: 14h
Bit Name
7:0
curr42_current
This register controls the curr42 current sink current.
Default
Access Description
Defines current into Current sink CURR42
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
ca
Bit
Bit Name
ch
Bit
Curr43 current
ni
Addr: 15h
curr43_current
Te
7:0
This register controls the curr43 current sink current.
Default
Access Description
Defines current into Current sink CURR43
00h = 0 mA
0
R/W
01h = 0.15 mA
...
FFh = 38.25 mA
7.4.5 LED Pattern Generator
The LED pattern generator is capable of producing a pattern with 32 bits length and 1 second duration (31.25ms
nd
rd
th
for each bit). The pattern itself can be started every second, every 2 , 3 or 4 second.
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With this pattern all current sinks can be controlled. The pattern itself switches the configured current sources
between 0 and their programmed current.
If everything else is switched off, the current consumption in this mode is IBAT. (excluding current through
switched on current source) and the charge pump, if required. The charge pump can be automatically switched
on/off depending on the pattern (see register cp_auto_on in the charge pump section) to reduce the overall
current consumption.
al
id
Figure 20 – LED Pattern Generator AS3688 for pattern_color = 0
Defined by bit in the setup register pattern_data
in this example the code is 101110011...
I
1 2 3 4 5 6 7 8 9 ... 32 1 2 3 4 5 6 7 8 9 ...
t
At this time a delay of 0s,1s(8s),2s(16s) or 3s(24s)
can be programmed
am
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31.25ms
(250ms if pattern_slow=1)
lv
any current sink
To select the different current sinks to be controlled by the LED pattern generator, see the ‘xxxx’_mode registers
(where ‘xxxx’ stands for the to be controlled current sink, e.g. curr1_mode for CURR1 current sink). See also the
descirption of the different current sinks.
To allow the generator of a color patterns set the bit pattern_color to ‘1’. Then the pattern can be connected e.g.
to RGB1/RGB2/RGB3 as follows:
Figure 21 – LED Pattern Generator AS3688 for pattern_color = 1
Defined by bit in the setup register pattern_data
in this example the code is 111110001011111000110111...
I
RGB1/CURR1/CURR41/CURR30
1 47
... 28 1 4 7
...
RGB2/CURR2/CURR42/CURR31
2 58
... 29 2 5 8
...
RGB3/
3 69
... 30 3 6 9
...
/CURR43/CURR32,33
t
ca
100ms
(800ms if pattern_slow=1)
At this time a delay of 0s,1s(8s),2s(16s) or 3s(24s)
can be programmed
ni
Only those current sinks will be controlled, where the ‘xxxx’_mode register is configured for LED pattern.
ch
If the register bit pattern_slow is set, all pattern times are increased by a factor of eigth. (bit duration: 250ms if
pattern_color=0 / 800ms if pattern_color=1, delays between pattern up to 24s).
7.4.5.1 Soft Dimming for Pattern
Te
The internal pattern generator can be combined with the internal pwm dimming modulator to obtain as shown in
the following figure:
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Figure 22 – Softdimming Architecture for the AS3688 (softdim_pattern=1 and pattern_color = 1)
out
set
RS
reset Flip Flop
out
set
RS
reset Flip Flop
out
RGB1/CURR1/CURR41/CURR30
Zero
Detect
8
RGB3/
/CURR43/CURR32,33
controls current sources (on/off) for
current source where
currX_mode = LED pattern
PWM
Modulator
lv
up down Dimming
Ramp
Gen
RGB2/CURR2/CURR42/CURR31
al
id
Pattern
Generator
set
RS
reset Flip Flop
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With the AS3688 smooth fade-in and fade-out effects can be automatically generated.
As there is only one dimming ramp generator and one pwm modulator following constraints have to be
considered when setting up the pattern (applies only if pattern_color=1):
Figure 23 – Softdimming example Waveform for RGB1, RGB2 and RGB3
A new dimming up (RGB2) can be
started after the dimming
down (RGB1) is finished
RGB1
ok
RGB2
ok
RGB3
not possible
ca
A new dimming up (RGB3) cannot be
started after or while one channel (RGB1)
is dimming up
However using the identical dimming waveform for two channels is possible as shown in the following figure:
RGB1
ch
RGB2
ni
Figure 24 – Softdimming example Waveform for RGB1, RGB2 and RGB3
ok
ok
Te
RGB3
ok
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7.4.5.2 LED Pattern Registers
Addr: 19h,1Ah,1Bh,1Ch
Pattern data0, Pattern data1, Pattern data2, Pattern data3
This registers contains the pattern data for the RGB current sinks.
Default
Access Description
Bit Name
7:0
pattern_data0[7:0] 1
0
R/W
Pattern data0; if this register is changed and patern_color=1
no current source must have currX_mode = ‘LED pattern
controlled’ (11)
7:0
pattern_data1[15:8] 1
0
R/W
Pattern data1; if this register is changed and patern_color=1
no current source must have currX_mode = ‘LED pattern
controlled’ (11)
7:0
pattern_data2[23:16] 1
0
R/W
Pattern data2; if this register is changed and patern_color=1
no current source must have currX_mode = ‘LED pattern
controlled’ (11)
7:0
pattern_data3[31:24] 1
0
R/W
Pattern data3; if this register is changed and patern_color=1
no current source must have currX_mode = ‘LED pattern
controlled’ (11)
1.
Update any of the pattern register only if none of the current sources is connected to the pattern
generator (‘xxxx’_mode must not be 11b). The pattern generator is automatically started at the
same time when any of the current sources is connected to the pattern generator
Pattern control
Addr: 18h
Bit Name
0
pattern_color
2:1
pattern_delay
3
softdim_pattern
4
curr30_pattern
5
curr31_pattern
ni
ch
curr32_pattern
Te
7
This register controls the LED pattern
Default
Access Description
Defines the pattern type for the current sinks
0b = single 32 bit pattern (also set currX_mode = ‘LED
0
R/W
pattern controlled (11))
1b = RGB pattern with each 10 bits (also set
currX_mode = ‘LED pattern controlled (11))
Delay between pattern
00b = 0 sec
01b = 1 sec (8 sec if pattern_slow=1)
0
R/W
10b = 2 sec (16 sec if pattern_slow=1)
11b = 3 sec (24 sec if pattern_slow=1)
Enable the ‘soft’ dimming feature for the pattern generator
0 = Pattern generator directly control current sources
1 = ‘Soft Dimming’ is performed – see section ’Soft Dimming
0b
R/W
for pattern’; do not use for CURR1 or CURR2; do not
set CURR3x_mode to ‘other’ if softdim_pattern=1
Additional CURR33 LED pattern control bit
0b = CURR30 controlled according curr30_mode register
0b
R/W
1b = CURR30 controlled by LED pattern generator
ca
Bit
6
lv
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Note:
al
id
Bit
curr33_pattern
R/W
Additional CURR33 LED pattern control bit
0b = CURR31 controlled according curr31_mode register
1b = CURR31 controlled by LED pattern generator
0b
R/W
Additional CURR33 LED pattern control bit
0b = CURR32 controlled according curr32_mode register
1b = CURR32 controlled by LED pattern generator
0b
R/W
Additional CURR33 LED pattern control bit
0b = CURR33 controlled according curr33_mode register
1b = CURR33 controlled by LED pattern generator
0b
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Addr: 2Ch
austriamicrosystems
gpio_current
Bit
Bit Name
Default
Access
6
pattern_slow
0
R/W
Description
Pattern timing control
0b = normal mode
1b = slow mode (all pattern times are increased by a
factor of eight)
al
id
7.4.6 Overtemp comparator
Table 15 – Overtemp comparator Characteristics
Parameter
Min
VOVtemp
Comparator switch level
Typ
Max
Unit
Note
am
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nt
st
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Symbol
lv
If the LED temperature for CURR3x flash led is monitored with an external temperature sensor, the current sink
CURR3x can be automatically switched from strobe to preview current levels, if the external temperature sensor’s
voltage drops below VOVtemp. to avoid overheating of the flash LED.
The overtemperature comparator is multiplexed to GPIO2 and is switched on automatically, if Bit
curr3x_ext_ovtemp is set.
1.22
1.25
1.28
V
7.4.6.1 Overtemp comparator Registers
Curr3 control1
Addr: 12h
Bit
Bit Name
0
preview_off_after
strobe
This register select the modes of the current sinks30..33 current.
Default Access Description
Select the switch off mode after strobe pulse
0b
R/W 0=normal preview/strobe mode,
1=switch off preview after strobe duration has expired
preview_ctrl
00b
R/W
3
0
0b
R/W
reserved
ca
2:1
Preview is triggered by
00b = off
01b = software trigger
10b = GPIO active high
11b = GPIO active low
curr3x_ext_ovtemp
5
curr3x_strobe_high
0b
R/W
6
0
0b
R/W
reserved
curr33_pattern
0b
R/W
Additional CURR33 control bit
0b = CURR33 controlled according curr33_mode register
1b = CURR33 controlled by LED pattern generator
Te
ch
ni
4
7
0b
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R/W
Selects overtemperature switch off of flash LED
0b = normal operation of CURR3x
1b = if the voltage on GPIO drops below 1.25V (above 1.25V if
ext_ov_temp_inv=1), CURR3x is switched from strobe to preview
current levels
(can be used to monitor the temperature of the flash led or as
general input to reduce the current through the flash LED e.g. to
temporarily reduce the current from the battery)
Doubles curr3x current during strobe
0b = normal operation of CURR3x (0..160 mA)
1b = Doubles current during strobe (0..320mA)
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Curr low voltage status2
Addr: 2Bh
Bit
Bit Name
5
ovtemp_ext
This register controls the curr42 current sink current.
Default
Access Description
Overtemp comparator status bit
0b = no overtemperature, GPIO2>1.25V
NA
R
1b = overtemperature, GPIO2<1.25V
gpio current
Bit Name
Default
Access
0
ext_ov_temp_inv
0
R/W
Description
Polarity of external overtemp comparator
0b = active high (Overtemperature when Vgpio>1.25V)
1b = active low (Overtemperature when Vgpio< 1.25V)
lv
Bit
al
id
Addr: 2Ch
7.4.7 External chargepump
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This external charge pump uses external schottky diodes and capacitors to generate low current outputs in the
range of –15V to +15V. The device delivers a square wave signals and an inverted square wave signals at
250kHz or 500kHz with full Battery voltage swing. Depending on the external configuration the battery voltage is
multiplied and / or inverted. A feedback loop with a dedicated regulation pin controls the output voltage by
modulating the duty circle.
E.g.: There are 3 Schottky Diodes, 2 Resistors and 3 Capacitors externally required for –6V output voltage.
For the Schottky Diodes the BAS40 (2 diodes in a SOT666 package) is recommended.
Table 16 – External Charge Pump Characteristics
Parameter
Min
Typ
Max
Unit
Note
Vfb00
Negative output mode
feedback voltage
-20
0
20
mV
Regulated, with internal current
source
Ifb
Feedback current
9.7
10
10.3
µA
Current sourced at feedback pin
for negative mode
Vfb01
Positive output mode
feedback voltage
1.22
1.25
1.28
V
Regulated, with two external
resistors
Vout00
Output Voltage mode 00b
-6
V
with external 600k resistor
Vout01
Output Voltage mode 01b
15
V
η
Efficiency
ni
and 1.375 MΩ
85
%
70
Battery Voltage 3.5V
Battery Voltage 4.2V
10
mA
@ -6V
Output Current
5
mA
@ +15V
Te
Iout
with external 125kΩ resistor
Output Current
ch
Iout
ca
Symbol
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7.4.7.1 External chargepump Registers
Reg. Control
Addr: 00h
Bit Name
4
cp_ext_on
Ext. chargepump mode
Bit Name
1:0
cp_ext_mode
3:2
cp_ext_clk<1:0>
4
cp_ext_lowcurr
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Bit
This register selects the modes of the external chargepump
Default
Access Description
Selects the mode of the Ext. charge pump
00b = regulate to negative voltage (e.g.: -6V)
0
R/W
01b = regulate to positive voltage (e.g.:+15V)
10b = unregulated (free running)
11b = reserved Select the mode of the current sink CURR41
Selects the switching frequency
00b = 250kHz
0
R/W
01b = 500kHz
10b = 1MHz
11b = NA
Driving capability of ext. charge pump
0b = normal current = Iout
0
R/W
1b = reduced current = Iout / 4
Output noise and ripple will be reduced
lv
Addr: 1Dh
al
id
Bit
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs, current
sinks, the Step Up DC/DC Converter.
Default
Access Description
Enable the external chargepump
0
R/W
0b = Disable the external chargepump.
1b = Enable the external chargepump
7.4.8 PWM Generator
The PWM generator can be used for any current sink (CURR1, CURR2, CURR3x, CURR4x, RGB).. It can be
programmed to use the pin GPIO0 (pwm_mode=0) or an internal PWM generator (pwm_mode=1). The setting
applies for all current sinks, which are controlled by the pwm generator (e.g. CURR1 is pwm controlled if
curr1_mode = 10, RGB1 is pwm controlled if rgb1_mode = 10). The pwm modulated signal (internal / external)
can switch on/off the current sinks and therefore depending on its duty cycle change the brightness of an
attached LED.
ca
7.4.8.1 Internal PWM Generator
If pwm_code bit 7 = 1
Then the upper 6 bits (Bits 7:2) of pwm_code are used for the 6 bits PWM generation, which controls the
selected currents sinks directly
ch
ni
The internal PWM generator uses the 2MHz internal clock as input frequency and its dimming range is 6 bits
digital (2MHz / 2^6 = 31.3kHz pwm frequency) and 2 bits analog. Depending on the actual code in the register
‘pwm_code’ the following algorithm is used:
If pwm_code bit 7 =0 and bit 6 = 1
Then bits 6:1 of pwm_code are used for the 6 bits PWM generation. This signal controls the selected current
sinks, but the analog current of these sinks is divided by 2
Te
If pwm_code bit 7 and bit 6 = 0
Then bits 5:0 of pwm_code are used for the 6 bits PWM generation. This signal controls the selected current
sinks, but the analog current of these sinks is divided by 4
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Figure 25 – PWM Control
0
to current sink(s) but analog
currents are divided by 4
6 bit PWM
to current sink(s) but analog
currents are divided by 2
6 bit PWM
6 bit PWM
to current sink(s)
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0 0
7 6 5 4 3 2 1 0
pwm_code
Automatic Up/Down Dimming
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If the register pwm_dim_mode is set to 01 (up dimming) or 10 (down dimming) the value within the register
th
th
pwm_code is increased (up dimming) or decreased (down dimming) every time and amount (either 1/4 or 1/8 )
defined by the register pwm_dim_speed. The maximum value of 255 (completely on) and the minimum value of
0 (off) is never exceeded. It is used to smoothly and automatically dim the brightness of the LEDs connceted to
any of the current sinks. The PWM code is readable all the time (Also during up and down dimming)
The waveform for up dimming looks as follows (cycles omitted for simplicity):
Figure 26 – PWM Dimming Waveform for up dimming (pwm_dim_mode = 01); currX_mode = PWM controlled (not all steps shown)
I
currX_current
I/2
I/4
t
next step: I/2 with
50% duty cycle
32µs
I/4 with up to
100% duty cycle
The internal pwm modulator circuit controls the current sinks as shown in the following figure:
ca
Figure 27 – PWM Control Circuit (currX_mode = 10b (PWM controlled)); X = any current sink
Adder Logic
currX_adder
currX_current
8
ni
pwm_code
ch
From serial
Interface
/2
Te
Dimming
Ramp
Gen
2MHz
0
8
/4
8
PWM
Modulator
if pwm_dim_mode = 01 or 10
subX_en
8
IDAC
CURRX
8
adder_currentX
Only for RGB1,2,3
CURR41,42,43
CURR1, CURR2
The adder logic (available for RGB1, RGB2, RGB3, CURR41, CURR42, CURR43, CURR1 and CURR2) is
intended to allow dimming not only from 0% to 100% (or 100% to 0%) of currX_current, but also e.g. from 10% to
110% (or 110% to 10%) of currX_current. That means for up dimming the starting current is defined by 0 +
currX_adder and the end current is defined by currX_current + currX_adder.
An overflow of the internal bus (8 Bits wide to the IDAC) has to be avoided by the register settings (currX_current
+ currX_adder must not exceed 255).
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If the register subX_en is set, the result from the pwm_modulator is inverted logically. That means for up
dimming the starting current is defined by currX_adder - 1 and the end current is defined by currX_adder currX_current - 1. An overflow of the internal bus (8 Bits wide to the IDAC) has to be avoided by the register
settings (currX_adder - currX_current - 1 must not be below zero).
Its purpose is to dim one channel e.g. CURR41 from e.g. 110% to 10% of curr41_current and at the same time
dim another channel e.g. CURR42 from 20% to 120% of curr42_current.
Note:
2.
The adder logic operates independent of the currX_mode setting, but its main purpose is to work
together with the pwm modulator (improved up/down dimming)
If the adder logic is not used anymore, set the bit currX_adder to 0. (Setting adder_currentX to 0 is
not sufficient)
Figure 28 – PWM Table
Seconds
Seconds Seconds
Step
%Dimming
PWM
%Dimming
PWM
50msec/
Step
25msec/
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
100,0
75,3
56,5
42,4
31,8
23,9
18,0
13,7
10,6
8,2
6,3
4,7
3,5
2,7
2,4
2,0
1,6
1,2
0,8
0,4
255
192
144
108
81
61
46
35
27
21
16
12
9
7
6
5
4
3
2
1
100,0
87,8
76,9
67,5
59,2
52,2
45,9
40,4
35,7
31,4
27,5
24,3
21,6
19,2
16,9
14,9
13,3
11,8
10,6
9,4
255
224
196
172
151
133
117
103
91
80
70
62
55
49
43
38
34
30
27
24
0,00s
0,05s
0,10s
0,15s
0,20s
0,25s
0,30s
0,35s
0,40s
0,45s
0,50s
0,55s
0,60s
0,65s
0,70s
0,75s
0,80s
0,85s
0,90s
0,95s
0,00s
0,03s
0,05s
0,08s
0,10s
0,13s
0,15s
0,18s
0,20s
0,23s
0,25s
0,28s
0,30s
0,33s
0,35s
0,38s
0,40s
0,43s
0,45s
0,48s
21
0,0
0
8,2
21
1,00s
7,5
6,7
5,9
5,5
5,1
4,7
4,3
3,9
3,5
3,1
2,7
2,4
2,0
1,6
19
17
15
14
13
12
11
10
9
8
7
6
5
4
1,05s
1,10s
1,15s
1,20s
1,25s
1,30s
1,35s
1,40s
1,45s
1,50s
1,55s
1,60s
1,65s
1,70s
5msec/
Step
2,5msec/
Step
0,000s
0,005s
0,010s
0,015s
0,020s
0,025s
0,030s
0,035s
0,040s
0,045s
0,050s
0,055s
0,060s
0,065s
0,070s
0,075s
0,080s
0,085s
0,090s
0,095s
0,000s
0,003s
0,005s
0,008s
0,010s
0,013s
0,015s
0,018s
0,020s
0,023s
0,025s
0,028s
0,030s
0,033s
0,035s
0,038s
0,040s
0,043s
0,045s
0,048s
0,50s
0,100s
0,050s
0,53s
0,55s
0,58s
0,60s
0,63s
0,65s
0,68s
0,70s
0,73s
0,75s
0,78s
0,80s
0,83s
0,85s
0,105s
0,110s
0,115s
0,120s
0,125s
0,130s
0,135s
0,140s
0,145s
0,150s
0,155s
0,160s
0,165s
0,170s
0,053s
0,055s
0,058s
0,060s
0,063s
0,065s
0,068s
0,070s
0,073s
0,075s
0,078s
0,080s
0,083s
0,085s
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22
23
24
25
26
27
28
29
30
31
32
33
34
35
Seconds
lv
Decrease by 1/4th every Decrease by 1/8th every
step
step
al
id
1.
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Decrease by 1/4th every Decrease by 1/8th every
step
step
Seconds
Seconds Seconds
Seconds
%Dimming
PWM
50msec/
Step
25msec/
Step
5msec/
Step
2,5msec/
Step
36
37
38
1,2
0,8
0,4
3
2
1
1,75s
1,80s
1,85s
0,88s
0,90s
0,93s
0,175s
0,180s
0,185s
0,088s
0,090s
0,093s
39
0,0
0
1,90s
0,95s
0,190s
0,095s
PWM
al
id
%Dimming
Step
7.4.8.2 PWM Generator Registers
Pwm control
Bit Name
0
pwm_mode
2:1
pwm_dim_mode
5:3
pwm_dim_speed
6
pwm_gpio2
ca
ni
Pwm code
ch
Addr: 17h
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Bit
This register controls PWM generator
Default
Access Description
Selects the PWM source
0b = Use external PWM from GPIO0 or GPIO2
1b
R/W
(defined by pwm_gpio2)
1b = Use internal PWM (default)
Selects the dimming mode
00b = no dimming; actual content of register pwm_code is
used for pwm generator
01b = logarithmic up dimming (codes are increased).
Start value is actual pwm_code
00b
R/W
10b = logarithmic down dimming (codes are decreased)
Start value is actual pwm_code; switch off the dimmed
current source after dimming is finished to avoid
unnecessary quiescent current
11b = NA
Defines dimming speed by increase/descrease pwm_code …
th
000b = … by 1/4 every 50 msec (total dim time 1.0s)
th
001b = … by 1/8 every 50 msec (total dim time 1.9s)
th
010b = … by 1/4 every 25 msec (total dim time 0.5s)
th
000b
R/W
011b = … by 1/8 every 25 msec (total dim time 0.95s)
th
100b = … by 1/4 every 5 msec (total dim time 100ms)
th
101b = … by 1/8 every 5 msec (total dim time 190ms)
th
110b = … by 1/4 every 2.5 msec (total dim time 50ms)
th
111b = … by 1/8 every 2.5 msec (total dim time 95ms)
Selects the PWM source
0b = Use GPIO0 for external pwm
0b
R/W
1b = Use GPIO2 for external pwm
lv
Addr: 16h
This register controls the Pwm code.
Bit Name
Default
Access
7:0
pwm_code
00b
R/W
Te
Bit
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Description
Selects the PWM code
00h = Always 0
...
FFh = Always 1
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Adder Current 1
Addr: 30h
Bit
Bit Name
7:0
adder_current1
This register defines the current which can be added to CURR1, CURR41, RGB1
Default
Access Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h = 0 (represents 0mA)
00b
R/W
...
FFh = 255 (represents 38.25mA)
Bit Name
7:0
adder_current2
This register defines the current which can be added to CURR2, CURR42, RGB2
Default
Access Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h = 0 (represents 0mA)
00b
R/W
...
FFh = 255 (represents 38.25mA)
lv
Bit
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Adder Current 2
Addr: 31h
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Adder Current 3
Addr: 32h
Bit
Bit Name
7:0
adder_current3
This register defines the current which can be added to CURR43, RGB3
Default
Access Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h = 0 (represents 0mA)
00b
R/W
...
FFh = 255 (represents 38.25mA)
Adder Enable 1
Addr: 33h
Bit Name
0
rgb1_adder
1
rgb2_adder
2
rgb3_adder
3
curr41_adder
4
curr42_adder
5
curr43_adder
ch
ni
ca
Bit
Enables the adder circuit for the selected current sources
Default
Access Description
Enables adder circuit for current source RGB1
0
R/W
0 = Normal Operation of the current source
1 = adder_current1 gets added to the current source current
Enables adder circuit for current source RGB2
0
R/W
0 = Normal Operation of the current source
1 = adder_current2 gets added to the current source current
Enables adder circuit for current source RGB3
0
R/W
0 = Normal Operation of the current source
1 = adder_current3 gets added to the current source current
Enables adder circuit for current source CURR41
0
R/W
0 = Normal Operation of the current source
1 = adder_current1 gets added to the current source current
Enables adder circuit for current source CURR42
0
R/W
0 = Normal Operation of the current source
1 = adder_current2 gets added to the current source current
Enables adder circuit for current source CURR43
0
R/W
0 = Normal Operation of the current source
1 = adder_current3 gets added to the current source current
Te
Addr: 34h
Adder Enable 2
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default
Access
0
curr1_adder
0
R/W
1
curr2_adder
0
R/W
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Description
Enables adder circuit for current source CURR1
0 = Normal Operation of the current source
1 = adder_current1 gets added to the current source current
Enables adder circuit for current source CURR2
0 = Normal Operation of the current source
1 = adder_current2 gets added to the current source current
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Subtract Enable
Addr: 35h
Enable the inversion from the signal from the pwm generator
Default
Access
0
sub_en1
0
R/W
1
sub_en2
0
R/W
2
sub_en3
0
R/W
General Purpose Input / Outputs
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7.5
Description
Inverts the signal from the pwm generator
0 = Direct Operation (no inversion)
1 = The signal from the pwm generator for which the adder
is enabled (curr1_adder = 1, curr41_adder = 1,
rgb1_adder = 1) is inverted
Inverts the signal from the pwm generator
0 = Direct Operation (no inversion)
1 = The signal from the pwm generator for which the adder
is enabled (curr2_adder = 1, curr42_adder = 1,
rgb2_adder = 1) is inverted
Inverts the signal from the pwm generator
0 = Direct Operation (no inversion)
1 = The signal from the pwm generator for which the adder
is enabled (curr42_adder = 1, rgb3_adder = 1) is inverted
al
id
Bit Name
lv
Bit
GPIO0 :GPIO2, GPI are four highly-configurable general purpose input/output pins which can be used for the
following functionality (each GPIO pin is independent from the other GPIO pins):
Digital Schmitt-Trigger Input
Digital Output with 4mA Driving Capability at 2.8V Supply (VDD_GPIO)
Tristate Output
Analog Input to the ADC (GPIO0, GPIO1, GPIO2, GPI)
Strobe for Camera Flash Current Sink (GPI)
Preview Current set input for Camera Flash Current Sink (GPIO2)
PWM operation with all current sinks (GPIO0); number of current sources using this PWM input is fully
configurable
Flash led overtemperature protection (GPIO2)
Default Mode for GPI is Input
Default Mode for GPIO0, GPIO1 and GPIO2 is Input (Pull-Down)
ca
GPIO4 not applicable in the AS3688
GPIO Pin
Pin #
TBD
ch
GPIO0
ni
Table 17 – GPIO Pin Function Summary
TBD
GPIO2
TBD
Te
GPIO1
GPI
Configuration
Additional Function
ADC Input; PWM Input
Digital Input, Totem-Pole Output (Push/Pull),
ADC Input; TXMask input
Open Drain (PMOS or NMOS), High-Z,
Pull-Down or Pull-Up Resistor
ADC Input; Preview Input for Photocamera
Flash LED (CURR3x); PWM Input
TBD
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Digital Input
Revision 1.1.1 / 20060707
ADC Input; Strobe Input for Photocamera
Flash LED (CURR3x)
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Figure 29 – GPIO Pin Connections
V DD_GPIO
al
id
Pullup
Open, when
gpio_pulls = 11 (ADC)
GPIO Pins
CPIO Control
Registers
Interface
GPIO0:GPIO2
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Pulldown
Vss
7.5.1 GPIO Characteristics
Table 18 – GPIO DC Characteristics
Symbol
Parameter
Min
Max
Unit
Pull up/Pull down
Resistance
30
75
kΩ
Supply Voltage
1.5
3.3
V
VIH
High Level Input Voltage
0.7·Vgpio
VIL
Low Level Input Voltage
VHYS
Hysteresis
0.1· Vgpio
Input Leakage Current
-5
Rpull
Vgpio
ILEAK
VOL
Low Level Output Voltage
ni
ca
High Level Output Voltage 0.8·Vgpio
Te
CLOAD
V
V
5
0.2· Vgpio
µA
To Vgpio and VSS
V
at - Iout
V
at Iout
4
Vgpio = 2.8V, gpioX_low_curr = 1
(page gpio0_low_curr)
16
Vgpio = 2.8V, gpioX_low_curr = 0
Driving Capability
mA
1
ch
Iout
V
0.3· Vgpio
VOH
Note
Vgpio = 1.5V, gpioX_low_curr = 1
guaranteed by design.
4
Capacitive Load
Vgpio = 1.5V, gpioX_low_curr = 0
guaranteed by design.
50
pF
Vgpio is used as the supply voltage for all GPIOs.
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7.5.2 GPIO Registers
GPIO Output
This register controls GPIO outputs.
Default
Access
0
gpio0_out
0
R/W
1
gpio1_out
0
R/W
2
gpio2_out
0
R/W
3
gpi_en
0
R/W
4
gpi_curr30_en
0
R/W
5
gpi_curr31_en
0
R/W
6
gpi_curr32_en
0
R/W
7
gpi_curr33_en
0
R/W
Bit
Bit Name
0
gpio0_in
1
gpio1_in
2
gpio2_in
3
gpi_in
4
5
This register controls GPIO outputs.
Default
Access
Description
Reads a logic signal from pin GPIO0; this is independent of
N/A
R
any other setting e.g., bits gpio1_mode.
Reads a logic signal from pin GPIO1; this is independent of
N/A
R
any other setting e.g., bits gpio1_mode.
Reads a logic signal from pin GPIO2; this is independent of
N/A
R
any other setting e.g., bits gpio1_mode.
R
Reads a logic signal from pin GPI; if gpi_en=1
curr30_in
N/A
R
Reads a logic signal from pin CURR30; if gpi_curr30_en=1
curr31_in
N/A
R
Reads a logic signal from pin CURR31; if gpi_curr31_en=1
curr32_in
N/A
R
Reads a logic signal from pin CURR32; if gpi_curr32_en=1
N/A
R
Reads a logic signal from pin CURR33; if gpi_curr33_en=1
ch
ni
ca
N/A
curr33_in
Te
7
Writes a logic signal to pin GPIO0; this is independent of
any other bit setting e.g., gpio0_mode.
Writes a logic signal to pin GPIO1; this is independent of
any other bit setting e.g., gpio1_mode.
Writes a logic signal to pin GPIO2; this is independent of
any other bit setting e.g., gpio2_mode.
Enables the GPI input. Set to 1 if used for strobe trigger.
0 = input disabled
1 = input enabled; can be used for strobe trigger
Enables the CURR30 input.
0 = input disabled
1 = input enabled
Enables the CURR31 input.
0 = input disabled
1 = input enabled
Enables the CURR32 input.
0 = input disabled
1 = input enabled
Enables the CURR33 input.
0 = input disabled
1 = input enabled
GPIO Signal
Addr: 06h
6
Description
al
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Bit Name
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Bit
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Addr: 05h
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GPIO01_control
Addr: 1Eh
This register controls GPIO0 and GPIO1 pin functions.
Access
1:0
gpio0_mode
00
R/W
3:2
gpio0_pulls
01
R/W
5:4
gpio1_mode
00
R/W
7:6
gpio1_pulls
Description
Defines the direction for pin GPIO0.
00 = Input only or used for PWM
01 = Output (push and pull).
10 = Output (open drain, only push; only NMOS is active).
11= Output (open drain, only pull; only PMOS is active).
Adds the following pullup/pulldown to pin GPIO0; this is
independent of setting of bits gpio0_mode.
00 = None
01 = Pulldown
10 = Pullup
11= ADC input (gpio0_mode = XX); recommended for analog
signals.
Defines the direction for pin GPIO1.
00 = Input only; can be used for TXMask
01 = Output (push and pull).
10 = Output (open drain, only push; only NMOS is active).
11= Output (open drain, only pull; only PMOS is active).
Adds the following pullup/pulldown to pin GPIO1; this is
independent of setting of bits gpio1_mode.
00 = None
01 = Pulldown
10 = Pullup
11= ADC input (gpio1_mode = XX); recommended for analog
signals.
al
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Default
lv
Bit Name
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Bit
01
R/W
GPIO23 control
Addr: 1Fh
Default
Access
1:0
gpio2_mode
00
R/W
3:2
gpio2_pulls
7:4
ca
Bit Name
ni
This register controls pins GPIO2 pin functions.
Bit
R/W
Te
ch
11
Description.
Defines the direction for pin GPIO2.
00 = Input only; can be used for PWM or preview mode
01 = Output (push and pull).
10 = Output (open drain, only push; only NMOS is active).
11= Output (open drain, only pull; only PMOS is active).
Adds the following pullup/pulldown to pin GPIO2; this is
independent of setting of bits gpio2_mode.
00 = None
01 = Pulldown
10 = Pullup
11= ADC input (gpio2_mode = XX); recommended for analog
signals.
N/A
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GPIO driving cap
Addr: 20h
This register enables low current mode for GPIOs.
Default
Access Description
Bit Name
0
gpio0_low_curr
0
R/W
Defines the driving capability of pin GPIO0.
0 = Iout
1 = Iout /4
1
gpio1_low_curr
0
R/W
Defines the driving capability of pin GPIO1.
0 = Iout
1 = Iout /4
2
gpio2_low_curr
0
R/W
al
id
Bit
Defines the driving capability of pin GPIO2.
0 = Iout
1 = Iout /4
N/A
lv
7:3
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7.6 LED Test
Figure 30 – LED Function Testing
Detect Shorted LEDs
From DCDC
Step Up
Converter
D1
C9
4.7µF
R3
1M
I(step_up_vtuning)
DCDC_FB
From Charge
Pump
CPOUT
C8
2.2µF
Baseband
Processor
Interface
ADC
...
Detect Open LEDs
ca
...
ch
ni
The AS3688 supports the verification of the functionality of the connected LEDs (open and shorted LEDs can be
detected). This feature is especially useful in production test to verify the correct assembly of the LEDs, all its
connectors and cables. It can also be used in the field to verify if any of the LEDs is damaged. A damaged LED
can then be disabled (to avoid unnecessary currents).
The current sources, charge pump, dcdc converter and the internal ADC are used to verify the forward voltage of
the LEDs. If this forward voltage is within the specified limits of the LEDs, the external circuitry is assumed to
operate.
7.6.1 Function Testing for single LEDs connected to the Charge Pump
Te
For any current source connected to the charge pump (usually RGB{1,2,3}, CURR{30,31,32,33,41,42,43}) where
only one LED is connected between the charge pump and the current sink (see Figure 1) use:
Table 19 – Function Testing for LEDs connected to the Charge Pump
Step
1.
Action
Example Code
Switch on the charge pump and set it into manual 1:2
Reg 23h <- 14h (cp_mode = 1:2, manual)
mode (to avoid automatic mode switching during
Reg 00h <- 04h (cp _on = 1)
measurements)
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Table 19 – Function Testing for LEDs connected to the Charge Pump
4.
5.
6.
7.
8.
Switch off the current sink for the LED to be tested
Compare the difference between the ADC
measurements (which is the actual voltage across the
tested LED) against the specification limits of the
tested LED
Do the same procedure for the next LED starting from
point 2
Switch off the charge pump
set chargepump automatic mode
Reg 03h <- 00h (curr31_mode = off)
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3.
Example Code
e.g. for register CURR31set to 9mA use
Switch on the current sink for the LED to be tested
Reg 10h <- 0Fh (curr3x_other = 9mA)
Reg 03h <- 0ch (curr31_mode = curr3x_other)
Reg 26h <- 95h (adc_select=CP_OUT,start ADC)
Measure with the ADC the voltage on CP_OUT
Fetch the ADC result from Reg 27h and 28h
Measure with the ADC the voltage on the switched on Reg 26h <- 8bh (adc_select=CURR31,start ADC)
current sink
Fetch the ADC result from Reg 27h and 28h
Calculation performed in baseband uProcessor
Jump to 2. If not all the LEDs have been tested
lv
2.
Action
Reg 00h <- 00h (cp _on = 0)
Reg 23h <- 00h
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Step
Note: For CURR41,42,43 first set the charge pump into 1:1 mode and test if the LED is shorted. Then use the
above described procedure.
7.6.2 Function Testing for LEDs connected to the Step Up DCDC Converter
For LEDs connected to the DCDC converter (usually current sinks CURR1and CURR2) use the following
procedure:
Table 20 – Function Testing for LEDs connected to the DCDC converter
Step
2.
3.
Switch on the current sink for the LED string to be
tested (CURR1 or CURR2)
Select the feedback path for the LED string to be
tested (e.g. step_up_fb = 01 for LED string on
CURR1)
Set the current for step_up_vtuning exactly above the
maximum forward voltage of the tested LED string +
0.6V (for the current sink) + 0.25V; add 6% margin
(accuracy of step_up_vtuning); this sets the maximum
output voltage limit for the DCDC converter
ca
1.
Action
Example Code
e.g. Test LEDs on CURR1:
Reg 01h <- 01h (curr1_mode=on)
Reg 09h <- 3ch (curr1 = 9mA)
Reg 21h <- 02h (feedback=curr1)
e.g. 4 LEDs with UfMAX = 4.1V gives 17.25V +6%
= 18.29V; if R3=1MΩ and R4 = open, then select
step_up_vtuning = 18 (Reg 21h <- 92h; results in
19.25V overvoltage protection voltage – see table
in DCDC section)
Set stepup_prot = 1
Reg 22h <- 04h
5.
Switch on the DCDC converter
Reg 00h <- 08h
6.
Wait 1ms (DCDC startup time)
7.
Measure the voltage on DCDC_FB (ADC)
ch
ni
4.
Reg 26h <- 96h (adc_select=DCDC_FB, start
ADC; Fetch the ADC result from Reg 27h and 28h)
8.
If the voltage on DCDC_FB is above 1.0V, the tested
(Code >199h)
LED string is broken – then skip the following steps
9.
Switch off the overvoltage protection (stepup_prot = 0) Reg 22h <- 00h
e.g.: Reg 21h <- 62h (step_up_vtuning=12): ADC
Reduce step_up_vtuning step by step until the
measured voltage on DCDC_FB (ADC) is above 1.0V. result=1,602V
11.
Measure voltage on DCDC_FB
e.g. DCDC_FB=1.602V
12.
Switch off the DCDC converter
Reg 00h <- 00h
Te
10.
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Table 20 – Function Testing for LEDs connected to the DCDC converter
13.
14.
Action
The voltage on the LED string can be calculated now
as follows (R4 = open):
VLEDSTRING = V(DCDC_FB) + I(step_up_vtuning) *
R3 – 0.5V (current sinks feedback voltage: VFB2).
V(DCDC_FB) = ADC Measurement from point 11
I(step_up_vtuing) = last setting used for point 10
Compare the calculated value against the
specification limits of the tested LEDs
Example Code
e.g.: VLED = (1.602V + 12V – 0.5V) / 4 = 3.276V
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Step
7.7
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With the above described procedures electrically open and shorted LEDs can be automatically detected. To
reduce the settling time of the DCDC converter to changes of step_up_vtuning, the external capacitors C10 and
C11 can be changed to C10=150pF and C11=1.5nF.
Analog-To-Digital Converter
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The AS3688 has a built-in 10-bit successive approximation analog-to-digital converter (ADC). It is internally
supplied by V2_5, which is also the full-scale input range (0V defines the ADC zero-code). For input signal
exceeding V2_5 (typ. 2.5V) a resistor divider with a gain of 0.4 (Ratioprescaler) is used to scale the input of the
ADC converter. Consequently the resolution is:
Table 21 – ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
VLSB
Note
GPIO0, GPIO1, GPIO2, GPI, DCDC_FB
0V-2.5V
2.44mV
VLSB=2.5/1024
ADCTEMP_CODE
TBD
1 / ADCTC
junction temperature
RGB1,RGB2,RGB3,
CURR{30, 31, 32, 33, 41, 42, 43}
VBAT2, CP_OUT
0V-5.5V
6.1mV
VLSB=2.5/1024 * 1/0.4;
internal resistor divider used
CURR1, CURR2
0V-1.0V
2.44mV
VLSB=2.5/1024
Table 22 – ADC Parameters
DNL
INL
Resolution
10
Input Voltage Range
VSS
Max
Unit
Vsupply
V
LSB
Integral Non-Linearity
± 0.5
LSB
Input Offset Voltage
± 0.25
LSB
Input Impedance
Cin
Input Capacitance
100
9
pF
Power Supply Range
2.5
V
Idd
Power Supply Current
500
µA
Idd
Power Down Current
100
nA
+/-5
°C
375
Code
TTOL
ADCTOFFSET
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Vsupply = V2_5
MΩ
Vsupply (V2_5)
Temperature Sensor
Accuracy
ADC temperature
measurement offset value
Note
Bit
± 0.25
Rin
Te
Typ
Differential Non-Linearity
ch
Vos
Min
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Vin
Parameter
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Symbol
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± 2%, internally trimmed used as
reference for ADC converter
During conversion only.
@ 25 °C
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Table 22 – ADC Parameters
Symbol
Parameter
ADCTC
Code temperature
coefficient
1.2939
Ratioprescaler
Ratio of Prescaler
0.4
IGPIOCURR
Voltage Compliance of
current source for GPIO
Current Accuracy for
GPIO current source
Typ
0.0
Max
Unit
Note
Temperature change per ADC
Code/°C
LSB
For all low voltage current sinks,
CP_OUT and VBAT2
1.35
V
+1.0µA
V
Current Source for pin GPIO2
-1.0µA
1-15µA
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VGPIOCURR
Min
Transient Parameters (2.5V, 25 ºC)
Conversion Time
27
µs
fc
Clock Frequency
1.0
MHz
All signal are Internally
generated and triggered by
start_conversion
lv
Tc
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ts
Settling Time of S&H
4
µs
The junction temperature (TJUNCTION) can be calculated with the following formula (ADCTEMP_CODE is the adc
conversion result for channel 15 selected by register adc_select = 000100b):
TJUNCTION [°C] = ADCTOFFSET - ADCTC * ADCTEMP_CODE
7.7.1 ADC Registers
ADC_control
Addr: 26h
This register input source selection and initialization of ADC.
Bit Name
Default
5:0
adc_select
ca
Bit
0
Te
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1
6
Access
R/W
Description
Selects input source as ADC input.
000000 (00h) = GPIO0
000001 (01h) = GPIO1
000010 (02h) = GPIO2
000011 (03h) = GPI
000100 (04h) = reserved
000101 (05h) = RGB1
000110 (06h) = RGB2
000111 (07h) = RGB3
001000 (08h) = CURR1
001001 (09h) = CURR2
001010 (0Ah) = CURR30
001011 (0Bh) = CURR31
001100 (0Ch) = CURR32
001101 (0Dh) = CURR33
001110 (0Eh) = CURR41
001111 (0Fh) = CURR42
010000 (10h) = CURR43
010001 (11h) = reserved
010010 (12h) = reserved
010011 (13h) = reserved
010100 (14h) = VBAT2
010101 (15h) = CP_OUT
010110 (16h) = DCDC_FB
010111 (17h) = ADCTEMP_CODE (junction temperature)
011xxx, 1xxxxx = reserved
NA
Writing a 1 into this bit starts one ADC conversion cycle.
7
start_conversion
N/A
W
Notes:
1. See Table ‘ADC Input Ranges, Compliances and Resolution’ for ADC ranges and possible
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GPIO current
Bit
Bit Name
3:1
gpio2_curr
controls the output current of pin GPIO (e.g. for light sensor)
Default
Access Description
000 off
001 2uA
000
R/W
010 4uA
…
111 14uA
ADC_MSB Result
Together with Register 27h, this register contains the results (MSB) of an ADC cycle.
Default
Access Description
Bit
Bit Name
6:0
D9:D3
N/A
R
7
result_not_ready
N/A
R
ADC results register.
Indicates end of ADC conversion cycle.
0 = Result is ready.
1 = Conversion is running.
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Addr: 27h
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ADC_LSB Result
Addr: 28h
Bit
Bit Name
2:0
D2:D0
7:3
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Addr: 2Ch
Together with Register 28h, this register contains the results (LSB) of an ADC cycle
Default
Access Description
N/A
R
ADC result register.
N/A
Figure 31 – ADC Timing Diagrams (TBD: TODO: Increase Sample Time to 16us)
Serial Bus
start_conversion _
1MHz Clock*
Sample Input*
result_not_ready**
D9:0**
Old Data
Data Not Valid
Data Ready
Te
ch
ni
* Internal Signals
** Register Bits
ca
ADC_ON*
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Figure 32 – ADC Pin Connections (TBD: TODO: Add new channels)
RGB1
CURR4
CURR30
gpio_select
CURR2
10-bit SAR
ADC
D9:0
GPIO0
GPIO1
lv
VDD_GPIO
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V2_5
CURR1
7.8
To avoid unwanted supply currents
when an analog signal is applied to a
GPIO pin, the GPIO Input Buffers are
turned off when gpio x_pulls = 11.
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GPIO Input
Buffers
Power-On Reset
The internal reset is controlled by two sources:
VBAT3 Supply
VDD_GPIO Voltage
If one of the voltages is lower than its limit, the internal reset is forced.
Table 23 – Reset Levels
Symbol
ca
The reset levels control the state of all registers. As long as VBAT and VDD_GPIO are below their reset
thresholds, the register contents are set to default. Access by serial interface is possible once the reset
thresholds are exceeded.
Parameter
Min
Typ
Overall Power-On
Reset
2.0
VGPIO_Vdd_TH_RISI
NG
Reset Level for
VDD_GPIO Rising
1.3
VGPIO_vdd_TH_FAL
LING
Reset Level for
VDD_GPIO Falling
1.0
Unit
V
Monitor voltage on V2_5; power-on
reset for all internal functions;
startup is guaranteed with
VBAT>=3.0V
Monitor voltage on pin VDD_GPIO;
rising level.
V
Monitor voltage on pin VDD_GPIO;
falling level.
V
1.5
Note
Te
ch
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VPOR_VBAT
Max
7.9
Temperature Supervision
An integrated temperature sensor provides over-temperature protection for the AS3688. This sensor generates a
flag if the device temperature reaches the overtemperature threshold of 140º. The threshold has a hysteresis to
prevent oscillation effects.
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If the device temperature exceeds the 140º threshold all current sources, the charge pump, the ldo and the dcdc
converter is disabled and the ov_temp flag is set. After decreasing the temperature by 5º (typically) operation is
resumed.
The ov_temp flag can only be reset by first writing a 1 and then a 0 to the (bit rst_ov_temp ).
Bit ov_temp_on = 1 activates temperature supervision.
Table 24 – Overtemperature Detection
Min
Typ
Max
T140
ov_temp Rising Threshold
140
ºC
Thyst
ov_temp Hystersis
5
ºC
7.9.1 Temperature Supervision Registers
Overtemp Control
Bit
Bit Name
0
ov_temp_on
1
ov_temp
2
rst_ov_temp
7:3
Note
This register reads and resets the overtemperature flag.
Default
Access Description
Activates/deactivates device temperature supervision.
Default: Off – all other bits are only valid if this bit is set to 1.
1
W
0 = Temperature supervision is disabled. No reset will be
generated if the device temperature exceeds 140ºC.
1 = Temperature supervision is enabled.
1 = Indicates that the overtemperature threshold has been
reached; this flag is not cleared by an overtemperature
N/A
R
reset. It has to be cleared using bit rst_ov_temp .
The ov_temp flag is cleared by first setting this bit to 1, and
0
R/W
then setting this bit to 0.
N/A
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Addr: 29h
Unit
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Parameter
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Symbol
7.10 Serial Interface
The AS3688 is controlled using serial interface pins CLK and DATA.
ca
7.10.1 Serial Interface Features
Fast Mode Capability (Maximum Clock Frequency is 400 kHz)
ni
7-bit Addressing Mode
ch
Write Formats
− Single-Byte Write
− Page-Write
Te
Read Formats
− Current-Address Read
− Random-Read
− Sequential-Read
DATA Input Delay and CLK Spike Filtering by Integrated RC Components
7.10.2 Device Address Selection
The serial interface address of the AS3688 has the following addresses (factory programmable to 80h,81h or
82h, 83h)
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80h – Write Commands
81h – Read Commands
Figure 33 – Complete Serial Data Transfer
CLK
Start
Condition
7.10.2.1
1-7
8
9
1-7
Address
R/W
ACK
8
9
Data
ACK
1-7
8
9
Data
P
ACK
Stop
Condition
lv
S
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DATA
Serial Data Transfer Formats
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Definitions used in the serial data transfer format diagrams are listed in the following table:
Table 25 – Serial Data Transfer Byte Definitions
Symbol
S
Definition
Start Condition after Stop
R
Notes
1 bit
Repeated Start
R
1 bit
DW
Device Address for Write
R
10000010b (80h).
DR
Device Address for Read
WA
Word Address
R
8 bits
A
Acknowledge
W
1 bit
N
Not Acknowledge
R
1 bit
reg_data
Register Data/Write
R
8 bits
data (n)
Register Data/read
R
1 bit
Stop Condition
R
8 bits
Increment Word Address Internally
R
During Acknowledge
Sr
P
R
10000011b (81h)
ca
WA++
R/W ( AS3688 Slave)
DW
A
ch
S
ni
Figure 34 – Serial Interface Byte Write
WA
A
reg_data
A P
Write Register
WA++
Te
AS3688 (= Slave) receives data
AS3688 (= Slave) transmits data
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Figure 35 – Serial Interface Page Write
S
DW
A
WA
A
reg_data 1
A
reg_data 2
Write Register
WA++
A
…
reg_data n
Write Register
WA++
A P
Write Register
WA++
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AS3688 (= Slave) receives data
AS3688 (= Slave) transmits data
Byte Write and Page Write formats are used to write data to the slave.
lv
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE
state (the bus is free). The device-write address is followed by the word address. After the word address any
number of data bytes can be sent to the slave. The word address is incremented internally, in order to write
subsequent data bytes on subsequent address locations.
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For reading data from the slave device, the master has to change the transfer direction. This can be done either
with a repeated START condition followed by the device-read address, or simply with a new transmission START
followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed
by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can
be read from the slave. The word address is incremented internally.
The following diagrams show the serial read formats supported by the AS3688.
Figure 36 – Serial Interface Random Read
S
DW
A
WA
A Sr
DR
A
data
N P
Read Register
WA++
AS3688 (= slave) receives data
AS3688 (= slave) transmits data
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the
direction after the data transfer from the master.
ca
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The
START condition is followed by the device-write address and the word address.
ch
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In order to change the data direction a repeated START condition is issued on the 1st CLK pulse after the
ACKNOWLEDGE bit of the word address transfer. After the reception of the device-read address, the slave
becomes the transmitter. In this state the slave transmits register data located by the previous received word
address vector. The master responds to the data byte with a NOT ACKNOWLEDGE, and issues a STOP
condition on the bus.
Te
Figure 37 – Serial Interface Sequential Read
S
DW
A
WA
A Sr
DR
A
data 1
A
data 2
...
A
data n
N P
Read Register
WA++
AS3688 (= slave) receives data
AS3688 (= slave) transmits data
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Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsequently
transferred.
In contrast to the Random Read, in a sequential read the transferred register-data bytes are responded by an
acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the
behavior of the word-address counter). To terminate the transmission the master has to send a NOT
ACKNOWLEDGE following the last data byte and subsequently generate the STOP condition.
S
DR
A
data 1
Read Register
WA++
A
data 2
Read Register
WA++
…
A
data n
Read Register
WA++
lv
AS3688 (= slave) receives data
AS3688 (= slave) transmits data
N P
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Figure 38 – Serial Interface Current Address Read
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To keep the access time as small as possible, this format allows a read access without the word address transfer
in advance to the data transfer. The bus is idle and the master issues a START condition followed by the DeviceRead address.
Analogous to Random Read, a single byte transfer is terminated with a NOT ACKNOWLEDGE after the 1st
register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the
data bytes must be responded to with an ACKNOWLEDGE from the master.
For termination of the transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a
subsequent STOP condition.
7.11 Operating Modes
If the voltage on VDD_GPIO is less than 0.3V, the AS3688 is in shutdown mode and its current consumption is
minimized (I(BAT) = ISHUTDOWN) and all internal registers are reset to their default values and the serial interface
is disabled.
If the voltage on VDD_GPIO rises above 1.5V, the AS3688 serial interface is enabled and the AS3688 and the
standby mode is selected.
If the LDO ANA1 is enabled (ldo_ana1_on=1) and ldo_ana1_lpo is set, the AS3688 enters low power mode
(I(BAT) = ILOWPOWER).
ca
The AS3688 is switched automatically from standby mode (I(BAT) = ISTANDBY) or low power mode into normal
mode (I(BAT) = IACTIVE) and back, if one of the following blocks are activated:
LDO ANA1 in normal mode (ldo_ana1_lpo=0)
LDO ANA2
Charge pump
External charge pump
Step up regulator
ch
ni
Any current sink
ADC conversion started
PWM active
Pattern mode active.
Te
If any of these blocks are already switched on (active mode) the internal oscillator is running and a write
instruction to the registers is directly evaluated within 1 internal CLK Cycle (Typ. 1usec)
If all these blocks are disabled (standby mode or lowpower mode), a write instruction to enable these blocks is
delayed by 64 CLK cycles (oscillator will startup, within max 200usec).
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8 Registermap
Table 26 – Registermap
Register Name
Adr
ess
Defa
ult
Reg. control
00h
00
curr12 control
01h
00h
curr rgb control
02h
00h
curr3 control1
03h
00h
curr4 control
04h
00h
GPIO output
05h
00h
gpi_cur
r33_en
gpi_cur
r32_en
gpi_cur
r31_en
gpi_cur
r30_en
gpi_en
gpio2_
out
gpio1_
out
gpio0_o
ut
GPIO signal
06h
00h
gpi_cur
r33_in
gpi_cur
r32_in
gpi_cur
r31_in
gpi_cur
r30_in
gpi_in
gpio2_i
n
gpio1_i
n
gpio0_in
Ldo ana1 voltage
07h
Fuse
Ldo ana2 voltage
08h
Fuse
Curr1 current
09h
00h
curr1_current
Curr2 current
0Ah
00h
curr2_current
Rgb1 current
0Bh
00h
rgb1_current
Rgb2 current
0Ch
00h
rgb2_current
Rgb3 current
0Dh
00h
rgb3_current
Curr3x strobe
0Eh
00h
curr3x_strobe
Curr3x preview
0Fh
00h
curr3x_preview
Curr3x other
10h
00h
curr3x_other
Curr3 strobe
control
11h
00h
b6
Content
b4
b3
b5
ldo_an
a1_lpo
cp_ext_
on
b2
step_u
p_on
curr2_mode
curr32_mode
curr31_mode
curr43_mode
curr42_mode
00h
Curr41 current
13h
00h
ldo_an
a2_pull
d
curr1_mode
rgb1_mode
curr30_mode
curr41_mode
ldo_ana2_voltage
strobe_timing
txmask
_invert
strobe_mode
curr3x_
strobe_
high
curr3x_
ext_ovt
emp
txmask
_on
strobe_ctrl
preview_ctrl
preview
_off_aft
er
strobe
pwm_dim_mode
pwm_m
ode
pattern_delay
pattern_
color
curr41_current
Curr42 current
14h
00h
curr42_current
Curr43 current
15h
00h
curr43_current
ch
ldo_ana
1_on
ldo_ana1_voltage
ca
12h
b0
lv
rgb2_mode
ldo_an
a2_on
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curr33_mode
rgb3_mode
ni
Curr3 control2
pwm_g
pio2
Pwm control
16h
01h
pwm code
17h
00h
Pattern control
18h
00h
Pattern data0
19h
00h
softdim
_patter
n
pattern_data[7:0]
Pattern data1
1Ah
00h
pattern_data[15:8]
Pattern data2
1Bh
00h
pattern_data[23:16]
Pattern data3
1Ch
00h
pattern_data[31:24]
Te
cp_on
b1
al
id
b7
pwm_dim_speed
pwm_code
curr33_
pattern
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curr32_
pattern
curr31_
pattern
curr30_
pattern
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AS3688
Datasheet, Confidential
austriamicrosystems
Register Name
Adr
ess
Defa
ult
Ext. Charge pump
mode
1Dh
00h
GPIO01_control
1Eh
44h
GPIO2_control
1Fh
0Ch
b7
b6
Content
b4
b3
b5
cp_ext_
lowcurr
gpio1_pulls
gpio1_mode
b2
b1
b0
cp_ext_clk
cp_ext_mode
gpio0_pulls
gpio0_mode
gpio2_pulls
gpio2_mode
gpio3_l
ow_cur
r
gpio2_l
ow_cur
r
gpio1_l
ow_cur
r
gpio0_lo
w_curr
20h
00h
DCDC control1
21h
00h
DCDC control2
22h
04h
CP control
23h
00h
cp_aut
o_on
CP mode Switch1
24h
00h
rgb3_o
n_cp
CP mode Switch2
25h
00h
ADC_control
26h
00h
start_c
onversi
on
ADC_MSB result
27h
NA
result_
not_rea
dy
ADC_LSB result
28h
NA
D2
D1
D0
rst_ov_
temp
ov_tem
p
ov_tem
p_on
step_up_vtuning
curr2_p
rot_on
step_up_fb
curr1_p
rot_on
step_u
p_lowc
ur
step_u
p_prot
cp_mode_switchin
g
cp_mode
rgb1_o
n_cp
curr33_
on_cp
curr32_
on_cp
curr31_
on_cp
curr30_
on_cp
curr43_
on_cp
curr42_
on_cp
curr41_
on_cp
curr2_o
n_cp
curr1_o
n_cp
D4
D3
adc_select
D9
D8
D7
D6
D5
Overtemp control
29h
01h
Curr low voltage
status1
2Ah
NA
Curr low voltage
status2
2Bh
NA
Gpio current
2Ch
00h
Adder Current 1
30h
00h
adder_current1 (can be enabled for RGB1, CURR41, CURR1)
Adder Current 2
31h
00h
adder_current2 (can be enabled for RGB2, CURR42, CURR2)
Adder Current 3
32h
00h
adder_current3 (can be enabled for RGB3, CURR43)
Adder Enable 1
33h
00h
rgb3_lo
w_v
pattern
_slow
ch
ni
ca
0
rgb2_lo
w_v
rgb1_lo
w_v
curr33_
low_v
curr32_
low_v
curr31_
low_v
curr30_l
ow_v
ovtemp
_ext
curr43_
low_v
curr42_
low_v
curr41_
low_v
curr2_l
ow_v
curr1_lo
w_v
0
0
curr43_
adder
curr42_
adder
Adder Enable 2
34h
00h
Subtract Enable
35h
00h
ASIC ID1
3Eh
C9h
1
1
0
0
ASIC ID2
3Fh
5xh
0
1
0
1
Te
step_up
_res
cp_clk
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on A
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nt
st
il
rgb2_o
n_cp
skip_fa
st
step_up
_frequ
lv
step_u
p_fb_a
uto
al
id
GPIO driving cap
gpio2_current
curr41_
adder
1
rgb3_a
dder
ext_ov_t
emp_inv
rgb2_a
dder
rgb1_ad
der
curr2_a
dder
curr1_a
dder
sub_en
3
sub_en
2
sub_en
1
0
0
1
revision
Note: If writing to register, write 0 to unused bits
Note: Write to read only bits will be ignored
Note: y yellow color = read only
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Revision 1.1.1 / 20060707
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AS3688
Datasheet, Confidential
austriamicrosystems
9 External Components
Table 27 – External Components List
min
C1
typ
max
100nF
C2
1µF
C3
4.7µF
2.2µF
C4
1µF
4.7µF
Tol
(min)
Rating
(max)
Package
(min)
+/-20%
6.3V
Ceramic, X5R (CREF)
0201
+/-20%
6.3V
Ceramic, X5R (SENSES_P)
0603
+/-20%
6.3V
+/-20%
6.3V
Notes
al
id
Value
Ceramic, X5R (VANA1) (e.g.
Taiyo Yuden
JDK105BJ225MV-F)
Ceramic, X5R (V2_5) (e.g.
Taiyo Yuden
JMK105BJ105KV-F)
Ceramic, X5R (VBAT1,
VBAT2) (e.g. Taiyo Yuden
JMK107BJ225MA-T)
Ceramic, X5R (Charge Pump)
(e.g. Taiyo Yuden
JMK107BJ225MA-T)
Ceramic, X5R (Charge Pump)
(e.g. Taiyo Yuden
JMK107BJ225MA-T)
Ceramic, X5R (Charge Pump
Output) (e.g. Taiyo Yuden
JMK107BJ475MA-T)
capacitor must have at least
1.5µF under all conditions
Ceramic, X5R, X7R (Step Up
DCDC converter output)
(e.g. Taiyo Yuden
TMK316BJ475KF)
Ceramic, X5R (Step Up DCDC
Feedback)
0402
0402
lv
Part Number
2.2µF
+/-20%
6.3V
C6
2.2µF
+/-20%
6.3V
2.2µF
+/-20%
6.3V
2.2µF/
4.7µF
+/-20%
6.3V
2.2µF
+/-20%
25V
1.5nF
+/-20%
25V
15nF
+/-20%
6.3V
2.2µF
+/-20%
6.3V
220kΩ
+/-1%
Bias Resistor
0201
100mΩ
+/-5%
Shunt Resistor
0805
1MΩ
+/-1%
Step Up DC/DC Converter
Voltage Feedback
0201
100kΩ
+/-1%
Step Up DC/DC Converter
Voltage Feedback – not
required for overvoltage
protection
0201
1-10kΩ
+/-20%
Serial DATA line Pullup
resistor
0201
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st
il
C5
C7
C8
C9
C10
C11
ca
C12
R2
ch
R3
ni
R1
Te
R4
R5
R6
L1
10µH
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+/-20%
Revision 1.1.1 / 20060707
Ceramic, X5R (Step Up DCDC
Feedback) – not required for
overvoltage detection
Ceramic, X5R (RGB3/VANA2)
(e.g. Taiyo Yuden
JDK105BJ225MV-F) (only if
VANA2 LDO is used)
0603
0603
0603
0603
1206
0402
0402
0402
Light Sensor – optional
Recommended Type:
Coiltronics SD- 12-100 or
Panasonic ELLSFG100MA
62 - 70
AS3688
Datasheet, Confidential
Part Number
austriamicrosystems
Value
min
typ
max
Tol
(min)
Rating
(max)
Notes
Shottky Diode; Central
Semiconductor (CMDSH2-3)
Philips, STM (BAT760)
CMDSH2-3, BAT760 or similar
D2:D15
LED
As required by application
Q1
Si1304, FDG313N or similar
NMOS switching transistor;
Vishay (Si1304), Fairchild
(FDG313N)
SOD232
SOT-232
Te
ch
ni
ca
am
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nt
st
il
lv
al
id
D1
Package
(min)
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AS3688
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austriamicrosystems
10 Pinout and Packaging
10.1 Pin Description
Table 28 – Pinlist QFN32
Name
1
GPI
Type
Description
2
C2_N
AIO
3
VBAT2
S
4
C2_P
AIO
Charge Pump flying capacitor; connect a ceramic capacitor of 2.2µF (±20%) to this
pin.
5
CP_OUT
AIO
Output voltage of the Charge Pump; connect a ceramic capacitor of 2.2µF (±20%) .
6
C1_P
7
VBAT1
8
C1_N
9
CURR33
10
CURR32
11
CURR31
12
CURR30
13
GPIO2
14
VDD_GPIO
15
GPIO1
16
GPIO0
17
CLK
18
DATA
19
CURR1
20
CURR2
21
VANA1
AO
22
VBAT3
S
DIO3 General purpose input
al
id
Pin
am
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st
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lv
Charge Pump flying capacitor; connect a ceramic capacitor of 2.2µF (±20%) to this
pin.
Charge Pump supply pad.
Note:Always connect this pin to VBAT.
AIO
AIO
AIO
Charge Pump flying capacitor; connect a ceramic capacitor of 2.2µF (±20%) to this
pin.
Supply pad for Charge Pump.
Note:Always connect this pin to VBAT.
Charge Pump flying capacitor; connect a ceramic capacitor of 2.2µF (±20%) to this
pin.
AI
Analog current sink input (intended for LED flash).
AI
Analog current sink input (intended for LED flash).
AI
Analog current sink input (intended for LED flash).
AI
Analog current sink input (intended for LED flash).
DIO3 General purpose input/output.
S
Supply pad for GPIOs and serial interface.
DIO3 General purpose input/output, ADC input.
DIO3 General purpose input/output, ADC input.
DI3
Clock input for serial interface.
ca
DIO3 Serial interface data input/output.
AI_HV Analog current sink input (intended for LED).
ch
ni
AI_HV Analog current sink input (intended for LED).
Output voltage of the Analog LDO VANA1. Connect a ceramic capacitor of 1µF
(±20%) or 2.2µF (+100%/-50%).
Supply pad; always connect to VBAT.
RGB Current sink input
AI (AO) Alternative function: Output voltage of the Analog LDO VANA2. Connect a ceramic
capacitor of 1µF (±20%) or 2.2µF (+100%/-50%) if this ldo is used.
Negative sense input of shunt resistor for Step Up DC/DC Converter.
SENSE_N
24
AIO
(CURR43)
Alternative function: General purposed current sink
Positive sense input of shunt resistor for Step Up DC/DC Converter.
SENSE_P
25
AIO
(CURR42)
Alternative function: General purposed current sink
26 DCDC_GATE
AO DCDC gate driver.
RGB3
(VANA2)
Te
23
27
RGB1
AI
RGB Current sink input
28
RGB2
AI
RGB Current sink input
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AS3688
Datasheet, Confidential
austriamicrosystems
Table 28 – Pinlist QFN32
Pin
Name
29
DCDC_FB
(CURR41)
Type
Description
AI
30
V2_5
AO3
31
CREF
AIO
Bypass capacitor for the internal voltage reference; always connect a capacitor of
100nF.
Caution: Do not load this pin.
32
RBIAS
AIO
External resistor; always connect a resistor of 220kΩ (±1%) to ground.
Caution: Do not load this pin.
33
VSS
VSS
Ground pad (QFN32: exposed paddle).
am
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nt
st
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lv
al
id
DCDC feedback. Connect to resistor string.
Alternative function: General purposed current sink
Output voltage of the Low-Power LDO; always connect a ceramic capacitor of 1µF
(±20%) or 2.2µF (+100%/-50%).
Caution: Do not load this pin during device startup.
Table 29 – Pin Type Definitions
Type
DI
DI3
DO
DIO
DIO3
OD
AIO
AI
AI_HV
AO
AO3
S
Digital Input
3.3V Digital Input
Digital Output
Digital Input/Output
3.3V Digital Input/Output
Open Drain (the device can only pulldown this type of pin)
Analog Pad
Analog Input
High-Voltage (15V) Pin
Analog Output (5V)
Analog Output (3.3V)
Supply Pad
Ground Pad
Te
ch
ni
ca
GND
Description
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AS3688
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10.2 Package Drawings and Markings
ch
ni
ca
am
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nt
st
il
AYWWIZZ
AS3688
lv
al
id
Figure 39 – QFN 32 – 5x5mm with Exposed Paddle
Te
JEDEC Package Outline Standard: MO-220 VHHD-5 – Lead Finish: 100% Sn “Matte Tin”.
Marking: AYWWIZZ
A: Pb-Free Identifier
Y: Last Digit of Manufacturing Year
WW: Manufacturing Week
I: Plant Identifier
ZZ: Traceability Code
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AS3688
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Te
ch
ni
ca
am
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st
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lv
al
id
Figure 40 – QFN 32 – Detail Diagram
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AS3688
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austriamicrosystems
11 Ordering Information
Part Number
AS3688-EAA-Z
Package Type
Delivery Form*
Description
QFN 32
Tape and Reel
AS3688-EBA-Z
QFN 32
Tube
5 x 5mm, Pitch = 0.5mm
5 x 5mm, Pitch = 0.5mm
AS3688B-EAA-Z
QFN 32
AS3688B-EBA-Z
QFN 32
AS3688B-PDR-Z
Tape and Reel 5 x 5mm, Pitch = 0.5mm; version with
CURR42 and CURR43 current
Tube
source but without dcdc converter
al
id
AS3688-PDR-Z
Where:
P = Package Type:
E = QFN 5 x 5 x 1mm
D = Delivery Form:
A = Tape and Reel
B = Tube
R = Revision
Z = Pb-Free IC Package
Te
ch
ni
ca
am
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on A
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nt
st
il
* Dry-pack sensitivity level = 3 in accordance with IPC/JEDEC J-STD-033A.
lv
Device ID
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AS3688
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Copyright
Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, AustriaEurope. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted,
merged, translated, stored, or used without the prior written consent of the copyright owner.
al
id
All products and companies mentioned are trademarks of their respective companies.
Disclaimer
am
lc s
on A
te G
nt
st
il
lv
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions
appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time
and without notice. Therefore, prior to designing this product into a system, it is necessary to check with
austriamicrosystems AG for current information. This product is intended for use in normal commercial
applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not
recommended without additional processing by austriamicrosystems AG for each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not
limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect,
special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise
or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters:
ni
ca
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692
[email protected]
For Sales Offices, Distributors and Representatives, please visit:
Te
ch
www.austriamicrosystems.com
austriamicrosystems
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– a leap ahead
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AS3688
Datasheet, Confidential
Te
ch
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am
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st
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austriamicrosystems
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