GD25Q64B GD25Q64B DATASHEET DATASHEET 44 - 1 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B Contents 1. FEATURES ..................................................................................................................................................... 44 2. GENERAL DESCRIPTION............................................................................................................................. 5 5 3. MEMORY ORGANIZATION ........................................................................................................................... 77 4. DEVICE OPERATION..................................................................................................................................... 88 5. DATA PROTECTION ...................................................................................................................................... 99 6. STATUS REGISTER..................................................................................................................................... 11 11 7. COMMANDS DESCRIPTION....................................................................................................................... 12 13 8. 7.1. WRITE ENABLE (WREN) (06H)................................................................................................................................ 15 16 7.2. WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 16 15 7.3. READ STATUS REGISTER (RDSR) (05H OR 35H) .......................................................................................................... 15 16 7.4. WRITE STATUS REGISTER (WRSR) (01H) ................................................................................................................... 16 17 7.5. READ DATA BYTES (READ) (03H)............................................................................................................................. 16 17 7.6. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).............................................................................................. 17 18 7.7. DUAL OUTPUT FAST READ (3BH).............................................................................................................................. 17 18 7.8. QUAD OUTPUT FAST READ (6BH) ............................................................................................................................. 18 19 7.9. DUAL I/O FAST READ (BBH) .................................................................................................................................... 18 19 7.10. QUAD I/O FAST READ (EBH) ................................................................................................................................... 19 20 7.11. QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 20 21 7.12. PAGE PROGRAM (PP) (02H).................................................................................................................................... 21 22 7.13. QUAD PAGE PROGRAM (32H).................................................................................................................................. 22 23 7.14. SECTOR ERASE (SE) (20H)....................................................................................................................................... 23 24 7.15. 25 32KB BLOCK ERASE (BE) (52H) ............................................................................................................................... 24 7.16. 25 64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 24 7.17. CHIP ERASE (CE) (60/C7H)..................................................................................................................................... 25 26 7.18. DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 25 26 7.19. RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH)............................. 26 27 7.20. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 27 28 7.21. READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 27 28 7.22. HIGH PERFORMANCE MODE (HPM) (A3H)................................................................................................................ 28 29 7.23. CONTINUOUS READ MODE RESET (CRMR) (FFH)........................................................................................................ 28 29 7.24. PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 29 30 7.25. PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 29 30 7.26. ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 30 31 7.27. PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 30 31 7.28. READ SECURITY REGISTERS (48H) ............................................................................................................................. 31 32 ELECTRICAL CHARACTERISTICS ........................................................................................................... 32 34 8.1. 34 POWER-ON TIMING ........................................................................................................................................... 32 8.2. INITIAL DELIVERY STATE..................................................................................................................................... 32 34 2 44 - 2 Rev.1.1 GD25Q64BxIGx Uniform sector dual and quad serial flash Uniform Sector Dual and Quad Serial Flash GD25Q64B 8.3. DATA RETENTION AND ENDURANCE .................................................................................................................32 34 8.4. LATCH UP CHARACTERISTICS .............................................................................................................................32 34 8.5. ABSOLUTE MAXIMUM RATINGS ........................................................................................................................33 35 8.6. CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................................33 35 8.7. DC CHARACTERISTIC ..........................................................................................................................................34 36 8.8. AC CHARACTERISTICS.........................................................................................................................................35 37 ORDERING INFORMATION ........................................................................................................................ 37 39 9. 10. PACKAGE INFORMATION ...................................................................................................................... 38 40 10.1. PACKAGE SOP8 208MIL ........................................................................................................................................38 40 10.2. PACKAGE TSOP8 208MIL ......................................................................................................................................39 41 10.3. PACKAGE DIP8 300MIL .........................................................................................................................................40 42 10.4. PACKAGE WSON8 (6*5MM)...................................................................................................................................41 43 10.5. PACKAGE WSON8 (8*6MM)...................................................................................................................................42 44 10.6. PACKAGE TFBGA-24BALL (6*4 BALL ARRAY) ............................................................................................................43 45 10.7. PACKAGE SOP16 300MIL ......................................................................................................................................44 46 44 3- 3 Rev.1.1 Uniform Sector Dual and Quad Serial Flash GD25Q64B Uniform sector dual and quad serial flash GD25Q64BxIGx 1. FEATURES � 64M-bit Serial Flash � Program/Erase Speed -8192K-byte -Page Program time: 0.7ms typical -256 bytes per programmable page -Sector Erase time: 100ms typical Standard, Dual, Quad SPI -Chip Erase time: 30s typical -Block Erase time: 0.2/0.4s typical � -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# -Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# � -Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 Flexible Architecture -Sector of 4K-byte -Block of 32/64k-byte � High Speed Clock Frequency � Low Power Consumption -120MHz for fast read with 30PF load -20mA maximum active current -Dual I/O Data transfer up to 240Mbits/s -5uA maximum power down current -Quad I/O Data transfer up to 480Mbits/s � Advanced security Features(1) -16-Bit Customer ID � Software/Hardware Write Protection -4*256-Byte Security Registers With OTP Lock -Write protect all/portion of memory via software -Enable/Disable protection with WP# Pin � -Top or Bottom, Sector or Block selection � Single Power Supply Voltage -Full voltage range:2.7~3.6V Minimum 100,000 Program/Erase Cycles � Package Information -SOP16 (300mil) � Typical 10 years Data Retention -SOP8 (208mil) -TSOP8 (208mil) -DIP8 (300mil) -WSON8 (6*5mm) -WSON8 (8*6mm) -TFBGA24 (6*4 ball array) 4 44 - 4 Rev.1.1 Uniform Sector Dual and Quad Serial Flash GD25Q64B Uniform sector dual and quad serial flash GD25Q64BxIGx 2. GENERAL DESCRIPTION The GD25Q64B (64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s. CONNECTION DIAGRAM 8 VCC 7 HOLD# 8 VCC CS# 1 7 HOLD# SO 2 3 6 SCLK WP# 3 6 SCLK 4 5 SI VSS 4 5 CS# 1 SO 2 WP# VSS Top View Top View SI 8–LEAD WSON 8–LEAD SOP/DIP Top View 4 NC VCC WP# HOLD# NC NC NC VSS NC SI NC NC NC SCLK CS# SO NC NC HOLD# 1 16 SCLK VCC 2 15 SI NC 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC CS# 7 10 VSS SO 8 9 WP# 3 2 1 NC NC NC NC NC NC A B C D E F 24-BALL TFBGA Top View 16-LEAD SOP PIN DESCRIPTION Pin Name I/O Description CS# I Chip Select Input SO (IO1) I/O Data Output (Data Input Output 1) WP# (IO2) I/O Write Protect Input (Data Input Output 2) Ground VSS SI (IO0) I/O Data Input (Data Input Output 0) SCLK I Serial Clock Input HOLD# (IO3) I/O Hold Input (Data Input Output 3) VCC Power Supply 5 44 - 5 Rev.1.1 GD25Q64BxIGx Uniform sector dual and quad serial flash Uniform Sector Dual and Quad Serial Flash GD25Q64B BLOCK DIAGRAM Write Control Logic Status Register HOLD#(IO3) SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP#(IO2) Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Byte Address Latch/Counter 44 6 -6 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 3. MEMORY ORGANIZATION GD25Q64B Each device has Each block has Each sector has Each page has 8M 64/32K 4K 256 bytes 32K 256/128 16 - pages 2048 16/8 - - sectors 128/256 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25Q64B 64K Bytes Block Sector Architecture Block 127 126 …… …… 2 1 0 Sector Address range 2047 7FF000H 7FFFFFH …… …… …… 2032 7F0000H 7F0FFFH 2031 7EF000H 7EFFFFH …… …… …… 2016 7E0000H 7E0FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 7 44 - 7 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 4. DEVICE OPERATION SPI Mode Standard SPI The GD25Q64B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q64B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q64B supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure 1. Hold Condition CS# SCLK HOLD# HOLD HOLD 8 44 - 8 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 5. DATA PROTECTION The GD25Q64B provide the following data protection methods: � Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) � Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory array that can be read but not change. � Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits. � Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Table1.0 GD25Q64B Protected area size (CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 126 to 127 7E0000H-7FFFFFH 128KB Upper 1/64 0 0 0 1 0 124 to 127 7C0000H-7FFFFFH 256KB Upper 1/32 0 0 0 1 1 120 to 127 780000H-7FFFFFH 512KB Upper 1/16 0 0 1 0 0 112 to 127 700000H-7FFFFFH 1MB Upper 1/8 0 0 1 0 1 96 to 127 600000H-7FFFFFH 2MB Upper 1/4 0 0 1 1 0 64 to 127 400000H-7FFFFFH 4MB Upper 1/2 0 1 0 0 1 0 to 1 000000H-01FFFFH 128KB Lower 1/64 0 1 0 1 0 0 to 3 000000H-03FFFFH 256KB Lower 1/32 0 1 0 1 1 0 to 7 000000H-07FFFFH 512KB Lower 1/16 0 1 1 0 0 0 to 15 000000H-0FFFFFH 1MB Lower 1/8 0 1 1 0 1 0 to 31 000000H-1FFFFFH 2MB Lower 1/4 0 1 1 1 0 0 to 63 000000H-3FFFFFH 4MB Lower 1/2 X X 1 1 1 0 to 127 000000H-7FFFFFH 8MB ALL 1 0 0 0 1 127 7FF000H-7FFFFFH 4KB Top Block 1 0 0 1 0 127 7FE000H-7FFFFFH 8KB Top Block 1 0 0 1 1 127 7FC000H-7FFFFFH 16KB Top Block 1 0 1 0 X 127 7F8000H-7FFFFFH 32KB Top Block 1 0 1 1 0 127 7F8000H-7FFFFFH 32KB Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block 1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block 1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block 1 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block 9 44 - 9 Rev.1.1 GD25Q64BxIGx Uniform sector dual and quad serial flash Uniform Sector Dual and Quad Serial Flash GD25Q64B Table1.1 GD25Q64B Protected area size (CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 ALL 000000H-7FFFFFH ALL ALL 0 0 0 0 1 0 to 125 000000H-7DFFFFH 8064KB Lower 63/64 0 0 0 1 0 0 to 123 000000H-7BFFFFH 7936KB Lower 31/32 0 0 0 1 1 0 to 119 000000H-77FFFFH 7680KB Lower 15/16 0 0 1 0 0 0 to 111 000000H-6FFFFFH 7MB Lower 7/8 0 0 1 0 1 0 to 95 000000H-5FFFFFH 6MB Lower 3/4 0 0 1 1 0 0 to 63 000000H-3FFFFFH 4MB Lower 1/2 0 1 0 0 1 2 to 127 020000H-7FFFFFH 8064KB Upper 63/64 0 1 0 1 0 4 to 127 040000H-7FFFFFH 7936KB Upper 31/32 0 1 0 1 1 8 to 127 080000H-7FFFFFH 7680KB Upper 15/16 0 1 1 0 0 16 to 127 100000H-7FFFFFH 7MB Upper 7/8 0 1 1 0 1 32 to 127 200000H-7FFFFFH 6MB Upper 3/4 0 1 1 1 0 64 to 127 400000H-7FFFFFH 4MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 to 127 000000H-7FEFFFH 8188KB L-2047/2048 1 0 0 1 0 0 to 127 000000H-7FDFFFH 8184KB L-1023/1024 1 0 0 1 1 0 to 127 000000H-7FBFFFH 8176KB L-511/512 1 0 1 0 X 0 to 127 000000H-7F7FFFH 8160KB L-255/256 1 0 1 1 0 0 to 127 000000H-7F7FFFH 8160KB L-255/256 1 1 0 0 1 0 to 127 001000H-7FFFFFH 8188KB U-2047/2048 1 1 0 1 0 0 to 127 002000H-7FFFFFH 8184KB U-1023/1024 1 1 0 1 1 0 to 127 004000H-7FFFFFH 8176KB U-511/512 1 1 1 0 X 0 to 127 008000H-7FFFFFH 8160KB U-255/256 1 1 1 1 0 0 to 127 008000H-7FFFFFH 8160KB U-255/256 44 10- 10 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 6. STATUS REGISTER S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP Reserved Reserved Reserved LB QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, BP0) bits and CMP are all 0 or all 1. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. SRP1 SRP0 #WP Status Register 0 0 X Software Protected 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X Power Supply Lock-Down(1) 1 1 X One Time Program Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) WP#=0, the Status Register locked and can not be written to. WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and can not be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 11 44 - 11 Rev.1.1 GD25Q64BxIGx Uniform sector dual and quad serial flash Uniform Sector Dual and Quad Serial Flash GD25Q64B QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground) LB bit. The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS bit The SUS bit is a read only bit in the status register (S15 ) that is set to 1 after executing an Erase/Program Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, power-up cycle. Uniform Sector Dual and Quad Serial Flash GD25Q64B 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands Command Name Byte 1 Byte 2 Write Enable Write Disable Read Status Register Read Status Register-1 Write Status Register Read Data Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read 06H 04H 05H 35H 01H 03H 0BH 3BH (S7-S0) (S15-S8) (S7-S0) A23-A16 A23-A16 A23-A16 BBH A23-A8(2) 6BH A23-A16 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) (S15-S8) A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy 44 A7-A012 M7-M0(2) A15-A8 12 (D7-D0)(1) (5) (3) A7-A0 (Next byte) (D7-D0) (D7-D0)(1) (continuous) (continuous) (continuous) Rev.1.1 (continuous) dummy (D7-D0)(3) (continuous) Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the GD25Q64BxIGx when the number of clock pulses after CS# being command is rejected, and is not executed. That is CS# mustsector driven highdual Uniform and quad serial flash driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands Command Name Byte 1 Byte 2 Byte 3 Byte 4 Write Enable 06H Write Disable 04H Read Status Register 05H (S7-S0) Read Status Register-1 35H (S15-S8) Write Status Register 01H (S7-S0) (S15-S8) Read Data 03H A23-A16 A15-A8 Fast Read 0BH A23-A16 A15-A8 Dual Output 3BH A23-A16 A15-A8 Fast Read Dual I/O BBH A23-A8(2) A7-A0 Fast Read M7-M0(2) Quad Output 6BH A23-A16 A15-A8 Fast Read Quad I/O EBH A23-A0 dummy(5) (4) Fast Read M7-M0 Quad I/O Word E7H A23-A0 dummy(6) (7) (4) Fast Read M7-M0 Continuous Read Reset FFH Page Program 02 H A23-A16 A15-A8 Quad Page Program 32H A23-A16 A15-A8 Sector Erase 20H A23-A16 A15-A8 Block Erase(32K) 52H A23-A16 A15-A8 Block Erase(64K) D8H A23-A16 A15-A8 Chip Erase C7/60 H Program/Erase 75H Suspend Program/Erase Resume 7AH Deep Power-Down B9H Release From Deep ABH dummy dummy Power-Down, AndUniform Sector Read Device ID Dual and Quad Serial Flash Release From Deep ABH Power-Down Manufacturer/ 90H dummy dummy Device ID 13 High Performance Mode A3H dummy dummy Read Identification (MID7(JDID159FH MID0) JDID8) Erase Security 44H A23-A16 A15-A8 Registers(8) Program Security 42H A23-A16 A15-A8 Registers(8) Read Security 48H A23-A16 A15-A8 Registers(8) NOTE: 1. Dual Output data Byte 5 Byte 6 n-Bytes (continuous) (continuous) A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy (Next byte) (D7-D0) (D7-D0)(1) (D7-D0)(1) A7-A0 (continuous) (continuous) (continuous) (continuous) dummy (D7-D0)(3) (continuous) (D7-D0)(3) (continuous) (D7-D0)(3) (continuous) A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) (D7-D0)(3) dummy (DID7DID0) 00H (MID7MID0) Next byte (continuous) GD25Q64B (DID7DID0) dummy (JDID7JDID0) A7-A0 (continuous) (continuous) A7-A0 (D7-D0) (D7-D0) A7-A0 dummy (D7-D0) IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) 44 - 13 Rev.1.1 High Performance Mode Read Identification Erase Security Registers(8) Program Security Registers(8) Read Security Registers(8) NOTE: 1. Dual Output data A3H 44H dummy (MID7MID0) A23-A16 dummy (JDID15JDID8) A15-A8 dummy (JDID7JDID0) A7-A0 42H A23-A16 A15-A8 A7-A0 (D7-D0) (D7-D0) 48H A23-A16 A15-A8 A7-A0 dummy (D7-D0) 9FH (continuous) GD25Q64BxIGx Uniform sector dual and quad serial flash IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Fast Word Read Quad I/O Data: the lowest address bit must be 0. 8. Security Registers Address: Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address; Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address; Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address; Security Uniform Register3: A23-A16=00H, Sector A15-A8=03H, A7-A0= Byte Address. Dual and Quad Serial Flash GD25Q64B 14 Table of ID Definitions: GD25Q64B Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH C8 40 17 90H C8 16 ABH 16 44 - 14 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low � sending the Write Enable command � CS# goes high. Figure 2. Write Enable Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low�Sending the Write Disable command �CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Figure 3. Write Disable Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 Command SI 04H High-Z SO 7.3. Read Status Register (RDSR) (05H or 35H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8. Figure 4. Read Status Register Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Command 05H or 35H High-Z 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 MSB 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 7 MSB 16 44 - 15 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 7.4. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure 5. Write Status Register Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 Command SI 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Status Register in 01H 7 6 MSB SO 5 4 3 2 1 0 15 14 13 12 11 10 9 8 High-Z 7.5. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 6. Read Data Bytes Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 24-bit address Command 03H High-Z 28 29 30 31 32 33 34 35 36 37 38 39 9 10 23 22 21 3 2 1 0 MSB MSB 17 44 - 16 7 6 5 Data Out1 4 3 2 1 Data Out2 0 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 7.6. Read Data Bytes at Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 7. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 Command SI 28 29 30 31 24-bit address 0BH 3 23 22 21 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI Dummy Byte 7 6 5 4 3 2 1 0 Data Out1 5 4 3 2 7 6 MSB SO 1 0 Data Out2 7 6 5 MSB 7.7. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 8. Dual Output Fast Read Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 Command 28 29 30 31 24-bit address 3BH 23 22 21 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dummy Clocks 6 0 6 Data Out2 Data Out1 7 5 3 1 7 5 3 1 MSB MSB 7 18 4 2 44 - 17 0 6 4 2 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 7.8. Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 9. Quad Output Fast Read Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 Command SI(IO0) 24-bit address 6BH 23 22 21 SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z CS# SCLK 28 29 30 31 3 2 1 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy Clocks SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 7.9. Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read command. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. 19 44 - 18 Rev.1.1 GD25Q64BxIGx Uniform SectorUniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B Figure 10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) CS# 1 0 SCLK 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 7 Command SI(IO0) BBH SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 6 5 3 1 7 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure 11. Dual I/O Fast Read Sequence Diagram (M7-0= AXH) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 7.10. Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Quad I/O Fast Read command. 20 44 - 19 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure 12. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) CS# 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 0 SCLK 1 2 3 4 5 6 7 Command SI(IO0) EBH A23-16 A15-8 A7-0 Dummy M7-0 Byte1 Byte2 Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0= AXH) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 7.11. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3h) must be executed once, prior to the Quad I/O Word Fast Read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. 21 44 - 20 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure 14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK 8 9 10 11 12 13 14 15 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 7.12. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI � at least 1 byte data on SI � CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page 22 44 - 21 Rev.1.1 Uniform sector dual and quad serial flash GD25Q64BxIGx Uniform Sector Dual and Quad Serial Flash GD25Q64B Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is not executed. Figure 16. Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 24-bit address 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 MSB 2079 2078 2077 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2076 CS# 2075 MSB 2074 02H Data Byte 1 2073 Command SI 28 29 30 31 32 33 34 35 36 37 38 39 2072 SCLK SCLK SI Data Byte 3 Data Byte 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB Data Byte 256 7 6 5 4 3 2 1 0 MSB 7.13. Quad Page Program (32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO pins. The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. 23 - 22 44 Rev.1.1 Uniform sector dual and quad serial flash GD25Q64BxIGx Uniform Sector Dual and Quad Serial Flash GD25Q64B A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is not executed. Figure 17. Quad Page Program Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 Command SI(IO0) 28 29 30 31 32 33 34 35 36 37 38 39 24-bit address 3 Byte1 Byte2 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 539 540 541 542 543 1 538 2 537 32H 23 22 21 MSB SO(IO1) SCLK 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Byte11Byte12 536 CS# Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 7.14. Sector Erase (SE) (20H) The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low � sending Sector Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table1.0&1.1) is not executed. 24 44 - 23 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B Figure 18. Sector Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 29 30 31 24 Bits Address Command SI 9 23 22 MSB 20H 2 1 0 7.15. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low � sending 32KB Block Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.0&1.1) is not executed. Figure 19. 32KB Block Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 52H 8 9 29 30 31 24 Bits Address 23 22 MSB 2 1 0 7.16. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low � sending 64KB Block Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.0&1.1) is not executed. 25 44 - 24 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B Figure 20. 64KB Block Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB D8H 2 1 0 7.17. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low � sending Chip Erase command � CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits and CMP are all 0 or all 1. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure 21. Chip Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 60H or C7H 7.18. Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low � sending Deep Power-Down command � CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep 26 44 - 25 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 22. Deep Power-Down Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 Command SI tDP 7 Stand-by mode Deep Power-down mode B9H 7.19. Release from Deep Power-Down Or High Performance Mode And Read Device ID (RDI) (ABH) The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the GD25Q64B is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 23. Release Power-Down Or High Performance Mode Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 t RES1 Command ABH Deep Power-down mode 27 44 - 26 Stand-by mode Rev.1.1 Uniform sector dual and quad serial flash GD25Q64BxIGx Uniform Sector Dual and Quad Serial Flash GD25Q64B Figure 24. Release Power-Down/Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 SCLK Command SI SO t RES2 3 Dummy Bytes 2 23 22 ABH 1 0 MSB High-Z MSB 7 Device ID 5 4 3 2 6 1 0 Deep Power-down Mode Stand-by Mode 7.20. Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 25. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 SCLK 1 2 4 5 6 7 8 9 10 Command SI 28 29 30 31 24-bit address 90H 3 23 22 21 2 1 0 High-Z SO CS# 3 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO 7 6 Manufacturer ID 5 4 3 2 1 MSB Device ID 0 7 6 5 4 3 2 1 0 MSB 7.21. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is Uniform Sectorstored in the memory, being shifted out on Serial Data Output, each bit being followed by the 24-bit device identification, Dual Quad Serial Flash sequence is shown in Figure26. The GD25Q64B shifted out during the fallingand edge of Serial Clock. The command Read Identification execute commands. (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device 26. ReadMode, Identification Sequence Diagramso that it can receive, decode and is put in the Standby Mode. OnceFigure in the Standby the deviceIDwaits to be selected, CS# SCLK 0 1 2 3 4 5 28 - 27 44 6 7 8 Rev.1.1 9 10 11 12 13 14 15 Uniform Sector sector dual and quad serialGD25Q64B flash GD25Q64BxIGx Dual and QuadUniform Serial Flash execute commands. Figure 26. Read Identification ID Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 9 10 11 12 13 14 15 7 6 7 9FH SI Command SO MSB CS# Manufacturer ID 5 4 3 2 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI 7 SO 6 5 4 3 2 1 Memory Type JDID15-JDID8 MSB 0 7 6 MSB 5 4 3 2 Capacity JDID7-JDID0 1 0 7.22. High Performance Mode (HPM) (A3H) The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of internal charge pumps so the voltages required for accessing the flash memory array are readily available. The command sequence: CS# goes low�Sending A3H command� Sending 3-dummy byte�CS# goes high. See Figure27. After the HPM command is executed, the device will maintain a slightly higher standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby current (Icc1). In addition, Write Enable command (06H) and Power-Down command (B9H) will also release the device from HPM mode back to standard SPI standby state. Figure 27. High Performance Mode Sequence Diagram CS# SCLK 0 1 SI 2 3 4 5 Command A3H 6 7 8 9 29 30 31 t HPM 3 Dummy Bytes 23 22 MSB 2 1 0 SO High Performance Mode 7.23. Continuous Read Mode Reset (CRMR) (FFH) The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the BBH/EBH/E7H command code. Because the GD25Q64B has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q64B will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in Figure28. 29 44 - 28 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B Figure 28. Continuous Read Mode Reset Sequence Diagram Mode Bit Reset for Quad/Dual I/O CS# 0 1 2 3 4 5 6 7 SCLK SI(IO0) FFH SO(IO1) Don`t Care WP#(IO2) Don`t Care HOLD#(IO3) Don`t Care 7.24. Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H) and Erase Security Registers (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command are not allowed during Program/Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared form 1 to 0 within “tsus” and the SUS bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure29. Figure 29. Program/Erase Suspend Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 tSUS Command 75H High-Z Accept read command 7.25. Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS bit equal to 1 and the WIP bit equal to 0. After issued the SUS bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure30. 30 44 - 29 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B Figure 30. Program/Erase Resume Sequence Diagram CS# 1 0 SCLK 2 3 4 5 6 7 Command SI 7AH SO Resume Erase/Program 7.26. Erase Security Registers (44H) The GD25Q64B provides four 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low � sending Erase Security Registers command � CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address A23-A16 A15-A10 A9-A0 Security Registers 00000000 000000 Don’t Care Figure 31. Erase Security Registers command Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 44H 8 9 29 30 31 24 Bits Address 23 22 MSB 2 1 0 7.27. Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. 31 44 - 30 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address A23-A16 A15-A8 A7-A0 Security Registers 0 00H 00H Byte Address Security Registers 1 00H 01H Byte Address Security Registers 2 00H 02H Byte Address Security Registers 3 00H 03H Byte Address Figure 32. Program Security Registers command Sequence Diagram CS# 5 6 7 8 9 10 Command 24-bit address 3 23 22 21 2 Data Byte 1 1 0 7 6 5 4 3 2 1 2078 42H 2079 SI 28 29 30 31 32 33 34 35 36 37 38 39 2077 4 2075 3 2076 2 1 0 0 MSB MSB 2072 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 1 2074 0 SCLK SCLK SI Data Byte 2 7 6 5 4 3 Data Byte 3 2 1 0 6 7 5 4 3 Data Byte 256 2 1 0 7 MSB MSB 6 5 4 3 2 MSB 7.28. Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high. Address Uniform SectorA23-A16 Security Registers Dual and Quad00000000 Serial Flash A15-A10 A9-A0 Address GD25Q64B 000000 Figure 33. Read Security Registers command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 Command SI 9 10 28 29 30 31 24-bit address 48H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dummy Byte 7 6 5 4 3 2 1 0 7 6 MSB 32 Data Out1 5 4 3 2 44 - 31 1 Data Out2 0 7 6 5 MSB Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Vcc(max) Program, Erase and Write command are ignored Chip Selection is not allowed Vcc(min) VWI tVSL Reset State Read command is allowed Device is fully accessible tPUW Time Table3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC(min) To CS# Low 10 us tPUW Time Delay from VCC(min) To Write Instruction 1 10 ms VWI Write Inhibit Voltage 1 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3. DATA RETENTION AND ENDURANCE Parameter Minimum Pattern Data Retention Time Erase/Program Endurance Test Condition Min Units 150� 10 Years 125� 20 Years -40 to 85� 100K Cycles 8.4. LATCH UP CHARACTERISTICS Parameter Min Input Voltage Respect To VSS On I/O Pins VCC Current 34 44 - 32 Max -1.0V VCC+1.0V -100mA 100mA Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 8.5. ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 � Storage Temperature -65 to 150 � Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V -0.5 to 4.0 V VCC 0.8VCC Input timing reference level 0.7VCC 0.3VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are<5ns 8.6. CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 Input Rise And Fall time pF 5 ns Input Pulse Voltage 0.2VCC to 0.8VCC V Input Timing Reference Voltage 0.3VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure 34. Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 35 44 - 33 20ns Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 8.7. DC CHARACTERISTIC (T= -40�~85�, VCC=2.7~3.6V) Symbol Parameter Test Condition Min. Typ Max. Unit. ILI Input Leakage Current ±2 �� ILO Output Leakage Current ±2 �� ICC1 Standby Current 1 5 �� 1 5 �� 15 20 mA 13 18 mA CS#=VCC, VIN=VCC or VSS ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS CLK=0.1VCC / 0.9VCC at 120MHz, ICC3 Operating Current (Read) Q=Open(*1 I/O) CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) ICC4 Operating Current (PP) CS#=VCC 10 mA ICC5 Operating Current(WRSR) CS#=VCC 10 mA ICC6 Operating Current (SE) CS#=VCC 10 mA ICC7 Operating Current (BE) CS#=VCC 10 mA I CC8 High Performance Current 800 uA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL =1.6mA 0.4 V VOH Output High Voltage IOH =-����� 600 VCC-0.2 36 44 - 34 V Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 8.8. AC CHARACTERISTICS (T= -40�~85�, VCC=2.7~3.6V, CL=30pf) Symbol fC Parameter Min. Serial Clock Frequency For: FAST_READ(0BH), Dual Output(3BH) Typ. Max. Unit. 120 MHz 120 MHz DC. 80 MHz DC. 80 MHz DC. Serial Clock Frequency For: Dual I/O(BBH), fC1 Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O DC. 80 With High Performance Mode) Serial Clock Frequency For: Dual I/O(BBH), fC2 Quad I/O(EBH) (Dual I/O & Quad I/O Without High Performance Mode) fR Serial Clock Frequency For: Read(03H) tCLH Serial Clock High Time 4 ns tCLL Serial Clock Low Time 4 ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (read/write) 20 ns tSHQZ Output Disable Time tCLQX Output Hold Time 0 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 2 ns tHLCH Hold# Low Setup Time (relative to Clock) 5 ns tHHCH Hold# High Setup Time (relative to Clock) 5 ns tCHHL Hold# High Hold Time (relative to Clock) 5 ns tCHHH Hold# Low Hold Time (relative to Clock) 5 ns tHLQZ Hold# Low To High-Z Output 6 ns tHHQX Hold# Low To Low-Z Output 6 ns tCLQV Clock Low To Output Valid 7 ns tWHSL Write Protect Setup Time Before CS# Low 20 ns tSHWL Write Protect Hold Time After CS# High 100 ns tDP CS# High To Deep Power-Down Mode tRES1 tRES2 tHPM 6 CS# High To Standby Mode Without Electronic Signature Read CS# High To Standby Mode With Electronic Signature Read CS# High To High Performance Mode 37 44 - 35 ns 0.1 �� 0.1 �� 0.1 �� 0.2 us Rev.1.1 GD25Q64BxIGx Uniform SectorUniform sector dual and quad serial flash Dual and Quad Serial Flash tSUS GD25Q64B CS# High To Next Command After Suspend 2 us 2 15 ms tW Write Status Register Cycle Time tPP Page Programming Time 0.7 2.4 ms tSE Sector Erase Time 100 300 ms tBE Block Erase Time(32K Bytes/64K Bytes) 0.2/0.4 1/1.2 s tCE Chip Erase Time(GD25Q64B) 30 60 s Figure 35. Serial Input Timing tSHSL CS# tCHSL SCLK tCHSH tSLCH tDVCH MSB SO High-Z tCHCL tCLCH tCHDX SI tSHCH LSB Figure 36. Output Timing CS# tCH SCLK tCLQV tCLQX tSHQZ tCL tCLQV tQLQH tCLQX SO LSB tQHQL SI Least significant address bit (LIB) in Figure 37. Hold Timing CS# SCLK SO tCHHL tHLCH tCHHH tHLQZ tHHCH tHHQX HOLD# SI do not care during HOLD operation. 4438- 36 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 9. ORDERING INFORMATION GD XX X XX X X X X X Packing Type T or no mark:Tube Y:Tray R:Tape & Reel Green Code G:Pb Free & Halogen Free Green Package Temperature Range I:Industrial(-40� to +85�) Package Type F: SOP16 300mil P: DIP8 300mil S: SOP8 208mil V: TSOP8 208mil W: WSON8 (6*5mm) Y: WSON8 (8*6mm) Z:TFBGA24 Generation B: B Version Density 64:64Mb Series Q:3V, 4KB Uniform Sector, Quad I/O Product Family 25:Serial Flash NOTE: 1. Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray etc.), please advise in advance. 39 44 - 37 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q64BxIGx Dual and Quad Serial Flash GD25Q64B 10. PACKAGE INFORMATION 10.1. Package SOP8 208MIL 8 � 5 E1 E L 1 L1 4 C D A2 S A1 b e A Dimensions Symbol A1 A2 b C D E E1 Min 0.05 1.70 0.31 0.18 5.13 7.70 5.18 Nom 0.15 1.80 0.41 0.21 5.23 7.90 5.28 0.25 1.91 0.51 0.25 5.33 8.10 Min 0.002 0.067 0.012 0.007 0.202 Nom 0.006 0.071 0.016 0.008 0.010 0.075 0.020 0.010 Unit mm Max Inch Max A 2.16 0.085 e L L1 S � 0.50 1.21 0.62 0 0.67 1.31 0.74 5 5.38 0.85 1.41 0.88 8 0.303 0.204 0.020 0.048 0.024 0 0.206 0.311 0.208 0.026 0.052 0.029 5 0.210 0.319 0.212 0.033 0.056 0.035 8 1.27 0.050 Note:Both package length and width do not include mold flash. 40 44 - 38 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 10.2. Package TSOP8 208MIL Dimensions Symbol A A1 A2 b D E E1 e L Min - 0.05 0.75 0.35 5.18 7.70 5.18 - 0.50 Nom - 0.10 0.80 0.42 5.28 7.90 5.28 1.27BSC 0.65 Max 1.00 0.15 0.85 0.48 5.38 8.10 5.38 - Min - 0.002 0.030 0.014 0.204 0.303 0.204 Nom - 0.004 0.031 0.017 0.206 0.311 Max 0.04 0.006 0.033 0.019 0.210 0.319 Unit mm Inch L1 C � 0.09 0° - - 0.80 0.2 10° - 0.020 0.004 0° 0.206 0.050BSC 0.026 0 - 0.210 - 0.031 0.008 10° 1.31REF 0.052REF Note:Both package length and width do not include mold flash. 41 44 - 39 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 10.3. Package DIP8 300MIL 4 1 E1 R0.005xDP0.020 5 8 E D 11° A2 L 11° A1 b S b1 5° C e eB Dimensions Symbol A1 A2 Min 0.38 3.00 mm Nom 0.72 Max Inch b E E1 eB L S 7.62 3.04 0.50 8.49 3.30 0.76 6.64 9.35 3.56 1.02 0.300 0.242 0.333 0.12 0.02 0.367 0.215 0.252 0.345 0.13 0.03 0.378 0.366 0.262 0.357 0.14 0.04 b1 C D 1.27 0.38 0.20 9.05 7.62 6.12 3.25 1.46 0.46 0.28 9.32 7.94 6.38 1.05 3.50 1.65 0.54 0.34 9.59 8.26 Min 0.015 0.118 0.05 0.015 0.008 0.356 Nom 0.028 0.128 0.058 0.018 0.011 Max 0.041 0.138 0.065 0.021 0.014 Unit e 2.54 0.1 Note:Both package length and width do not include mold flash. 42 44 - 40 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 10.4. Package WSON8 (6*5mm) D A2 y E A1 A Top View L Side View D1 b 1 E1 e Bottom View Dimensions Symbol Unit mm Inch A A1 A2 b D D1 E E1 e y L 0.00 0.50 0.04 0.60 Min 0.70 0.19 0.35 5.90 3.25 4.90 3.85 Nom 0.75 0.22 0.42 6.00 3.37 5.00 3.97 Max 0.80 0.25 0.48 6.10 3.50 5.10 4.10 0.08 0.75 Min 0.028 0.007 0.014 0.232 0.128 0.193 0.151 0.000 0.020 Nom 0.030 0.009 0.016 0.236 0.133 0.197 0.156 0.001 0.024 Max 0.032 0.010 0.019 0.240 0.138 0.201 0.161 0.003 0.030 0.05 0.002 1.27 0.05 Note:Both package length and width do not include mold flash. 43 44 - 41 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 10.5. Package WSON8 (8*6mm) D A2 E A1 A Top View L Side View D1 K b 1 E1 e Bottom View Dimensions Symbol Unit mm Inch A Min 0.70 Nom 0.75 Max 0.80 Min 0.028 Nom 0.030 Max 0.032 A1 A2 0.20 0.05 0.008 0.002 b D D1 E E1 e K L 0.35 7.90 3.25 5.90 4.15 0.40 8.00 3.42 6.00 4.22 0.45 8.10 3.50 6.10 4.40 0.65 0.014 0.311 0.128 0.232 0.163 0.022 0.016 0.315 0.135 0.236 0.166 0.019 0.319 0.138 0.240 0.173 0.55 1.27 0.050 1.80 0.071 0.60 0.024 0.027 Note:Both package length and width do not include mold flash. 44 44 - 42 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 10.6. Package TFBGA-24BALL (6*4 ball array) 1 2 3 4 4 3 2 1 A A e B B C C E1 E D D E E F F D D1 �b 0.10 C A1 0.10 e C C A2 A SEATING PLANE Dimensions Symbol A mm D 0.35 5.90 0.40 6.00 0.35 0.45 6.10 8.10 Min 0.010 0.014 0.232 0.311 Nom 0.012 0.016 0.236 0.018 0.240 Min 0.25 Nom 0.30 Max Inch A1 Max 1.20 0.047 0.014 A2 0.85 0.033 D1 E b Unit E1 e 5.00 1.00 0.200 0.039 7.90 3.00 0.120 8.00 0.315 0.319 Note:Both package length and width do not include mold flash. 45 44 - 43 Rev.1.1 GD25Q64BxIGx Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q64B 10.7. Package SOP16 300MIL � 9 15 E1 E L 1 L1 8 C D A A2 S A1 b e Dimensions Symbol A A1 A2 b C D E E1 Min 2.36 0.10 2.24 0.36 0.20 10.10 10.10 7.42 Nom 2.55 0.20 2.34 0.41 0.25 10.30 10.35 7.52 Max 2.75 0.30 2.44 0.51 0.30 10.50 10.60 Min 0.093 0.004 0.088 0.014 0.008 0.397 Nom 0.100 0.008 0.092 0.016 0.010 Max 0.108 0.012 0.096 0.020 0.012 Unit mm Inch e L L1 S 0.40 1.31 0.51 0 0.84 1.44 0.64 5 7.60 1.27 1.57 0.77 8 0.397 0.292 0.016 0.052 0.020 0 0.405 0.407 0.296 0.033 0.057 0.025 5 0.413 0.417 0.299 0.050 0.062 0.030 8 1.27 0.050 � Note:Both package length and width do not include mold flash. 46 44 - 44 Rev.1.1