GD25Q10 DATASHEET 34 - 1 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash Dual and Quad Serial Flash GD25Q10/512 GD25Q10xIGx Contents 1. FEATURES ..................................................................................................................................................... 44 2. GENERAL DESCRIPTION............................................................................................................................. 55 3. MEMORY ORGANIZATION ........................................................................................................................... 76 4. DEVICE OPERATION..................................................................................................................................... 87 5. DATA PROTECTION ...................................................................................................................................... 89 6. STATUS REGISTER..................................................................................................................................... 11 9 7. COMMANDS DESCRIPTION....................................................................................................................... 12 10 8. 7.1. WRITE ENABLE (WREN) (06H)................................................................................................................................ 15 12 7.2. WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 15 12 7.3. READ STATUS REGISTER (RDSR) (05H OR 35H) .......................................................................................................... 12 15 7.4. WRITE STATUS REGISTER (WRSR) (01H) ................................................................................................................... 16 13 7.5. READ DATA BYTES (READ) (03H)............................................................................................................................. 16 13 7.6. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) ............................................................................................. 17 14 7.7. DUAL OUTPUT FAST READ (3BH).............................................................................................................................. 17 14 7.8. QUAD OUTPUT FAST READ (6BH) ............................................................................................................................. 18 15 7.9. DUAL I/O FAST READ (BBH) .................................................................................................................................... 15 18 7.10. QUAD I/O FAST READ (EBH) ................................................................................................................................... 17 20 7.11. QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 18 21 7.12. PAGE PROGRAM (PP) (02H).................................................................................................................................... 19 22 7.13. SECTOR ERASE (SE) (20H)....................................................................................................................................... 23 20 7.14. 32KB BLOCK ERASE (BE) (52H) ............................................................................................................................... 23 20 7.15. 64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 24 21 7.16. CHIP ERASE (CE) (60/C7HEX).................................................................................................................................. 24 21 7.17. DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 25 22 7.18. RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH).............................. 25 22 7.19. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 26 23 7.20. READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 27 24 7.21. HIGH PERFORMANCE MODE (HPM) (A3H)................................................................................................................ 27 24 7.22. CONTINUOUS READ MODE RESET (CRMR) (FFH)........................................................................................................ 28 25 ELECTRICAL CHARACTERISTICS ........................................................................................................... 29 26 8.1. POWER-ON TIMING ........................................................................................................................................... 29 26 8.2. INITIAL DELIVERY STATE..................................................................................................................................... 29 26 8.3. DATA RETENTION AND ENDURANCE ................................................................................................................. 29 26 8.4. LATCH UP CHARACTERISTICS ............................................................................................................................. 29 26 8.5. ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 30 27 8.6. CAPACITANCE MEASUREMENT CONDITIONS .................................................................................................... 30 27 8.7. DC CHARACTERISTIC .......................................................................................................................................... 28 31 8.8. AC CHARACTERISTICS......................................................................................................................................... 29 32 2 34 - 2 Rev.1.1 Uniform sector dual and quad serial flash GD25Q10xIGx Uniform Sector Dual and Quad Serial Flash GD25Q10/512 9. ORDERING INFORMATION ........................................................................................................................ 34 31 10. PACKAGE INFORMATION ...................................................................................................................... 35 32 10.1. PACKAGE SOP8 150MIL ........................................................................................................................................ 35 32 10.2. PACKAGE USON8 (3*2MM).................................................................................................................................... 36 33 10.3. PACKAGE TSSOP8 173MIL..................................................................................................................................... 37 34 34 3- 3 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 1. FEATURES 1M-bit Serial Flash � � Program/Erase Speed -128/64K-byte -Page Program time:0.7ms typical -256 bytes per programmable page -Sector Erase time:100ms typical -Block Erase time:0.3/0.5s typical Standard, Dual, Quad SPI � -Chip Erase time: 1/0.5s typical -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# -Dual SPI:SCLK, CS#, IO0, IO1, WP#, HOLD# � -Quad SPI:SCLK, CS#, IO0, IO1, IO2, IO3 Flexible Architecture -Sector of 4K-byte -Block of 32/64K-byte High Speed Clock Frequency � -120MHz for fast read with 30PF load Low Power Consumption -Dual I/O Data transfer up to 240Mbits/s -20mA maximum active current -Quad I/O Data transfer up to 480Mbits/s -5uA maximum power down current Software/Hardware Write Protection � � � -Write protect all/portion of memory via software Single Power Supply Voltage -Full voltage range:2.7~3.6V -Enable/Disable protection with WP# Pin -Top or Bottom, Sector or Block selection � Package Information -SOP8 (150mil) � Minimum 100,000 Program/Erase Cycles -TSOP (173mil) � Typical 10 years Data Retention -USON8 (3*2mm) 4 34 - 4 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 2. GENERAL DESCRIPTION The GD25Q10 Serial flash supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). Serial clock frequencies of up to 120MHz are supported allowing equivalent clock rates of 240MHz for Dual Output & Dual I/O read command, and 480MHz for Quad output & Quad I/O read command. CONNECTION DIAGRAM 8 VCC CS# 1 7 HOLD# SO 2 3 6 SCLK WP# 3 6 SCLK 4 5 SI VSS 4 5 CS# 1 SO 2 WP# VSS Top View 8–LEAD SOP/TSSOP Top View 8 VCC 7 HOLD# SI 8–LEAD USON PIN DESCRIPTION Pin Name I/O Description CS# I Chip Select Input SO (IO1) I/O Data Output (Data Input Output 1) WP# (IO2) I/O Write Protect Input (Data Input Output 2) Ground VSS SI (IO0) I/O Data Input (Data Input Output 0) SCLK I Serial Clock Input HOLD# (IO3) I/O Hold Input (Data Input Output 3) VCC Power Supply 5 34 - 5 Rev.1.1 Uniform Sector Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 Dual and Quad Serial Flash GD25Q10/512 BLOCK DIAGRAM BLOCK DIAGRAM Write Control Write Control Logic Logic Status Status Register Register HOLD#(IO3) HOLD#(IO3) SCLK SCLK CS# CS# SPI SPI Command & Command & Control Logic Control Logic High Voltage High Voltage Generators Generators Page Address Page Address Latch/Counter Latch/Counter Write Protect Logic and Row Decode Write Protect Logic and Row Decode WP#(IO2) WP#(IO2) Flash Flash Memory Memory Column Decode And Column Decode And 256-Byte Page Buffer 256-Byte Page Buffer SI(IO0) SI(IO0) SO(IO1) SO(IO1) Byte Address Byte Address Latch/Counter Latch/Counter Uniform Sector Dual and Quad Serial Flash GD25Q10/512 3. MEMORY ORGANIZATION GD25Q10 Each device has Each block has Each sector has Each page has 128K 64/32K 4K 256 bytes 512 256/128 16 - pages 32 16/8 - - sectors 2/4 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25Q10 64K Bytes Block Sector Architecture Block 1 0 Sector Address range 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 6 34 - 66 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 4. DEVICE OPERATION SPI Mode Standard SPI The GD25Q10 feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q10 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q10 supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure 1 Hold Condition CS# SCLK HOLD# HOLD HOLD 8 34 - 7 Rev.1.1 Uniform Uniform Sector Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual Dual and and Quad Quad Serial Serial Flash Flash GD25Q10/512 GD25Q10/512 5. 5.DATA DATA PROTECTION PROTECTION TheThe GD25Q10 GD25Q10 provides provides the the following following datadata protection protection methods: methods: � Write Write Enable Enable (WREN) (WREN) command: command: TheThe WREN WREN command command is set is � the set the Write Write Enable Enable Latch Latch bit (WEL). bit (WEL). TheThe WEL WEL bit will bit will return return to reset to reset by the by the following following situation: situation: -Power-Up -Power-Up -Write -Write Disable Disable (WRDI) (WRDI) -Write -Write Status Status Register Register (WRSR) (WRSR) -Page -Page Program Program (PP)(PP) -Sector -Sector Erase Erase (SE)(SE) -Block -Block Erase Erase (BE)(BE) -Chip -Chip Erase Erase (CE)(CE) � Software Software Protection Protection Mode: Mode: TheThe Block Block Protect Protect (BP4, (BP4, BP3, BP3, BP2, BP2, BP1, BP1, BP0) BP0) bits bits define define the � the section section of the of the memory memory array array thatthat can can be read be read but but not not change. change. � � Hardware Hardware Protection Protection Mode: Mode: WP# WP# going going low low to protected to protected the the BP0~BP4 BP0~BP4 bits bits andand SRP0~1 SRP0~1 bits.bits. � � Deep Deep Power-Down Power-Down Mode: Mode: In Deep In Deep Power-Down Power-Down Mode, Mode, all commands all commands are are ignored ignored except except the the Release Release fromfrom Deep Deep Power-Down Power-Down Mode Mode command. command. Table1. Table1. GD25Q10 GD25Q10 Protected Protected areaarea sizesize Status Status Register Register Content Content Memory Memory Content Content BP4BP4BP3BP3BP2BP2BP1BP1BP0BP0 Blocks Blocks Addresses Addresses Density Density Portion Portion NONE NONE NONE NONE NONE NONE 0 0 X X X X 0 0 0 0 NONE NONE 0 0 0 0 X X 0 0 1 1 1 1 010000H-01FFFFH 010000H-01FFFFH 64KB 64KB Upper Upper 1/2 1/2 0 0 1 1 X X 0 0 1 1 0 0 000000H-00FFFFH 000000H-00FFFFH 64KB 64KB Lower Lower 1/2 1/2 0 0 X X X X 1 1 X X 0 to01to 1 000000H-01FFFFH 000000H-01FFFFH 128KB 128KB ALLALL 1 1 X X 0 0 0 0 0 0 NONE NONE NONE NONE NONE NONE NONE NONE 1 1 0 0 0 0 0 0 1 1 1 1 01F000H-01FFFFH 01F000H-01FFFFH 4KB4KB Top Top Block Block 1 1 0 0 0 0 1 1 0 0 1 1 01E000H-01FFFFH 01E000H-01FFFFH 8KB8KB Top Top Block Block 1 1 0 0 0 0 1 1 1 1 1 1 01C000H-01FFFFH 01C000H-01FFFFH 16KB 16KB Top Top Block Block 1 1 0 0 1 1 0 0 X X 1 1 018000H-01FFFFH 018000H-01FFFFH 32KB 32KB Top Top Block Block 1 1 0 0 1 1 1 1 0 0 1 1 018000H-01FFFFH 018000H-01FFFFH 32KB 32KB Top Top Block Block 1 1 1 1 0 0 0 0 1 1 0 0 000000H-000FFFH 000000H-000FFFH 4KB4KB Bottom Bottom Block Block 1 1 1 1 0 0 1 1 0 0 0 0 000000H-001FFFH 000000H-001FFFH 8KB8KB Bottom Bottom Block Block 1 1 1 1 0 0 1 1 1 1 0 0 000000H-003FFFH 000000H-003FFFH 16KB 16KB Bottom Bottom Block Block 1 1 1 1 1 1 0 0 X X 0 0 000000H-007FFFH 000000H-007FFFH 32KB 32KB Bottom Bottom Block Block 1 1 1 1 1 1 1 1 0 0 0 0 000000H-007FFFH 000000H-007FFFH 32KB 32KB Bottom Bottom Block Block 1 1 X X 1 1 1 1 1 1 000000H-01FFFFH 000000H-01FFFFH 128KB 128KB ALLALL 0 to01to 1 9 9 34 - 8 Rev.1.1 Uniform Sector Dual and Quad Serial Flash GD25Q10/512 Uniform sector dual and quad serial flash GD25Q10xIGx 6. STATUS REGISTER S15-S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Reserved QE SRP1 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block Protect (BP4,BP3,BP2,BP1,BP0) bits are set to “None protected”. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. SRP1 SRP0 #WP Status Register 0 0 X Software Protected 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X Power Supply Lock-Down(1) 1 1 X One Time Program Description WP# pin has no control. The Status Register can be written to after a Write Enable command, WEL=1.(Default) When WP# pin is low the Status Register locked and can not be written to. When WP# pin is high the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. Status Register is protected and can not be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and can not be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground) 11 34 - 9 Rev.1.1 Uniform Sector Dual and Quad Serial Flash GD25Q10/512 Uniform sector dual and quad serial flash GD25Q10xIGx 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands Command Name Byte 1 Byte 2 Write Enable Write Disable Read Status Register Read Status Register-1 Write Status Register Read Data Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Fast Read Quad I/O Word Fast Read(7) Continuous Read Reset Page Program Sector Erase Block Erase(32K) Block Erase(64K)(8) Chip Erase Deep Power-Down Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Manufacturer/ Device ID High Performance Mode Read Identification 06H 04H 05H 35H 01H 03H 0BH 3BH (S7-S0) (S15-S8) (S7-S0) A23-A16 A23-A16 A23-A16 BBH A23-A8(2) 6BH A23-A16 EBH E7H FFH 02 H 20H 52H D8H C7/60 H B9H ABH Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) (S15-S8) A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy (Next byte) (D7-D0) (D7-D0)(1) (D7-D0)(1) (continuous) (continuous) (continuous) A7-A0 M7-M0(2) A15-A8 (continuous) A7-A0 A23-A0 M7-M0(4) A23-A0 M7-M0(4) dummy(5) (D7-D0)(3) (continuous) dummy(6) (D7-D0)(3) (continuous) A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 D7-D0 dummy dummy dummy (DID7DID0) dummy dummy 00H dummy (D7-D0)(3) (continuous) Next byte (continuous) ABH 90H A3H 9FH (MID7MID0) dummy dummy dummy (MID7-MID0)(JDID15-JDID8)(JDID7-JDID0) (DID7DID0) (continuous) (continuous) 12 34 - 10 Rev.1.1 Uniform Sector Dual and Quad Serial Flash GD25Q10/512 GD25Q10xIGx Uniform sector dual and quad serial flash NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Fast WordSector Read Quad I/O Data: the lowest address bit must be 0. Uniform Dual and Quad Serial Flash GD25Q10/512 Table of ID Definitions: GD25Q10 Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH C8 40 11 90H C8 10 ABH 10 13 34 - 11 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low � sending the Write Enable command � CS# goes high. Figure 2. Write Enable Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low�Sending the Write Disable command �CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Figure 3. Write Disable Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 Command SI 04H High-Z SO 7.3. Read Status Register (RDSR) (05H or 35H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8. Figure 4. Read Status Register Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Command 05H or 35H High-Z 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 MSB 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 7 MSB 15 34 - 12 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.4. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S15~S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure 5. Write Status Register Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 8 Command SI Status Register in 01H 7 6 MSB SO 5 4 3 2 1 0 15 14 13 12 11 10 9 8 High-Z 7.5. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 6. Read Data Bytes Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 Command 03H High-Z 9 10 28 29 30 31 32 33 34 35 36 37 38 39 24-bit address 3 23 22 21 2 1 0 MSB MSB 16 34 - 13 7 6 5 Data Out1 4 3 2 1 Data Out2 0 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 7. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 8 7 9 10 24-bit address Command SI 28 29 30 31 1 2 3 23 22 21 0BH 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI Dummy Byte 7 6 5 4 3 2 1 0 Data Out1 5 4 3 2 7 6 MSB SO 1 0 Data Out2 7 6 5 MSB 7.7. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 8. Dual Output Fast Read Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 24-bit address Command 3BH 3 23 22 21 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO Dummy Clocks 0 6 Data Out2 Data Out1 7 5 3 1 7 5 3 1 MSB MSB 7 6 17 4 2 34 - 14 0 6 4 2 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.8. Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 9. Quad Output Fast Read Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 7 9 10 Command SI(IO0) 24-bit address 6BH SO(IO1) 1 2 0 High-Z High-Z HOLD#(IO3) High-Z SCLK 3 23 22 21 WP#(IO2) CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Dummy Clocks SI(IO0) 4 0 SO(IO1) 5 1 WP#(IO2) HOLD#(IO3) 4 0 5 6 2 7 3 Byte1 1 6 4 5 2 0 1 6 4 5 2 0 1 6 4 5 2 6 7 3 7 3 7 3 7 Byte2 Byte3 Byte4 7.9. Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read command. Dual I/O Fast Read With “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. 18 34 - 15 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 Figure 10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Command SI(IO0) BBH SO(IO1) A23-16 A15-8 A7-0 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure 11. Dual I/O Fast Read Sequence Diagram (M7-0= AXH) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 5 3 1 7 7 A23-16 A15-8 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 19 34 - 16 Byte4 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.10. Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Quad I/O Fast Read command. Quad I/O Fast Read With “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure 12. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH) CS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 0 SCLK Command SI(IO0) EBH A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0= AXH) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK 8 A23-16 A15-8 A7-0 M7-0 20 34 - 17 9 10 11 12 13 14 15 Dummy Byte1 Byte2 Rev.1.1 Uniform Sector Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 flash GD25Q10xIGx 7.11. Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3h) must be executed once, prior to the Quad I/O Word Fast Read command. Quad I/O Word Fast Read With “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before issuing normal command. Figure 14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH) CS# 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 0 SCLK 1 2 3 4 5 6 7 Command SI(IO0) E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK 8 9 10 11 12 13 14 15 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 21 34 - 18 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.12. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI � at least 1 byte data on SI � CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is not executed. Figure 16. Page Program Sequence Diagram CS# 5 6 8 7 24-bit address 23 22 21 02H 2 3 Data Byte 1 6 5 4 3 2 1 2079 Command SI 28 29 30 31 32 33 34 35 36 37 38 39 9 10 2078 4 2076 3 2077 2 2075 1 2074 0 SCLK 1 0 0 7 1 MSB 0 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 7 6 SCLK SI Data Byte 3 Data Byte 2 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 Data Byte 256 1 MSB 0 5 4 3 2 MSB 22 34 - 19 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.13. Sector Erase (SE) (20H) The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low � sending Sector Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table1.) is not executed. Figure 17. Sector Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 29 30 31 24 Bits Address Command SI 9 23 22 MSB 20H 2 1 0 7.14. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low � sending 32KB Block Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.) is not executed. Figure 18 . 32KB Block Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 9 29 30 31 24 Bits Address Command 52H 8 23 22 MSB 23 34 - 20 2 1 0 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.15. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low � sending 64KB Block Erase command � 3-byte address on SI � CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.) is not executed. Figure 19. 64KB Block Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 8 7 9 24 Bits Address Command SI 29 30 31 23 22 MSB D8H 2 1 0 7.16. Chip Erase (CE) (60/C7Hex) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low � sending Chip Erase command � CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP4,BP3,BP2,BP1,BP0) bits are set to “None protected”. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure 20. Chip Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 60H or C7H 24 34 - 21 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.17. Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low � sending Deep Power-Down command � CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 21�Deep Power-Down Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 tDP 7 Command Stand-by mode Deep Power-down mode B9H 7.18. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure22. The Device ID value for the GD25Q10 is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other 25 34 - 22 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 22. Release Power-Down or High Performance Mode Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 t RES1 7 Command SI ABH Deep Power-down mode Stand-by mode Figure 23. Release Power-Down/Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 SCLK Command SI SO t RES2 3 Dummy Bytes 2 23 22 ABH 1 0 MSB High-Z MSB 7 Device ID 5 4 3 2 6 1 0 Deep Power-down Mode Stand-by Mode 7.19. Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 24. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 SCLK 2 3 4 5 6 7 8 9 10 28 29 30 31 24-bit address Command SI 90H 23 22 21 3 2 1 0 High-Z SO CS# 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO 7 MSB 6 Manufacturer ID 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 1 0 MSB 26 - 23 34 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 7.20. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure25. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure 25. Read Identification ID Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 9FH SI Command SO MSB CS# Manufacturer ID 5 4 3 2 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI 7 SO MSB 6 5 4 3 2 1 Memory Type JDID15-JDID8 0 7 MSB 6 5 4 3 2 Capacity JDID7-JDID0 1 0 7.21. High Performance Mode (HPM) (A3H) The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when operating at high frequencies (see fR and fC in AC Electrical Characteristics). This command allows pre-charging of internal charge pumps so the voltages required for accessing the flash memory array are readily available. The command sequence: CS# goes low�Sending A3H command� Sending 3-dummy byte�CS# goes high. See Figure26. After the HPM command is executed, the device will maintain a slightly higher standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI standby current (Icc1). In addition, Write Enable command (06H) and Power-Down command (B9H) will also release the device from HPM mode back to standard SPI standby state. 27 34 - 24 Rev.1.1 Uniform Sector flash GD25Q10xIGx Uniform sector dual and quad serial Dual and Quad Serial Flash GD25Q10/512 Figure 26. High Performance Mode Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI A3H 9 29 30 31 t HPM 3 Dummy Bytes 2 23 22 MSB 1 0 SO High Performance Mode 7.22. Continuous Read Mode Reset (CRMR) (FFH) The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the BBH/EBH/E7H command code. If the system controller is reset during operation it will likely send a standard SPI command, such as Read ID (9FH) or Fast Read (0BH), to the device. Because the GD25Q10 has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q10 will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in Figure27. Figure 27. Continuous Read Mode Reset Sequence Diagram Mode Bit Reset for Quad/Dual I/O CS# 0 1 2 3 4 5 6 7 SCLK SI(IO0) FFH SO(IO1) Don`t Care WP#(IO2) Don`t Care HOLD#(IO3) Don`t Care 28 34 - 25 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Vcc(max) Program, Erase and Write command are ignored Chip Selection is not allowed Vcc(min) VWI tVSL Reset State Read command is allowed Device is fully accessible tPUW Time Table3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC(min) to CS# Low 10 us tPUW Time Delay Before Write Instruction 1 10 ms VWI Write Inhibit Voltage 1 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3. DATA RETENTION AND ENDURANCE Parameter Minimum Pattern Data Retention Time Erase/Program Endurance Test Condition Min Units 150� 10 Years 125� 20 Years -40 to 85� 100K Cycles 8.4. LATCH UP CHARACTERISTICS Parameter Min Input Voltage Respect To VSS On I/O Pins VCC Current 29 34 - 26 Max -1.0V VCC+1.0V -100mA 100mA Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 8.5. ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 � Storage Temperature -65 to 150 � Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V -0.5 to 4.0 V VCC 0.8VCC Input timing reference level 0.7VCC 0.3VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are<5ns 8.6. CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 Input Rise And Fall time pF 5 ns Input Pulse Voltage 0.2VCC to 0.8VCC V Input Timing Reference Voltage 0.3VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure 28. Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 30 34 - 27 20ns Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 8.7. DC CHARACTERISTIC (T= -40�~85�, VCC=2.7~3.6V) Symbol Parameter Test Condition Min. Typ Max. Unit. ILI Input Leakage Current ±2 �� ILO Output Leakage Current ±2 �� ICC1 Standby Current 1 5 �� 1 5 �� 15 20 mA 13 18 mA CS#=VCC, VIN=VCC or VSS ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS CLK=0.1VCC / 0.9VCC at 120MHz, ICC3 Operating Current (Read) Q=Open(*1 I/O) CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) ICC4 Operating Current (PP) CS#=VCC 15 mA ICC5 Operating Current(WRSR) CS#=VCC 15 mA ICC6 Operating Current (SE) CS#=VCC 15 mA ICC7 Operating Current (BE) CS#=VCC 15 mA I CC8 High Performance Current 800 uA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL =1.6mA 0.4 V VOH Output High Voltage IOH =-����� 500 VCC-0.2 31 34 - 28 V Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 8.8. AC CHARACTERISTICS (T= -40�~85�, VCC=2.7~3.6V, CL=30pf) Symbol Max. Unit. DC. 120 MHz Serial Clock Frequency For: Read, RDSR, RDID DC. 80 MHz tCLH Serial Clock High Time 3.5 ns tCLL Serial Clock Low Time 3.5 ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (read/write) 20 ns tSHQZ Output Disable Time tCLQX Output Hold Time 0 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 5 ns tHLCH Hold# Low Setup Time (relative to Clock) 5 ns tHHCH Hold# High Setup Time (relative to Clock) 5 ns tCHHL Hold# High Hold Time (relative to Clock) 5 ns tCHHH Hold# Low Hold Time (relative to Clock) 5 ns tHLQZ Hold# Low To High-Z Output 6 ns tHHQX Hold# Low To Low-Z Output 6 ns tCLQV Clock Low To Output Valid 6 ns tWHSL Write Protect Setup Time Before CS# Low 20 ns tSHWL Write Protect Hold Time After CS# High 100 ns tDP CS# High To Deep Power-Down Mode fC fR tRES1 tRES2 tHPM Parameter Min. Serial Clock Frequency For: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, WRSR (*1,*2,*4 I/O) Typ. 6 CS# High To Standby Mode Without Electronic Signature Read CS# High To Standby Mode With Electronic Signature Read CS# High To High Performance Mode ns 0.1 �� 0.1 �� 0.1 �� 0.2 us tW Write Status Register Cycle Time 10 15 ms tPP Page Programming Time 0.7 2.4 ms tSE Sector Erase Time 100 300 ms tBE Block Erase Time(32K\64K) 0.3/0.5 1.2/1.5 s tCE Chip Erase Time(GD25Q10) 1/0.5 2.5/1.5 s 32 34 - 29 Rev.1.1 Uniform Sector Dual and Quad Serial Flash GD25Q10/512 Uniform sector dual and quad serial flash GD25Q10xIGx Figure 29. Serial Input Timing tSHSL CS# tCHSL SCLK tCHSH tSLCH tDVCH MSB SO High-Z tCHCL tCLCH tCHDX SI tSHCH LSB Figure 30. Output Timing CS# tCH SCLK tCLQV tCLQX tCLQV tSHQZ tCL tQLQH tCLQX SO LSB tQHQL SI Least significant address bit (LIB) in Figure 31. Hold Timing CS# SCLK SO tCHHL tHLCH tCHHH tHLQZ tHHCH tHHQX HOLD# SI do not care during HOLD operation. 33 34 - 30 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 9. ORDERING INFORMATION GD XX X XX X X X X Packing Type T or no mark:Tube Y:Tray R:Tape & Reel Green Code G:Pb Free & Halogen Free Green Package Temperature Range I:Industrial(-40� to +85�) Package Type O: TSSOP8 173mil T: SOP8 150mil U: USON8 (3*2mm) Density 10:1Mb Series Q:3V, 4KB Uniform Sector, Quad I/O Product Family 25:Serial Flash NOTE: 1. Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray etc.), please advise in advance. 34 34 - 31 Rev.1.1 Uniform Sector flash GD25Q10xIGx Dual and Quad Serial FlashUniform sector dual and quad serial GD25Q10/512 10. PACKAGE INFORMATION 10.1. Package SOP8 150MIL 8 � 5 E1 E L1 L 1 4 C D A2 S Seating plane Gauge plane A1 b e A 0.10 Detail "�" E1 e Dimensions Symbol A A1 A2 b C D E Min 1.35 0.05 1.35 0.31 0.15 4.77 5.80 - Nom - - - - - 4.90 6.00 Max 1.75 0.25 1.55 0.51 0.25 5.03 Min 0.053 0.002 0.053 0.012 0.006 Nom - - - 0.016 Max 0.069 0.010 0.061 0.020 Unit mm Inch L L1 S � � � - 0.40 0.85 0.71 0° 6° 11° 3.90 1.27 - 1.06 0.76 - 7° 12° 6.20 - - 0.90 1.27 0.81 8° 8° 13° 0.188 0.228 - - 0.016 0.033 0.028 0° 6° 11° - 0.193 0.236 0.154 0.050 - 0.042 0.030 - 7° 12° 0.010 0.198 0.244 - - 0.035 0.050 0.032 8° 8° 13° Note:Both package length and width do not include mold flash. 35 34 - 32 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 10.2. Package USON8 (3*2mm) D A2 y E A1 A Top View L Side View D1 b 1 E1 e Bottom View Dimensions Symbol Unit mm Inch A A1 A2 b D D1 E E1 e y L 0.00 0.30 Min 0.50 0.18 0.18 2.95 1.65 1.95 1.50 Nom 0.55 0.20 0.25 3.00 1.80 2.00 1.65 Max 0.60 0.25 0.30 3.15 1.90 2.05 1.75 0.05 0.50 Min 0.020 0.007 0.007 0.116 0.065 0.077 0.059 0.000 0.012 Nom 0.022 0.008 0.010 0.118 0.071 0.079 0.065 Max 0.024 0.010 0.012 0.124 0.075 0.081 0.069 0.05 0.002 0.50 0.40 0.020 0.016 0.002 0.020 Note:Both package length and width do not include mold flash. 36 34 - 33 Rev.1.1 Uniform Sector Uniform sector dual and quad serial flash GD25Q10xIGx Dual and Quad Serial Flash GD25Q10/512 10.3. Package TSSOP8 173MIL 8 � 5 E1 E L1 L 1 4 C D A2 S b e A A1 Dimensions Symbol A Unit mm Inch A1 A2 b C D E E1 e L L1 � Min - 0.05 0.80 0.19 0.09 2.83 6.20 4.30 - 0.45 0.85 0 Nom - 0.10 0.92 0.24 0.14 2.96 6.40 4.40 0.65 0.60 1.00 4 Max 1.20 0.15 1.05 0.30 0.20 3.10 6.60 4.50 - 0.75 1.15 8 Min - 0.002 0.031 0.007 0.003 0.111 0.244 0.169 - 0.018 0.033 0 Nom - 0.004 0.036 0.010 0.006 0.116 0.252 0.173 0.026 0.024 0.039 4 Max 0.047 0.006 0.041 0.012 0.008 0.122 0.260 0.177 - 0.030 0.045 8 Note:Both package length and width do not include mold flash. 37 34 - 34 Rev.1.1