ROHM BD9150MUV

Single-chip Type with Built-in FET Switching Regulator Series
Output 1.5A or Less High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9150MUV
No.09027EAT13
●Description
ROHM’s high efficiency dual step-down switching regulator BD9150MUV is a 2ch output power supply designed to produce a
low voltage including 3.3,1.2 volts from 5.0 volts power supply line. Offers high efficiency with our original pulse skip control
technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to
sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) and SLLM (Simple Light Load Mode)
3) 2ch output power supply.
4) Each of EN controls 2ch output.
5) Incorporates soft-start function.
6) Incorporates ULVO functions.
7) Incorporates thermal protection and short-current protection circuit with time delay function.
8) Incorporates shutdown function Icc=0μA(Typ.)
9) Output current max 1.5A/1.5A.
10)Employs small surface mount package : VQFN020V4040
●Use
Power supply for LSI including DSP, Micro computer and ASIC
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1/18
2009.05 - Rev.A
Technical Note
BD9150MUV
●Absolute Maximum Rating (Ta=25℃)
Parameter
Symbol
Limit
VCC
-0.3～+7 *
Vcc Voltage
EN Voltage
SW Voltage
V
V
VEN1
-0.3～+7
VEN2
-0.3～+7
V
VSW1
-0.3～+7
V
VSW2
-0.3～+7
Pd1
0.34*
Pd2
V
2
W
0.70 *
3
W
Pd3
1.21 *
4
W
Pd4
3.56*
Operating Temperature Range
Topr
-40～+85
℃
Storage Temperature Range
Tstg
-55～+150
℃
Tjmax
+150
℃
Power Dissipation
Maximum Junction Temperature
*1
*2
*3
*4
*5
Unit
1
5
W
Pd should not be exceeded.
IC only
1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , in each layers
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
●Operating Conditions (Ta=-40～+85℃)
Parameter
Symbol
Min.
Typ.
Max.
VCC
4.75
5.0
5.5
V
VEN1
0
-
5.5
V
VEN2
0
-
0.8
-
5.5
2.5
V
VOUT2
Vcc Voltage
EN Voltage
Output Voltage range
SW Average Output Current
*6
Unit
V
ISW1
-
-
1.5*
6
ISW2
-
-
1.5*
6
A
A
Pd and ASO should not be exceeded.
●Electrical Characteristics
◎BD9150MUV (Ta=25℃ AVCC=PVCC=5.0V, EN1=EN2=AVCC ,unless otherwise specified.)
Limit
Parameter
Symbol
Unit
Min.
Typ.
Max.
Condition
Standby Current
ISTB
-
0
10
μA
Bias Current
ICC
-
500
800
μA
EN Low Voltage
VENL
-
GND
0.8
V
Standby Mode
EN High Voltage
VENH
2.0
Vcc
-
V
Active Mode
EN Input Current
IEN
-
1
10
μA
FOSC
1.2
1.5
1.8
MHz
0.17
0.3
Ω
Vcc=5V
0.17
0.3
Ω
Vcc=5V
0.13
0.2
Ω
Vcc=5V
0.13
0.2
Ω
Vcc=5V
3.35
V
±1.5%
0.812
V
±1.5%
Oscillation Frequency
Pch FET ON Resistance
Nch FET ON Resistance
FB Reference Voltage
RONP1
RONP2
RONN1
RONN2
FB1
FB2
3.25
3.3
0.788
0.8
EN1=EN2=0V
VEN1=VEN2=2V
UVLO Threshold Voltage
VUVLO1
3.6
3.8
4.0
V
VCC=5→0V
UVLO Release Voltage
VUVLO2
3.65
3.9
4.2
V
VCC=0→5V
TSS
0.4
0.8
1.6
ms
Timer Latch Time
TLATCH
0.68
1.36
2.72
ms
SCP/TSD ON
Output Short circuit
Threshold Voltage
VSCP1
-
1.65
2.4
V
FB1=3.3→0V
VSCP2
-
0.4
0.56
V
FB2=0.8→0V
Soft Start Time
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2/18
2009.05 - Rev.A
Technical Note
BD9150MUV
●Block Diagram, Application Circuit
AVCC
【BD9150MUV】
PVCC
4.0±0.1
FB1
Current
Comp
R
Gm Amp
4.0±0.1
Current
D9150
Q
Sense/
Slope1
EN1
1.0Max.
Lot No.
AGND
SW1
Protect
S
+
Soft
Start1
Driver
Logic
ITH1
0.08 S
C0.2 2.1±0.1
16
1.0
10
0.5
SCP/
TSD
UVLO
CLK2
PVCC
SCP2
6
15
OSC
5
20
PGND1
CLK1
VREF
2.1±0.1
0.4±0.1
1
0.02 +0.03
-0.02
(0.22)
S
SCP1
Current
Current
Comp
R
Gm Amp
FB2
Q
S
11
Sense/
Protect
Soft
Start2
EN2
0.25 +0.05
-0.04
SW2
+
Slope2
Driver
CLK2
Logic
PGND2
ITH2
(Unit : mm)
AGND
Fig.1 BD9150MUV TOP View
Fig.2 BD9150MUV Block Diagram
●Pin No. & function table
Pin
Pin
Pin
Pin
No.
name
No.
name
1
PGND2
Ch2 Lowside source pin
11
ITH1
2
PVcc
Highside FET source pin
12
AGND
3
PVcc
Highside FET source pin
13
N.C.
Non Connection
4
PVcc
Highside FET source pin
14
AVcc
VCC power supply input pin
5
PGND1
Ch1 Lowside source pin
15
ITH2
6
PGND1
Ch1 Lowside source pin
16
FB2
Ch2 output voltage detect pin
7
SW1
Ch1 Pch/Nch FET drain output pin
17
EN2
Ch2 Enable pin(High Active）
8
SW1
Ch1 Pch/Nch FET drain output pin
18
SW2
Ch2 Pch/Nch FET drain output pin
9
EN1
Ch1 Enable pin(High Active)
19
SW2
Ch2 Pch/Nch FET drain output pin
10
FB1
Ch1 output voltage detect pin
20
PGND2
Function
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3/18
Function
Ch1
GmAmp
output
pin/Connected
phase compensation capacitor
Ground
Ch1
GmAmp
output
pin/Connected
phase compensation capacitor
Ch2 Lowside source pin
2009.05 - Rev.A
Technical Note
BD9150MUV
●Characteristics data【BD9150MUV】
3.5
Ta=25℃
Io=1.5A
2.5
3.5
3.0
2.0
【VOUT1=3.3V】
1.5
【VOUT2=1.2V】
1.0
0.5
0.0
【VOUT1=3.3V】
2.5
2.0
【VOUT2=1.2V】
1.5
VCC=5V
Ta=25℃
Io=0A
1.0
0.5
1
2
3
4
INPUT VOLTAGE:VCC[V]
0
5
1
2
3
4
【VOUT2=1.2V】
1.5
1.0
0.5
0
5
90
3.25
VCC=5V
Io=0A
1.20
1.18
VCC=5V
Io=0A
0
20
40
60
TEMPERATURE:Ta[℃]
-40
80
-20
70
60
【VOUT2=1.5V】
50
40
【VOUT2=1.2V】
30
VCC=5V
Ta=25℃
20
10
1.15
3.20
【
VOUT2=2.5V】
【VOUT1=3.3V
】
80
1.23
EFFICIENCY: η[%]
OUTPUT VOLTAGE:VOUT[V]
3.30
0
20
40
60
TEMPERATURE:Ta[℃ ]
0
80
10
200
1.5
1.4
VCC=5V
ON RESISTANCE:RON[mΩ]
FREQUENCY:FOSC[MHz]
FREQUENCY:Fosc[MHz]
175
1.6
1.6
1.5
1.4
1.3
80
4.75
5
5.25
INPUT VOLTAGE:VCC[V]
5.5
Fig.10 Vcc - Fosc
75
50
VCC=5V
CIRCUIT CURRENT:ICC[μA]
1.6
1.4
1.2
1.0
0.8
VCC=5V
-40
-20
0
20
40
60
80
TEMPERATURE:Ta[℃]
100
Fig.11 Ta – RONN, RONP
VCC=5V,Ta=25℃
1.8
EN VOLTAGE:VEN[V]
NMOS
100
Ta=25℃
600
2.0
0.4
125
0
4.5
Fig.9 Ta - Fosc
0.6
PMOS
150
25
1.3
0
20
40
60
TEMPERATURE:Ta[℃]
10000
Fig.8 Efficiency
1.7
-20
100
1000
OUTPUT CURRENT:IOUT[mA]
Fig. 7 Ta - VOUT
Fig. 6 Ta - VOUT
1.7
4
100
【VOUT2=1.2V
設定】
【VOUT2=1.2V】
3.35
-40
1
2
3
OUTPUT CURRENT:IOUT[A]
Fig.5 IOUT - VOUT
1.25
【VOUT1=3.3V】
VCC=5V
Ta=25℃
2.0
Fig.4 VEN - VOUT
3.40
-20
2.5
EN VOLTAGE:VEN[V]
Fig.3 Vcc - VOUT
-40
【VOUT1=3.3V】
3.0
0.0
0.0
0
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
3.0
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
3.5
500
400
EN1=E2
300
VOUT1
200
VCC=5V
VOUT2
100
0.2
0
0.0
-40
-20
0
20
40
60
80
TEMPERATURE:Ta[℃]
Fig.12 Ta-VEN
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c 2009 ROHM Co., Ltd. All rights reserved.
○
-40
-20
0
20
40
60
80
TEMPERATURE:Ta[℃]
Fig.13 Ta-ICC
4/18
Fig.14 Soft start waveform
(Io=0mA)
2009.05 - Rev.A
Technical Note
BD9150MUV
●Characteristics data【BD9150MUV】
VCC=5V,Ta=25℃
VCC=5V,Ta=25℃
VCC=5V,Ta=25℃
SW1
SW1
VOUT1
VOUT1
EN1=E2
VOUT1
VOUT2
Fig.16 SW1 waveform
(Io=0mA)
Fig.15 Soft start waveform
(Io=1.5A)
VCC=5V,Ta=25℃,VOUT2=1.2V
Fig.17 SW1 waveform
(Io=1.5A)
VCC=5V,Ta=25℃,VOUT2=1.2V
SW2
SW2
VOUT2
VOUT2
Fig.18 SW2 waveform
(Io=0mA)
VOUT1
IOUT1
Fig.19 SW2 waveform
(Io=1.5A)
VCC=5V,Ta=25℃
VCC=5V,Ta=25℃
Fig.20 VOUT1 Transient Response
(Io0.5A→1.5A / usec)
VCC=5V,Ta=25℃,VOUT2=1.2V
VCC=5V,Ta=25℃,VOUT2=1.2V
VOUT1
VOUT2
VOUT2
IOUT1
IOUT2
IOUT2
Fig.21VOUT1 Transient Response
(Io1.5A→0.5A/ usec)
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Fig.22 VOUT2 Transient Response
(Io0.5A→1.5A/ usec)
5/18
Fig.23 VOUT2 Transient Response
(Io1.5A→0.5A/ usec)
2009.05 - Rev.A
Technical Note
BD9150MUV
●Information on advantages
Advantage 1：Offers fast transient response with current mode control system.
BD9150MUV (Load response IO=1.5A→0.5A)
BD9150MUV (Load response IO=0.5A→1.5A)
VOUT
VOUT
IOUT
IOUT
Fig.24Transient response
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor.
ON resistance of Highside MOS FET : 170mΩ(Typ.)
ON resistance of Lowside MOS FET : 130mΩ(Typ.)
Achieves efficiency improvement for heavier load.
Efficiency η[%]
100
SLLM
②
50
①
PWM
①inprovement by SLLM system
②improvement by synchronous rectifier
0
0.001
Offers high efficiency for all load range with the improvements mentioned above.
0.01
0.1
Output current Io[A]
1
Fig.25 Efficiency
Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 22μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor
・Incorporates FET + Boot strap diode
Reduces a mounting area required.
VOUT1
L1
FB1
ITH1
RITH1
CITH1
SW1
SW1
PGND1
AGND
PVcc
PVcc
AVcc
PVcc
FB2
20mm
COUT1
COUT1 CIN1
CIN2
COUT2
PGND1
N.C.
ITH2
RITH2
CITH2
EN1
CIN1
15mm
CIN2
PGND2
EN2 SW2 SW2 PGND2
L1
COUT2
L2
RITH1 RITH2
R2
CITH1 CITH2
VOUT2
L2
R1
R2
R1
Fig.26 Example application
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2009.05 - Rev.A
Technical Note
BD9150MUV
●Operation
BD9150MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its
P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation
of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS
FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a
current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues
a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a lowside MOS
FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is
designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp,
it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF
and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching
dissipation and improves the efficiency.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
ITH
S
IL
Driver
Logic
VOUT
SW
Load
OSC
Fig.27 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
PVCC
SENSE
Current
Comp
FB
FB
SET
GND
SET
GND
RESET
GND
RESET
GND
SW
GND
SW
IL
GND
IL(AVE)
IL
0A
VOUT
VOUT
VOUT(AVE)
VOUT(AVE)
Not switching
Fig.28 PWM switching timing chart
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Fig.29 SLLM
7/18
TM
switching timing chart
2009.05 - Rev.A
Technical Note
BD9150MUV
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage
circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
100mV (Typ.) is provided to prevent output chattering.
Hysteresis 100mV
VCC
EN1,EN2
VOUT1, VOUT2
Tss
Tss
Tss
Soft start
Standby mode
Operating mode
UVLO
Standby
mode
Operating mode
UVLO
Standby
mode
EN
Operating mode
Standby mode
UVLO
Fig.30 Soft start, Shutdown, UVLO timing chart
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2009.05 - Rev.A
Technical Note
BD9150MUV
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN1＝EN2
Output Short circuit
Threshold Voltage
VOUT1
Output OFF
Latch
VOUT2
IL Limit
IL1
IL2
t2=TLATCH
t1<TLATCH
Operating mode
Standby
mode
Standby
mode
Timer latch
EN
Operating mode
EN
Fig.31 Short-current protection circuit with time delay timing chart
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET：PD(I R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
3)PD(SW)=
2
Vin ×CRSS×IOUT×f
IDRIVE
(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
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9/18
2009.05 - Rev.A
Technical Note
BD9150MUV
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage,
higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be
carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because
the conduction losses are considered to play the leading role among other dissipation mentioned above including gate
charge/discharge dissipation and switching dissipation.
4.5
2
① 4 layers (copper foil area : 5505mm )
(copper foil in each layers)
θj-a=32.1℃/W
2
② 4 layers (copper foil area : 10.29mm )
(copper foil in each layers)
θj-a=82.6℃/W
2
③ 1 layer (copper foil area : 0mm )
θj-a=160.1℃/W
④IC only
θj-a=249.5℃/W
4.0
Power dissipation:Pd [W]
①3.56W
3.0
2.0
②1.21W
1.0
③0.70W
④0.34W
0
0
25
50
75
100 105
125
150
Ambient temperature:Ta [℃]
Fig.32 Thermal derating curve
(VQFN020V4040)
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RONH：ON resistance of Highside MOS FET
RONL：ON resistance of Lowside MOS FET
IOUT：Output current
If VCC=5V, VOUT1=3.3V, VOUT2=1.2V, RONH=170mΩ, RONL=130mΩ
IOUT=1.5A, for example,
D1=VOUT1/VCC=3.3/5=0.66
D2=VOUT2/VCC=1.2/5=0.24
RON1=0.66×0.170+(1-0.66)×0.130
=0.1122+0.0442
=0.1564[Ω]
RON2=0.24×0.170+(1-0.24)×0.130
=0.0408+0.0988
=0.1397[Ω]
P=1.52×0.1564+1.52×0.1397=0.666[W]
As RONH is greater than RONL in this IC, the dissipation increases as the ON duty becomes greater.
consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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With the
2009.05 - Rev.A
Technical Note
BD9150MUV
●Selection of components externally connected
1. Selection of inductor (L)
IL
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
(VCC-VOUT)×VOUT
ΔIL=
[A]・・・(1)
L×VCC×f
ΔIL
VCC
IL
Appropriate ripple current at output should be 20% more or less of the
maximum output current.
VOUT
L
ΔIL=0.2×IOUTmax. [A]・・・(2)
Co
L=
Fig.33 Output ripple current
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5.0V, VOUT=1.2V, f=1.5MHz, ΔIL=0.2×1.5A=0.3A, for example,(BD9150MUV)
L=
(5-1.2)×1.2
0.3×5×1.5M
=2.02μ → 2.2[μH]
※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better
efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
VOUT
L
Output ripple voltage is determined by the equation (4)：
ESR
ΔVOUT=ΔIL×ESR [V]・・・(4)
Co
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
Fig.34 Output capacitor
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○
※Rating of the capacitor should be determined allowing sufficient margin against
output voltage. A 22μF to 100μF ceramic capacitor is recommended.
Less ESR allows reduction in output ripple voltage.
11/18
2009.05 - Rev.A
Technical Note
BD9150MUV
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (5):
Cin
VOUT
L
IRMS=IOUT×
Co
√VOUT(VCC-VOUT)
VCC
[A]・・・(5)
< Worst case > IRMS(max.)
When Vcc=2×VOUT, IRMS=
IOUT
2
If VCC=5.0V, VOUT=1.2V, and IOUTmax.=1.5A, (BD9150MUV)
Fig.35 Input capacitor
IRMS=2×
√1.2(5.0-1.2)
5.0
=0.85[ARMS]
A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due
to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency
area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power
amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
A
Gain
[dB]
0
fz(ESR)
IOUTMin.
Phase
[deg]
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
fp(Max.)
IOUTMax.
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
0
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.36 Open loop gain characteristics
A
fz(Amp.)
Gain
[dB]
[Hz] ←with heavier load
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
0
0
Phase
[deg]
-90
fz(Amp.)=
1
2π×RITH×CITH
Fig.37 Error amp phase compensation characteristics
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12/18
2009.05 - Rev.A
Technical Note
BD9150MUV
VOUT1
L1
FB1
EN1
SW1
SW1
ITH1
RITH1
CITH1
RITH2
CITH2
PGND1
RO1
PGND1
AGND
PVcc
N.C.
PVcc
AVcc
PVcc
ITH2
PGND2
FB2
ESR
COUT1
EN2 SW2 SW2 PGND2
CIN1
CIN2
COUT2
ESR
VOUT2
L2
R2
RO2
R1
Fig.38 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance
with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
=
1
2π×ROMax.×CO
5. Determination of output voltage
The output voltage VOUT is determined by the equation (6):
VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
L2
Output
SW2
FB2
Adjustable output voltage range : 0.8V～2.5V
Cout2
R2
R1
Fig.39 Determination of output voltage
Use 1 kΩ～100 kΩ resistor for R1. If a resistor of the resistance higher than 100 kΩ is used, check the assembled set
carefully for ripple voltage etc.
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13/18
2009.05 - Rev.A
Technical Note
BD9150MUV
●BD9150MUV
Cautions on PC Board layout
VOUT1
L1
FB1 EN1 SW1 SW1 PGND1
ITH1
RITH1
CITH1
RITH2
CITH2
COUT1
PGND1
AGND
PVcc
N.C.
PVcc
AVcc
PVcc
ITH2
PGND2
FB2
EN2 SW2 SW2 PGND2
CIN1
CIN2
COUT2
VOUT2
L2
R2
R1
Fig.40 Layout diagram
①
②
Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the
pin PGND.
Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
※
VQFN020V4040 (BD9150MUV) has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of
PCB.
●Recommended components Lists on above application
Symbol
L1,2
Part
Coil
Value
2.2uH
Manufacturer
TDK
Series
LTF5022-2R2N3R2
2.2uH
TDK
LTF5022-2R2N3R2
CIN1,CIN2
Ceramic capacitor
22uF
Murata
GRM32EB11A226KE20
Cout1,Cout2
Ceramic capacitor
22uF
Murata
GRM31CB30J226KE18
CITH1
Ceramic capacitor
330pF
Murata
CRM18 Serise
RITH1
Resistance
56kΩ
Rohm
MCR03 Serise
CITH2
RITH2
Ceramic capacitor
Resistance
VOUT=1.0V
330pF
Murata
CRM18 Serise
VOUT=1.2V
VOUT=1.5V
330pF
330pF
Murata
Murata
GRM18 Serise
GRM18 Serise
VOUT=1.8V
VOUT=2.5V
VOUT=1.0V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
VOUT=2.5V
330pF
330pF
39kΩ
47kΩ
56kΩ
75kΩ
91kΩ
Murata
Murata
Rohm
Rohm
Rohm
Rohm
Rohm
GRM18 Serise
GRM18 Serise
MCR03 Serise
MCR03 Serise
MCR03 Serise
MCR03 Serise
MCR03 Serise
※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and this IC when employing the depicted circuit with other circuit
constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC
pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
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14/18
2009.05 - Rev.A
Technical Note
BD9150MUV
●I/O equivalence circuit
【BD9150MUV】
・EN1,EN2 pin
・SW1,SW2
PVCC
PVCC
PVCC
EN1,EN2
SW1,SW2
・FB1,FB2 pin
・ITH1,ITH2 pin
AVCC
FB1,FB2
ITH1,ITH2
Fig.41 I/O equivalence circuit
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○
15/18
2009.05 - Rev.A
Technical Note
BD9150MUV
●Cautions on use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum
ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode
or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute
maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor
must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to
assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process,
be sure to turn OFF the power supply before it is connected and removed.
6. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 42.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner
that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of
parasitic elements.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
P
+
N
P
P
+
N
Parasitic
element
N
P+
P substrate
Parasitic element
GND
B
N
P
P
C
+
N
E
Parasitic
element
P substrate
Parasitic element
GND
GND
GND
Other adjacent elements
Fig.42 Simplified structure of monorisic IC
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16/18
2009.05 - Rev.A
Technical Note
BD9150MUV
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from
the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring
pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention
not to cause fluctuations in the GND wiring pattern of external parts as well.
8 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, in case output
voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output
voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection
will be activated and output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins
for variation between external devices and this IC, including transient as well as static characteristics. Furthermore, in any
case, it is recommended to start up the output with EN after supply voltage is within operation range.
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17/18
2009.05 - Rev.A
Technical Note
BD9150MUV
 Ordering part number
B
D
9
Part No.
1
5
0
M
Part No.
U
V
-
Package
MUV: VQFN020V4040
E
2
Packaging and forming specification
E2: Embossed tape and reel
VQFN020V4040
<Tape and Reel information>
4.0±0.1
4.0±0.1
2.1±0.1
1.0
0.4±0.1
1
6
16
10
15
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
5
20
0.5
2500pcs
(0.22)
S
C0.2
Embossed carrier tape
Quantity
11
2.1±0.1
0.08
S
+0.03
0.02 –0.02
1.0MAX
1PIN MARK
Tape
+0.05
0.25 –0.04
1pin
Reel
(Unit : mm)
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18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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