MOSFET Super mini DIP-IPM

<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
PSM03S93E5-A / PSM05S93E5-A
Table of contents
CHAPTER 1 INTRODUCTION .................................................................................................................................2
1.1 Features of MOSFET Super mini DIPIPM.............................................................................................................. 2
1.2 Functions ............................................................................................................................................................... 2
1.3 Target Applications ................................................................................................................................................. 3
1.4 Product Line-up...................................................................................................................................................... 3
CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS ...................................................................................4
2.1 MOSFET Super mini DIPIPM Specifications .......................................................................................................... 4
2.1.1 Maximum Ratings.................................................................................................................................................................................................... 4
2.1.2 Thermal Resistance ................................................................................................................................................................................................ 6
2.1.3 Electric Characteristics and Recommended Conditions ......................................................................................................................................... 7
2.1.4 Mechanical Characteristics and Ratings ................................................................................................................................................................. 9
2.2 Protective Functions and Operating Sequence .................................................................................................... 10
2.2.1 Short Circuit Protection ......................................................................................................................................................................................... 10
2.2.2 Control Supply UV Protection ............................................................................................................................................................................... 12
2.2.3 OT Protection ........................................................................................................................................................................................................ 14
2.3 Package Outlines ................................................................................................................................................. 15
2.3.1 Package outlines ................................................................................................................................................................................................... 15
2.3.2 Marking .................................................................................................................................................................................................................. 16
2.3.3 Terminal Description .............................................................................................................................................................................................. 17
2.4 Mounting Method ................................................................................................................................................. 19
2.4.1 Electric Spacing ..................................................................................................................................................................................................... 19
2.4.2 Mounting Method and Precautions ....................................................................................................................................................................... 19
2.4.3 Soldering Conditions ............................................................................................................................................................................................. 20
CHAPTER 3 SYSTEM APPLICATION GUIDANCE ................................................................................................21
3.1 Application Guidance ........................................................................................................................................... 21
3.1.1 System connection ................................................................................................................................................................................................ 21
3.1.2 Interface Circuit (Direct Coupling Interface example for using one shunt resistor) .............................................................................................. 22
3.1.3 Interface Circuit (Example of Opto-coupler Isolated Interface) ............................................................................................................................ 23
3.1.4 External SC Protection Circuit with Using Three Shunt Resistors ....................................................................................................................... 24
3.1.5 Circuits of Signal Input Terminals and Fo Terminal ............................................................................................................................................... 24
3.1.6 Snubber Circuit...................................................................................................................................................................................................... 26
3.1.7 Recommended Wiring Method around Shunt Resistor ........................................................................................................................................ 26
3.1.8 Precaution for Wiring on PCB ............................................................................................................................................................................... 28
3.1.9 Parallel operation of MOS DIPIPM ....................................................................................................................................................................... 29
3.1.10 SOA of MOS DIPIPM .......................................................................................................................................................................................... 29
3.1.11 SCSOA ................................................................................................................................................................................................................ 30
3.1.12 Power Life Cycles................................................................................................................................................................................................ 31
3.2 Power Loss and Thermal Dissipation Calculation ................................................................................................ 32
3.2.1 Power Loss Calculation......................................................................................................................................................................................... 32
3.2.2 Temperature Rise Considerations and Calculation Example ............................................................................................................................... 34
3.3 Noise and ESD Withstand Capability ................................................................................................................... 35
3.3.1 Evaluation Circuit of Noise Withstand Capability .................................................................................................................................................. 35
3.3.2 Countermeasures and Precautions ...................................................................................................................................................................... 35
3.3.3 Static Electricity Withstand Capability ................................................................................................................................................................... 36
CHAPTER 4 Bootstrap Circuit Operation ...............................................................................................................37
4.1 Bootstrap Circuit Operation .................................................................................................................................. 37
4.2 Bootstrap Supply Circuit Current at Switching State ............................................................................................ 38
4.3 Note for designing the bootstrap circuit ................................................................................................................ 39
CHAPTER 5 PACKAGE HANDLING ......................................................................................................................40
5.1 Packaging Specification ....................................................................................................................................... 40
5.2 Handling Precautions ........................................................................................................................................... 41
Publication Date:March 2014
1
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
CHAPTER 1 INTRODUCTION
1.1 Features of MOSFET Super mini DIPIPM
MOSFET Super mini DIPIPM (hereinafter called DIPIPM) is the transfer molding type intelligent power module
(IPM) which integrates power chips, drive and protection circuits in one package. It is favorable for
AC100-240Vinput class low power motor inverter control. Since DIPIPM integrates MOSFET as switching
power chip, it can realize low loss at low current operation. And also it has insulated sheet structure with very
low thermal resistance and ultra small package. Thanks to them, it is most suitable for inverterized refrigerator,
which continues to operate for long time at ultra low current. Main features of DIPIPM are as below.
・MOSFET are integrated for improving efficiency at low current.
・Incorporating bootstrap diode with current limiting resistor for P-side gate driving supply
・Easy to replace from current Ver.5 due to same pin compatibility and package
Fig.1-1-1 and Fig.1-1-2 show the outline and internal cross-section structure respectively.
Cu frame
Aluminum wire
MOSFET
Insulated thermal
radiating sheet
(Copper foil + insulated resin)
Fig.1-1-1 Package photograph
IC
Di
Gold wire
Mold resin
Fig.1-1-2 Internal cross-section structure
1.2 Functions
MOS DIPIPM has following functions and inner block diagram is described in Fig.1-2-1.
●
●
●
●
●
●
For P-side:
- Drive circuit;
- High voltage level shift circuit;
- Control supply under voltage (UV) lockout circuit (without fault signal output).
- Built-in bootstrap diode (BSD) with current limiting resistor
For N-side:
-Drive circuit;
-Short circuit (SC) protection circuit (by inserting external shunt resistor into main current path)
-Control supply under voltage (UV) lockout circuit (with fault signal output)
-Over temperature (OT) protection by monitoring LVIC temperature.
Fault Signal Output
-Corresponding to N-side MOSFET SC, N-side UV and OT protection.
MOSFET Drive Supply
-Single DC15V power supply (in the case of using bootstrap method)
Control Input Interface
-Schmitt-triggered 3V,5V input compatible, high active logic.
UL recognized : UL1557 File E323585
Publication Date: March 2014
2
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
Bootstrap Diode
with current limiting
resistor
MOSFET
HVIC
VP1
VCC
VUFB
VUB
UP
UP
VVFB
VVB
VP
VP
VWFB
VWB
WP
WP
VNC
COM
P
UOUT
VUS
U
VOUT
VVS
V
W OUT
VWS
W
LVIC
UOUT
VN1
VCC
UN
UN
VN
VN
WN
WN
Fo
Fo
NU
VOUT
NV
W OUT
NW
VNC
GND
CIN
CIN
Fig.1-2-1 Inner block diagram
1.3 Target Applications
Motor drives for household electric appliances, such as refrigerators
Low power industrial motor drive such a small fan control except automotive applications
1.4 Product Line-up
Table 1-4-1 MOS DIPIPM Line-up
Type Name (Note 1)
MOSFET Rating
Motor Rating (Note 2)
PSM03S93E5-A
3A/500V
0.2kW/220VAC
PSM05S93E5-A
5A/500V
0.4kW/220VAC
Note 1: Suffix ‘A’ indicates long pin shape. Please refer to chapter 2 for details.
Note 2: The motor ratings are simulation results. It will vary by operation conditions.
Publication Date: March 2014
3
Isolation Voltage
Viso = 1500Vrms
(Sine 60Hz, 1min
All shorted pins-heat sink)
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS
2.1 MOSFET Super mini DIPIPM Specifications
MOS DIPIPM specifications are described below by using PSM05S93E5 (5A/500V) as an example. Please
refer to respective datasheet for the detailed description of other types.
2.1.1 Maximum Ratings
The maximum ratings of PSM05S93E5 are shown in Table 2-1-1.
Table 2-1-1 Maximum Ratings
INVERTER PART
Ratings
Unit
VDD
Symbol
Supply voltage
Parameter
Applied between P-NU,NV,NW
Condition
400
V
VDD(surge)
Supply voltage (surge)
Applied between P-NU,NV,NW
450
V
VDSS
Drain-source voltage
±ID
Each MOSFET drain current
TC= 25°C
±IDP
Each MOSFET drain current (peak)
TC= 25°C, less than 1ms
PD
Drain dissipation
TC= 25°C, per 1 chip
Tch
Channel temperature
(Note 1)
(Note2)
500
V
5
A
10
A
35.7
W
-20~+150
°C
(1)
(2)
(3)
(4)
(5)
Note1: Pulse width and period are limited due to channel temperature.
Note2: The maximum channel temperature rating of built-in power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the
average channel temperature should be limited to Tch(Ave)≤125°C (@Tc≤100°C).
CONTROL (PROTECTION) PART
Condition
Ratings
VD
Symbol
Control supply voltage
Parameter
Applied between
VP1-VNC, VN1-VNC
20
Unit
V
VDB
Control supply voltage
Applied between
VUFB-U, VVFB-V, VWFB-W
20
V
V
VIN
Input voltage
Applied between
UP, VP, W P-VPC, UN, VN, W N-VNC
-0.5~VD+0.5
VFO
Fault output supply voltage
Applied between
FO-VNC
-0.5~VD+0.5
V
IFO
Fault output current
Sink current at FO terminal
1
mA
VSC
Current sensing input voltage
Applied between CIN-VNC
-0.5~VD+0.5
V
Ratings
Unit
400
V
TOTAL SYSTEM
Symbol
TC
Parameter
Self protection supply voltage limit
(Short circuit protection capability)
Module case operation temperature
Tstg
Storage temperature
Viso
Isolation voltage
VDD(PROT)
Condition
VD = 13.5~16.5V, Inverter Part
Tch = 125°C, non-repetitive, less than 2μs
Measurement point of Tc is provided in Fig.1
60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate
-20~+100
°C
-40~+125
°C
1500
Vrms
(6)
(7)
Tc measurement position
Control terminals
11.6mm
(8)
3mm
MOSFET chip position
Tc point
Heat sink side
Power terminals
(1)
VDD
(2)
VDD(surge)
(3)
(4)
VDSS
±ID
(5)
Tch
Maximum voltage can be biased between P-N. A voltage suppressing circuit such as a brake
circuit is necessary if P-N voltage exceeds this value.
Maximum P-N surge voltage in switching state. If P-N voltage exceeds this voltage, a snubber
circuit is necessary to absorb the surge so that the surge voltage is kept under this voltage.
Maximum sustained drain-source voltage of built-in MOSFET
Allowable DC current flowing at drain electrode (Tc=25°C) Pulse width and period are limited
due to junction temperature Tch.
Maximum channel temperature rating is 150°C.But for safe operation, it is recommended to
limit the average channel temperature up to 125°C. Repetitive temperature variation ΔTch
affects life time of power cycle.
Publication Date: March 2014
4
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
(6)
VDD(PROT)
(7)
Isolation
voltage
Maximum supply voltage for turning off MOSFET safely in the case of an SC or OC fault. The
power chip might be damaged if supply voltage exceeded this specification.
Isolation voltage of Super mini DIPIPM is the voltage between all shorted pins and copper
surface of DIPIPM. The maximum rating of isolation voltage of Super mini DIPIPM is 1500Vrms.
But if such as convex shape heat radiation fin will be used for enlarging clearance between
outer terminals and heat radiation fin (2.5mm or more is recommended), it is able to correspond
isolation voltage 2500Vrms. Super mini DIPIPM is recognized by UL at the condition 2500Vrms
with convex shape heat radiation fin.
Heat radiation part (Cu surface)
min 1.45
（3.0）
（1.9）
min 1.05
min 2.5
Heat radiation fin
Fig.2-1-1 In the case of using convex fin (unit: mm)
(8)
Tc position
Tc (case temperature) is defined to be the temperature just beneath the specified power chip.
Please mount a thermocouple on the heat sink surface at the defined position to get accurate
temperature information. Due to the control schemes such different control between P and
N-side, there is the possibility that highest Tc point is different from above point. In such cases, it
is necessary to change the measuring point to that under the highest power chip.
[Power chip position]
Fig.2-1-2 indicates the position of the each power chips. (This figure is the view from laser marked side.)
Dimension in mm
WN
VN
UN
WP VP UP
Fig.2-1-2 Power chip position
Publication Date: March 2014
5
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.1.2 Thermal Resistance
Table 2-1-2 shows the thermal resistance of PSM05S93E5.
Table 2-1-2 Thermal resistance of PSM05S93E5
THERMAL RESISTANCE
Symbol
Rth(ch-c)Q
Parameter
Junction to case thermal resistance
Condition
(Note)
Min.
-
1/6 module
Limits
Typ.
-
Max.
2.8
Unit
K/W
Note : Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface
of DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and
the thermal conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal
conductivity: 1.0W/m•k).
The above data shows the thermal resistance between chip channel and case at steady state. The thermal
resistance goes into saturation in about 10 seconds. The unsaturated thermal resistance is called as
transient thermal impedance which is shown in Fig.2-1-3. Zth(j-c)* is the normalized value of the transient
thermal impedance. (Zth(j-c)*= Zth(j-c) / Rth(j-c)max)
For example, the MOSFET transient thermal impedance of PSM05S93E5 in 0.3s is 2.8×0.8=2.2K/W.
The transient thermal impedance isn’t used for constantly current, but for short period current (ms order).
(e.g. In the cases at motor starting, at motor lock･･･)
Thermal impedance Zth(ch-c)
1.0
0.1
0.01
0.1
1
Time(s)
Fig.2-1-3 Typical transient thermal impedance
Publication Date: March 2014
6
10
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.1.3 Electric Characteristics and Recommended Conditions
Table 2-1-3 shows the typical static characteristics and switching characteristics of PSM05S93E5.
Table 2-1-3 Static characteristics and switching characteristics of PSM05S93E5
INVERTER PART (Tch = 25°C, unless otherwise noted)
Symbol
VDS(on)
VSD
ton
tC(on)
toff
tC(off)
trr
IDSS
Parameter
Condition
Drain-source on-state
resistance
VD=VDB = 15V, VIN= 5V, ID= 5A
Source-drain voltage drop
VIN= 0V, -ID= 5A
Switching times
VDD= 300V, VD= VDB= 15V
ID= 5A, Tch= 125°C, VIN= 0↔5V
Inductive Load (upper-lower arm)
Drain-source cut-off
current
VDS=VDSS
Min.
0.65
-
Tch= 25°C
Tch= 125°C
Tch= 25°C
Tch= 125°C
Limits
Typ.
0.60
1.30
0.90
1.15
0.35
1.00
0.10
0.25
-
Max.
0.80
1.70
1.30
1.65
0.55
1.50
0.20
1
10
Unit
Ω
V
μs
μs
μs
μs
μs
mA
Switching time definition and performance test method are shown in Fig.2-1-4 and 2-1-5.
Switching characteristics are measured by half bridge circuit with inductance load.
VUFB,VVFB,VWFB
trr
VCE
Irr
Ic
90%
90%
VP1
P-side SW
input signal
UP,VP,W P
VCC
IN
COM
10%
10%
tc(on)
10%
10%
tc(off)
VCIN
td(on)
tr
( ton=td(on)+tr )
VD
N-side SW
input signal
VN1
UN,VN,W N
VNC
P
VB
L-load
HO
N-side
VS
U,V,W
VCC
IN
GND
P-side
VDD
L- load
LO
NU,NV,NW
CIN
td(off)
tf
( toff=td(off)+tf )
Fig.2-1-4 Switching time definition
Turn on
VIN(5V⇔0V)
VDB
CIN
ID
Fig.2-1-5 Evaluation circuit (inductive load)
Short A for N-side MOSFET, and short B for P-side MOSFET evaluation
t:200ns/div
Turn off
ID(2A/div)
t:200ns/div
VDS(100V/div)
VDS(100V/div)
ID(2A/div)
Fig.2-1-6 Typical switching waveform (PSM05S93E5)
Conditions: VDD=300V, VD=VDB=15V, Tch=25°C, ID=5A, Inductive load half-bridge circuit
Publication Date: March 2014
7
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
Table 2-1-4 shows the typical control part characteristics of PSM05S93E5.
Table 2-1-4 Control (Protection) characteristics of PSM05S93E5
CONTROL (PROTECTION) PART (Tch = 25°C, unless otherwise noted)
Symbol
Parameter
ID
Condition
VD=15V, VIN=0V
VD=15V, VIN=5V
VD=VDB=15V, VIN=0V
VD=VDB=15V, VIN=5V
Total of VP1-VNC, VN1-VNC
Circuit current
Each part of VUFB-U,
VVFB-V, VWFB-W
IDB
VSC(ref)
UVDBt
UVDBr
UVDt
UVDr
OTt
OTrh
VFOH
VFOL
tFO
IIN
Vth(on)
Vth(off)
Vth(hys)
VF
R
Short circuit trip level
VD = 15V
P-side Control supply
under-voltage protection(UV)
Trip level
Reset level
Tch ≤125°C
Trip level
Reset level
VD = 15V
Trip level
Detect LVIC temperature
Hysteresis of trip-reset
VSC = 0V, FO terminal pulled up to 5V by 10kΩ
VSC = 1V, IFO = 1mA
N-side Control supply
under-voltage protection(UV)
Overt temperature protection
(Note2)
Fault output voltage
(Note 1)
Fault output pulse width
Input current
ON threshold voltage
OFF threshold voltage
ON/OFF threshold
hysteresis voltage
Bootstrap Di forward voltage
IF=10mA including voltage drop by limiting resistor
Built-in limiting resistance
Included in bootstrap Di
(Note 3)
VIN = 5V
Applied between UP, VP, WP, UN, VN, WN-VNC
Min.
0.43
7.0
7.0
10.3
10.8
100
4.9
20
0.70
0.80
Limits
Typ.
0.48
10.0
10.0
120
10
1.00
2.10
1.30
Max.
2.80
2.80
0.10
0.10
0.53
12.0
12.0
12.5
13.0
140
0.95
1.50
2.60
-
0.35
0.65
-
1.1
80
1.7
100
2.3
120
Unit
mA
V
V
V
V
V
°C
°C
V
V
μs
mA
V
V
Ω
Note 1 : SC protection works only for N-side MOSFET. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current
rating.
Note 2 : When the LVIC temperature exceeds OT trip temperature level(OTt), OT protection works and Fo outputs. In that case if the heat sink dropped off or fixed
loosely, don't reuse that DIPIPM. (There is a possibility that channel temperature of power chips exceeded maximum Tch(150°C).
3 : Fault signal Fo outputs when SC, UV or OT protection works. Fo pulse width is different for each protection modes. At SC failure, Fo pulse width is a fixed
width (=minimum 20μs), but at UV or OT failure, Fo outputs continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)
Recommended operating conditions of PSM05S93E5 are given in Table 2-1-5.
Although these conditions are the recommended but not the necessary ones, it is highly recommended to
operate the modules within these conditions so as to ensure MOS DIPIPM safe operation.
Table 2-1-5 Recommended operating conditions of PSM05S93E5
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VDD
VD
VDB
ΔVD, ΔVDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
IO
Allowable r.m.s. current
Limits
Typ.
300
15.0
15.0
-
Max.
400
16.5
18.5
+1
20
fPWM= 5kHz
-
-
2.5
fPWM= 15kHz
-
-
2.0
0.7
0.7
-5.0
-20
-
+5.0
+125
Applied between P-NU, NV, NW
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
For each input signal
TC ≤ 100°C, Tch ≤ 125°C
VDD = 300V, VD = 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tch ≤ 125°C
(Note1)
PWIN(on)
PWIN(off)
VNC
Tch
Min.
0
13.5
13.0
-1
1.0
-
Condition
Minimum input pulse width
VNC variation
Channel temperature
(Note 2)
Between VNC-NU, NV, NW (including surge)
Unit
V
V
V
V/μs
μs
kHz
Arms
Note 1: Allowable r.m.s. current depends on the actual application conditions.
2: DIPIPM might not make response if the input signal pulse width is less than PWIN(on), PWIN(off).
About Control supply variation
If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous
operation. To avoid such problem, line ripple voltage should meet the following specifications:
dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p
Publication Date: March 2014
8
μs
V
°C
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.1.4 Mechanical Characteristics and Ratings
The mechanical characteristics and ratings are shown in Table 2-1-6.
Please refer to Section 2.4 for the detailed mounting instruction of MOS DIPIPM.
Table 2-1-6 Mechanical characteristics and ratings of PSM05S93E5
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Mounting torque
Terminal pulling strength
Terminal bending strength
Min.
0.59
Limits
Typ.
0.69
Max.
0.78
N·m
EIAJ-ED-4701
10
-
-
s
EIAJ-ED-4701
2
-
-
times
-
8.5
-
g
-50
-
100
μm
Condition
Mounting screw : M3 (Note 1)
Control terminal: Load 4.9N
Power terminal: Load 9.8N
Control terminal: Load 2.45N
Power terminal: Load 4.9N
90deg. bend
Recommended 0.69N·m
Weight
Heat-sink flatness
(Note 2)
Note 1: Plain washers (ISO 7089~7094) are recommended.
Note 2: Measurement point of heat sink flatness
+ -
Measurement position
4.6mm
17.5mm
Heat sink side
-
+
Heat sink side
Publication Date: March 2014
9
Unit
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.2 Protective Functions and Operating Sequence
MOS DIPIPM has Short circuit (SC), Under Voltage of control supply (UV) and Over Temperature (OT) for
protection function. The operating principle and sequence are described below.
2.2.1 Short Circuit Protection
1. General
DIPIPM uses external shunt resistor for the current detection as shown in Fig.2-2-1. The internal protection
circuit inside the IC captures the excessive large current by comparing the CIN voltage generated at the shunt
resistor with the referenced SC trip voltage, and perform protection automatically. The threshold voltage trip
level of the SC protection Vsc(ref) is typ. 0.48V.
In case of SC protection happens, all the gates of N-side three phase MOSFETs are interrupted together
with fault signal output. To prevent DIPIPM erroneous protection due to normal switching noise and/or recovery
current, it is necessary to set an RC filter (time constant: 1.5μ~2μs is recommended) to the CIN terminal input
(Fig.2-2-1, 2-2-2). Also, please make the pattern wiring around the shunt resistor as short as possible.
Gate Drive circuit
P-side MOSFETs
Drain current ID
P
U
V
W
N-side MOSFETs
SC Protection External Parts
Shunt resistor
N1
C
R
SC protective level
N
VNC
Drain
current
Gate Drive circuit
CIN
0
SC protection
2
Input pulse width tw (μs)
DIPIPM
Fig.2-2-1 SC protecting circuit
Fig.2-2-2 Filter time constant setting
2. SC protection Sequence
SC protection (N-side only with the external shunt resistor and RC filter)
a1. Normal operation: MOSFET ON and carrying current.
a2. Short circuit current detection (SC trigger).
(It is recommended to set RC time constant 1.5~2.0μs so that MOSFET shut down within 2.0μs when SC.)
a3. All N-side MOSFETs’ gate are hard interrupted.
a4. All N-side MOSFETs turn OFF.
a5. Fo outputs for tFo=minimum 20μs.
a6. Input = “L”. MOSFET OFF
a7. Fo finishes output, but MOSFETs don't turn on until inputting next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: MOSFET ON and outputs current.
Lower-side control
input
a6
SET
Protection circuit state
RESET
a3
Internal MOSFET gate
a4
SC trip current level
Output current ID
a8
a1
a2
Sense voltage of
the shunt resistor
a7
SC reference voltage
Delay by RC filtering
Error output Fo
a5
Fig.2-2-3 SC protection timing chart
Publication Date: March 2014
10
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3. Determination of Shunt Resistance
(1) Shunt resistance
The value of current sensing resistance is calculated by the following expression:
RShunt = VSC(ref)/SC
where VSC(ref) is the referenced SC trip voltage.
The maximum SC trip level SC(max) should be set less than the MOSFET minimum saturation current
which is 1.7 times as large as the rated current. For example, the SC(max) of PSM05S93E5 should be set to
5A x1.7=8.5A. The parameters (VSC(ref), RShunt) dispersion should be considered when designing the SC trip
level.
For example of PSM05S93E5, there is +/-0.05V dispersion in the spec of VSC(ref) as shown in Table 2-2-1.
Table 2-2-1 Specification for VSC(ref)
Condition
at Tch=25°C, VD=15V
(unit: V)
Min
0.43
Typ
0.48
Max
0.53
Then, the range of SC trip level can be calculated by the following expressions:
RShunt(min)=VSC(ref) max /SC(max)
RShunt(typ)= RShunt(min) / 0.95* then SC(typ) = VSC(ref) typ / RShunt(typ)
RShunt(max)= RShunt(typ) x 1.05* then SC(min)= VSC(ref) min / RShunt(max)
*)This is the case that shunt resistance dispersion is within +/-5%.
So the SC trip level range is described as Table 2-2-2.
Table 2-2-2 Operative SC Range (RShunt=62.4mΩ (min), 65.7mΩ (typ), 69.0mΩ(max)
Condition
at Tch=25°C
min.
6.2A
typ.
7.3A
Max.
8.5A
(e.g. 62.4mΩ (Rshunt(min))= 0.53V (=VSC(max)) / 8.5A(=SC(max))
There is the possibility that the actual SC protection level becomes less than the calculated value. This is
considered due to the resonant signals caused mainly by parasitic inductance and parasitic capacity. It is
recommended to make a confirmation of the resistance by prototype experiment.
(2) RC Filter Time Constant
It is necessary to set an RC filter in the SC sensing circuit in order to prevent malfunction of SC protection
due to noise interference. The RC time constant is determined depending on the applying time of noise
interference and the SCSOA of the DIPIPM.
When the voltage drop on the external shunt resistor exceeds the SC trip level, The time (t1) that the CIN
terminal voltage rises to the referenced SC trip level can be calculated by the following expression:
VSC = R shunt ⋅ I c ⋅ (1 − ε
t1 = −τ ⋅ ln(1 −
−
t1
τ
)
VSC
)
R shunt ⋅ I c
Vsc : the CIN terminal input voltage, Ic : the peak current, τ : the RC time constant
On the other hand, the typical time delay t2 (from Vsc voltage reaches Vsc(ref) to MOSFET gate
shutdown) of IC is shown in Table 2-2-3.
Table 2-2-3 Internal time delay of IC
Item
min
IC transfer delay time
-
typ
-
max
0.5
Unit
μs
Therefore, the total delay time from an SC level current happened to the MOSFET gate shutdown
becomes:
tTOTAL=t1+t2
Publication Date: March 2014
11
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.2.2 Control Supply UV Protection
The UV protection is designed to prevent unexpected operating behavior as described in Table 2-2-4.
Both P-side and N-side have UV protecting function. However, fault signal (Fo) output only corresponds to
N-side UV protection. Fo output continuously during UV state.
In addition, there is a noise filter (typ. 10μs) integrated in the UV protection circuit to prevent instantaneous
UV erroneous trip. Therefore, the control signals are still transferred in the initial 10μs after UV happened.
Table 2-2-4 DIPIPM operating behavior versus control supply voltage
Control supply voltage
Operating behavior
In this voltage range, built-in control IC may not work properly.
Normal operating of each protection function (UV, Fo output etc.) is
not also assured.
0-4.0V (P, N)
Normally MOSFET does not work. But external noise may cause
DIPIPM malfunction (turns ON), so DC-link voltage need to start up
after control supply starts-up.
UV function becomes active and output Fo (N-side only).
4.0-UVDt (N), UVDBt (P)
Even if control signals are applied, MOSFET does not work
MOSFET can work. However, conducting loss and switching loss will
UVDt (N)-13.5V
UVDBt (P)-13.0V
increase, and result extra temperature rise at this state,.
13.5-16.5V (N)
Recommended conditions.
13.0-18.5V (P)
MOSFET works. However, switching speed becomes fast and
16.5-20.0V (N)
saturation current becomes large at this state, increasing SC broken
18.5-20.0V (P)
risk.
20.0V- (P, N)
The control circuit will be destroyed.
Ripple Voltage Limitation of Control Supply
If high frequency noise superimposed to the control supply line, IC malfunction might happen and
cause DIPIPM erroneous operation. To avoid such problem happens, line ripple voltage should meet the
following specifications:
dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p
Publication Date: March 2014
12
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
[N-side UV Protection Sequence]
a1. Control supply voltage V D exceeds under voltage reset level (UVDr), but MOSFET turns ON by
next ON signal (LH).(MOSFET of each phase can return to normal state by inputting ON signal to each
phase.)
a2. Normal operation: MOSFET ON and carrying current.
a3. VD level dips to under voltage trip level. (UVDt).
a4. All N-side MOSFETs turn OFF in spite of control input condition.
a5. Fo outputs for tFo=minimum 20μs, but output is extended during VD keeps below UVDr.
a6. VD level reaches UVDr.
a7. Normal operation: MOSFET ON and outputs current.
Control input
RESET
Protection circuit state
Control supply voltage VD
UVDr
RESET
SET
a1
UVDt
a6
a3
a7
a4
a2
Output current Ic
a5
Error output Fo
Fig.2-2-4 Timing chart of N-side UV protection
[P-side UV Protection Sequence]
a1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr,
MOSFET turns on by next ON signal (LH).
a2. Normal operation: MOSFET ON and outputs current.
a3. VDB level dips to under voltage trip level (UVDBt).
a4. MOSFET of the correspond phase only turns OFF in spite of control input signal level,
but there is no FO signal output.
a5. VDB level reaches UVDBr.
a6. Normal operation: MOSFET ON and outputs current.
Control input
Protection circuit state
RESET
SET
a1
UVDBt
UVDBr
Control supply voltage VDB
a2
RESET
a3
a5
a6
c4
Output current Ic
Error output Fo
Keep High-level (no fault output)
Fig.2-2-5 Timing Chart of P-side UV protection
Publication Date: March 2014
13
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.2.3 OT Protection
DIPIPM series have OT (over temperature) protection function by monitoring LVIC temperature rise.
While LVIC temperature exceeds and keeps over OT trip temperature, error signal Fo outputs and all N-side
MOSFETs are shut down without reference to input signal. (P-side MOSFETs are not shut down)
The specification of OT trip temperature and its sequence are described in Table 2-2-5 and Fig.2-2-6.
Table 2-2-5 OT trip temperature specification
Item
Symbol
OTt
OTrh
Over temperature
protection
Condition
Trip level
Trip/reset hysteresis
Min.
100
-
VD=15V,
At temperature of LVIC
Typ.
120
10
Max.
140
-
Unit
°C
[OT Protection Sequence]
a1. Normal operation: MOSFET ON and outputs current.
a2. LVIC temperature exceeds over temperature trip level(OTt).
a3. All N-side MOSFETs turn OFF in spite of control input condition.
a4. Fo outputs for tFo=minimum 20μs, but output is extended during LVIC temperature keeps over OTt.
a5. LVIC temperature drops to over temperature reset level.
a6. Normal operation: MOSFET turns on by next ON signal (LH).
(MOSFET of each phase can return to normal state by inputting ON signal to each phase.)
Control input
SET
Protection circuit state
OTt
RESET
a2
a5
Temperature of LVIC
a1
a3
OTt - OTrh
a6
Output current Ic
a4
Error output Fo
Fig.2-2-6 Timing Chart of OT protection
MOSFET
←LVIC
(Detecting point)
LVIC
Power Chip Area
Heatsink
Fig.2-2-7 Temperature detecting point
Temperature of
LIVC is affected
from heatsink.
Fig.2-2-8 Thermal conducting from power chips
Precaution about this OT protection function
(1)This OT protection will not work effectively in the case of rapid temperature rise like motor lock or over
current. (This protection monitors LVIC temperature, so it cannot respond to rapid temperature rise of
power chips.)
(2)If the cooling system is abnormal state (e.g. heat sink comes off, fixed loosely, or cooling fun stops)
when OT protection works, can't reuse the DIPIPM. (Because the channel temperature of power chips
will exceeded the maximum rating of Tch(150°C).)
Publication Date: March 2014
14
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.3 Package Outlines
Fig.2-3-1 Package outline drawing
Publication Date: March 2014
15
QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries.
(Note: Connect only one VNC terminal to the system GND and leave another one open)
Dimensions in mm
2.3.1 Package outlines
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.3.2 Marking
The laser marking specification of DIPIPM is described in Fig.2-3-2. Mitsubishi Corporate crest, Type name,
Lot number, and QR code mark are marked in the upper side of module.
Lot number
Fig.2-3-2 Laser marking view
The Lot number indicates production year, month, running number and country of origin.
The detailed is described as below.
(Example)
H 3 9 AA1
Running number
Product month (however O: October, N: November, D: December)
Last figure of Product year (e.g. 2013)
Factory identification
No mark : Manufactured at the factory in Japan
C
: Manufactured at the factory A in China
H
: Manufactured at the factory B in China
Publication Date: March 2014
16
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.3.3 Terminal Description
Table 2-3-1 Terminal description
Pin
1-A
Name
2
(VNC)*
1-B
(VP1)*
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VUFB
VVFB
VWFB
UP
VP
WP
VP1
1
VNC*
UN
VN
WN
VN1
FO
CIN
1
VNC*
NC
18
19
20
21
22
23
24
25
NW
NV
NU
W
V
U
P
NC
2
Description
Inner used terminal
It has control GND potential, so it should be left no connection.
Inner used terminal
It has control supply potential, so it should be left no connection.
U-phase P-side drive supply positive terminal
V-phase P-side drive supply positive terminal
W-phase P-side drive supply positive terminal
U-phase P-side control input terminal
V-phase P-side control input terminal
W-phase P-side control input terminal
P-side control supply positive terminal
P-side control supply GND terminal
U-phase N-side control input terminal
V-phase N-side control input terminal
W-phase N-side control input terminal
N-side control supply positive terminal
Fault signal output terminal
SC trip voltage detecting terminal
N-side control supply GND terminal
No connection
(There isn't any connection inside DIPIPM.)
WN-phase MOSFET emitter
VN-phase MOSFET emitter
UN-phase MOSFET emitter
W-phase output terminal(W-phase drive supply GND)
V-phase output terminal (V-phase drive supply GND)
U-phase output terminal (U-phase drive supply GND)
Inverter DC-link positive terminal
No connection (There isn't any connection inside DIPIPM.)
*1) Connect only one VNC terminal to the system GND and leave another one open.
*2) No.1-A,1-B are inner used terminals, so it is necessary to leave no connection.
Publication Date: March 2014
17
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
Table 2-3-2 Detailed description of input and output terminals
Item
Symbol
Description
• Drive supply terminals for P-side MOSFETs.
• By mounting bootstrap capacitor, individual isolated power supplies are not
needed for the P-side MOSFET drive. Each bootstrap capacitor is charged
by the N-side VD supply when potential of outpurt terminal is almost GND
P-side drive supply
positive terminal
level.
VUFB-U
• Abnormal operation might happen if the VD supply is not aptly stabilized or
VVFB-V
has insufficient current capability due to ripple or surge. In order to prevent
P-side drive supply VWFB-W
malfunction, a bypass capacitor with favorable frequency and temperature
GND terminal
characteristics should be mounted very closely to each pair of these
terminals.
• Inserting a Zener diode (24V/1W) between each pair of control supply
terminals is helpful to prevent control IC from surge destruction.
• Control supply terminals for the built-in HVIC and LVIC.
P-side control
• In order to prevent malfunction caused by noise and ripple in the supply
voltage, a bypass capacitor with favorable frequency characteristics should
supply terminal
be mounted very closely to these terminals.
VP1
VN1
• Carefully design the supply so that the voltage ripple caused by noise or by
system operation is within the specified minimum limitation.
N-side control
• It is recommended to insert a Zener diode (24V/1W) between each pair of
supply terminal
control supply terminals to prevent surge destruction.
• Control ground terminal for the built-in HVIC and LVIC.
• Ensure that line current of the power circuit does not flow through this
N-side control
VNC
terminal in order to avoid noise influences.
GND terminal
• Connect only one VNC terminal (9 or 16pin) to the GND, and leave another
one open.
• Control signal input terminals.Voltage input type.
• These terminals are internally connected to Schmitt trigger circuit.
UP,VP,W P
Control input
• The wiring of each input should be as short as possible to protect the
DIPIPM from noise interference.
terminal
UN,VN,W N
• Use RC filter in case of signal oscillation. (Pay attention to threshold voltage
of input terminal, because input circuit has pull down resistor (min 3.3kΩ))
Short-circuit trip
• For inverter part SC protection, input the potential of shuint resistor to CIN
terminal through RC filter (for the noise immunity).
voltage detecting
CIN
• The time constant of RC filter is recommended to be up to 2μs.
terminal
• Fault signal output terminal.
Fault signal output
• Fo signal line should be pulled up to a 5V logic supply with over 5kΩ resistor
FO
terminal
(for limitting the Fo sink current IFo up to 1mA.) Normally 10kΩ is
recommended.
• DC-link positive power supply terminal.
• Internally connected to the collectors of all P-side MOSFETs.
Inverter DC-link
• To suppress surge voltage caused by DC-link wiring or PCB pattern
P
positive terminal
inductance, smoothing capacitor should be located very closely to the P and
N terminal of DIPIPM. It is also effective to add small film capacitor with
good frequency characteristics.
• Open emitter terminal of each N-side MOSFET
Inverter DC-link
NU,NV,NW • Usually, these terminals are connected to the power GND through individual
negative terminal
shunt resistor.
• Inverter output terminals for connection to inverter load (e.g. motor).
Inverter power
• Each terminal is internally connected to the intermidiate point of the
U, V, W
output terminal
corresponding MOSFET half bridge arm.
Note: Use oscilloscope to check voltage waveform of each power supply terminals and P&N terminals, the time division of OSC
should be set to about 1μs/div. Please ensure the voltage (including surge) not exceed the specified limitation.
Publication Date: March 2014
18
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.4 Mounting Method
This section shows the electric spacing and mounting precautions of MOS DIPIPM.
2.4.1 Electric Spacing
The electric spacing specification of DIPIPM is shown in Table 2-4-1
Table 2-4-1 Minimum insulation distance of DIPIPM
Between live terminals with high potential
Between terminals and heat sink
Clearance (mm)
2.50
1.45
Creepage (mm)
3.00
1.50
2.4.2 Mounting Method and Precautions
When installing the module to the heat sink, excessive or uneven fastening force might apply stress to inside chips.
Then it will lead to a broken or degradation of the chips or insulation structure. The recommended fastening
procedure is shown in Fig.2-4-1. When fastening, it is necessary to use the torque wrench and fasten up to the
specified torque. And pay attention not to have any foreign particle on the contact surface between the module and
the heat sink. Even if the fixing of heatsink was done by proper procedure and condition, there is a possibility of
damaging the package because of tightening by unexpected excessive toruque or tucking particle. For ensuring
safety it is recommended to conduct the confirmation test(e.g. insulation inspection) on the final product after fixing
the DIPIPM with the heatsink.
(2)
Temporary fastening
(1)→(2)
(1)
Permanent fastening
(1)→(2)
Note: Generally, the temporary fastening torque is
set to 20-30% of the maximum torque rating.
Not care the order of fastening (1) or (2), but need
to fasten alternately.
Fig.2-4-1 Recommended screw fastening order
Table 2-4-2 Mounting torque and heat sink flatness specifications
Item
Condition
Min.
Mounting torque
Recommended 0.69N·m, Screw : M3
0.59
Flatness of outer heat sink
Refer Fig.2-4-2
-50
Note : Recommend to use plain washer (ISO7089-7094) in fastening the screws.
Measurement part
for heat sink flatness
-+
Typ.
-
Max.
0.78
+100
Unit
N·m
μm
+
Measurement part
for heat sink flatness
Outer heat sink
Fig.2-4-2 Measurement point of heat sink flatness
In order to get effective heat dissipation, it is necessary to enlarge the contact area as much as possible to
minimize the contact thermal resistance. Regarding the heat sink flatness (warp/concavity and convexity) on the
module installation surface, the surface finishing-treatment should be within Rz12.
Evenly apply thermally-conductive grease with 100μ-200μm thickness over the contact surface between a
module and a heat sink, which is also useful for preventing corrosion. Furthermore, the grease should be with
stable quality and long-term endurance within wide operating temperature range. The contacting thermal
resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness:
20μm, thermal conductivity: 1.0W/m·k). When applying grease and fixing heat sink, pay attention not to take air into
grease. It might lead to make contact thermal resistance worse or loosen fixing in operation.
Publication Date: March 2014
19
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
2.4.3 Soldering Conditions
The recommended soldering condition is mentioned as below.
(Note: The reflow soldering cannot be recommended for DIPIPM.)
(1) Flow (wave) Soldering
MOS DIPIPM is tested on the condition described in Table 2-4-3 about the soldering thermostability, so
the recommended conditions for flow (wave) soldering are soldering temperature is up to 265°C and the
immersion time is within 11s.
However, the condition might need some adjustment based on flow condition of solder, the speed of the
conveyer, the land pattern and the through hole shape on the PCB, etc.
It is necessary to confirm whether it is appropriate or not for your real PCB finally.
Table 2-4-3 Reliability test specification
Item
Condition
Soldering thermostability
260±5°C, 10±1s
(2) Hand soldering
Since the temperature impressed upon the DIPIPM may changes based on the soldering iron types
(wattages, shape of soldering tip, etc.) and the land pattern on PCB, the unambiguous hand soldering
condition cannot be decided.
As a general requirement of the temperature profile for hand soldering, the temperature of the root of the
DIPIPM terminal should be kept under 150°C for considering glass transition temperature (Tg) of the
package molding resin and the thermal withstand capability of internal chips. Therefore, it is necessary to
check the DIPIPM terminal root temperature, solderability and so on in your real PCB, when configure the
soldering temperature profile. (It is recommended to set the soldering time as short as possible.)
For reference, the evaluation example of hand soldering with 50W soldering iron is described as below.
[Evaluation method]
a. Sample: Super mini DIPIPM (Short lead type)
b. Evaluation procedure
- Put the soldering tip of 50W iron (temperature set to 350/400°C) on the terminal within 1mm from the toe.
(The lowest heat capacity terminal (=control terminal) is selected.)
- Measure the temperature rise of the terminal root part by the thermocouple installed on the terminal root.
1mm
200
Temp. of terminal root (°C)
Soldering iron
150
100
50
350°C
400°C
0
Thermocouple
DIPIPM
Fig.2-4-3 Heating and measuring point
0
5
10
15
Heating time (s)
Fig.2-4-4 Temperature alteration of the terminal root (Example)
[Note]
For soldering iron, it is recommended to select one for semiconductor soldering (12~24V low voltage type,
and the earthed iron tip) and with temperature adjustment function.
Publication Date: March 2014
20
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
CHAPTER 3 SYSTEM APPLICATION GUIDANCE
3.1 Application Guidance
This chapter states the MOS DIPIPM application method and interface circuit design hints.
3.1.1 System connection
C1: Electrolytic type with good temperature and frequency
characteristics.
Note: the capacitance also depends on the PWM control
strategy of the application system
C2:0.22μ-2μF ceramic capacitor with good temperature,
frequency and DC bias characteristics
C3: For snubber, 0.1μ-0.22μF capacitor (e.g. film capacitor)
D1:Zener diode 24V/1W for surge absorber
P-side input(PWM)
Input signal
conditioning
Input signal
conditioning
Input signal
conditioning
Level shift
Level shift
Level shift
UV lockout
circuit
Inrush limiting circuit
Drive circuit
UV lockout
circuit
Drive circuit
C2
C1
D1
UV lockout
circuit
Drive circuit
DIPIPM
P
P-side MOSFETs
AC line input
Noise filter
U
C3
Varistor
M
V
W
AC output
C
GDT
N
N1
N-side MOSFETs
VNC
CIN
Drive circuit
C : AC filter(ceramic capacitor 2.2n -6.5nF)
(Common-mode noise filter)
Input signal conditioning
Fo Logic
Protection
circuit (SC)
UV lockout
circuit
D1
Fo
N-side input(PWM)
C2
C1
Fo output
VNC
Fig.3-1-1 Application System block diagram
Publication Date: March 2014
21
(15V line)
VD
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.2 Interface Circuit (Direct Coupling Interface example for using one shunt resistor)
Fig.3-1-2 shows a typical application circuit of interface schematic, in which control signals are transferred directly input from
a controller (e.g. MCU, DSP).
+
+
P(24)
MOSFET1
C1 D1 C2 VUFB(2)
+
VVFB(3)
U(23)
MOSFET2
VWFB(4)
UP(5)
Bootstrap negative electrodes
should be connected to U,V,W
terminals directly and separated
from the main output wires
HVIC
V(22)
VP(6)
M
MOSFET3
W P(7)
VP1(8)
W(21)
C2
+
MCU
VNC(9)
C3
MOSFET4
UN(10)
VN(11)
NU(20)
W N(12)
MOSFET5
5V
Fo(14)
LVIC
NV(19)
MOSFET6
15V VD
VN1(13)
C1 + D1
C2
VNC(16)
Long wiring might cause SC level
fluctuation and malfunction.
CIN(15)
Long GND wiring might generate
noise to input signal and cause
MOSFET malfunction.
Long wiring might cause
short circuit failure
NW(18)
B
C4
C
D
R1
Shunt
resistor
A
Control GND wiring
N1
Power GND wiring
Fig.3-1-2 Interface circuit example in the case of using with one shunt resistor
If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation.
It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor).
(2) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction.
(3) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time
might vary with the wiring pattern, so the enough evaluation on the real system is necessary.
(5) To prevent malfunction, the wiring of A, B, C should be as short as possible.
(6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals should be
connected at near NU, NV, NW terminals.
(7) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic type
and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
(8) Input drive is High-active type. There is a minimum 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring
of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and
turn-off threshold voltage.
(9) Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes IFo up to 1mA.
(IFO is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V,
10kΩ (5kΩ or more) is recommended.)
(10) Thanks to built-in HVIC, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
(11) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open.
(12) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation.
To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(1)
Publication Date: March 2014
22
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.3 Interface Circuit (Example of Opto-coupler Isolated Interface)
MOSFET1
C1 D1 C2 VUFB(2)
+
+
VVFB(3)
U(23)
5V
+
MOSFET2
VWFB(4)
UP(5)
P(24)
HVIC
V(22)
VP(6)
M
MOSFET3
W P(7)
C2
VP1(8)
W(21)
MCU
+
VNC(9)
C3
MOSFET4
UN(10)
VN(11)
NU(20)
W N(12)
MOSFET5
Fo(14)
LVIC
NV(19)
MOSFET6
15V VD
C1 + D1
VN1(13)
C2
NW(18)
VNC(16)
CIN(15)
C4
R1
Shunt
resistor
N1
Fig.3-1-3 Interface circuit example with opto-coupler
Note:
(1) High speed (high CMR) opto-coupler is recommended.
(2) Fo terminal sink current for inverter part is max.1mA.
Publication Date: March 2014
23
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.4 External SC Protection Circuit with Using Three Shunt Resistors
DIPIPM
Drive circuit
P
P-side MOSFETs
U
V
W
N-side MOSFETs
External protection circuit
Drive circuit
VNC
Protection circuit
NW
NV
NU
Rf
C
Cf
B
-
Vref
+
Rf
D
Cf
CIN
Vref
Rf
Shunt
resistors
A
Cf
N1
5V
OR output
+
-
Vref
+
Comparators
(Open collector output type)
Fig.3-1-4 Interface circuit example
Note:
(1) It is necessary to set the time constant RfCf of external comparator input so that MOSFET stop within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) The threshold voltage Vref should be set up the same rating of short circuit trip level (Vsc(ref) typ. 0.48V).
(3) Select the external shunt resistance so that SC trip-level is less than specified value.
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be near the terminal of shunt resistor.
(6) OR output high level should be over 0.53V (=maximum Vsc(ref)).
(7) GND of Comparator, Vref circuit and Cf should be not connected to noisy power GND but to control GND wiring.
3.1.5 Circuits of Signal Input Terminals and Fo Terminal
DIPIPM
(1) Internal Circuit of Control Input Terminals
MOS DIPIPM is high-active input logic.
A 3.3kΩ(min) pull-down resistor is built-in each input
circuits of the DIPIPM as shown in Fig.3-1-5 , so
external pull-down resistor is not needed.
Furthermore, by lowering the turn on and turn off
threshold value of input signal as shown in Table 3-1-1,
a direct coupling to 3V class microcomputer or DSP
becomes possible.
1kΩ
UP,VP,W P
Level
Shift
Circuit
Gate
Drive
Circuit
3.3kΩ(min)
Gate
Drive
Circuit
1kΩ
UN,VN,W N
3.3kΩ(min)
Fig.3-1-5 Internal structure of control input terminals
Table 3-1-1 Input threshold voltage ratings(Tch=25°C)
Item
Symbol
Condition
Turn-on threshold voltage
Vth(on)
UP,VP,W P-VNC terminals
Turn-off threshold voltage
Vth(off)
UN,VN,W N-VNC terminals
Threshold voltage hysterisis
Vth(hys)
Min.
0.8
0.35
Typ.
2.1
1.3
0.65
Max.
2.6
-
Unit
V
Note: There are specifications for the minimum input pulse width in MOS DIPIPM. DIPIPM might make no response
if the input signal pulse width (both on and off) is less than the specified value. Please refer to the datasheet
for the specification.
Publication Date: March 2014
24
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
5Vline
10kΩ
DIPIPM
UP,VP,W P,UN,VN,W N
MCU
Fo
VNC(Logic)
Fig.3-1-6 Control input connection
Note: The RC coupling (parts shown in the dotted line) at each input depends on user’s PWM control strategy and the wiring
impedance of the printed circuit board.
The DIPIPM signal input section integrates a 3.3kΩ(min) pull-down resistor. Therefore, when using an external
filtering resistor, please pay attention to the signal voltage drop at input terminal.
(2) Internal Circuit of Fo Terminal
FO terminal is an open drain type, it should be pulled up to a 5V supply as shown in Fig.3-1-6. Fig.3-1-7
shows the typical V-I characteristics of Fo terminal. The maximum sink current of Fo terminal is 1mA.
If the opto-coupler is applied to this output, please pay attention to the opto-coupler drive ability.
Table 3-1-2 Electric characteristics of Fo terminal
Item
Symbol
Condition
VFOH
VSC=0V,Fo=10kΩ,5V pulled-up
Fault output voltage
VFOL
VSC=1V,Fo=1mA
Min.
4.9
-
Typ.
-
1.0
0.9
0.8
0.7
VFO(V)
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
0.2
0.4
0.6
0.8
1.0
IFO(mA)
Fig.3-1-7 Fo terminal typical V-I characteristics (VD=15V, Tch=25°C)
Publication Date: March 2014
25
Max.
0.95
Unit
V
V
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.6 Snubber Circuit
In order to prevent MOS DIPIPM from destruction by extra surge, the wiring length between the smoothing
capacitor and DIPIPM P terminal – N1 points (shunt resistor terminal) should be as short as possible. Also, a
0.1μ~0.22μF/630V snubber capacitor should be mounted in the DC-link and near to P, N1.
There are two positions ((1)or(2)) to mount a snubber capacitor as shown in Fig.3-1-8. Snubber capacitor
should be installed in the position (2) so as to suppress surge voltage effectively. However, the charging and
discharging currents generated by the wiring inductance and the snubber capacitor will flow through the shunt
resistor, which might cause erroneous protection if this current is large enough.
In order to suppress the surge voltage maximally, the wiring at part-A (including shunt resistor parasitic
inductance) and part-B should be as small as possible. A better wiring example is shown in location (3).
DIPIPM
Wiring Inductance
P
+
(1)
(2)
(3)
A
Shunt resistor
NU
NV
NW
Fig.3-1-8 Recommended snubber circuit location
3.1.7 Recommended Wiring Method around Shunt Resistor
External shunt resistor is employed to detect short-circuit accident. A longer wiring between the shunt
resistor and DIPIPM causes so much large surge that might damage built-in IC. To decrease the pattern
inductance, the wiring between the shunt resistor and DIPIPM should be as short as possible and using low
inductance type resistor such as SMD resistor instead of long-lead type resistor.
NU, NV, NW should be connected each other at near terminals.
DIPIPM
It is recommended to make the inductance of this part
(including the shunt resistor) under 10nH.
e.g.
Inductance of copper pattern (width=3mm,
length=17mm) is about 10nH.
NU
N1
NV
VNC
NW
Shunt resistor
Connect GND wiring from VNC terminal to the shunt
resistor terminal as close as possible.
Fig.3-1-9 Wiring instruction (In the case of using with one shunt resistor)
Publication Date: March 2014
26
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
DIPIPM
It is recommended to make the inductance of each
phase (including the shunt resistor) under 10nH.
e.g.
Inductance of copper pattern (width=3mm,
length=17mm) is about 10nH.
NU
N1
NV
VNC
NW
Connect GND wiring from VNC terminal to the shunt
resistor terminal as close as possible.
Shunt resistors
Fig.3-1-10 Wiring instruction (In the case of using with three shunt resistors)
Influence of pattern wiring around the shunt resistor is shown below.
Drive circuit
P
External protection circuit
P-side MOSFETs
U
V
W
N-side MOSFETs
DC-bus current path
B
Drive circuit
Protection circuit
NW
NV
NU
CIN
A
R2
C
C1
VNC
D
Shunt
resistor
N1
Fig.3-1-11 External protection circuit
(1) Influence of the part-A wiring
The ground of N-side MOSFET gate is VNC. If part-A wiring pattern in Fig.3-1-11 is too long, extra voltage
generated by the wiring parasitic inductance will result the potential of MOSFET source variation during
switching operation. Please install shunt resistor as close to the N terminal as possible.
(2) Influence of the part-B wiring
The part-B wiring affects SC protection level. SC protection works by detecting the voltage of the CIN
terminals. If part-B wiring is too long, extra surge voltage generated by the wiring inductance will lead to
deterioration of SC protection level. It is necessary to connect CIN and VNC terminals directly to the two ends of
shunt resistor and avoid long wiring.
(3) Influence of the part-C wiring pattern
R2C1 filter is added to remove noise influence occurring on shunt resistor. Filter effect will dropdown and noise
will easily superimpose on the wiring if part-C wiring is too long. It is necessary to install the R2C1 filter near CIN,
VNC terminals as close as possible.
(4) Influence of the part-D wiring pattern
Part-D wiring pattern gives influence to all the items described above, maximally shorten the GND wiring is
expected.
Publication Date: March 2014
27
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.8 Precaution for Wiring on PCB
This section shows main points to notice about PCB patterning.
Floating control supply V*FB and V*FS wire potential fluctuates between VDD and
GND potential at switching, so it may cause malfunction if wires for control
(e.g. control input Vin, control supply) are located near by or cross these wires.
Particularly pay attention when using multi layered PCB.
4
Supply GND for P-side driving
3
Capacitor and
Zener diode
should be located
at near terminals
Power supply
P
VUFB,VVFB,
VWFB
Output
(to motor)
UP,VP,WP
Vin
UN,VN,WN
U,V,W
Bootstrap negative electrodes
VN1,VP1 should be connected to U,V,W
VD1
VNC,VPC
Control
GND
terminals directly and separated
from the main output wires
Snubber
capacitor
2
NU
NV
NW
CIN
Connect CIN filter's
capacitor to control GND
(not to Power GND)
Shunt
resistor
Locate snubber
capacitor between
P and N1 and as
near by terminals
as possible
N1
Power GND
1
Wiring to CIN terminal
should be divided at near
shunt resistor terminal and
as short as possible.
Control
GND
Wiring between NU, NV, NW
and shunt resistor should be
as short as possible.
It is recommended to
connect control GND and
power GND at only a point
N1. (Not connect common
broad pattern)
Fig.3-1-12 Precaution for wiring on PCB
The case example of trouble due to PCB pattern
1
Case example
•Control GND pattern overlaps
power GND pattern.
•Ground loop pattern exists.
2
•Large inductance of wiring
between N and N1 terminal
3
Capacitors or zener diodes are
nothing or located far from the
terminals.
The input lines are located parallel
and close to the floating supply
lines for P-side drive.
4
Matter of trouble
The surge, generated by the wiring pattern and di/dt of noncontiguous big
current flows to power GND, transfers to control GND pattern. It causes the
control GND level fluctuation, so that the input signal based on the control
GND fluctuates too. Then the arm short might occur.
Stray current flows to GND loop pattern, so that the control GND level and
input signal level (based on the GND) fluctuates. Then the arm short might
occur.
Long wiring pattern has big parasitic inductance and generates high surge
when switching. This surge causes the matter as below.
•HVIC malfunction due to VS voltage (output terminal potential) dropping
excessively.
•LVIC surge destruction
IC surge destruction or malfunction might occur.
Cross talk noise might be transferred through the capacitance between
these floating supply lines and input lines to DIPIPM. Then incorrect signals
are input to DIPIPM input, and arm short (short circuit) might occur.
Publication Date: March 2014
28
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.9 Parallel operation of MOS DIPIPM
Fig.3-1-13 shows the circuitry of parallel connection of two DIPIPMs. Route (1) and (2) indicate the gate charging
path of low-side MOSFET in DIPIPM No.1 & 2 respectively. In the case of DIPIPM 1, the parasitic inductance
becomes large by long wiring and it might have a negative effect on DIPIPM's switching operation. (Chare
operation of bootstrap capacitor for high-side might be affected too.) Also, such a wiring makes DIPIPM be affected
by noise easily, then it might lead to malfunction. If more DIPIPMs are connected in parallel, GND pattern becomes
longer and the influence to other circuit (protection circuit etc.) by the fluctuation of GND potential is conceivable,
therefore parallel connection is not recommended.
Because DIPIPM doesn't consider the fluctuation of characteristics between each phases definitely, it cannot be
recommended to drive same load by parallel connection with other phase MOSFET or MOSFET of other DIPIPM.
DIPIPM 1
VP1
P
DC15V
U,V,W
M
AC input
VN1
VNC
N
Shunt resistor
(1)
DIPIPM 2
VP1
P
U,V,W
VN1
VNC
N
M
Shunt resistor
(2)
Fig.3-1-13 Parallel operation
3.1.10 SOA of MOS DIPIPM
The following describes the SOA (Safety Operating Area) of the MOS DIPIPM.
VDSS :
Maximum rating of MOSFET drain-source voltage
Supply voltage applied on P-N terminals
VDD :
VDD(surge): Total amount of VDD and surge voltage generated by the wiring inductance and the DC-link capacitor.
VDD(PROT) : DC-link voltage that DIPIPM can protect itself.
Drain current ID
≤VDD(surge)
≤VDD
VDS=0，ID=0
≤VDD(surge)
Short-circuit
current
≤VDD(PROT)
VDS=0，ID=0
≤2μs
Fig.3-1-14 SOA at switching mode and short-circuit mode
In case of switching
VDSS represents the maximum voltage rating (500V) of the MOSFET. By subtracting the surge voltage
(50V or less) generated by internal wiring inductance from VDSS is VDD(surge), that is 450V. Furthermore, by
subtracting the surge voltage (50V or less) generated by the wiring inductor between DIPIPM and DC-link
capacitor from VDD(surge) derives VDD, that is 400V.
In case of Short-circuit
VDSS represents the maximum voltage rating (500V) of the MOSFET. By subtracting the surge voltage
(50V or less) generated by internal wiring inductor from VDSS is VDD(surge), that is, 450V. Furthermore, by
subtracting the surge voltage (50V or less) generated by the wiring inductor between the DIPIPM and the
electrolytic capacitor from VDD(surge) derives VDD, that is, 400V.
Publication Date: March 2014
29
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.11 SCSOA
The typical SCSOA performance curves of MOS DIPIPM are shown as below.
(Conditions: VDD=400V, Tch=125°C at initial state, VDD(surge)≤450V(surge included), non-repetitive,2m load.)
In the case of PSM05S93E5, it can shut down safely an SC current that is about 12 times of its current rating
under the conditions only if the MOSFET conducting period is less than 14.7μs. Since the SCSOA operation area
will vary with the control supply voltage, DC-link voltage, and etc, it is necessary to set time constant of RC filter
with a margin.
70
VD=18.5V
68
66
VD=16.5V
VD=15V
ID (A peak)
64
↑
Max. Saturation
Current≈63A
@VD=16.5V
62
60
58
56
SC operation area
54
52
50
10
12
14
16
18
Input pulse width [μs]
Fig.3-1-15 Typical SCSOA curve of PSM05S93E5
30
VD=18.5V
29
VD=16.5V
28
ID (A peak)
27
VD=15V
↑
Max. Saturation
26
Current≈27.5A
@VD=16.5V
25
24
SC operation area
23
22
21
20
12
13
14
15
16
Input pulse width [μs]
Fig.3-1-16 Typical SCSOA curve of PSM03S93E5
Publication Date: March 2014
30
17
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.1.12 Power Life Cycles
When DIPIPM is in operation, repetitive temperature variation will happens on the MOSFET channels (ΔTch).
The amplitude and the times of the channel temperature variation affect the device lifetime. Fig.3-1-17 shows
the MOSFET power cycle curve as a function of average channel temperature variation (ΔTch).
(The curve is a regression curve based on 3 points of ΔTch=46, 88, 98K with regarding to failure rate of 0.1%, 1%
and 10%. These data are obtained from the reliability test of intermittent conducting operation)
10000000
1%
0.1%
1000000
Power Cycles
10%
100000
10000
1000
10
100
Average channel temperature variation ΔTch(K)
Fig.3-1-17 Power cycle curve
Publication Date: March 2014
31
1000
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.2 Power Loss and Thermal Dissipation Calculation
3.2.1 Power Loss Calculation
Simple expressions for calculating average power loss are given below:
● Scope
The power loss calculation intends to provide users a way of selecting a matched power device for their
VVVF inverter application. However, it is not expected to use for limit thermal dissipation design.
● Assumptions
(1) PWM controlled VVVF inverter with sinusoidal output;
(2) PWM signals are generated by the comparison of sine waveform and triangular waveform.
(3) Duty amplitude of PWM signals varies between
1− D 1+ D
(%/100), (D: modulation depth).
～
2
2
(4) Output current various with Icp·sinx and it does not include ripple.
(5) Power factor of load output current is cosθ, ideal inductive load is used for switching.
● Expressions Derivation
PWM signal duty is a function of phase angle x as
1 + D × sin x
which is equivalent to the output voltage
2
variation. From the power factor cosθ, the output current and its corresponding PWM duty at any phase
angle x can be obtained as below:
Output current = IDP × sin x
1 + D × sin( x + θ )
PWM Duty =
2
Then, VDS and VSD at the phase x can be calculated by using a linear approximation:
VDS = VDS (@ IDP × sin x)
VSD = (−1) × VSD (@ ISDP (= IDP ) × sin x)
Thus, the static loss of Tr part of MOSFET is given by:
1
2π
∫
π
0
( IDP × sin x) ×VDS @ IDP × sin x) ×
1 + D sin( x + θ )
• dx
2
Similarly, the static loss of free-wheeling diode part is given by:
1
2π
2π
∫π
((−1) × IDP × sin x)((−1) × VSD (@ IDP × sin x) ×
1 + D sin( x + θ )
• dx
2
On the other hand, the dynamic loss of Tr part of MOSFET, which does not depend on PWM duty,
is given by:
1
2π
∫
π
0
( Psw(on)(@ IDP × sin x) + Psw(off )(@ IDP × sin x)) × fc • dx
Publication Date: March 2014
32
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
Recovery loss of FWDi part can be approximated by the ideal wave form shown in Fig.3-2-1, and its
dynamic loss can be calculated by the following expression:
trr
IEC
VEC
t
Irr
Vcc
Fig.3-2-1 Ideal FWDi part recovery wave form
Psw =
Irr × VDD × trr
4
Recovery occurs only in the half cycle of the output current, thus the dynamic loss is calculated by:
1 2π Irr (@ IDP × sin x) × VDD × trr (@ IDP × sin x)
× fc • dx
4
2 ∫π
1 2π
= ∫ Irr (@ IDP × sin x) × VDD × trr (@ IDP × sin x) × fc • dx
8 ρ
 Attention of applying the power loss simulation for inverter designs
・ Divide the output current period into fine-steps and calculate the losses at each step based on the
actual values of PWM duty, output current, VDS, VSD, and Psw corresponding to the output current.
The worst condition is most important.
・ PWM duty depends on the signal generating way.
・ The relationship between output current waveform or output current and PWM duty changes with
the way of signal generating, load, and other various factors. Thus, calculation should be carried
out on the basis of actual waveform data.
・ MOSFET works as Tr and Di by one chip, so its loss becomes the sum of Tr part and Di part loss.
・ VDS,VSD and Psw(on, off) should be the values at Tch=125°C.
Publication Date: March 2014
33
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.2.2 Temperature Rise Considerations and Calculation Example
Fig.3-2-2 shows the typical characteristics of allowable motor rms current versus carrier frequency under the
following inverter operating conditions based on power loss simulation results.
Conditions: VDD=300V, VD=VDB=15V, VCE(sat)=Typ., Switching loss=Typ., Tch=125°C, Tf=100°C, Rth(j-c)=Max.,
Rth(c-f)=0.3K/W (per 1/6 module), P.F=0.8, 3-phase PWM modulation, 60Hz sine waveform output
4.0
3.5
PSM05S93E5
Io(A rms)
3.0
2.5
2.0
PSM03S93E5
1.5
1.0
0.5
0.0
0
5
10
15
20
fc(kHz)
Fig.3-2-2 Effective current-carrier frequency characteristics
Fig.3-2-2 shows an example of estimating allowable inverter output rms current under different carrier
frequency and permissible maximum operating temperature condition (Tf=100°C. Tch=125°C). The results may
change for different control strategy and motor types. Anyway please ensure that there is no large current over
device rating flowing continuously.
Inverter loss can be calclated by the free power loss simulation software will be uploaded to the web site.
URL: http://www.mitsubishielectric.com/semiconductors/
Fig.3-2-3 Loss simulator screen image
Publication Date: March 2014
34
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.3 Noise and ESD Withstand Capability
3.3.1 Evaluation Circuit of Noise Withstand Capability
MOS DIPIPM series have been confirmed to be with over +/-2.0kV noise withstand capability by the noise
evaluation under the conditions shown in Fig.3-3-1. However, noise withstand capability greatly depends on the
test environment, the wiring patterns of control substrate, parts layout, and other factors; therefore an additional
confirmation on prototype is necessary.
C
R
Breaker
AC input
U
V
W
DIPIPM
S
T
Voltage
slider
M
Fo
Control supply
(15V single power source)
I/F
Isolation
transformer
Heat sink
Inverter
Noise simulator
DC supply
AC100V
Fig.3-3-1 Noise withstand capability evaluation circuit
Note:
C1: AC line common-mode filter 4700pF, PWM signals are input from microcomputer by using opto-couplers, 15V
single power supply, Test is performed with IM
Test conditions
VDD=300V, VD=15V, Ta=25°C, no load
Scheme of applying noise: From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05-1μs, input in random.
3.3.2 Countermeasures and Precautions
MOS DIPIPM improves noise withstand capabilities by means of reducing parts quantity, lowering internal
wiring parasitic inductance, and reducing leakage current. But when the noise affects on the control terminals of
DIPIPM (due to wiring pattern on PCB), the short circuit or malfunction of SC protection may occur. In that case,
below countermeasures are recommended.
+
Increase the capacitance of
C2 and locate it as close to
the terminal as possible.
+
+
C2 VUFB(2)
P(24)
VVFB(3)
U(23)
VWFB(4)
UP(5)
HVIC
V(22)
VP(6)
M
W P(7)
C2
W(21)
VNC(9)
MCU
Insert the RC filter
VP1(8)
UN(10)
VN(11)
NU(20)
W N(12)
5V
Fo(14)
Increase the capacitance of
C4 with keeping the same
time constant R1·C4, and
locate the C4 as close to the
terminal as possible.
15V
+
LVIC
NV(19)
VN1(13)
C2
NW(18)
VNC(16)
CIN(15)
C4
R1
Fig.3-3-2 Example of countermeasures for inverter part
Publication Date: March 2014
35
Shunt
resistor
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
3.3.3 Static Electricity Withstand Capability
Withstand capability against static electricity is confirmed by the following tests shown in Fig.3-3-3, 4.
The results (typical data) are described in Table 3-3-1.
LVIC
R=0Ω
C=200pF
HVIC
R=0Ω
VP1
VN1
UN
VN
WN
UP
C=200pF
VNC
VPC
Fig.3-3-3 LVIC terminal Surge Test circuit
VUFB
VG
VUFS(U)
Fig.3-3-4 HVIC terminal Surge Test circuit
Conditions: Surge voltage increases by degree and only one-shot surge pulse is impressed at each surge
voltage. (Limit voltage of surge simulator: ±4.0kV, Judgment method; change in V-I characteristic)
Table 3-3-1 Typical ESD capability
[Control terminal part] Common data for PSM03/PSM05 because of all types have same interface circuit.
Terminals
UP, VP, WP-VNC
VP1 – VNC
VUFB-U, VVFB-V,VWFB-W
UN, VN, WN-VNC
VN1-VNC
CIN-VNC
Fo-VNC
[Power terminal part]
PSM05S93E5
Terminals
P-NU,NV,NW
U-NU, V-NV, W-NW
PSM03S93E5
Terminals
P-NU,NV,NW
U-NU, V-NV, W-NW
+
0.6
1.3
1.5
0.6
4.0 or more
0.3
0.5
0.7
1.1
1.9
0.6
2.8
0.5
1.1
+
1.8
4.0 or more
3.2
4.0 or more
+
1.4
4.0 or more
3.9
4.0 or more
Publication Date: March 2014
36
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
CHAPTER 4 Bootstrap Circuit Operation
4.1 Bootstrap Circuit Operation
For three phase inverter circuit driving, normally four isolated control supplies (three for P-side driving and
one for N-side driving) are necessary. But using floating control supply with bootstrap circuit can reduce the
number of isolated control supplies from four to one (N-side control supply).
Bootstrap circuit consists of a bootstrap diode(BSD), a bootstrap capacitor(BSC) and a current limiting
resistor. (MOSFET Super mini DIPIPM series integrates BSD and limiting resistor and can make bootstrap
circuit by adding outer BSC only.) It uses the BSC as a control supply for driving P-side MOSFET. The BSC
supplies gate charge when P-side MOSFET turning ON and circuit current of logic circuit on P-side driving IC.
(Fig.4-1-2) Since a capacitor is used as substitute for isolated supply, its supply capability is limited. This
floating supply driving with bootstrap circuit is suitable for small supply current products like DIPIPM.
Charge consumed by driving circuit is re-charged from N-side 15V control supply to BSC via current limiting
resistor and BSD when voltage of output terminal (U, V or W) goes down to GND potential in inverter operation.
But there is the possibility that enough charge doesn't perform due to the conditions such as switching
sequence, capacitance of BSC and so on. Deficient charge leads to low voltage of BSC and might work under
voltage protection (UV). This situation makes the loss of P-side MOSFET increase by low gate voltage or stop
switching. So it is necessary to consider and evaluate enough for designing bootstrap circuit. For more detail
information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap Circuit Design
Manual"
The BSD characteristics for MOSFET Super mini DIPIPM series and the circuit current characteristics in
switching situation of P-side MOSFET are described as below.
Current limiting
resistor
Bootstrap diode
(BSD)
Bootstrap capacitor
(BSC)
BSC
+
VD=15V
VN1
LVIC
N-side
MOSFET
VPC
P(Vcc)
+
Gate Drive
↑High voltage area
Logic & UV
protection
U,V,W
VFB
Level Shift
VFS
VP1
P-side
MOSFET
Low voltage area
Level Shift
VPC
VFB
BSD
P(VDD)
HVIC
VP1
15V
P-side
MOSFET
VFS
U,V,W
Voltage of VFS that is reference voltage of BSC swings between
VCC and GND level. If voltage of BSC is lower than 15V when
VFS becomes to GND potential, BSC is charged from 15V N-side
control supply.
VNC
N(GND)
Fig.4-1-1 Bootstrap Circuit Diagram
Fig.4-1-2 Bootstrap Circuit Diagram
Publication Date: March 2014
37
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
4.2 Bootstrap Supply Circuit Current at Switching State
Bootstrap supply circuit current IDB at steady state is maximum 0.1mA for this series. But at switching state,
because gate charge and discharge are repeated by switching, the circuit current exceeds 0.1mA and
increases proportional to carrier frequency. For reference, Fig.4-2-1,2 show IDB - carrier frequency fc
characteristics for PSM05S93E5 and PSM03S93E5.
Conditions: VD=VDB=15V, Tch=125°C, MOSFET ON Duty=10, 30, 50, 70, 90%
800
Circuit current (μA)
700
600
500
10%
400
30%
300
50%
200
70%
100
90%
0
0
5
10
Carrier frequency (kHz)
15
20
Fig.4-2-1 IDB vs. Carrier frequency for PSM05S93E5
400
Circuit current (μA)
350
300
250
10%
200
30%
150
50%
100
70%
50
90%
0
0
5
10
Carrier frequency (kHz)
15
Fig.4-2-2 IDB vs. Carrier frequency for PSM03S93E5
Publication Date: March 2014
38
20
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
4.3 Note for designing the bootstrap circuit
When each device for bootstrap circuit is designed, it is necessary to consider various conditions such as
temperature characteristics, change by lifetime, variation and so on. Note for designing these devices are listed
as below. For more detail information about driving by the bootstrap circuit, refer the DIPIPM application note
"Bootstrap Circuit Design Manual"
(1) Bootstrap capacitor
Electrolytic capacitors are used for BSC generally. And recently ceramic capacitors with large capacitance are also
applied. But DC bias characteristic of the ceramic capacitor when applying DC voltage is considerably different from
that of electrolytic capacitor. (Especially large capacitance type) Some differences of capacitance characteristics
between electrolytic and ceramic capacitors are listed in Table 4-3-1.
Table 4-3-1 Differences of capacitance characteristics between electrolytic and ceramic capacitors
Electrolytic capacitor
Aluminum type:
Low temp.: -10% High temp: +10%
• Conductive polymer aluminum solid type:
Low temp.: -5% High temp: +10%
•
Temperature
characteristics
(Ta:-20~ 85°C)
DC bias
characteristics
(Applying DC15V)
Ceramic capacitor
(large capacitance type)
Different due to temp. characteristics rank
Low temp.: -5%~0%
High temp.: -5%~-10%
(in the case of B,X5R,X7R ranks)
Different due to temp. characteristics,
rating voltage, package size and so on
-70%~-15%
Nothing within rating voltage
DC bias characteristic of electrolytic capacitor is not matter. But it is necessary to note ripple capability by
repetitive charge and discharge, life time which is greatly affected by ambient temperature and so on. Above
characteristics are just example data which are obtained from the WEB, please refer to the capacitor
manufacturers about detailed characteristics.
(2) Bootstrap diode
MOS DIPIPM integrates bootstrap diode for P-side driving supply. This BSD incorporates current limiting
resistor (typ. 100Ω). The VF-IF characteristics (including voltage drop by built-in current limiting resistor) is shown
in Fig.4-3-1 and Table 4-3-2.
160
30
140
25
20
100
IF [mA]
IF [mA]
120
80
60
15
10
40
5
20
0
0
1 2
3
4 5
6
0
7 8 9 10 11 12 13 14 15
V F [V]
0.0
0.5
1.0
1.5
2.0
V F [V]
2.5
3.0
Fig.4-3-1 VF-IF curve for bootstrap Diode (The left figure is enlarged view)
Table 4-3-2 Electric characteristics of built-in bootstrap diode
Item
Bootstrap Di forward
voltage
Built-in limiting resistance
Symbol
Condition
Min.
Typ.
Max.
Unit
VF
IF=10mA including voltage
drop by limiting resistor
Included in bootstrap Di
1.1
1.7
2.3
V
80
100
120
Ω
R
Publication Date: March 2014
39
3.5
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
CHAPTER 5 PACKAGE HANDLING
5.1 Packaging Specification
(44)
(22)
Plastic Tube
Quantity:
DIPIPM
12pcs per 1 tube
(520)
5 columns
Total amount in one box (max):
Tube Quantity: 5 × 7=35pcs
IPM Quantity: 35 × 12=420pcs
•••
•••
•••
•••
•••
7 stages When it isn't fully filled by tubes
at top stage, cardboard spacers
or empty tubes are inserted for
filling the space of top stage.
(230)
Weight (max):
About 8.5g per 1pcs of DIPIPM
(175) About 200g per 1 tube
About 8.3kg per 1 box
Packaging box
(545)
Spacers are put on the top and bottom of the box. If there is some space on top of the box, additional buffer materials
are also inserted.
Fig.5-1 Packaging Specification
Publication Date: March 2014
40
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
5.2 Handling Precautions
！
Cautions
Transportation
·Put package boxes in the correct direction. Putting them upside down, leaning them or
giving them uneven stress might cause electrode terminals to be deformed or resin case
to be damaged.
·Throwing or dropping the packaging boxes might cause the devices to be damaged.
·Wetting the packaging boxes might cause the breakdown of devices when operating.
Pay attention not to wet them when transporting on a rainy or a snowy day.
Storage
·We recommend temperature and humidity in the ranges 5-35°C and 45-75%,
respectively, for the storage of modules. The quality or reliability of the modules might
decline if the storage conditions are much different from the above.
Long storage
·When storing modules for a long time (more than one year), keep them dry. Also, when
using them after long storage, make sure that there is no visible flaw, stain or rust, etc. on
their exterior.
Surroundings
·Keep modules away from places where water or organic solvent may attach to them
directly or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They
might cause serious problems.
Flame
resistance
·The epoxy resin and the case materials are flame-resistant type (UL standard 94-V0), but
they are not noninflammable.
Static electricity
·ICs and power chips with MOS gate structure are used for the DIPIPM power modules.
Please keep the following notices to prevent modules from being damaged by static
electricity.
(1)Precautions against the device destruction caused by the ESD
When the ESD of human bodies, packaging and etc. are applied to terminal, it may
damage and destroy devices. The basis of anti-electrostatic is to inhibit generating static
electricity possibly and quick dissipation of the charged electricity.
·Containers that charge static electricity easily should not be used for transit and for
storage.
·Terminals should be always shorted with a carbon cloth or the like until just before using
the module. Never touch terminals with bare hands.
·Should not be taking out DIPIPM from tubes until just before using DIPIPM and never
touch terminals with bare hands.
·During assembly and after taking out DIPIPM from tubes, always earth the equipment
and your body. It is recommended to cover the work bench and its surrounding floor with
earthed conductive mats.
·When the terminals are open on the printed circuit board with mounted modules, the
modules might be damaged by static electricity on the printed circuit board.
·If using a soldering iron, earth its tip.
(2)Notice when the control terminals are open
·When the control terminals are open, do not apply voltage between the drain and source.
It might cause malfunction.
·Short the terminals before taking a module off.
Publication Date: March 2014
41
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
Revision Record
Rev.
Date
Page
-
20/ 3/2013
-
Points
New
Publication Date: March 2014
42
<Dual-In-Line Package Intelligent Power Module>
MOSFET Super mini DIPIPM APPLICATION NOTE
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
•All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are subject
to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It
is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product
listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means,
including the Mitsubishi Semiconductor home page (http://www.MitsubishiElectric.com/).
•When using any or all of the information contained in these materials, including product data, diagrams,
charts, programs, and algorithms, please be sure to evaluate all information as a total system before making
a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
•Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or systems
for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or
in part these materials.
•If these products or technologies are subject to the Japanese export control restrictions, they must be
exported under a license from the Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or re-export contrary to the export control laws and regulations of Japan and/or the country of
destination is prohibited.
•Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
for further details on these materials or the products contained therein.
© 2014 MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERVED.
DIPIPM is registered trademark of MITSUBISHI ELECTRIC CORPORATION.
Publication Date: March 2014
43